Microchip Technology Inc 24C02BT-E-SN, 24C02BT-E-P, 24C02B-E-SN, 24C01BT-E-SN, 24C01BT-E-P Datasheet
...
M
1K/2K 5.0V I
FEATURES
• Single supply with 5.0V operation
• Low power CMOS technology
- 1 mA active current typical
- 10 µ A standby current typical at 5.0V
-5 µ A standby current typical at 5.0V
• Organized as a single block of 128 b ytes (128 x 8)
or 256 bytes (256 x 8)
• 2-wire serial interface bus, I
• 100 kHz compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 8 bytes
• 2 ms typical write cycle time for page-write
• Hardware write protect for entire memory
• Can be operated as a serial ROM
• ESD protection > 3,000V
• 1,000,000 ERASE/WRITE cycles guaranteed
Data retention > 200 years
• 8 pin DIP or SOIC package
• Available for extended temperature ranges
- Automotive (E): -40˚C to +125˚C
DESCRIPTION
2
C compatible
24C01B/02B
2
™
C
Serial EEPROM
PACKA GE TYPES
PDIP
SOIC
NC
NC
NC
Vss
NC
NC
NC
Vss
1
2
3
4
1
2
3
4
24C01B/02B
24C01B/02B
8
Vcc
7
WP
6
SCL
5
SDA
8
Vcc
7
WP
6
SCL
5
SDA
The Microchip Technology Inc. 24C01B and 24C02B
are 1K bit and 2K bit Electrically Erasable PROMs. The
devices are organized as a single bloc k of 128 x 8 bit or
256 x 8 bit memory with a 2-wire serial interface. The
24C01B and 24C02B also have page-write capability
for up to 8 bytes of data. The 24C01B and 24C02B are
available in the standard 8-pin DIP and an 8-pin surf ace
mount SOIC package.
These devices are for extended temperature
applications only. It is recommended that all other
applications use Microchip’s 24LC01B/02B.
BLOCK DIAGRAM
WP
I/O
CONTROL
LOGIC
SDA SCL
VCC
VSS
MEMORY
CONTROL
LOGIC
XDEC
HV GENERATOR
EEPROM
ARRAY
PAGE LATCHES
YDEC
SENSE AMP
R/W CONTROL
2
I
C is a trademark of Philips Corporation.
1997 Microchip Technology Inc.
Preliminary
DS21233A-page 1
24C01B/02B
µ
µ
µ
1.0 ELECTRICAL CHARACTERISTICS
TABLE 1-1: PIN FUNCTION TABLE
1.1 Maximum Ratings*
V
...................................................................................7.0V
CC
All inputs and outputs w.r.t. V
Storage temperature.....................................-65˚C to +150˚C
Ambient temp. with power applied.................-65˚C to +125˚C
Soldering temperature of leads (10 seconds).............+300˚C
ESD protection on all pins............................................. ≥ 4 kV
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
................-0.6V to V
SS
CC
+1.0V
TABLE 1-1: DC CHARACTERISTICS
All parameters apply across the specified operating ranges unless otherwise
noted.
Parameter Symbol Min. Max. Units Conditions
WP, SCL and SDA pins:
High level input voltage
Low level input voltage V
Hysteresis of Schmidt trigger inputs V
Low level output voltage V
Input leakage current I
Output leakage current I
Pin capacitance (all inputs/outputs) C
Operating current I
Standby current I
Note: This parameter is periodically sampled and not 100% tested.
CC
V
= +4.5V to 5.5V
Automotive (E): Tamb = -40 ° C to 125 ° C
IH
V
IL
HYS
OL
LI
LO
,
IN
C
OUT
Write — 3 mA V
CC
I
CC
Read — 1 mA
CCS
CC
.7 V
.3 V
.05 V
CC
-10 10
-10 10
—10pFV
—30 µ AV
100
Name Function
V
SS
SDA
SCL
WP
V
CC
NC
Ground
Serial Address/Data I/O
Serial Clock
Write Protect Input
+5.0V Power Supply
No Internal Connection
V
CC
V
— V (Note)
.40 V I
mA V
OL
= 3.0 mA, V
AV
= .1V to 5.5V
IN
OUT
= 5.0V (Note 1)
CC
Tamb = 25˚C, F
= 5.5V, SCL = 100 kHz
CC
= 3.0V, SDA = SCL = V
CC
AV
CC
= 5.5V, SDA = SCL = V
CC
= .1V to 5.5V
CLK
= 2.5V
= 1 MHz
CC
CC
FIGURE 1-1: BUS TIMING START/STOP
SCL
T
SU:STA
SDA
DS21233A-page 2
START STOP
THD:STA
VHYS
Preliminary
TSU:STO
1997 Microchip Technology Inc.
24C01B/02B
TABLE 1-2: AC CHARACTERISTICS
All Parameters apply across the
specified operating ranges unless
otherwise noted
Parameter Symbol Min. Max. Units Remarks
Clock frequency F
Clock high time T
Clock low time T
SDA and SCL rise time T
SDA and SCL fall time T
START condition hold time T
START condition setup time T
Data input hold time T
Data input setup time T
STOP condition setup time T
Output valid from clock T
Bus free time T
Output fall time from V
minimum to V
IL
IH
maximum
Input filter spike suppression
(SDA and SCL pins)
Write cycle time T
Endurance — 1M — cycles 25 ° C, Vcc = 5.0V, Block Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
SP
spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained on our BBS or website.
Vcc = 4.5V to 5.5V
Automotive (E): T amb = -40˚C to +125˚C ,
and V
CLK
HIGH
LOW
R
F
:
HD
STA
:
SU
STA
HD
DAT
:
:
SU
DAT
SU
:
STO
AA
BUF
OF
T
SP
T
WR
specifications are due to Schmitt trigger inputs which provide improved noise
HYS
— 100 kHz
4000 — ns
4700 — ns
— 1000 ns (Note 1)
— 300 ns (Note 1)
4000 — ns After this period the first clock pulse is
4700 — ns Only relevant for repeated
0 — ns (Note 2)
250 — ns
4000 — ns
— 3500 ns (Note 2)
4700 — ns Time the bus must be free before a new
— 250 ns (Note 1), CB ≤ 100 pF
— 50 ns (Note 3)
— 10 ms Byte or Page mode
generated
START condition
transmission can start
FIGURE 1-2: BUS TIMING DATA
TF
TLOW
SCL
TSU:STA
HD:STA
SDA
IN
SDA
OUT
1997 Microchip Technology Inc.
TSP
TAA
T
THD:STA
THIGH
Preliminary
TR
TSU:STOTSU:DATTHD:DAT
TBUFTAA
DS21233A-page 3
24C01B/02B
2.0 FUNCTIONAL DESCRIPTION
The 24C01B/02B supports a bi-directional two wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as transmitter, and a
device receiving data as receiver. The bus has to be
controlled by a master device which generates the
serial clock (SCL), controls the bus access, and generates the START and STOP conditions, while the
24C01B/02B works as slave. Both master and slave
can operate as transmitter or receiver but the master
device determines which mode is activated.
3.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenev er the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1 Bus Not Busy (A)
Both data and clock lines remain HIGH.
3.2 Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condition.
3.3 Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4 Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last sixteen will be stored when doing a write operation. When
an overwrite does occur it will replace data in a first in
first out fashion.
3.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Note: The 24C01B/02B does not generate any
acknowledge bits if an internal programming cycle is in progress.
The device that acknowledges has to pull down the
SDA line during the acknowledge cloc k pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must lea ve the data line HIGH to enab le
the master to generate the STOP condition.
FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
A) (B) (D) (D) (C) (A)
(
SCL
SDA
START
CONDITION
DS21233A-page 4
ADDRESS OR
ACKNOWLEDGE
VALID
Preliminary
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
1997 Microchip Technology Inc.
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