Microchip Technology Inc 24C02SC-WF08, 24C02SC-WF, 24C02SC-W08, 24C02SC-W, 24C02SC-S08 Datasheet



C 

24C01SC/02SC

1K/2K 5.0V I

2

C Serial EEPROMs for Smart Cards

FEATURES

• ISO Standard 7816 pad locations

• Low power CMOS technology

- 1 mA active current typical

- 10 µ A standby current typical at 5.5V

• Organized as a single block of 128 bytes (128 x 8)
or 256 bytes (256 x 8)

• Two-wire serial interface bus, I

• 100 kHz and 400 kHz compatibility

• Self-timed write cycle (including auto-erase)

• Page-write buffer for up to 8 bytes

• 2 ms typical write cycle time for page-write

• ESD protection > 4 kV

• 1,000,000 E/W cycles guaranteed

• Data retention > 200 years

• Available for extended temperature ranges

- Commercial (C): 0 ° C to +70 ° C

2

compatible

DESCRIPTION

The Microchip Technology Inc. 24C01SC and
24C02SC are 1K-bit and 2K-bit Electrically Erasable
PROMs with bondpad positions optimized for smart
card applications. The devices are organized as a sin­gle block of 128 x 8-bit or 256 x 8-bit memory with a
two-wire serial interface. The 24C01SC and 24C02SC
also have page-write capability for up to 8 b ytes of data.

DIE LAYOUT

V

SS

SDA

DC

BLOCK DIAGRAM

I/O

CONTROL

LOGIC

SDA SCL

VCC
VSS

MEMORY

CONTROL

LOGIC

XDEC

CC

V

SCL

HV GENERATOR

EEPROM

ARRAY

PAGE LATCHES

YDEC

SENSE AMP

R/W CONTROL

2

I

C is a trademark of Philips Corporation.

1996 Microchip Technology Inc.

Preliminary

DS21170A-page 1



24C01SC/02SC

µ

µ

µ

1.0 ELECTRICAL CHARACTERISTICS

Maximum Ratings*

CC

V

........................................................................7.0V

All inputs and outputs w.r.t. V

Storage temperature...........................-65˚C to +150˚C

Ambient temp. with power applied.......-65˚C to +125˚C

ESD protection on all pads .....................................≥ 4 kV

*Notice: Stresses above those listed under “Maximum ratings”

may cause permanent damage to the device. This is a stress rat­ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

TABLE 1-2: DC CHARACTERISTICS

Parameter Symbol Min. Max. Units Conditions

SCL and SDA pads:

High level input voltage V
Low level input voltage V
Hysteresis of Schmidt trigger inputs V

Low level output voltage V
Input leakage current (SCL) I
Output leakage current (SDA) I
Pin capacitance (all inputs/outputs) C

Operating current I

Standby current I

......-0.6V to V

SS

+1.0V

CC

V

CC

= +4.5V to +5.5V Commercial (C): Tamb = 0˚C to +70˚C

IH

IL

HYS

OL
LI

LO

IN

,

C

OUT

CC

Write — 3 mA V

CC

I

Read — 1 mA Vcc = 5.5V, SCL = 400 KHz

CCS

TABLE 1-1: PAD FUNCTION TABLE

Name Function

SS

V
SDA
SCL

CC

V

DC

.7 V

CC

— .3 V

.05 V

CC

——

CC

— V (Note)

— .40 V I

-10 10

-10 10
—10pFV

— 100

Ground
Serial Address/Data I/O
Serial Clock
+4.5V to 5.5V Power Supply
Don’t connect

V

= 3.0 mA, V

OL

AV

IN

= .1V to 5.5V

OUT

AV

= .1V to 5.5V

CC

= 5.0V (Note 1)

Tamb = 25˚C, F

CC

= 5.5V

CC

AV

= 5.5V, SDA = SCL = V

= 4.5V

CC

CLK

= 1 MHz

CC

Note: This parameter is periodically sampled and not 100% tested.

FIGURE 1-1: BUS TIMING START/STOP

VHYS

SCL

SU:STA

T

SDA

DS21170A-page 2

START STOP

THD:STA

Preliminary

TSU:STO

1996 Microchip Technology Inc.

TABLE 1-3: AC CHARACTERISTICS

Parameter Symbol Min. Max. Units Remarks



24C01SC/02SC

Clock frequency F
Clock high time T
Clock low time T
SDA and SCL rise time T
SDA and SCL fall time T
START condition hold time T

START condition setup time T

Data input hold time T
Data input setup time T
STOP condition setup time T

HD

SU

HD
SU
SU

Output valid from clock T
Bus free time T

Output fall time from V
minimum to V

IL

Input filter spike suppression

IH

maximum

T

T

(SDA and SCL pins)

CLK

HIGH

LOW

R
F

:

STA

:

STA

DAT

:
:

DAT

:

STO

AA

BUF

OF

SP

— 400 kHz

600 — ns

1300 — ns

— 300 ns (Note 1)
— 300 ns (Note 1)

600 — ns After this period the first clock

pulse is generated

600 — ns Only relevant for repeated

START condition

0 — ns (Note 2)
100 — ns
600 — ns

— 900 ns (Note 2)

1300 — ns Time the bus must be free

before a new transmission can
start

20 +0.1

250 ns (Note 1), CB ≤ 100 pF

CB

— 50 ns (Note 3)

Write cycle time T
Endurance —

WR

— 10 ms Byte or Page mode

10

6

— cycles 25 ° C, Vcc = 5V, Block Mode

(Note 4)

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined T

SP

and V

HYS

specifications are due to new Schmitt trigger inputs which provide improved

noise spike suppression. This eliminates the need for a TI specification for standard operation.

4: This parameter is not tested but guaranteed b y characterization. For endurance estimates in a specific appli-

cation, please consult the Total Endurance Model which can be obtained on our BBS or website.

FIGURE 1-2: BUS TIMING DATA

TR

TBUFTAA

SCL

SDA

IN

SDA
OUT

TSU:STA

TSP

TAA

TF

TLOW

T

HD:STA

THIGH

TSU:STOTSU:DATTHD:DAT

THD:STA

1996 Microchip Technology Inc.

Preliminary

DS21170A-page 3

24C01SC/02SC



2.0 FUNCTIONAL DESCRIPTION

The 24C01SC/02SC supports a bi-directional two-wire
bus and data transmission protocol. A device that
sends data onto the bus is defined as transmitter, and
a device receiving data as receiver. The bus has to be
controlled by a master device which generates the
serial clock (SCL), controls the bus access, and gener­ates the START and STOP conditions, while the
24C01SC/02SC works as slave. Both master and slave
can operate as transmitter or receiver, but the master
device determines which mode is activated.

3.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the b us is
not busy.

• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1 Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2 Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.

3.3 Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

3.4 Data Valid (D)

The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.

Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last 16
will be stored when doing a write operation. When an
overwrite does occur, it will replace data in a first in first
out fashion.

3.5 Acknowledge

Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.

Note: The 24C01SC/02SC does not generate

any acknowledge bits if an internal pro­gramming cycle is in progress.

The device that acknowledges has to pull down the
SDA line during the acknowledge cloc k pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the sla ve. In this case,
the slave must leave the data line HIGH to enable the
master to generate the STOP condition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(

A) (B) (D) (D) (C) (A)

SCL

SDA

START

CONDITION

DS21170A-page 4

ADDRESS OR

ACKNOWLEDGE

VALID

Preliminary

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

1996 Microchip Technology Inc.

24C01SC/02SC

4.0 BUS CHARACTERISTICS

4.1 Slave Address

After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit device
code (1010) for the 24C01SC/02SC, followed by three
don't care bits.

The eighth bit of slave address determines if the master
device wants to read or write to the 24C01SC/02SC
(Figure 4-1).

The 24C01SC/02SC monitors the bus for its corre­sponding slave address all the time. It generates an
acknowledge bit if the slave address was true, and it is
not in a programming mode.

Operation

Read
Write

Control

Code

1010
1010

FIGURE 4-1: CONTROL BYTE

ALLOCATION

START

SLAVE ADDRESS

1010XXX

X = Don’t care

Chip

Select

XXX
XXX

READ/WRITE

R/W A

R/W

1
0

5.0 WRITE OPERATION

5.1 Byte Write

Following the start signal from the master, the device
code (4 bits), the don't care bits (3 bits), and the R/W
bit, which is a logic low, is placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a b yte with a word address will follo w
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore, the next byte transmitted
by the master is the word address and will be written
into the address pointer of the 24C01SC/02SC. After
receiving another acknowledge signal from the
24C01SC/02SC, the master device will transmit the
data word to be written into the addressed memory
location. The 24C01SC/02SC acknowledges again and
the master generates a stop condition. This initiates the
internal write cycle, and during this time the
24C01SC/02SC will not generate acknowledge signals
(Figure 5-1).

5.2 Page Write

The write control byte, word address, and the first data
byte are transmitted to the 24C01SC/02SC in the same
way as in a byte write. But instead of generating a stop
condition, the master transmits up to eight data bytes to
the 24C01SC/02SC, which are temporarily stored in
the on-chip page buffer and will be written into the
memory after the master has transmitted a stop condi­tion. After the receipt of each word, the three lower
order address pointer bits are internally incremented by
one. The higher order five bits of the word address
remains constant. If the master should transmit more
than eight words prior to generating the stop condition,
the address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter­nal write cycle will begin (Figure 5-2).

FIGURE 5-1: BYTE WRITE

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

CONTROL

BYTE

WORD

ADDRESS

DATA

S P

A
C
K

A
C
K

A
C
K

S
T
O
P

FIGURE 5-2: PAGE WRITE

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

 1996 Microchip Technology Inc. Preliminary DS21170A-page 5

S
T
A
R
T

CONTROL

BYTE

WORD

ADDRESS (n)

DATA n DATAn + 7

DATAn + 1

S P

A
C
K

A
C
K

A
C
K

A
C
K

A
C
K

S
T
O
P

24C01SC/02SC

6.0 ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com­mand has been issued from the master, the device ini­tiates the internally timed write cycle. ACK polling can
be initiated immediately. This in v olv es the master send­ing a start condition followed by the control byte for a
write command (R/W
the write cycle, then NO ACK will be returned. If the
cycle is complete, then the device will return the ACK,
and the master can then proceed with the next read or
write command. See Figure 6-1 for flow diagram.

FIGURE 6-1: ACKNOWLEDGE POLLING

= 0). If the de vice is still b usy with

FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

YES

Next

Operation

NO

7.0 READ OPERATION

Read operations are initiated in the same way as write
operations with the exception that the R/W
slave address is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.

7.1 Current Address Read

The 24C01SC/02SC contains an address counter that
maintains the address of the last word accessed, inter­nally incremented by one. Therefore, if the previous
access (either a read or write operation) was to address
n, the next current address read operation would
access data from address n + 1. Upon receipt of the
slave address with R/W
24C01SC/02SC issues an acknowledge and transmits
the 8-bit data word. The master will not acknowledge
the transfer but does generate a stop condition and the
24C01SC/02SC discontinues transmission
(Figure 8-2).

bit set to one, the

7.2 Random Read

Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24C01SC/02SC as part of a write operation. After the
word address is sent, the master generates a start con­dition following the acknowledge. This terminates the
write operation, but not before the internal address
pointer is set. Then, the master issues the control byte
again but with the R/W
24C01SC/02SC will then issue an acknowledge and
transmits the 8-bit data word. The master will not
acknowledge the transfer b ut does generate a stop con­dition and the 24C01SC/02SC discontinues transmis­sion (Figure 8-3).

bit set to a one. The

7.3 Sequential Read

Sequential reads are initiated in the same way as a ran­dom read except that after the 24C01SC/02SC trans­mits the first data byte, the master issues an
acknowledge as opposed to a stop condition in a ran­dom read. This directs the 24C01SC/02SC to transmit
the next sequentially addressed 8-bit word (Figure 9-1).

To provide sequential reads the 24C01SC/02SC con­tains an internal address pointer which is incremented
by one at the completion of each operation. This
address pointer allows the entire memory contents to
be serially read during one operation.

bit of the

DS21170A-page 6 Preliminary  1996 Microchip Technology Inc.

7.4 Noise Protection

The 24C01SC/02SC employs a VCC threshold detector
circuit which disables the internal erase/write logic if the
V

CC is below 1.5 volts at nominal conditions.

The SCL and SDA inputs hav e Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.

FIGURE 7-1: CURRENT ADDRESS READ

S

BUS ACTIVITY
MASTER

T
A
R
T

CONTROL

BYTE

24C01SC/02SC

S

DATA n

T
O
P

SDA LINE

SP

BUS ACTIVITY

FIGURE 7-2: RANDOM READ

S
T

BUS ACTIVITY
MASTER

SDA LINE

CONTROL

A

BYTE

R
T

S P

BUS ACTIVITY

FIGURE 7-3: SEQUENTIAL READ

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

A
C

DATA n

K

A
C
K

S

WORD

ADDRESS (n)

T
A
R
T

CONTROL

BYTE

DATA n

S

A
C
K

A
C
K

DATA n + 1 DATA n + 2 DATA n + X

A
C
K

A
C
K

A
C
K

A
C
K

N

O

A
C
K

S
T
O
P

N
O

A

C

K

S
T
O
P

P

N
O

A
C
K

 1996 Microchip Technology Inc. Preliminary DS21170A-page 7

24C01SC/02SC

8.0 PAD DESCRIPTIONS

8.1 SDA Serial Address/Data Input/Output

This is a bi-directional pad used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to V
kHz).

For normal data transfer SD A is allowed to change only
during SCL low. Changes during SCL high are reserved
for indicating the START and STOP conditions.

8.2 SCL Serial Clock

This input is used to synchronize the data transfer from
and to the device.

8.3 DC Don’t Connect

This pad is used for test purposes and should not be
bonded out. It will be pulled to V
resistor.

CC (typical 10KΩ for 100 kHz, 1KΩ for 400

SS through an internal

9.0 DIE CHARACTERISTICS

Figure 9-1 shows the die layout of the 24C01SC/02SC,
including bondpad positions. Table 9-1 shows the
actual coordinates of the bondpad midpoints with
respect to the center of the die.

FIGURE 9-1: DIE LAYOUT

DIP

V

SS

CC

V

SDA

DC

TABLE 9-1: BONDPAD COORDINATES

Pad Name

SS -495.000 749.130

V
SDA -605.875 -271.875
SCL 479.875 -746.625
V

CC 605.875 -261.375

Note 1: Dimensions are in microns.

2: Center of die is at the 0,0 point.

Pad Midpoint,

X dir.

SCL

Pad Midpoint,

Y dir.

DS21170A-page 8 Preliminary  1996 Microchip Technology Inc.

NOTES:

24C01SC/02SC

 1996 Microchip Technology Inc. Preliminary DS21170A-page 9

24C01SC/02SC

NOTES:

DS21170A-page 10 Preliminary  1996 Microchip Technology Inc.

24C01SC/02SC

24C01SC/02SC Product Identification System

To order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed
sales offices.

24C01SC/02SC — /S XX

Die Thickness Blank = 11 mils

08 = 8 mils

Other die thicknesses available, please
consult factory.

Package: S = Die in Wafer Pak

W = Wafer

WF = Sawed Wafer on Frame

Temperature Blank = 0°C to +70°C
Range:

Device: 24C01SC

24C02SC

2

1K 1

C ISO Smart Card die

2

2K 1

C ISO Smart Card die

 1996 Microchip Technology Inc. Preliminary DS21170A-page 11

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5/10/96

All rights reserved.  1996, Microchip Technology Incorporated, USA. 5/96

Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No repre­sentation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement
of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not autho­rized except with express written approval by Microchip . No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and
name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.

DS21170A-page 12 Preliminary  1996 Microchip Technology Inc.