Microchip Technology Inc 24C01CT-I-SN, 24C01CT-I-P, 24C01CT-E-ST, 24C01CT-E-SN, 24C01CT-E-P Datasheet



1997 Microchip Technology Inc.

Preliminary

DS21201A-page 1

M

24C01C

FEATURES

• Single supply with operation from 4.5 to 5.5V

• Low power CMOS technology

- 1 mA active current typical

- 10 µ A standby current typical at 5.5V

• Organized as a single block of 128 bytes (128 x 8)

• 2-wire serial interface bus, I

2

C compatible

• 100kHz and 400 kHz compatibility

• Page-write buffer for up to 16 bytes

• Self-timed write cycle (including auto-erase)

• Fast 1 mS write cycle time for byte or page mode

• Address lines allow up to eight devices on bus

• 1,000,000 erase/write cycles guaranteed

• ESD protection > 4,000V

• Data retention > 200 years

• 8-pin PDIP, SOIC or TSSOP packages

• Available for extended temperature ranges

DESCRIPTION

The Microchip Technology Inc. 24C01C is a 1K bit
Serial Electrically Erasable PROM with a voltage range
of 4.5V to 5.5V. The device is organized as a single
block of 128 x 8-bit memory with a 2-wire serial inter­face. Low current design permits operation with typical
standby and active currents of only 10 µ A and 1 mA
respectively. The device has a page-write capability for
up to 16 bytes of data and has fast write cycle times of
only 1 mS for both byte and page writes. Functional
address lines allow the connection of up to eight
24C01C devices on the same bus for up to 8K bits of
contiguous EEPROM memory. The device is available
in the standard 8-pin PDIP, 8-pin SOIC (150 mil), and
TSSOP packages.

PACKA GE TYPES

BLOCK DIAGRAM

- Commercial (C): 0 ° C to +70 ° C

- Industrial (I): -40 ° C to +85 ° C

- Automotive (E) -40 ° C to +125 ° C

PDIP/SOIC

TSSOP

A0

A1

A2

Vss

Vcc

TEST

SCL

SDA

24C01C

24C01C

1

2

3

4

8

7

6

5

A0
A1
A2

V

SS

VCC
TEST
SCL
SDA

1
2
3

4

8
7
6

5

I/O
Control
Logic

Memory
Control

Logic

XDEC

HV Generator

EEPROM
Array

YDEC

Vcc

Vss

SENSE AMP
R/W CONTROL

SDA

SCL

A0 A1 A2

1K 5.0V I

2

C

™

Serial EEPROM

I

2

C is a trademark of Philips Corporation.

24C01C

DS21201A-page 2

Preliminary



1997 Microchip Technology Inc.

1.0 ELECTRICAL
CHARACTERISTICS

1.1 Maxim

um Ratings*

V

CC

........................................................................7.0V

All inputs and outputs w.r.t. V

SS

......-0.6V to V

CC

+1.0V

Storage temperature...........................-65˚C to +150˚C

Ambient temp. with power applied.......-65˚C to +125˚C

Soldering temperature of leads (10 seconds)...+300˚C

ESD protection on all pins ......................................≥ 4 kV

*Notice: Stresses above those listed under “Maximum ratings” may

cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended peri­ods may affect device reliability.

TABLE 1-1: PIN FUNCTION TABLE

Name Function

V

SS

SDA
SCL
V

CC

A0, A1, A2

Test

Ground
Serial Data
Serial Clock
+4.5V to 5.5V Power Supply
Chip Selects
Test Pin: may be tied high, low or

left floating

TABLE 1-2: DC CHARACTERISTICS

All parameters apply across the speci­fied operating ranges unless otherwise
noted.

V

CC

= +4.5V to +5.5V
Commercial (C): Tamb = 0 ° C to +70 ° C
Industrial (I): Tamb = -40 ° C to +85 ° C
Automotive (E): Tamb = -40 ° C to +125 ° C

Parameter Symbol Min. Max. Units Conditions

SCL and SDA pins:

High level input voltage V

IH

0.7 V

CC

V

Low level input voltage V

IL

.3 V

CC

V

Hysteresis of Schmitt trigger inputs V

HYS

0.05 V

CC

— V (Note)

Low level output voltage V

OL

.40 V I

OL

= 3.0 mA, V

CC

= 4.5V

Input leakage current I

LI

-10 10

µ

A V

IN

= 0.1V to 5.5V, WP = Vss

Output leakage current I

LO

-10 10

µ

A V

OUT

= 0.1V to 5.5V

Pin capacitance (all inputs/outputs)

C

IN

, C

OUT

— 10 pF V

CC

= 5.0V (Note)

Tamb = 25 ° C, f = 1 MHz

Operating current

I

CC

Read — 1 mA V

CC

= 5.5V, SCL = 400 kHz

I

CC

Write — 3 mA V

CC

= 5.5V

Standby current I

CCS

— 50

µ

A V

CC

= 5.5V, SDA = SCL = V

CC

Note : This parameter is periodically sampled and not 100% tested.

24C01C



1997 Microchip Technology Inc.

Preliminary

DS21201A-page 3

TABLE 1-3: AC CHARACTERISTICS

FIGURE 1-1: BUS TIMING DATA

All parameters apply across the specified oper­ating ranges unless otherwise noted.

Vcc = 4.5V to 5.5V
Commercial (C): Tamb = 0 ° C to +70 ° C
Industrial (I): Tamb = -40 ° C to +85 ° C
Automotive (E): Tamb = -40 ° C to +125 ° C

Parameter Symbol

Tamb > +85 ° C -40 ° C

≤

Tamb

≤

+85 ° C

Units Remarks

Min. Max. Min. Max.

Clock frequency F

CLK

— 100 — 400 kHz

Clock high time T

HIGH

4000 — 600 — ns

Clock low time T

LOW

4700 — 1300 — ns

SDA and SCL rise time T

R

— 1000 — 300 ns (Note 1)

SDA and SCL fall time T

F

— 300 — 300 ns (Note 1)

START condition hold time T

HD

:

STA

4000 — 600 — ns After this period the first

clock pulse is generated

START condition setup time T

SU

:

STA

4700 — 600 — ns Only relevant for repeated

START condition

Data input hold time T

HD

:

DAT

0 — 0 — ns (Note 2)

Data input setup time T

SU

:

DAT

250 — 100 — ns

STOP condition setup time T

SU

:

STO

4000 — 600 — ns

Output valid from clock T

AA

— 3500 — 900 ns (Note 2)

Bus free time T

BUF

4700 — 1300 — ns Time the bus must be free

before a new transmission
can start

Output fall time from V

IH

minimum to V

IL

maximum

T

OF

— 250 20 +0.1 C

B

250 ns (Note 1), C

B

≤

100 pF

Input filter spike suppression
(SDA and SCL pins)

T

SP

— 50 — 50 ns (Note 3)

Write cycle time T

WR

— 1.5 — 1 ms Byte or Page mode

Endurance 1M — 1M — cycles 25 ° C, V

CC

= 5.0V, Block

Mode (Note 4)

Note 1: Not 100% tested. C

B

= total capacitance of one bus line in pF.

2:

As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined T

SP and VHYS specifications are due to Schmitt trigger inputs which provide improved noise

spike suppression. This eliminates the need for a TI specification for standard operation.

4: This parameter is not tested but guaranteed by characterization. F or endur ance estimates in a specific appli-

cation, please consult the Total Endurance Model which can be obtained on our BBS or website.

SCL

SDA
IN

TSU:STA

SDA
OUT

THD:STA

TLOW

THIGH

TR

TBUF

TAA

THD:DAT TSU:DAT TSU:STO

TSP

TF

24C01C

DS21201A-page 4 Preliminary  1997 Microchip Technology Inc.

2.0 PIN DESCRIPTIONS

2.1 SDA Serial Data

This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to V

CC (typical 10 kΩ for 100 kHz, 2 kΩ for

400 kHz).
For normal data transfer SD A is allow ed to change only

during SCL low. Changes during SCL high are reserved
for indicating the START and STOP conditions.

2.2 SCL Serial Clock

This input is used to synchronize the data transfer from
and to the device.

2.3 A0, A1, A2

The levels on these inputs are compared with the cor­responding bits in the slave address. The chip is
selected if the compare is true.

Up to eight 24C01C devices may be connected to the
same bus by using different chip select bit combina­tions. These inputs must be connected to either V

CC or

V

SS.

2.4 Test

This pin is utilized for testing purposes only. It may be
tied high, tied low or left floating.

2.5 Noise Protection

The 24C01C employs a VCC threshold detector circuit
which disables the internal erase/write logic if the V

CC

is below 3.8 volts at nominal conditions.
The SCL and SDA inputs hav e Schmitt trigger and filter

circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.

3.0 FUNCTIONAL DESCRIPTION

The 24C01C supports a bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The b us has to be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24C01C works
as slave. Both master and slave can operate as trans­mitter or receiver but the master device determines
which mode is activated.

24C01C

 1997 Microchip Technology Inc. Preliminary DS21201A-page 5

4.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the b us is
not busy.

• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (Figure 4-1).

4.1 Bus not Busy (A)

Both data and clock lines remain HIGH.

4.2 Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.

4.3 Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

4.4 Data Valid (D)

The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one bit of data per
clock pulse.

Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last six­teen will be stored when doing a write operation. When
an overwrite does occur it will replace data in a first in
first out fashion.

4.5 Acknowledge

Each receiving device, when addressed, is required to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.

The device that acknowledges has to pull down the
SDA line during the acknowledge cloc k pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the sla ve. In this case,
the slave must leave the data line HIGH to enable the
master to generate the STOP condition (Figure 4-2).

FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS

FIGURE 4-2: ACKNOWLEDGE TIMING

Note: The 24C01C does not generate any

acknowledge bits if an internal program­ming cycle is in progress.

(A) (B) (C) (D) (A)(C)

SCL

SDA

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

SCL

987654321 1 2 3

Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.

Receiver must release the SDA line at this point
so the Transmitter can continue sending data.

Data from transmitter

Data from transmitter

SDA

Acknowledge

Bit

24C01C

DS21201A-page 6 Preliminary  1997 Microchip Technology Inc.

5.0 DEVICE ADDRESSING

A control byte is the first byte received following the
start condition from the master device (Figure 5-1). The
control byte consists of a four bit control code; for the
24C01C this is set as 1010 binary for read and write
operations. The next three bits of the control byte are
the chip select bits (A2, A1, A0). The chip select bits
allow the use of up to eight 24C01C devices on the
same bus and are used to select which device is
accessed. The chip select bits in the control byte must
correspond to the logic levels on the corresponding A2,
A1, and A0 pins for the device to respond. These bits
are in effect the three most significant bits of the word
address.

The last bit of the control byte defines the operation to
be performed. When set to a one a read operation is
selected, and when set to a zero a write operation is
selected. Following the start condition, the 24C01C
monitors the SDA bus checking the control byte being
transmitted. Upon receiving a 1010 code and appropri­ate chip select bits, the slave device outputs an
acknowledge signal on the SDA line . Depending on the
state of the R/W

bit, the 24C01C will select a read or

write operation.

FIGURE 5-1: CONTROL BYTE FORMAT

5.1 Contiguous Ad

dressing Across

Multiple Devices

The chip select bits A2, A1, A0 can be used to expand
the contiguous address space for up to 8K bits by add­ing up to eight 24C01C devices on the same bus. In this
case, software can use A0 of the control b

yte as
address bit A8, A1 as address bit A9, and A2 as
address bit A10. It is not possib le to write or read across
device boundaries.

1 0 1 0 A2 A1 A0S ACKR/W

Control Code

Chip Select

Bits

Slave Address

Acknowledge Bit

Start Bit

Read/Wr

ite Bit

24C01C

 1997 Microchip Technology Inc. Preliminary DS21201A-page 7

6.0 WRITE OPERATIONS

6.1 Byte Write

Following the start signal from the master, the device
code (4 bits), the chip select bits (3 bits), and the R/W
bit which is a logic low is placed onto the bus by the
master transmitter. The device will acknowledge this
control byte during the ninth clock pulse. The next byte
transmitted by the master is the word address and will
be written into the address pointer of the 24C01C. After
receiving another acknowledge signal from the
24C01C the master device will transmit the data word
to be written into the addressed memory location. The
24C01C acknowledges again and the master gener­ates a stop condition. This initiates the internal write
cycle, and during this time the 24C01C will not generate
acknowledge signals (Figure 6-1).

6.2 Page Write

The write control byte, word address and the first data
byte are transmitted to the 24C01C in the same wa y as
in a byte write. But instead of generating a stop condi­tion, the master transmits up to 15 additional data bytes
to the 24C01C which are temporarily stored in the on­chip page buffer and will be written into the memory
after the master has transmitted a stop condition. After
the receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
higher order four bits of the word address remains con­stant. If the master should transmit more than 16 bytes
prior to generating the stop condition, the address
counter will roll over and the previously received data
will be overwritten. As with the byte write operation,
once the stop condition is received an internal write
cycle will begin (Figure 6-2).

FIGURE 6-1: BYTE WRITE

FIGURE 6-2: PAGE WRITE

S P

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

S
T
O
P

CONTROL

BYTE

WORD

ADDRESS

DATA

A
C
K

A
C
K

A

C

K

S P

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

CONTROL

BYTE

WORD

ADDRESS (n)

DATA n DATA n + 15

S
T
O
P

A
C
K

A
C
K

A
C
K

A
C
K

A
C
K

DATA n +1

24C01C

DS21201A-page 8 Preliminary  1997 Microchip Technology Inc.

7.0 ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com­mand has been issued from the master, the device ini­tiates the internally timed write cycle. ACK polling can
be initiated immediately . This in v olv es the master send­ing a start condition followed by the control byte for a
write command (R/W

= 0). If the de vice is still b usy with
the write cycle, then no ACK will be returned. If no ACK
is returned, then the start bit and control byte must be
re-sent. If the cycle is complete, then the device will
return the ACK and the master can then proceed with
the next read or write command. See Figure 7-1 for flow
diagram.

FIGURE 7-1: ACKNOWLEDGE POLLING

FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Next

Operation

NO

YES

24C01C

 1997 Microchip Technology Inc. Preliminary DS21201A-page 9

8.0 READ OPERATIONS

Read operations are initiated in the same way as write
operations with the exception that the R/W

bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.

8.1 Current Address Read

The 24C01C contains an address counter that main­tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address n, the next current address read
operation would access data from address n + 1. Upon
receipt of the slave address with the R/W

bit set to one,
the 24C01C issues an acknowledge and transmits the
eight bit data word. The master will not acknowledge
the transfer but does generate a stop condition and the
24C01C discontinues transmission (Figure 8-1).

8.2 Random Read

Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24C01C as part of a write operation. After the word

address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the R/W

bit set to a one. The 24C01C will then
issue an acknowledge and transmits the eight bit data
word. The master will not acknowledge the transfer but
does generate a stop condition and the 24C01C dis­continues transmission (Figure 8-2). After this com­mand, the internal address counter will point to the
address location following the one that was just read.

8.3 Sequential Read

Sequential reads are initiated in the same way as a ran­dom read except that after the 24C01C transmits the
first data byte, the master issues an acknowledge as
opposed to a stop condition in a random read. This
directs the 24C01C to transmit the next sequentially
addressed 8-bit word (Figure 8-3).

To provide sequential reads the 24C01C contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation. The internal address pointer will
automatically roll over from address 7F to address 00.

FIGURE 8-1: CURRENT ADDRESS READ

FIGURE 8-2: RANDOM READ

FIGURE 8-3: SEQUENTIAL READ

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

P

S

S
T
O
P

CONTROL

BYTE

S
T
A
R
T

DATA

A
C
K

N
O

A

C

K

S P

S

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

S
T
O
P

CONTROL

BYTE

A
C
K

WORD

ADDRESS (n)

CONTROL

BYTE

S
T
A
R
T

DATA (n)

A
C
K

A
C
K

N
O

A
C
K

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

DATA n DATA n + 1 DATA n + 2 DATA n + X

N
O

A
C
K

A
C
K

A
C
K

A
C
K

A
C
K

S
T
O
P

P

24C01C

DS21201A-page 10 Preliminary  1997 Microchip Technology Inc.

NOTES:

24C01C

 1997 Microchip Technology Inc. Preliminary DS21201A-page 11

24C01C PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Sales and Support

Package:

P = Plastic DIP (300 mil Body), 8-lead

SN = Plastic SOIC, (150 mil Body), 8-lead

ST = TSSOP (4.4 mm Body), 8-lead

Temperature
Range:

Blank = 0°C to +70°C

I = –40°C to +85°C

E = –40°C to +125°C

Device:

24C01C 1K I

2

C Serial EEPROM

24C01CT 1K I

2

C Serial EEPROM (Tape and Reel)

24C01C — /P

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom­mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office.

2. The Microchip Corporate Literature Center U.S. FAX: [phone].

3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).

Inf or mation contained in this publication regarding d evice applications and the like is intended f or suggestion only and may b e superseded by updates . No representation or
warranty is gi v en and no liability is assumed by Microchi p Technology Inco r porated with respect to the accu r acy or use of suc h inf or mation, or inf ringement of patents or other
intellectual prope r ty r ights a r ising from such use or otherwis e . Use of Microchip ’ s products as c r itical components in li fe support systems is not autho r ized e xcept with e xpress
written appro val by Microchi p. No licenses are con v eyed, implicitly or otherwise, under any intellectual prope r ty right s. The Microchip logo and name are registered t rademar ks
of Microchi p Technology Inc . in the U.S .A. and other count r ies. All rights rese r v ed. All other tradema r ks mentioned herein are the proper ty of their respective companies.

DS21201A-page 12

Preliminary



1997 Microchip Technology Inc.

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JAPAN

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Kanagawa 222 J apan

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