Microchip Technology Inc 24C02BT-E-SN, 24C02BT-E-P, 24C02B-E-SN, 24C01BT-E-SN, 24C01BT-E-P Datasheet



M

1K/2K 5.0V I

FEATURES

• Single supply with 5.0V operation

• Low power CMOS technology

- 1 mA active current typical

- 10 µ A standby current typical at 5.0V

-5 µ A standby current typical at 5.0V

• Organized as a single block of 128 b ytes (128 x 8)
or 256 bytes (256 x 8)

• 2-wire serial interface bus, I

• 100 kHz compatibility

• Self-timed write cycle (including auto-erase)

• Page-write buffer for up to 8 bytes

• 2 ms typical write cycle time for page-write

• Hardware write protect for entire memory

• Can be operated as a serial ROM

• ESD protection > 3,000V

• 1,000,000 ERASE/WRITE cycles guaranteed
Data retention > 200 years

• 8 pin DIP or SOIC package

• Available for extended temperature ranges

- Automotive (E): -40˚C to +125˚C

DESCRIPTION

2

C compatible

24C01B/02B

2

™

C

Serial EEPROM

PACKA GE TYPES

PDIP

SOIC

NC
NC

NC

Vss

NC
NC

NC

Vss

1
2

3

4

1
2

3

4

24C01B/02B

24C01B/02B

8

Vcc

7

WP

6

SCL

5

SDA

8

Vcc

7

WP

6

SCL

5

SDA

The Microchip Technology Inc. 24C01B and 24C02B
are 1K bit and 2K bit Electrically Erasable PROMs. The
devices are organized as a single bloc k of 128 x 8 bit or
256 x 8 bit memory with a 2-wire serial interface. The
24C01B and 24C02B also have page-write capability
for up to 8 bytes of data. The 24C01B and 24C02B are
available in the standard 8-pin DIP and an 8-pin surf ace
mount SOIC package.

These devices are for extended temperature
applications only. It is recommended that all other
applications use Microchip’s 24LC01B/02B.

BLOCK DIAGRAM

WP

I/O

CONTROL

LOGIC

SDA SCL

VCC
VSS

MEMORY

CONTROL

LOGIC

XDEC

HV GENERATOR

EEPROM

ARRAY

PAGE LATCHES

YDEC

SENSE AMP

R/W CONTROL

2

I

C is a trademark of Philips Corporation.

1997 Microchip Technology Inc.

Preliminary

DS21233A-page 1



24C01B/02B

µ

µ

µ

1.0 ELECTRICAL CHARACTERISTICS

TABLE 1-1: PIN FUNCTION TABLE

1.1 Maximum Ratings*

V

...................................................................................7.0V

CC

All inputs and outputs w.r.t. V

Storage temperature.....................................-65˚C to +150˚C

Ambient temp. with power applied.................-65˚C to +125˚C

Soldering temperature of leads (10 seconds).............+300˚C

ESD protection on all pins............................................. ≥ 4 kV

*Notice: Stresses above those listed under “Maximum ratings”

may cause permanent damage to the device. This is a stress rat­ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

................-0.6V to V

SS

CC

+1.0V

TABLE 1-1: DC CHARACTERISTICS

All parameters apply across the speci­fied operating ranges unless otherwise
noted.

Parameter Symbol Min. Max. Units Conditions

WP, SCL and SDA pins:

High level input voltage
Low level input voltage V
Hysteresis of Schmidt trigger inputs V

Low level output voltage V
Input leakage current I
Output leakage current I
Pin capacitance (all inputs/outputs) C

Operating current I

Standby current I

Note: This parameter is periodically sampled and not 100% tested.

CC

V

= +4.5V to 5.5V

Automotive (E): Tamb = -40 ° C to 125 ° C

IH

V

IL

HYS

OL

LI

LO

,

IN

C

OUT

Write — 3 mA V

CC

I

CC

Read — 1 mA

CCS

CC

.7 V

.3 V

.05 V

CC

-10 10

-10 10
—10pFV

—30 µ AV

100

Name Function

V

SS

SDA
SCL

WP
V

CC

NC

Ground
Serial Address/Data I/O
Serial Clock
Write Protect Input
+5.0V Power Supply
No Internal Connection

V

CC

V

— V (Note)

.40 V I

mA V

OL

= 3.0 mA, V

AV

= .1V to 5.5V

IN
OUT

= 5.0V (Note 1)

CC

Tamb = 25˚C, F

= 5.5V, SCL = 100 kHz

CC

= 3.0V, SDA = SCL = V

CC

AV

CC

= 5.5V, SDA = SCL = V

CC

= .1V to 5.5V

CLK

= 2.5V

= 1 MHz

CC
CC

FIGURE 1-1: BUS TIMING START/STOP

SCL

T

SU:STA

SDA

DS21233A-page 2

START STOP

THD:STA

VHYS

Preliminary

TSU:STO

1997 Microchip Technology Inc.



24C01B/02B

TABLE 1-2: AC CHARACTERISTICS

All Parameters apply across the
specified operating ranges unless
otherwise noted

Parameter Symbol Min. Max. Units Remarks

Clock frequency F
Clock high time T
Clock low time T
SDA and SCL rise time T
SDA and SCL fall time T
START condition hold time T

START condition setup time T

Data input hold time T
Data input setup time T
STOP condition setup time T
Output valid from clock T
Bus free time T

Output fall time from V
minimum to V

IL

IH

maximum

Input filter spike suppression
(SDA and SCL pins)

Write cycle time T
Endurance — 1M — cycles 25 ° C, Vcc = 5.0V, Block Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined T

SP

spike suppression. This eliminates the need for a TI specification for standard operation.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific

application, please consult the Total Endurance Model which can be obtained on our BBS or website.

Vcc = 4.5V to 5.5V
Automotive (E): T amb = -40˚C to +125˚C ,

and V

CLK

HIGH

LOW

R

F

:

HD

STA

:

SU

STA

HD

DAT

:
:

SU

DAT

SU

:

STO

AA

BUF

OF

T

SP

T

WR

specifications are due to Schmitt trigger inputs which provide improved noise

HYS

— 100 kHz
4000 — ns
4700 — ns

— 1000 ns (Note 1)

— 300 ns (Note 1)
4000 — ns After this period the first clock pulse is

4700 — ns Only relevant for repeated

0 — ns (Note 2)

250 — ns

4000 — ns

— 3500 ns (Note 2)
4700 — ns Time the bus must be free before a new

— 250 ns (Note 1), CB ≤ 100 pF

— 50 ns (Note 3)

— 10 ms Byte or Page mode

generated

START condition

transmission can start

FIGURE 1-2: BUS TIMING DATA

TF

TLOW

SCL

TSU:STA

HD:STA

SDA

IN

SDA
OUT

1997 Microchip Technology Inc.

TSP

TAA

T

THD:STA

THIGH

Preliminary

TR

TSU:STOTSU:DATTHD:DAT

TBUFTAA

DS21233A-page 3

24C01B/02B

2.0 FUNCTIONAL DESCRIPTION

The 24C01B/02B supports a bi-directional two wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as transmitter, and a
device receiving data as receiver. The bus has to be
controlled by a master device which generates the
serial clock (SCL), controls the bus access, and gener­ates the START and STOP conditions, while the
24C01B/02B works as slave. Both master and slave
can operate as transmitter or receiver but the master
device determines which mode is activated.

3.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus
is not busy.

• During data transfer, the data line must remain
stable whenev er the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1 Bus Not Busy (A)

Both data and clock lines remain HIGH.

3.2 Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condi­tion.

3.3 Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

3.4 Data Valid (D)

The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.

Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last six­teen will be stored when doing a write operation. When
an overwrite does occur it will replace data in a first in
first out fashion.

3.5 Acknowledge

Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.

Note: The 24C01B/02B does not generate any

acknowledge bits if an internal program­ming cycle is in progress.

The device that acknowledges has to pull down the
SDA line during the acknowledge cloc k pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must lea ve the data line HIGH to enab le
the master to generate the STOP condition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

A) (B) (D) (D) (C) (A)

(

SCL

SDA

START

CONDITION

DS21233A-page 4

ADDRESS OR

ACKNOWLEDGE

VALID

Preliminary

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

 1997 Microchip Technology Inc.

24C01B/02B

3.6 Device Address

After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit de vice
code (1010) for the 24C01B/02B, followed by three
don't care bits.

The eighth bit of slave address determines if the master
device wants to read or write to the 24C01B/02B
(Figure 3-2).

The 24C01B/02B monitors the bus for its correspond­ing slave address all the time. It generates an acknowl­edge bit if the slave address was true and it is not in a
programming mode.

Operation

Read
Write

Control

Code

1010
1010

Chip

Select

XXX
XXX

R/W

1
0

FIGURE 3-2: CONTROL BYTE

ALLOCATION

READ/WRITESTART

SLAVE ADDRESS

1 010XXX

X = Don’t care

R/W A

4.0 WRITE OPERATION

4.1 Byte Write

Following the start signal from the master, the device
code (4 bits), the don't care bits (3 bits), and the R/W
bit which is a logic low is placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a b yte with a word address will follo w
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore the next byte transmitted
by the master is the word address and will be written
into the address pointer of the 24C01B/02B. After
receiving another acknowledge signal from the
24C01B/02B the master device will transmit the data
word to be written into the addressed memory location.
The 24C01B/02B acknowledges again and the master
generates a stop condition. This initiates the internal
write cycle, and during this time the 24C01B/02B will
not generate acknowledge signals (Figure 4-1).

4.2 Page Write

The write control byte, word address and the first data
byte are transmitted to the 24C01B/02B in the same
way as in a byte write. But instead of generating a stop
condition the master transmits up to eight data bytes to
the 24C01B/02B which are temporarily stored in the
on-chip page buffer and will be written into the memory
after the master has transmitted a stop condition. After
the receipt of each word, the three lower order address
pointer bits are internally incremented by one. The
higher order five bits of the word address remains con­stant. If the master should transmit more than eight
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter­nal write cycle will begin (Figure 4-2).

FIGURE 4-1: BYTE WRITE

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

CONTROL

BYTE

WORD

ADDRESS

DATA

S P

A
C
K

A
C
K

A
C
K

S
T
O
P

FIGURE 4-2: PAGE WRITE

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

 1997 Microchip Technology Inc. Preliminary DS21233A-page 5

S
T
A
R
T

CONTROL

BYTE

WORD

ADDRESS (n)

DATA n DATAn + 7

DATAn + 1

S P

A
C
K

A
C
K

A
C
K

A
C
K

A
C
K

S
T
O
P

24C01B/02B

5.0 ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com­mand has been issued from the master, the device ini­tiates the internally timed write cycle. ACK polling can
be initiated immediately . This inv olv es the master send­ing a start condition followed by the control byte for a
write command (R/W
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 5-1 for flow diagram.

FIGURE 5-1: ACKNOWLEDGE POLLING

= 0). If the de vice is still b usy with

FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

7.0 READ OPERATION

Read operations are initiated in the same way as write
operations with the exception that the R/W
slave address is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.

7.1 Current Address Read

The 24C01B/02B contains an address counter that
maintains the address of the last word accessed, inter­nally incremented by one. Therefore, if the previous
access (either a read or write operation) was to
address n, the next current address read operation
would access data from address n + 1. Upon receipt of
the slave address with R/W
02B issues an acknowledge and transmits the eight bit
data word. The master will not acknowledge the trans­fer but does generate a stop condition and the 24C01B/
02B discontinues transmission (Figure 7-1).

bit set to one, the 24C01B/

7.2 Random Read

Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24C01B/02B as part of a write operation. After the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the R/W
issue an acknowledge and transmits the eight bit data
word. The master will not acknowledge the transf er but
does generate a stop condition and the 24C01B/02B
discontinues transmission (Figure 7-2).

bit set to a one. The 24C01B/02B will then

bit of the

Did Device

Acknowledge

(ACK = 0)?

YES

Next

Operation

NO

6.0 WRITE PROTECTION

The 24C01B/02B can be used as a serial ROM when
the WP pin is connected to V
inhibited and the entire memory will be write-protected.

DS21233A-page 6 Preliminary  1997 Microchip Technology Inc.

CC. Programming will be

7.3 Sequential Read

Sequential reads are initiated in the same way as a ran­dom read except that after the 24C01B/02B transmits
the first data byte, the master issues an acknowledge
as opposed to a stop condition in a random read. This
directs the 24C01B/02B to transmit the next sequen­tially addressed 8-bit word (Figure 7-3).

To provide sequential reads the 24C01B/02B contains
an internal address pointer which is incremented by
one at the completion of each operation. This address
pointer allows the entire memory contents to be serially
read during one operation.

7.4 Noise Protection

The 24C01B/02B employs a VCC threshold detector cir­cuit which disables the internal erase/write logic if the
V

CC is below 1.5 volts at nominal conditions.

The SCL and SDA inputs hav e Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.

FIGURE 7-1: CURRENT ADDRESS READ

S

BUS ACTIVITY
MASTER

T
A
R
T

CONTROL

BYTE

DATA n

24C01B/02B

S
T
O
P

SDA LINE

BUS ACTIVITY

SP

FIGURE 7-2: RANDOM READ

S
T

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

CONTROL

A

BYTE

R
T

S P

FIGURE 7-3: SEQUENTIAL READ

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

A
C

DATA n

K

A
C
K

S
T

WORD

ADDRESS (n)

A
R
T

CONTROL

BYTE

DATA n

S

A
C
K

A
C
K

DATA n + 1 DATA n + 2 DATA n + X

A
C
K

A
C
K

A
C
K

A
C
K

N
O

A
C
K

S
T
O
P

N
O

A
C
K

S
T
O
P

P

N
O

A
C
K

8.0 PIN DESCRIPTIONS

8.1 Serial Data

This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA b us requires a pull-up
resistor to V

For normal data transfer SD A is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-

CC (typically 10 KΩ for 100 kHz).

8.3 WP

This pin must be connected to either VSS or VCC.
If tied to V

(read/write the entire memory).
If tied to V

entire memory will be write-protected. Read operations
are not affected.

This feature allows the user to use the 24C01B/02B as
a serial ROM when WP is enabled (tied to V

SS, normal memory operation is enabled

CC, WRITE operations are inhibited. The

CC).

tions.

8.2 SCL Serial Clock

This input is used to synchronize the data transfer from
and to the device.

 1997 Microchip Technology Inc. Preliminary DS21233A-page 7

24C01B/02B

NOTES:

DS21233A-page 8 Preliminary  1997 Microchip Technology Inc.

NOTES:

24C01B/02B

 1997 Microchip Technology Inc. Preliminary DS21233A-page 9

24C01B/02B

NOTES:

DS21233A-page 10 Preliminary  1997 Microchip Technology Inc.

24C01B/02B

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

24C01B/02B — /P

Package:

Temperature E = -40°C to +125°C
Range:

Device:

24C01BT 1K I

24C02BT 2K I

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom­mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office.

2. The Microchip Corporate Literature Center U.S. FAX: [phone].

3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

P = Plastic DIP (300 mil Body), 8-lead

SN = Plastic SOIC (150 mil Body)

2

24C01B 1K I

24C02B 2K I

C Serial EEPROM

2

C Serial EEPROM (Tape and Reel)

2

C Serial EEPROM

2

C Serial EEPROM (Tape and Reel)

 1997 Microchip Technology Inc. Preliminary DS21233A-page 11



M

W

ORLDWIDE

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10/31/97

All rights reserved. © 1997, Microchip Technology Incorporated, USA. 12/97 Printed on recycled paper.

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DS21233A-page 12

Preliminary

1997 Microchip Technology Inc.