Microchip Technology Inc 24LC256T-I-SM, 24LC256T-I-P, 24LC256T-E-SM, 24LC256-I-SM, 24LC256-I-P Datasheet



M

2

256K I

DEVICE SELECTION TABLE

Part

Number

24AA256 1.8-5.5V 400 kHz
24LC256 2.5-5.5V 400 kHz

†

100 kHz for V

‡

100 kHz for E temperature range.

FEATURES

• Low power CMOS technology

- Maximum write current 3 mA at 5.5V

- Maximum read current 400 µ A at 5.5V

- Standby current 100 nA typical at 5.5V

• 2-wire serial interface bus, I

• Cascadable for up to eight devices

• Self-timed ERASE/WRITE cycle

• 64-byte page-write mode available

• 5 ms max write-cycle time

• Hardware write protect for entire array

• Schmitt trigger inputs for noise suppression

• 100,000 erase/write cycles guaranteed

• Electrostatic discharge protection > 4000V

• Data retention > 200 years

• 8-pin PDIP and SOIC (208 mil) packages

• Temperature ranges:

- Industrial (I): -40 ° C to +85 ° C

- Automotive (E): -40 ° C to +125 ° C

CC

V

Range

CC

< 2.5V.

Max Clock
Frequency

2

C compatible

™

C

†
‡

24AA256/24LC256

CMOS Serial EEPROM

P ACKA GE TYPE

Temp

Ranges

I

I, E

PDIP

A0

1

A1

2

A2

3

Vss

4

SOIC

A0
A1
A2

SS

V

1
2

3
4

BLOCK DIAGRAM

WP

MEMORY

CONTROL

LOGIC

I/O

CONTROL

LOGIC

A0…A2

24xx256

8

24xx256

7
6
5

XDEC

Vcc

8

WP

7

SCL

6

SDA

5

VCC
WP
SCL
SDA

HV GENERATOR

EEPROM

PAGE LATCHES

ARRAY

DESCRIPTION

The Microchip Technology Inc. 24AA256/24LC256
(24xx256*) is a 32K x 8 (256K bit) Serial Electrically
Erasable PROM, capable of operation across a broad
voltage range (1.8V to 5.5V). It has been developed for
advanced, low power applications such as personal
communications or data acquisition. This device also
has a page-write capability of up to 64 bytes of data.
This device is capable of both random and sequential
reads up to the 256K boundary. Functional address
lines allow up to eight devices on the same bus, for up
to 2 Mbit address space. This device is available in the
standard 8-pin plastic DIP, and 8-pin SOIC (208 mil)
packages.

2

I

C is a trademark of Philips Corporation.

*24xx256 is used in this document as a generic part number for the 24AA256/24LC256 devices.

1998 Microchip Technology Inc. DS21203C-page 1

I/O

SDA

VCC

VSS

SCL

YDEC

SENSE AMP

R/W CONTROL



24AA256/24LC256

≥

µ

µ

µ

1.0 ELECTRICAL

TABLE 1-1 PIN FUNCTION TABLE

CHARACTERISTICS

1.1 Maximum Ratings*

CC

V

.................................................................................................7.0V

All inputs and outputs w.r.t. V

Storage temperature...................................................-65 ° C to +150 ° C

Ambient temp. with power applied...............................-65 ° C to +125 ° C

Soldering temperature of leads (10 seconds)...........................+300 ° C

ESD protection on all pins .................................................................≥ 4 kV

*Notice: Stresses above those listed under “Maximum Ratings” may

cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended peri­ods may affect device reliability.

TABLE 1-2 DC CHARACTERISTICS

All parameters apply across the
specified operating ranges unless
otherwise noted.

Parameter Symbol Min Max Units Conditions

A0, A1, A2,
SCL, SDA, and WP pins:

High level input voltage V
Low level input voltage V

Hysteresis of Schmitt Trigger
inputs (SDA, SCL pins)

Low level output voltage V

Input leakage current I

Output leakage current I
Pin capacitance

(all inputs/outputs)
Operating current I

Standby current I

Note: This parameter is periodically sampled and not 100% tested.

............................. -0.6V to V

SS

Industrial (I): V
Automotive (E): V

IN

C

CC
CC

I

+1.0V

CC

CC

= +1.8V to 5.5V Tamb = -40 ° C to +85 ° C
= +4.5V to 5.5V Tamb = -40 ° C to 125 ° C

CC

V

IH
IL

HYS

OL

LI

LO

, C

OUT

0.7 V

CC

— 0.3 V

CC

0.05 V

— 0.40 V I

-10 10

-10 10
—10pFV

Write — 3 mA V

Read — 400

CCS

—1 µ A SCL = SDA = V

Name Function

A0, A1, A2 User Configurable Chip Selects

SS

V

Ground
SDA Serial Data
SCL Serial Clock

WP Write Protect Input

CC

V

+1.8 to 5.5V (24AA256)

+2.5 to 5.5V (24LC256)

—V

CC
CC

0.2 V
—VV

VVVcc ≥ 2.5V

Vcc < 2.5V

CC

2.5V (Note)

OL

= 3.0 mA @ V

OL

I

= 2.1 mA @ V

AV

IN

= V

SS

V

= V

IN

SS

OUT

AV

= V

CC

= 5.0V (Note)

Tamb = 25˚C, f

CC

= 5.5V

CC

AV

= 5.5V, SCL = 400 kHz

A0, A1, A2, WP = V

or V
or V

SS

CC
CC

or V

CC
CC

, WP = V
, WP = V

CC

= 1 MHz

c

= 5.5V

CC

SS

= 4.5V
= 2.5V

SS
CC

FIGURE 1-1: BUS TIMING DATA

TF

SCL

SDA
IN

SDA
OUT

WP

DS21203C-page 2

TSU:STA

TSP

TLOW

THD:STA

THIGH

THD:DAT TSU:DAT TSU:STO

TAA

(protected)

(unprotected)

VHYS

TR

TSU:WP

TBUF

THD:WP

1998 Microchip Technology Inc.

TABLE 1-3 AC CHARACTERISTICS

24AA256/24LC256



All parameters apply across the spec­ified operating ranges unless other­wise noted.

Parameter Symbol Min Max Units Conditions

Clock frequency FCLK —

Clock high time THIGH 4000

Clock low time TLOW 4700

SDA and SCL rise time
(Note 1)

SDA and SCL fall time T
START condition hold time THD:STA 4000

START condition setup time TSU:STA 4700

Data input hold time THD:DAT 0 — ns (Note 2)
Data input setup time TSU:DAT 250

STOP condition setup time TSU:STO 4000

WP setup time TSU:WP 4000

WP hold time THD:WP 4700

Output valid from clock
(Note 2)

Bus free time: Time the bus must be
free before a new transmission can
start

Output fall time from VIH
minimum to VIL maximum

Input filter spike suppression
(SDA and SCL pins)

Write cycle time (byte or page) TWC —5
Endurance

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum

300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined T

suppression. This eliminates the need for a TI specification for standard operation.

4: This parameter is not tested but guaranteed b y characterization. F or endurance estimates in a specific application, please

consult the Total Endurance Model which can be obtained on Microchip’s BBS or website.

SP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise spike

Industrial (I): V
Automotive (E): V

TR —

F — 300 ns (Note 1)

TAA —

TBUF 4700

TOF 10 250 ns CB ≤ 100 pF (Note 1)

TSP — 50 ns (Notes 1 and 3)

—
—

4000

600

4700
1300

—
—

4000

600

4700

600

250
100

4000

600

4000

600

4700
1300

—
—

4700
1300

100,000

CC

= +1.8V to 5.5V Tamb = -40 ° C to +85 ° C

CC

= +4.5V to 5.5V Tamb = -40°C to 125°C

100
100
400

1000
1000

300

3500
3500

900

kHz 4.5V ≤ VCC ≤ 5.5V (E Temp range)

1.8V ≤ VCC ≤ 2.5V

2.5V ≤ VCC ≤ 5.5V

—
—
—

—
—
—

—
—
—

—
—
—

—
—
—

—
—
—

—
—
—

—
—
—

—
—
—

— cycles 25°C, V

ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)

1.8V ≤ VCC ≤ 2.5V

2.5V ≤ VCC ≤ 5.5V

ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)

1.8V ≤ VCC ≤ 2.5V

2.5V ≤ VCC ≤ 5.5V

ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)

1.8V ≤ VCC ≤ 2.5V

2.5V ≤ VCC ≤ 5.5V

ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)

1.8V ≤ VCC ≤ 2.5V

2.5V ≤ VCC ≤ 5.5V

ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)

1.8V ≤ VCC ≤ 2.5V

2.5V ≤ VCC ≤ 5.5V

ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)

1.8V ≤ VCC ≤ 2.5V

2.5V ≤ VCC ≤ 5.5V

ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)

1.8V ≤ VCC ≤ 2.5V

2.5V ≤ VCC ≤ 5.5V

ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)

1.8V ≤ VCC ≤ 2.5V

2.5V ≤ VCC ≤ 5.5V

ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)

1.8V ≤ VCC ≤ 2.5V

2.5V ≤ VCC ≤ 5.5V

ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)

1.8V ≤ VCC ≤ 2.5V

2.5V ≤ VCC ≤ 5.5V

ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)

1.8V ≤ VCC ≤ 2.5V

2.5V ≤ VCC ≤ 5.5V

ms

CC = 5.0V, Block Mode (Note 4)

1998 Microchip Technology Inc. DS21203C-page 3

24AA256/24LC256

2.0 PIN DESCRIPTIONS

2.1 A0, A1, A2 Chip Address Inputs

The A0, A1, A2 inputs are used by the 24xx256 for
multiple device operation. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.

Up to eight devices may be connected to the same b us
by using different chip select bit combinations. If left
unconnected, these inputs will be pulled down
internally to V

2.2 SDA Serial Data

This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open­drain terminal, therefore, the SDA bus requires a pull­up resistor to V
400 kHz)

For normal data transfer SD A is allowed to change only
during SCL low. Changes during SCL high are reserved
for indicating the START and STOP conditions.

2.3 SCL Serial Clock

This input is used to synchronize the data transfer from
and to the device.

SS.

CC (typical 10 kΩ for 100 kHz, 2 kΩ for

4.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the b us is
not busy.

• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (Figure 4-1).

4.1 Bus not Busy (A)

Both data and clock lines remain HIGH.

4.2 Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.

4.3 Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must end with a STOP condition.

4.4 Data Valid (D)

2.4 WP

This pin can be connected to either VSS, VCC or left
floating. An internal pull-down on this pin will keep the
device in the unprotected state if left floating. If tied to
V

SS or left floating, normal memory operation is

enabled (read/write the entire memory 0000-7FFF).
If tied to V

operations are not affected.

CC, WRITE operations are inhibited. Read

3.0 FUNCTIONAL DESCRIPTION

The 24xx256 supports a bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data as a receiver. The bus must be con­trolled by a master device which generates the serial
clock (SCL), controls the bus access, and generates
the START and STOP conditions while the 24xx256
works as a slave. Both master and slav e can operate as
a transmitter or receiver, but the master device deter­mines which mode is activated.

The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one bit of data per
clock pulse.

Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device.

4.5 Acknowledge

Each receiving device, when addressed, is obliged to
generate an acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this acknowledge
bit.

Note: The 24xx256 does not generate any

acknowledge bits if an internal program­ming cycle is in progress.

A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LO W during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. Dur­ing reads, a master must signal an end of data to the
slave by NO T generating an ackno wledge bit on the last
byte that has been clocked out of the sla ve. In this case ,
the slave (24xx256) will leave the data line HIGH to
enable the master to generate the STOP condition.

DS21203C-page 4  1998 Microchip Technology Inc.

24AA256/24LC256

FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A) (B) (D) (D) (C) (A)

SCL

SDA

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

FIGURE 4-2: ACKNOWLEDGE TIMING

SCL

SDA

Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.

Data from transmitter

DATA

ALLOWED

TO CHANGE

Acknowledge

STOP

CONDITION

Bit

987654321 123

Data from transmitter

Receiver must release the SDA line at this point
so the Transmitter can continue sending data.

 1998 Microchip Technology Inc. DS21203C-page 5

24AA256/24LC256

5.0 DEVICE ADDRESSING

A control byte is the first byte received following the
start condition from the master device (Figure 5-1). The
control byte consists of a 4-bit control code; for the
24xx256 this is set as 1010 binary for read and write
operations. The next three bits of the control byte are
the chip select bits (A2, A1, A0). The chip select bits
allow the use of up to eight 24xx256 devices on the
same bus and are used to select which device is
accessed. The chip select bits in the control byte must
correspond to the logic levels on the corresponding A2,
A1, and A0 pins for the device to respond. These bits
are in effect the three most significant bits of the word
address.

The last bit of the control byte defines the operation to
be performed. When set to a one a read operation is
selected, and when set to a zero a write operation is
selected. The next two bytes received define the
address of the first data byte (Figure 5-2). Because
only A14…A0 are used, the upper address bit is a don’t
care bit. The upper address bits are transf erred first, fol­lowed by the less significant bits.

Following the start condition, the 24xx256 monitors the
SDA bus checking the control byte being transmitted.
Upon receiving a 1010 code and appropriate device
select bits, the slave device outputs an acknowledge
signal on the SDA line. Depending on the state of
the R/W
operation.

bit, the 24xx256 will select a read or write

FIGURE 5-1: CONTROL BYTE FORMAT

Read/Wr

Control Code

1 0 1 0 A2 A1 A0SACKR/W

Slave Address

Start Bit

ite Bit

Chip Select

Bits

Acknowledge Bit

5.1 Contiguous Addressing Across

Multiple Devices

The chip select bits A2, A1, A0 can be used to expand
the contiguous address space for up to 2 Mbit
by adding up to eight 24xx256's on the same bus. In
this case, software can use A0 of the control b
address bit A15; A1, as address bit A16; and A2, as
address bit A17. It is not possible to read or write
across device boundaries.

yte as

FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS

CONTROL BYTE ADDRESS HIGH BYTE ADDRESS LOW BYTE

1010

CONTROL

CODE

A2A1A

CHIP

SELECT

BITS

R/W X

0

A

14

A

A

13

X = Don’t Care Bit

12

A11A10A

A

9

8

A

••••••

7

A

0

DS21203C-page 6  1998 Microchip Technology Inc.

24AA256/24LC256

6.0 WRITE OPERATIONS

6.1 Byte Write

Following the start condition from the master, the
control code (four bits), the chip select (three bits), and
the R/W
bus by the master transmitter. This indicates to the
addressed slave receiver that the address high b yte will
follow after it has generated an ac kno wledge bit during
the ninth clock cycle. Therefore the next byte
transmitted by the master is the high-order byte of the
word address and will be written into the address
pointer of the 24xx256. The next byte is the least signif­icant address byte. After receiving another acknowl­edge signal from the 24xx256, the master device will
transmit the data word to be written into the addressed
memory location. The 24xx256 acknowledges again
and the master generates a stop condition. This ini­tiates the internal write cycle, and, during this time, the
24xx256 will not generate acknowledge signals
(Figure 6-1). If an attempt is made to write to the array
with the WP pin held high, the device will acknowledge
the command but no write cycle will occur, no data will
be written, and the device will immediately accept a
new command. After a byte write command, the inter­nal address counter will point to the address location
following the one that was just written.

bit (which is a logic low) are clocked onto the

6.2 Page Write

The write control byte, word address, and the first data
byte are transmitted to the 24xx256 in the same wa y as
in a byte write. But instead of generating a stop condi­tion, the master transmits up to 63 additional bytes,
which are temporarily stored in the on-chip page buffer
and will be written into memory after the master has
transmitted a stop condition. After receipt of each w ord,
the six lower address pointer bits are internally incre­mented by one. If the master should transmit more than
64 bytes prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received, an inter­nal write cycle will begin (Figure 6-2). If an attempt is
made to write to the array with the WP pin held high, the
device will acknowledge the command but no write
cycle will occur, no data will be written, and the device
will immediately accept a new command subject to
T

BUF.

6.3 Write Protection

The WP pin allows the user to write-protect the entire
array (0000-7FFF) when the pin is tied to V
V

SS or left floating, the write protection is disabled. The

WP pin is sampled at the STOP bit for e v ery write com­mand (Figure 1-1) Toggling the WP pin after the STOP
bit will have no eff ect on the execution of the write cycle.

CC. If tied to

FIGURE 6-1: BYTE WRITE

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

X = don’t care bit

S
T
A
R
T

S1010

FIGURE 6-2: PAGE WRITE

S

T
BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

X = don’t care bit

CONTROL

A

BYTE

R

T

S1010 0

A2A1A

CONTROL

0

A
C
K

BYTE

X

A
2

A1A

0

0

A
C
K

ADDRESS

HIGH BYTE

ADDRESS

HIGH BYTE

X

A
C
K

A
C
K

ADDRESS
LOW BYTE

ADDRESS
LOW BYTE

DATA BYTE 0

A
C
K

S

DATA

A
C
K

A
C
K

T
O
P

P

A
C
K

DATA BYTE 63

S
T
O
P

P

A
C
K

 1998 Microchip Technology Inc. DS21203C-page 7

24AA256/24LC256

7.0 ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (This feature can be used to maximize bus
throughput.) Once the stop condition for a write com­mand has been issued from the master, the device ini­tiates the internally timed write cycle. ACK polling can
be initiated immediately . This involv es the master send­ing a start condition, followed by the control byte for a
write command (R/W
the write cycle, then no ACK will be returned. If no A CK
is returned, then the start bit and control byte must be
resent. If the cycle is complete, then the device will
return the ACK, and the master can then proceed with
the next read or write command. See Figure 7-1 for
flow diagram.

= 0). If the de vice is still b usy with

FIGURE 7-1: ACKNOWLEDGE POLLING

FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

YES

Next

Operation

NO

DS21203C-page 8  1998 Microchip Technology Inc.

24AA256/24LC256

8.0 READ OPERATION

Read operations are initiated in the same way as write
operations with the exception that the R/W
control byte is set to one. There are three basic types of
read operations: current address read, random read,
and sequential read.

8.1 Current Address Read

The 24xx256 contains an address counter that
maintains the address of the last word accessed, inter­nally incremented by one. Therefore, if the previous
read access was to address n (n is any legal address),
the next current address read operation would access
data from address n + 1.

Upon receipt of the control byte with R/W
the 24xx256 issues an acknowledge and transmits the
8-bit data word. The master will not acknowledge the
transfer but does generate a stop condition and the
24xx256 discontinues transmission (Figure 8-1).

FIGURE 8-1: CURRENT ADDRESS READ

S

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

T

CONTROL

A
R
T

S

1100

BYTE

AAA
210

1

A
C
K

bit of the

bit set to one,

DATA

BYTE

N
O

A
C
K

S
T
O
P

P

8.2 Random Read

Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24xx256 as part of a write operation (R/W

bit set to 0).
After the word address is sent, the master generates a
start condition following the acknowledge. This
terminates the write operation, but not before the inter­nal address pointer is set. Then, the master issues the
control byte again but with the R/W

bit set to a one. The
24xx256 will then issue an acknowledge and transmit
the 8-bit data word. The master will not acknowledge
the transfer but does generate a stop condition which
causes the 24xx256 to discontinue transmission
(Figure 8-2). After a random read command, the
internal address counter will point to the address
location following the one that was just read.

8.3 Sequential Read

Sequential reads are initiated in the same way as a
random read except that after the 24xx256 transmits
the first data byte, the master issues an acknowledge
as opposed to the stop condition used in a random
read. This ac knowledge directs the 24xx256 to transmit
the next sequentially addressed 8-bit word (Figure 8-

3). Following the final byte transmitted to the master,
the master will NOT generate an acknowledge but will
generate a stop condition. T o pro vide sequential reads ,
the 24xx256 contains an internal address pointer which
is incremented by one at the completion of each
operation. This address pointer allows the entire
memory contents to be serially read during one
operation. The internal address pointer will automati­cally roll over from address 7FFF to address 0000 if the
master acknowledges the byte received from the array
address 7FFF.

FIGURE 8-2: RANDOM READ

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

X = Don’t Care Bit

S
T

CONTROL

A

BYTE

R
T

S1010

AAA
210

0

X

A
C
K

ADDRESS

HIGH BYTE

A
C
K

ADDRESS

LOW BYTE

S
T
A
R
T

S1010

A
C
K

CONTROL

BYTE

AAA
210

DATA

BYTE

1

A
C
K

S
T
O
P

P

N
O

A
C
K

FIGURE 8-3: SEQUENTIAL READ

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

DATA n DATA n + 1 DATA n + 2 DATA n + X

A
C
K

A
C
K

A
C
K

A
C
K

 1998 Microchip Technology Inc. DS21203C-page 9

S
T
O
P

P

N
O

A
C
K

24AA256/24LC256

NOTES:

DS21203C-page 10  1998 Microchip Technology Inc.

24AA256/24LC256

24xx256 PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

24xx256 — /P

Package:
Temperature I = -40°C to +85°C

Range: E = -40°C to -125°C

24AA256 256K bit 1.8V I

Device:

24AA256T 256K bit 1.8V I

24LC256 256K bit 2.5V I

24LC256T 256K bit 2.5V I

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom­mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office (see last page).

2. The Microchip Corporate Literature Center U.S. FAX: [phone].

3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

P = Plastic DIP (300 mil Body), 8-lead

SM = Plastic SOIC (208 mil Body, EIAJ standard), 8-lead

2

C Serial EEPROM

2

C Serial EEPROM (Tape and Reel)

2

C Serial EEPROM

2

C Serial EEPROM (Tape and Reel)

 1998 Microchip Technology Inc. DS21203C-page 11



M

W

AMERICAS

Corporate Office

Microchip T echnology Inc.
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: [phone] Fax: [phone]

Technical Support:
Web:

http://www.microchip.com

Atlanta

Microchip T echnology Inc.
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: [phone] Fax: [phone]

Boston

Microchip T echnology Inc.
5 Mount Royal Avenue
Marlborough, MA 01752
Tel: [phone] Fax: [phone]

Chicago

Microchip T echnology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: [phone] Fax: [phone]

Dallas

Microchip T echnology Inc.
14651 Dallas Parkway, Suite 816
Dallas, TX 75240-8809
Tel: [phone] Fax: [phone]

Dayton

Microchip T echnology Inc.
Two Prestige Place, Suite 150
Miamisburg, OH 45342
Tel: [phone] Fax: [phone]

Los Angeles

Microchip T echnology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: [phone] Fax: [phone]

New Y ork

Microchip T echnology Inc.
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Tel: [phone] Fax: [phone]

San Jose

Microchip T echnology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: [phone] Fax: [phone]

Toronto

Microchip T echnology Inc.
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: [phone] Fax: [phone]

602 786-7627

ORLDWIDE

ASIA/PACIFIC

Hong Kong

Microchip Asia Pacific
RM 3801B, To wer Two
Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: [phone] Fax: [phone]

India

Microchip T echnology Inc.
India Liaison Office
No. 6, Legacy, Convent Road
Bangalore 560 025, India
Tel: [phone] Fax: [phone]

Korea

Microchip T echnology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea
Tel: [phone] Fax: [phone]

Shanghai

Microchip T echnology
RM 406 Shanghai Golden Bridge Bldg.
2077 Yan’an Road West, Hong Qiao District
Shanghai, PRC 200335
Tel: [phone]
Fax: [phone]

Singapore

Microchip T echnology Taiwan
Singapore Branch
200 Middle Road
#07-02 Prime Centre
Singapore 188980
Tel: [phone] Fax: [phone]

Taiwan, R.O.C

Microchip T echnology Taiwan
10F-1C 207
Tung Hua North Road
T aipei, Taiwan, ROC
Tel: [phone] Fax: [phone]

ALES

S

AND

ERVICE

S

EUROPE

United Kingdom

Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh T riangle
Wokingham
Berkshire, England RG41 5TU
Tel: [phone] Fax: [phone]

France

Arizona Microchip Technology SARL
Zone Industrielle de la Bonde
2 Rue du Buisson aux Fraises
91300 Massy, France
Tel: [phone] Fax: [phone]

Germany

Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 Müchen, Germany
Tel: [phone] Fax: [phone]

Italy

Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: [phone] Fax: [phone]

JAP AN

Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa 222 Japan
Tel: [phone] Fax: [phone]

12/30/97

All rights reserved. © 1998, Microchip Technology Incorporated, USA. 1/98 Printed on recycled paper.

Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no
liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use
or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or
otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other
trademarks mentioned herein are the property of their respective companies.

DS21203C-page 12

1998 Microchip Technology Inc.