Microchip Technology Inc 24AA08T-I-SM, 24AA08T-I-SL, 24AA08T-SN, 24AA08T-SM, 24AA08T-SL Datasheet



1996 Microchip Technology Inc. DS21053E-page 1

FEATURES

• Single supply with operation down to 1.8V

• Low power CMOS technology

- 1 mA active current typical

- 10 µ A standby current typical at 5.5V

-3 µ A standby current typical at 1.8V

• Organized as 2 or 4 blocks of 256 bytes
(2 x 256 x 8) or (4 x 256 x 8)

• 2-wire serial interface bus, I

2

C 

compatible

• Schmitt trigger, filtered inputs for noise suppres­sion

• Output slope control to eliminate ground bounce

• 100 kHz (1.8V) and 400 kHz (5V) compatibility

• Self-timed write cycle (including auto-erase)

• Page-write buffer for up to 16 bytes

• 2 ms typical write cycle time for page-write

• Hardware write protect for entire memory

• Can be operated as a serial ROM

• ESD protection > 4,000V

• 1,000,000 ERASE/WRITE cycles guaranteed

• Data retention > 200 years

• 8-pin DIP, 8-lead or 14-lead SOIC packages

• Available for extended temperature ranges

DESCRIPTION

The Microchip T echnology Inc. 24AA04/08 is a 4K bit or
8K bit Electrically Erasable PROM. The device is orga­nized as two or four blocks of 256 x 8-bit memory with
a two wire serial interface. Low voltage design permits
operation down to 1.8 volts with standby and active cur­rents of only 3 µ A and 1 mA respectively. The 24AA04/
08 also has a page-write capability for up to 16 bytes of
data. The 24AA04/08 is available in the standard 8-pin
DIP and both 8-lead and 14-lead surface mount SOIC
packages.

- Commercial (C): 0 ° C to +70 ° C

- Industrial (I): -40 ° C to +85 ° C

P ACKA GE TYPES

BLOCK DIAGRAM

NC

SS

CC

A0
A1

NC

A2

NC

V

1
2
3
4

5
6
7

14
13

12

NC
SCL

SDA
NC

9
8

11

10

WP

V

NC

24AA04/08

14-Lead
SOIC

24AA04/08

A0
A1

A2

V

SS

1
2

3

4

8
7

6

5

VCC
WP

SCL

SDA

24AA04/08

A0
A1

A2

V

SS

1
2

3

4

8
7

6

5

V

CC

WP

SCL

SDA

DIP

8-lead
SOIC

HV GENERATOR

EEPROM

ARRAY

PAGE LATCHES

YDEC

XDEC

SENSE AMP

R/W CONTROL

MEMORY

CONTROL

LOGIC

I/O

CONTROL

LOGIC

WP

SDA SCL

V

CC

VSS

24AA04/08

4K/8K 1.8V I

2

C



Serial EEPROMs

I

2

C is a trademark of Philips Corporation.

24AA04/08

DS21053E-page 2



1996 Microchip Technology Inc.

1.0 ELECTRICAL
CHARACTERISTICS

1.1 Maxim

um Ratings*

V

CC

...................................................................................7.0V

All inputs and outputs w.r.t. V

SS

.............. -0.6V to VCC +1.0V

Storage temperature.....................................-65˚C to +150˚C

Ambient temp. with power applied................-65˚C to +125˚C

Soldering temperature of leads (10 seconds).............+300˚C

ESD protection on all pins ..................................................≥ 4 kV

*Notice: Stresses above those listed under “Maximum ratings”

may cause permanent damage to the device. This is a stress rat­ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

TABLE 1-1: PIN FUNCTION TABLE

Name Function

V

SS

Ground

SDA Serial Address/Data I/O

SCL Serial Clock

WP Write Protect Input
Vcc +1.8V to 5.5V Power Supply

A0, A1, A2 No Internal Connection

TABLE 1-2: DC CHARACTERISTICS

FIGURE 1-1: BUS TIMING START/STOP

V

CC

= +1.8V to +5.5V
Commercial (C): Tamb = 0˚C to +70˚C
Industrial (I): Tamb = -40 ° C to +85 ° C

Parameter Sym Min Typ Max Units Conditions

WP, SCL and SDA pins:

High level input voltage V

IH

.7 Vcc — — V

Low Level input voltage V

IL

— — .3 V

CC

V

Hysteresis of Schmitt trigger
inputs

V

HYS

.05 V

CC

— — V (Note)

Low level output voltage V

OL

— — .40 V I

OL

= 3.0 mA, V

CC

= 1.8V

Input leakage current I

LI

-10 — 10

µ

AV

IN

= .1V to V

CC

Output leakage current I

LO

-10 — 10

µ

AV

OUT

= .1V to V

CC

Pin capacitance
(all inputs/outputs)

C

IN

, C

OUT

— — 10 pF V

CC

= 5.0V (Note 1)

Tamb = 25˚C, F

CLK

= 1 MHz

Operating current I

CC

W

RITE

I

CC

R

EAD

—
—
—
—

—

0.5
—

0.05

3

—

1

—

mA
mA
mA
mA

V

CC

= 5.5V, SCL = 400 kHz

V

CC

= 1.8V, SCL = 100 kHz

V

CC

= 5.5V, SCL = 400 kHz

V

CC

= 1.8V, SCL = 100 kHz

Standby current I

CCS

—
—
—3

100

30
—

µ A µ A µ

A

V

CC

= 5.5V, SDA=SCL=V

CC

V

CC

= 3.0V, SDA=SCL=V

CC

V

CC

= 1.8V, SDA=SCL=V

CC

Note:This parameter is periodically sampled and not 100% tested.

TSU:STA

THD:STA

VHYS

TSU:STO

START STOP

SCL

SDA



1996 Microchip Technology Inc. DS21053E-page 3

24AA04/08

TABLE 1-3: AC CHARACTERISTICS

FIGURE 1-2: BUS TIMING DATA

Parameter Symbol

Standard Mode

V

CC

= 4.5-5.5V

Fast Mode

Units Remarks

Min Max Min Max

Clock frequency Fclk — 100 — 400 kHz
Clock high time Thigh 4000 — 600 — ns
Clock low time Tlow 4700 — 1300 — ns
SDA and SCL rise time Tr — 1000 — 300 ns (Note 1)
SDA and SCL fall time Tf — 300 — 300 ns (Note 1)
START condition hold time T

HD

:

STA

4000 — 600 — ns After this period the first clock

pulse is generated

START condition setup
time

T

SU

:

STA

4700 — 600 — ns Only relevant for repeated

START condition

Data input hold time T

HD

:

DAT

0— 0 —ns

Data input setup time T

SU

:

DAT

250 — 100 — ns

STOP condition setup time T

SU

:

STO

4000 — 600 — ns

Output valid from clock T

AA

— 3500 — 900 ns (Note 2)

Bus free time T

BUF

4700 — 1300 — ns Time the bus must be free before

a new transmission can start

Output fall time from V

IH

min to V

IL

max

T

OF

— 250 20 + 0.1

C

B

250 ns (Note 1), C

B

≤

100 pF

Input filter spike suppres­sion (SDA and SCL pins)

T

SP

— 50 — 50 ns (Note 3)

Write cycle time T

WR

— 10 — 10 ms Byte or Page mode

Endurance 24AA04

24AA08

— 10M

1M

— 10M

1M

— cycles 25 ° C, Vcc = 5.0V, Block Mode

(Note 4)

Note 1: Not 100% tested. C

B

= total capacitance of one bus line in pF.

2: As a transmitter , the device must provide an internal minimum delay time to bridge the undefined region (min-

imum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined T

SP

and V

HYS

specifications are due to new Schmitt trigger inputs which provide improved

noise and spike suppression. This eliminates the need for a T

I

specification for standard operation.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-

cation, please consult the Total Endurance Model which can be obtained on our BBS or website.

TSU:STA

TF

TLOW

THIGH

TR

THD:DAT TSU:DAT

TSU:STO

THD:STA

TBUF

TAA

TAA

TSP

THD:STA

SCL

SCL

IN

SCL
OUT

24AA04/08

DS21053E-page 4



1996 Microchip Technology Inc.

2.0 FUNCTIONAL DESCRIPTION

The 24AA04/08 supports a Bi-directional 2-wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24AA04/08
works as slave. Both master and slave can operate as
transmitter or receiver, but the master device deter­mines which mode is activated.

3.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus is
not busy.

• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1 Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2 Star

t Data Transfer (B)

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a STAR T condition. All
commands must be preceded by a START condition.

3.3 Stop Data

Transfer (C)

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

3.4 Data

Valid (D)

The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.

Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last six­teen will be stored when doing a write operation. When
an overwrite does occur it will replace data in a first in
first out fashion.

3.5 Ac

knowledge

Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.

The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.

Note: The 24AA04/08 does not generate any

acknowledge bits if an internal program­ming cycle is in progress.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A) (B) (D) (D) (A)(C)

SCL

SDA

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION