Microchip Technology Inc 24LC00-I-P, 24LC00-ST, 24LC00-SN, 24LC00-P, 24LC00-OT Datasheet



M

128 Bit I

24AA00/24LC00/24C00

2

C™ Bus Serial EEPROM

DEVICE SELECTION TABLE

Device V

24AA00 1.8 - 6.0 C,I
24LC00 2.5 - 6.0 C,I

24C00 4.5 - 5.5 C,I,E

CC

Range Temp Range

FEATURES

• Low power CMOS technology

- 500 µ A typical active current

- 500 nA typical standby current

• Organized as 16 bytes x 8 bits

• 2-wire serial interface bus, I

• 100kHz (1.8V) and 400kHz (5V) compatibility

• Self-timed write cycle (including auto-erase)

• 4 ms maximum byte write cycle time

• 1,000,000 erase/write cycles guaranteed

• ESD protection > 4kV

• Data retention > 200 years

• 8L DIP, SOIC, TSSOP and 5L SOT-23 packages

• Temperature ranges available:

- Commercial (C): 0 ° C to +70 ° C

- Industrial (I): -40 ° C to +85 ° C

- Automotive (E) -40 ° C to +125 ° C

2

C™ compatible

PACKA GE TYPES

8-PIN PDIP/SOIC

SCL

VSS

SDA

1
2

3
4

1
2
3
4

1

2

3

NC
NC

NC

VSS

8-PIN TSSOP

NC
NC
NC

Vss

5-PIN SOT-23

24xx00

24xx00

5

24xx00

4

8
7

6
5

8
7
6
5

VCC

NC

VCC
NC

SCL
SDA

Vcc
NC
SCL
SDA

DESCRIPTION

The Microchip Technology Inc. 24AA00/24LC00/24C00
(24xx00*) is a 128-bit Electrically Erasable PROM
memory organized as 16 x 8 with a 2-wire serial inter­face. Low voltage design permits operation down to 1.8
volts for the 24xx00 version, and every version main­tains a maximum standby current of only 1 µ A and typ­ical active current of only 500 µ A. This device was
designed where a small amount of EEPROM is needed
for the storage of calibration values, ID numbers or
manufacturing information, etc. The 24xx00 is available
in 8ld PDIP, 8ld SOIC (150 mil), 8ld TSSOP and the 5ld
SOT-23 packages.

*24xx00 is used in this document as a generic part number for the 24AA00/24LC00/24C00 devices.

2

I

C is a trademark of Philips Corporation.

1996 Microchip Technology Inc.

Preliminary

BLOCK DIAGRAM

I/O

CONTROL

LOGIC

SCL

SDA

VCC

VSS

MEMORY

CONTROL

LOGIC

XDEC

HV GENERATOR

EEPROM

ARRAY

YDEC

SENSE AMP

R/W CONTROL

DS21178A-page 1

24xx00



µ

µ

1.0 ELECTRICAL
CHARACTERISTICS

1.1 Maxim

Vcc...................................................................................7.0V

All inputs and outputs w.r.t. Vss.................-0.6V to Vcc +1.0V

Storage temperature.....................................-65˚C to +150˚C

Ambient temp. with power applied................. -65˚C to +125˚C

Soldering temperature of leads (10 seconds).............+300˚C

ESD protection on all pins................................................4 kV

*Notice: Stresses above those listed under “Maximum ratings” may

cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended peri­ods may affect device reliability.

um Ratings*

TABLE 1-1 PIN FUNCTION TABLE

Name Function

V
SDA
SCL

V

NC

TABLE 1-2 DC CHARACTERISTICS

All Parameters apply across the recom­mended operating ranges unless other­wise noted

Parameter Symbol Min. Max. Units Conditions

SCL and SDA pins:

High level input voltage V
Low level input voltage V
Hysteresis of Schmitt trigger inputs V
Low level output voltage V

Input leakage current I
Output leakage current I
Pin capacitance (all inputs/outputs) C

Operating current I

Standby current I
Note: This parameter is periodically sampled and not 100% tested.

Commercial (C): Tamb = 0˚C to +70˚C, Vcc = 1.8V to 6.0V
Industrial (I): Tamb = -40˚C to +85˚C, Vcc = 1.8V to 6.0V
Automotive (E) Tamb = -40˚C to +125˚C, Vcc = 4.5V to 5.5V

IH
IL

HYS

OL
LI

LO

,

IN

C

OUT

Write — 2 mA V

CC

CC

I

Read — 1 mA V

CCS

CC

.7 V

CC

.05 V

-10 10

-10 10
—10pFV

—1

SS

Ground
Serial Data
Serial Clock

CC

+1.8V to 6.0V (24AA00)
+2.5V to 6.0V (24LC00)
+4.5V to 5.5V (24C00)
No Internal Connection

V (Note)

.3 V

CC

V (Note)

— V (Note)

.40 V I

AV
AV

µ

AV

= 3.0 mA, V

OL

= 0.1V to 5.5V

IN
OUT

= 0.1V to 5.5V

= 5.0V (Note)

CC

CC

= Vcc

Tamb = 25˚C, f = 1 MHz

= 5.5V, SCL = 400 kHz

CC
CC

= 5.5V, SCL = 400 kHz
= 5.5V, SDA = SCL = V

CC

MIN

CC

FIGURE 1-1: BUS TIMING DATA

TF

SCL

SDA
IN

SDA
OUT

DS21178A-page 2

TSU:STA

TSP

TLOW

THD:STA

THIGH

THD:DAT TSU:DAT TSU:STO

TAA

TR

Preliminary

TBUF

1996 Microchip Technology Inc.

TABLE 1-3 AC CHARACTERISTICS



24xx00

All Parameters apply across all
recommended operating ranges
unless otherwise noted

Commercial (C): Tamb = 0˚C to +70˚C, Vcc = 1.8V to 6.0V
Industrial (I): Tamb = -40˚C to +85˚C, Vcc = 1.8V to 6.0V
Automotive (E): Tamb = -40˚C to +125˚C, Vcc = 4.5V to 5.5V

Parameter Symbol Min Max Units Conditions

Clock frequency F

Clock high time T

Clock low time T

SDA and SCL rise time

CLK

HIGH

LOW

T

R

(Note 1)

SDA and SCL fall time T
START condition hold time T

HD

F

:

STA

START condition setup time TSU:STA 4700

—
—
—

4000
4000

600

4700
4700
1300

—
—
—

100
100
400

—
—
—

—
—
—

1000
1000

300

kHz 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

1.8V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 6.0V

ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

1.8V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 6.0V

ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

1.8V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 6.0V

ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

1.8V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 6.0V

— 300 ns (Note 1)

4000
4000

600

4700

600

—
—
—

—
—
—

ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

1.8V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 6.0V

ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

1.8V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 6.0V
Data input hold time THD:DAT 0 — ns (Note 2)
Data input setup time T

SU:DAT 250

250
100

STOP condition setup time TSU:STO 4000

4000

600

Output valid from clock
(Note 2)

TAA —

—
—

Bus free time: Time the b us m ust
be free before a new transmission
can start

Output fall time from VIH
minimum to VIL maximum

Input filter spike suppression

TBUF 4700

4700
1300

OF 20+0.1

T

CB

SP — 50 ns (Notes 1, 3)

T

—
—
—

—
—
—

3500
3500

900

—
—
—

ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

1.8V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 6.0V

ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

1.8V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 6.0V

ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

1.8V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 6.0V

ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

1.8V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 6.0V

250 ns (Note 1), CB ≤ 100 pF

(SDA and SCL pins)
Write cycle time T
Endurance 1M — cycles 25°C, V

WC —4ms

CC = 5.0V, Block Mode (Note 4)

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined T

SP and VHYS specifications are due to new Schmitt trigger inputs which provide improved

noise spike suppression. This eliminates the need for a TI specification for standard operation.

4: This parameter is not tested b ut guaranteed by characterization. For endurance estimates in a specific appli-

cation, please consult the Total Endurance Model which can be obtained on Microchip’s BBS or website.

1996 Microchip Technology Inc.

Preliminary

DS21178A-page 3

24xx00

2.0 PIN DESCRIPTIONS

2.1 SDA Serial Data

This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA b us requires a pull-up
resistor to V
kHz).

For normal data transfer SD A is allow ed to change only
during SCL low. Changes during SCL high are reserved
for indicating the START and STOP conditions.

CC (typical 10kΩ for 100 kHz, 1kΩ for 400

2.2 SCL Serial Clock

This input is used to synchronize the data transfer from
and to the device.

2.3 Noise Protection

The SCL and SDA inputs hav e Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.

3.0 FUNCTIONAL DESCRIPTION

The 24xx00 supports a bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data as a receiver. The bus has to be con­trolled by a master device which generates the serial
clock (SCL), controls the bus access, and generates
the START and STOP conditions, while the 24xx00
works as slave. Both master and slave can operate as
transmitter or receiver, but the master device deter­mines which mode is activated.

4.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the b us is
not busy.

• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (Figure 4-1).

0.1 Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

4.3 Data Valid (D)

The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one bit of data per
clock pulse.

Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited.

4.4 Acknowledge

Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.

Note: The 24xx00 does not generate any

acknowledge bits if an internal program­ming cycle is in progress.

The device that acknowledges has to pull down the
SDA line during the acknowledge cloc k pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the sla ve. In this case,
the slave must leave the data line HIGH to enable the
master to generate the STOP condition (Figure 4-2).

4.1 Bus not Busy (A)

Both data and clock lines remain HIGH.

4.2 Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.

DS21178A-page 4 Preliminary  1996 Microchip Technology Inc.

FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

24xx00

SCL

SDA

(A)

START

CONDITION

(C)

ADDRESS OR

ACKNOWLEDGE

VALID

(B)

FIGURE 4-2: ACKNOWLEDGE TIMING

SCL

SDA

Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.

Data from transmitter

5.0 DEVICE ADDRESSING

After generating a START condition, the bus master
transmits a control byte consisting of a slave address
and a Read/Wr
tion is to be performed. The slave address for the
24xx00 consists of a 4-bit device code (1010) followed
by three don't care bits.

The last bit of the control byte determines the operation
to be performed. When set to a one a read operation is
selected, and when set to a zero a write operation is
selected. (Figure 5-1). The 24xx00 monitors the bus for
its corresponding slave address all the time. It gener­ates an acknowledge bit if the slave address was true
and it is not in a programming mode.

ite bit that indicates what type of opera-

(D)

DATA

ALLOWED

TO CHANGE

Acknowledge

Bit

987654321 123

Data from transmitter

Receiver must release the SDA line at this point
so the Transmitter can continue sending data.

FIGURE 5-1: CONTROL BYTE FORMAT

Read/Wr

Device Select

Bits

1010XXXSACKR/W

Slave Address

Start Bit

Don’t Care

Bits

Acknowledge Bit

ite Bit

STOP

CONDITION

(A)(C)

 1996 Microchip Technology Inc. Preliminary DS21178A-page 5

24xx00

6.0 WRITE OPERATIONS

6.1 Byte Write

Following the start signal from the master, the device
code (4 bits), the don't care bits (3 bits), and the R/W
(which is a logic low) are placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a b yte with a word address will f ollow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore, the next byte transmitted
by the master is the word address and will be written
into the address pointer of the 24xx00. Only the lower
four address bits are used by the de vice, and the upper
four bits are don’t cares. The 24xx00 will acknowledge
the address byte and the master device will then trans­mit the data word to be written into the addressed mem­ory location. The 24xx00 acknowledges again and the
master generates a stop condition. This initiates the
internal write cycle, and during this time the 24xx00 will
not generate acknowledge signals (Figure 7-2). After a
byte write command, the internal address counter will
not be incremented and will point to the same address
location that was just written. If a stop bit is transmitted
to the device at any point in the write command
sequence before the entire sequence is complete, then
the command will abort and no data will be written. If
more than 8 data bits are transmitted before the stop bit
is sent, then the device will clear the previously loaded
byte and begin loading the data buffer again. If more
than one data byte is transmitted to the device and a
stop bit is sent before a full eight data bits have been
transmitted, then the write command will abort and no
data will be written. The 24xx00 employs a V
old detector circuit which disables the internal erase/
write logic if the V

CC is below 1.5V (24AA00 and

24LC00) or 3.8V (24C00) at nominal conditions.

bit

CC thresh-

7.0 ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a wr ite com­mand has been issued from the master, the device ini­tiates the internally timed write cycle. ACK polling can
be initiated immediately . This inv olv es the master send­ing a start condition followed by the control byte for a
write command (R/W
the write cycle, then no ACK will be returned. If no A CK
is returned, then the start bit and control byte must be
re-sent. If the cycle is complete, then the device will
return the ACK and the master can then proceed with
the next read or write command. See Figure 7-1 for flow
diagram.

FIGURE 7-1: ACKNOWLEDGE POLLING

= 0). If the de vice is still b usy with

FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

NO

(ACK = 0)?

YES

Next

Operation

FIGURE 7-2: BYTE WRITE

S

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

X = Don’t Care Bit

DS21178A-page 6 Preliminary  1996 Microchip Technology Inc.

T
A
R
T

S

10 X10 XXX

CONTROL

BYTE

0

A
C
K

WORD

ADDRESS

XXX

DATA

A
C
K

S
T
O
P

P

A
C
K

24xx00

8.0 READ OPERATIONS

Read operations are initiated in the same way as write
operations with the exception that the R/W
slave address is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.

8.1 Current Address Read

The 24xx00 contains an address counter that maintains
the address of the last word accessed, internally incre­mented by one. Therefore, if the previous read access
was to address n, the next current address read opera­tion would access data from address n + 1. Upon
receipt of the slave address with the R/W
the device issues an acknowledge and transmits the
eight bit data word. The master will not acknowledge
the transfer but does generate a stop condition and the
device discontinues transmission (Figure 8-1).

8.2 Random Read

Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the

bit of the

bit set to one,

device as part of a write operation. After the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the R/W

bit set to a one. The 24xx00 will then issue
an acknowledge and transmits the eight bit data word.
The master will not acknowledge the transfer but does
generate a stop condition and the device discontinues
transmission (Figure 8-2). After this command, the
internal address counter will point to the address loca­tion following the one that was just read.

8.3 Sequential Read

Sequential reads are initiated in the same way as a ran­dom read except that after the device transmits the first
data byte, the master issues an acknowledge as
opposed to a stop condition in a random read. This
directs the device to transmit the next sequentially
addressed 8-bit word (Figure 8-3).

To provide sequential reads the 24xx00 contains an
internal address pointer which is incremented by one at
the completion of each read operation. This address
pointer allows the entire memory contents to be serially
read during one operation.

FIGURE 8-1: CURRENT ADDRESS READ

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

X = Don’t Care Bit

FIGURE 8-2: RANDOM READ

S

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

X = Don’t Care Bit

T

CONTROL

A

BYTE

R
T

S1 100XXX0

ADDRESS (n)

XXXX

A
C
K

FIGURE 8-3: SEQUENTIAL READ

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

DATA n DATA n + 1 DATA n + 2 DATA n + X

A
C
K

A
C
K

S
T

CONTROL

A

BYTE

R
T

S

1100XXX1

WORD

A
C
K

A
C

DATA

K

S
T

CONTROL

A

BYTE

R
T

S1 100XXX1

A
C
K

S
T
O
P

P

N
O

A
C
K

S
T
O
P

P

A
C

DATA (n)

K

N
O

A
C
K

S
T
O
P

P

A
C
K

N
O

A
C
K

 1996 Microchip Technology Inc. Preliminary DS21178A-page 7

24xx00

NOTES:

DS21178A-page 8 Preliminary  1996 Microchip Technology Inc.

NOTES:

24xx00

 1996 Microchip Technology Inc. Preliminary DS21178A-page 9

24xx00

NOTES:

DS21178A-page 10 Preliminary  1996 Microchip Technology Inc.

24xx00

24XX00 PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

24xx00 — /P

Package: P = Plastic DIP (300 mil Body), 8-lead

Temperature Blank = 0˚C to +70˚C
Range: I = –40˚C to +85˚C

Device: 24AA00 128 bit 1.8V I

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom­mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office (see last page)

2. The Microchip Corporate Literature Center U.S. FAX: [phone]

3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

Development T ools

For the latest version inf ormation and upgrade kits for Microchip De velopment Tools , please call 1-800-755-2345 or 1-602-786-7302.
The latest version of Development Tools software can be downloaded from either our Bulletin Board or Worldwide Web Site. (Infor­mation on how to connect to our BBS or WWW site can be found in the On-Line Support section of this data sheet.)

SN = Plastic SOIC (150 mil Body)

ST = TSSOP, 8-lead

OT = SOT-23, 5 lead

E = –40˚C to +125˚C

24AA00T 128 bit 1.8V K I

24LC00 128 bit 2.5V I

24LC00T 128 bit 2.5V K I

24C00 128 bit 5.0V I

24C00T 128 bit 5.0V K I

2

C Serial EEPROM

2

C Serial EEPROM (Tape and Reel)

2

C Serial EEPROM

2

C Serial EEPROM (Tape and Reel)

2

C Serial EEPROM

2

C Serial EEPROM (Tape and Reel)

 1996 Microchip Technology Inc. Preliminary DS21178A-page 11



Worldwide Sales & Service

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Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan Italy
Tel: [phone] Fax: [phone]

JAPAN

Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shin Yokohama
Kohoku-Ku, Yokohama
Kanagawa 222 Japan
Tel: [phone] Fax: [phone]

12/6/96

All rights reserved. © 1996, Microchip Technology Incorporated, USA. 12/96

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Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No repre­sentation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement
of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not autho­rized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and
name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.

DS21178A-page 12

Preliminary

1996 Microchip Technology Inc.