Microchip Technology WINC3400 User Manual

ATWINC3400-MR210CA
IEEE 802.11 b/g/n Network Controller Module with
Integrated Bluetooth Low Energy 4.0

Introduction

The ATWINC3400-MR210CA is an IEEE 802.11 b/g/n RF/Baseband/Medium Access Control (MAC) network controller module with Bluetooth Low Energy technology that is compliant with Bluetooth version
4.0. This module is optimized for low power and high performance mobile applications. This module features small form factor when integrating Power Amplifier (PA), Low-Noise Amplifier (LNA), Transmit/ Receive (T/R) switch (for Wi-Fi and Bluetooth), Power Management Unit (PMU), and Chip Antenna. The ATWINC3400-MR210CA module requires a 32.768 kHz clock for Sleep operation.
The ATWINC3400-MR210CA module utilizes highly optimized IEEE 802.11 Bluetooth coexistence protocols, and provides Serial Peripheral Interface (SPI) to interface with the host controller.

Features

Wi-Fi features:
IEEE 802.11 b/g/n RF/PHY/MAC
IEEE 802.11 b/g/n (1x1) with single spatial stream, up to 72 Mbps PHY rate in 2.4 GHz ISM band
Integrated chip antenna
Superior sensitivity and range via advanced PHY signal processing
Advanced equalization and channel estimation
Advanced carrier and timing synchronization
Supports Soft-AP
Supports IEEE 802.11 WEP, WPA, and WPA2
Superior MAC throughput through hardware accelerated two-level A-MSDU/A-MPDU frame aggregation and block acknowledgment
On-chip memory management engine to reduce the host load
Operating temperature range from -40°C to +85°C
Wi-Fi Alliance® certified for connectivity and optimizations
ID: WFA62065
Integrated on-chip microcontroller
SPI host interface
Integrated Flash memory for Wi-Fi and Bluetooth system software
Low leakage on-chip memory for state variables
Fast AP re-association (150 ms)
On-chip network stack to offload MCU
Integrated network IP slack to minimize the host CPU requirements
Network features: Firmware version 1:2:x
© 2017 Microchip Technology Inc.
Draft Datasheet Preliminary
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TCP, UDP, DHCP, ARP, HTTP, SSL, DNS, and SNTP
Bluetooth features:
Bluetooth 4.0 (Bluetooth Low Energy) certifications
Controller QD ID - 77870
Host QD ID - 77451
Class 2 transmission
Adaptive Frequency Hopping (AFH)
Superior sensitivity and range
ATWINC3400-MR210CA
© 2017 Microchip Technology Inc.
Draft Datasheet Preliminary
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Table of Contents

Introduction......................................................................................................................1
Features.......................................................................................................................... 1
1. Ordering Information and Module Marking................................................................ 5
2. Block Diagram........................................................................................................... 6
3. Pinout and Package Information............................................................................... 7
3.1. Package Description.................................................................................................................. 10
4. Electrical Characteristics..........................................................................................11
4.1. Absolute Maximum Ratings........................................................................................................11
4.2. Recommended Operating Conditions........................................................................................ 11
4.3. DC Characteristics..................................................................................................................... 12
4.4. IEEE 802.11 b/g/n Radio Performance...................................................................................... 12
4.5. Bluetooth Radio Performance.................................................................................................... 14
4.6. Timing Characteristics................................................................................................................ 16
5. Power Management................................................................................................ 21
5.1. Device States............................................................................................................................. 21
5.2. Controlling Device States...........................................................................................................21
5.3. Power-Up/Down Sequence........................................................................................................22
5.4. Digital I/O Pin Behavior During Power-Up Sequences...............................................................23
6. Clocking...................................................................................................................24
6.1. Low-Power Clock....................................................................................................................... 24
7. CPU and Memory Subsystem................................................................................. 25
7.1. Processor................................................................................................................................... 25
7.2. Memory Subsystem....................................................................................................................25
7.3. Nonvolatile Memory....................................................................................................................25
8. WLAN Subsystem................................................................................................... 27
8.1. MAC........................................................................................................................................... 27
8.2. PHY............................................................................................................................................28
8.3. Radio..........................................................................................................................................28
9. Bluetooth Low Energy 4.0....................................................................................... 30
10. External Interfaces...................................................................................................31
10.1. Interfacing with the Host Microcontroller.................................................................................... 31
10.2. SPI Interface...............................................................................................................................32
10.3. UART Interface...........................................................................................................................34
11. Application Reference Design................................................................................. 35
© 2017 Microchip Technology Inc.
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ATWINC3400-MR210CA
11.1. Host Interface - SPI.................................................................................................................... 35
12. Module Outline Drawings........................................................................................ 37
13. Design Consideration.............................................................................................. 38
13.1. Module Placement and Routing Guidelines............................................................................... 38
13.2. Antenna Performance................................................................................................................ 39
14. Reflow Profile Information....................................................................................... 41
14.1. Storage Condition.......................................................................................................................41
14.2. Solder Paste...............................................................................................................................41
14.3. Stencil Design............................................................................................................................ 41
14.4. Baking Conditions...................................................................................................................... 41
14.5. Soldering and Reflow Condition................................................................................................. 41
15. Module Assembly Considerations........................................................................... 44
16. Regulatory Approval................................................................................................45
16.1. United States..............................................................................................................................45
16.2. Canada.......................................................................................................................................46
16.3. Europe........................................................................................................................................48
16.4. Other Regulatory Information..................................................................................................... 49
17. Reference Documentation.......................................................................................50
18. Document Revision History..................................................................................... 51
The Microchip Web Site................................................................................................ 52
Customer Change Notification Service..........................................................................52
Customer Support......................................................................................................... 52
Product Identification System........................................................................................53
Microchip Devices Code Protection Feature................................................................. 53
Legal Notice...................................................................................................................53
Trademarks................................................................................................................... 53
Quality Management System Certified by DNV.............................................................54
Worldwide Sales and Service........................................................................................55
© 2017 Microchip Technology Inc.
Draft Datasheet Preliminary
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1. Ordering Information and Module Marking

MR
2 1
0
C
Device name
MR: Industrial
2: OTA with shield
1: Reserved
1: Reserved
C: Chip antenna
Revision letter
Software version
ATWINC3400
A xxx
The following table provides the ordering details for the ATWINC3400-MR210CA module.
Table 1-1. Ordering Details
ATWINC3400-MR210CA
Model Number Ordering Code Package Description
ATWINC3400­MR210CA
Note: 
1. 'xxx' in the preceding table and following figure denotes the software version. Order code changes as per the software version. For example, current version of the software is v1.22, so its equivalent order code is ATWINC3400-MR210CA122.
2. CE certification pending.
The following figure illustrates the ATWINC3400-MR210CA module marking information.
Figure 1-1. Marking Information
ATWINC3400-MR210CAxxx 122.43 x
14.73 x 2.0 mm
Certified module with chip antenna
Regulatory Information
FCC, IC, CE
2
© 2017 Microchip Technology Inc.
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2. Block Diagram

ATWINC3400 IC
The following figure shows the block diagram of the ATWINC3400-MR210CA module.
Figure 2-1. ATWINC3400-MR210CA Module Block Diagram
ATWINC3400-MR210CA
© 2017 Microchip Technology Inc.
Draft Datasheet Preliminary
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3. Pinout and Package Information

ATWINC3400-MR210CA
MODULE
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
J31
J32
J33
J34
J35
J36
GND
I2C_SDA_M
I2C_SCL_M
IRQN
GPIO20
GPIO19
GPIO18
GPIO17
GND
GPIO7
SPI_MOSI
SPI_SSN
SPI_MISO
SPI_SCK
GPIO8
GND
RTC_CLK
CHIP_EN
VBAT
UART_RXD
UART_TXD
GPIO4
GPIO3
GND
VDDIO
BT_RXD
BT_TXD
RESETN
N/C
N/C
N/C
N/C
SPI_CFG
GND
I2C_SDA_S
I2C_SCL_S
This package contains an exposed paddle that must be connected to the system board ground. The ATWINC3400-MR210CA module pin assignment is shown in following figure.
Figure 3-1. ATWINC3400-MR210CA Module Pin Assignment
ATWINC3400-MR210CA
The following table provides the ATWINC3400-MR210CA module pin description.
© 2017 Microchip Technology Inc.
Draft Datasheet Preliminary
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ATWINC3400-MR210CA
Table 3-1. ATWINC3400-MR210CA Module Pin Description
Pin # Pin Name Pin Type Description
1 GND GND Ground pin.
2 SPI_CFG Digital Input Serial Peripheral Interface pin, which must be
died to VDDIO.
3 NC - No connection.
4 NC - No connection.
5 NC - No connection.
6 NC - No connection.
7 RESETN Digital Input Active-low hard Reset pin.
When the Reset pin is asserted low, the module is in the Reset state. When the Reset pin is asserted high, the module functions normally.
This pin must connect to a host output that is low by default on power-up. If the host output is tri-stated, add a 1 MOhm pull down resistor to ensure a low level at power-up.
8 BT_TXD Digital I/O,
Programmable pull up
9 BT_RXD Digital I/O,
Programmable pull up
10 I2C_SDA_S Digital I/O,
Programmable pull up
11 I2C_SCL_S Digital I/O,
Programmable pull up
12 VDDIO Power Digital I/O power supply.
13 GND GND Ground pin.
14 GPIO3 Digital I/O,
Programmable pull up
Bluetooth UART transmit data output pin.
Bluetooth UART receive data input pin.
I2C Slave data pin.
Used only for debug development purposes. It is recommended to add a test point for this pin.
I2C is the default configuration. <TBD>
I2C Slave clock pin.
Used only for debug development purposes. It is recommended to add a test point for this pin.
I2C is the default configuration. <TBD>
General Purpose Input/Output pin.
15 GPIO4 Digital I/O,
© 2017 Microchip Technology Inc.
Programmable pull up
Draft Datasheet Preliminary
General Purpose Input/Output pin.
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ATWINC3400-MR210CA
Pin # Pin Name Pin Type Description
16 UART_TXD Digital I/O,
Programmable pull up
17 UART_RXD Digital I/O,
Programmable pull up
18 VBAT Power Power supply pin for DC/DC converter and PA.
19 CHIP_EN Digital Input PMU enable pin.
20 RTC_CLK Digital I/O,
Programmable pull up
Wi-Fi UART TxD output pin.
Used only for debug development purposes. It is recommended to add a test point for this pin.
Wi-Fi UART RxD input pin.
Used only for debug development purposes. It is recommended to add a test point for this pin.
When the CHIP_EN pin is asserted high, the module is enbled. When the CHIP_EN pin is asserted low, the module is disabled or put into Power-Down mode.
Connect to a host output that is low by default at power-up. If the host output is tri-stated, add a 1 MOhm pull down resistor if necessary to ensure a low level at power-up.
RTC Clock input pin.
This pin must connect to a 32.768 kHz clock source.
21 GND GND Ground pin.
22 GPIO8 Digital I/O,
Programmable pull up
23 SPI_SCK Digital I/O,
Programmable pull up
24 SPI_MISO Digital I/O,
Programmable pull up
25 SPI_SSN Digital I/O,
Programmable pull up
26 SPI_MOSI Digital I/O,
Programmable pull up
27 GPIO7 Digital I/O,
Programmable pull up
28 GND GND Ground pin.
29 GPIO17 Digital I/O,
Programmable pull up
30 GPIO18 Digital I/O,
Programmable pull up
General Purpose Input/Output pin.
SPI clock pin.
SPI MISO (Master In Slave Out) pin.
Active-low SPI SSN (Slave Select) pin.
SPI MOSI (Master Out Slave In) pin.
General Purpose Input/Output pin.
General Purpose Input/Output pin.
General Purpose Input/Output pin.
© 2017 Microchip Technology Inc.
Draft Datasheet Preliminary
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ATWINC3400-MR210CA
Pin # Pin Name Pin Type Description
31 GPIO19 Digital I/O,
32 GPIO20 Digital I/O,
33 IRQN Digital output,
34 I2C_SCL_M Digital I/O,
35 I2C_SDA_M Digital I/O,
36 GND GND Ground pin.
37 PADDLE VSS Power Connect to system board ground.

3.1 Package Description

The following table provides the ATWINC3400-MR210CA module package dimensions.
Programmable pull up
Programmable pull up
Programmable pull up
Programmable pull up
Programmable pull up
General Purpose Input/Output pin.
General Purpose Input/Output pin.
ATWINC3400-MR210CA module host interrupt request output pin.
This pin must connect to a host interrupt pin.
I2C Master clock pin.
I2C Master data pin.
Table 3-2. ATWINC3400-MR210CA Module Package Information
Parameter Value Unit
Pad count 36 -
Package size 22.43 x 14.73 mm
Total thickness 2.09
Pad pitch 1.20
Pad width 0.81
Exposed pad size 4.4 x 4.4
© 2017 Microchip Technology Inc.
Draft Datasheet Preliminary
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4. Electrical Characteristics

This chapter provides an overview of the electrical characteristics of the ATWINC3400-MR210CA module.

4.1 Absolute Maximum Ratings

The following table provides the absolute maximum ratings for the ATWINC3400-MR210CA module.
Table 4-1. ATWINC3400-MR210CA Module Absolute Maximum Ratings
Symbol Parameter Min. Max. Unit
VDDIO I/O supply voltage -0.3 5.0 V
VBAT Battery supply voltage -0.3 5.0
ATWINC3400-MR210CA
V
IN
V
AIN
V
ESDHBM
Digital input voltage -0.3 VDDIO
Analog input voltage -0.3 1.5
Eelectrostatic dischage Human Body Model
-1000, -2000 (see notes below)
+1000, +2000 (see
notes below)
(HBM)
T
A
Storage temperature -65 150 ºC
- Junction temperature - 125
- RF input power - 23 dBm
1. VIN corresponds to all the digital pins.
2. For V
ESDHBM
, each pin is classified as Class 1, or Class 2, or both:
2.1. The Class 1 pins include all the pins (both analog and digital).
2.2. The Class 2 pins include all digital pins only.
2.3. V
ESDHBM
is ±1 kV for Class 1 pins. V
ESDHBM
is ± 2 kV for Class 2 pins.
Caution:  Stresses beyond those listed under “Absolute Maximum Ratings” cause permanent damage to the device. This is a stress rating only. The functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods affects the device reliability.

4.2 Recommended Operating Conditions

The following table provides the recommended operating conditions for the ATWINC3400-MR210CA module.
© 2017 Microchip Technology Inc.
Draft Datasheet Preliminary
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Table 4-2. ATWINC3400-MR210CA Module Recommended Operating Conditions
Symbol Parameter Min. Typ. Max. Units
VDDIO I/O supply voltage
VBAT Battery supply voltage
- Operating temperature -40 - 85
Note: 
1. I/O supply voltage is applied to the VDDIO pin.
2. Battery supply voltage is applied to the VBAT pin.
3. The ATWINC3400-MR210CA module is functional across this range of voltages; however, optimal RF performance is guaranteed for VBAT in the range ≥ 3.0V VBAT ≤ 4.2V.

4.3 DC Characteristics

The following table provides the DC characteristics for the ATWINC3400-MR210CA module digital pads.
Table 4-3. DC Electrical Characteristics
(1)
(2)(3)
ATWINC3400-MR210CA
2.7 3.3 3.6 V
3.0 3.6 4.2 V
º
C
Symbol Parameter Min Typ Max Unit
V
IL
Input Low
-0.30 - 0.60 V
Voltage
V
IH
Input High
VDDIO-0.60 - VDDIO+0.30
Voltage
V
OL
Output Low
- - 0.45
Voltage
V
OH
Output High
VDDIO-0.50 - -
Voltage
- Output Load
- - 20 pF
Capacitance
- Digital Input
- - 6 Load Capacitance

4.4 IEEE 802.11 b/g/n Radio Performance

4.4.1 Receiver Performance

The receiver performance is tested under following conditions:
VBAT = 3.3V
VDDIO = 3.3V
Temp = 25°C
Measured after RF matching network
The following table provides the receiver performance characteristics for the ATWINC3400-MR210CA module.
© 2017 Microchip Technology Inc.
Draft Datasheet Preliminary
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ATWINC3400-MR210CA
Table 4-4. IEEE 802.11 Receiver Performance Characteristics
Parameter Description Min. Typ. Max. Unit
Frequency - 2,412 - 2,472 MHz
Sensitivity 802.11b 1 Mbps DSSS - -95.0 - dBm
2 Mbps DSSS - -93.5 -
5.5 Mbps DSSS - -90.0 -
11 Mbps DSSS - -86.0 -
Sensitivity 802.11g 6 Mbps OFDM - -90.0 - dBm
9 Mbps OFDM - -88.5 -
12 Mbps OFDM - -86.0 -
18 Mbps OFDM - -84.5 -
24 Mbps OFDM - -82.0 -
36 Mbps OFDM - -78.5 -
48 Mbps OFDM - -74.5 -
Sensitivity 802.11n (BW=20 MHz, 800ns GI)
Maximum receive signal level
Adjacent channel rejection
54 Mbps OFDM - -73.0 -
MCS 0 - -89.0 - dBm
MCS 1 - -87.0 -
MCS 2 - -84.0 -
MCS 3 - -81.5 -
MCS 4 - -78.0 -
MCS 5 - -74.0 -
MCS 6 - -72.0 -
MCS 7 - -70.0 -
1-11 Mbps DSSS - 0 - dBm
6-54 Mbps OFDM - 0 -
MCS 0 - 7 (800ns GI) - 0 -
1 Mbps DSSS (30 MHz offset) - 50 - dB
11 Mbps DSSS (25 MHz offset) - 43 -
6 Mbps OFDM (25 MHz offset) - 40 -
54 Mbps OFDM (25 MHz offset) - 25 -
MCS 0 – 20 MHz BW (25 MHz offset)
MCS 7 – 20 MHz BW (25 MHz offset)
© 2017 Microchip Technology Inc.
- 40 -
- 20 -
Draft Datasheet Preliminary
DS00000000A-page 13

4.4.2 Transmitter Performance

The transmitter performance is tested under following conditions:
VBAT = 3.3V
VDDIO = 3.3V
Temp = 25°C
The following table provides the transmitter performance characteristics for the ATWINC3400-MR210CA module.
Table 4-5. IEEE 802.11 Transmitter Performance Characteristics
Parameter Description Minimum Typical Max. Unit
Frequency - 2,412 - 2,472 MHz
Output power 802.11b 1 Mbps - 16.7
Tx power accuracy - - ±1.5
ATWINC3400-MR210CA
802.11b 11 Mbps - 17.5
802.11g OFDM 6 Mbps - 18.3
802.11g OFDM 54 Mbps - 13.0
802.11n HT20 MCS 0 (800ns GI)
802.11n HT20 MCS 7 (800ns GI)
- 17.5
- 12.5
(1)
(1)
(1)
(1)
(1)
(1)
(2)
- dBm
-
-
-
-
-
- dB
Carrier suppression - - 30.0 - dBc
Harmonic output power (Radiated, Regulatory mode)
nd
2
rd
3
Note: 
1. Measured at IEEE 802.11 specification compliant EVM/Spectral mask.
2. Measured after RF matching network.
3. Operating temperature range is -40°C to +85°C. RF performance guaranteed at room temperature of 25°C with a 2-3dB change at boundary conditions.
4. With respect to Tx power, different (higher/lower) RF output power settings may be used for specific antennas and/or enclosures, in which case recertification may be required.
5. The availability of some specific channels and/or operational frequency bands are country dependent and should be programmed at the host product factory to match the intended destination. Regulatory bodies prohibit exposing the settings to the end user. This requirement needs to be taken care of via host implementation.

4.5 Bluetooth Radio Performance

4.5.1 Receiver Performance

The receiver performance is tested under following conditions:
VBAT = 3.3V
- - -41 dBm/MHz
- - -41
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ATWINC3400-MR210CA
VDDIO = 3.3V
Temp: 25°C
Measured after RF matching network.
The following table provides the Bluetooth receiver performance characteristics for the ATWINC3400­MR210CA module.
Table 4-6. Bluetooth Receiver Performance Characteristics
Parameter Description Min. Typ. Max. Unit
Frequency - 2,402 - 2,480 MHz
Sensitivity (ideal Tx) Bluetooth Low Energy (GFSK) - -92.5 - dBm
Maximum receive signal level
Interference performance (Bluetooth Low Energy)

4.5.2 Transmitter Performance

The transmitter performance is tested under following conditions:
VBAT = 3.3V
VDDIO = 3.3V
Temp: 25°C
Measured after RF matching network.
Bluetooth Low Energy (GFSK) - -3.5 -
Co-channel - 12 dB
adjacent + 1 MHz - 0 -
adjacent - 1 MHz - 3 -
adjacent + 2 MHz(image frequency)
adjacent - 2 MHz - -41 -
adjacent + 3 MHz (adjacent to image)
adjacent - 3 MHz - -35 -
adjacent + 4 MHz - -45 -
adjacent - 4 MHz - -30 -
adjacent +5 MHz - -34 -
adjacent - 5 MHz - -30 -
- -25 -
- -35 -
The following table provides the Bluetooth transmitter performance characteristics for the ATWINC3400­MR210CA module.
Table 4-7. Bluetooth Transmitter Performance Characteristics
Parameter Description Min. Typ. Max. Unit
Frequency - 2,402 - 2,480 MHz
Output power Bluetooth Low Energy (GFSK) - 3.2 3.7 dBm
© 2017 Microchip Technology Inc.
Draft Datasheet Preliminary
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ATWINC3400-MR210CA
Parameter Description Min. Typ. Max. Unit
In-band spurious emission (Bluetooth Low Energy)

4.6 Timing Characteristics

4.6.1 I2C Slave Timing

The I2C Slave timing diagram for the ATWINC3400-MR210CA module is shown in the following figure.
Figure 4-1. I2C Slave Timing Diagram
N+2 (Image frequency) - -33 -
N + 3 (Adjacent to image
- -32 -
frequency)
N-2 - -50 -
N-3 - -49 -
The following table provides the I2C Slave timing parameters for the ATWINC3400-MR210CA module.
Table 4-8. I2C Slave Timing Parameters
Parameter Symbol Min. Max. Units Remarks
SCL Clock Frequency f
SCL Low Pulse Width t
SCL High Pulse Width t
SCL, SDA Fall Time t
SCL, SDA Rise Time t
START Setup Time t
START Hold Time t
SDA Setup Time t
SDA Hold Time t
© 2017 Microchip Technology Inc.
SCL
WL
WH
HL
LH
SUSTA
HDSTA
SUDAT
HDDAT
Draft Datasheet Preliminary
0 400 kHz -
1.3 -
-
µs
0.6 - -
- 300
- 300
0.6 -
ns
This is dictated by external components
-
-
µs
0.6 - -
100 - ns -
0 - ns Slave and Master Default
DS00000000A-page 16
ATWINC3400-MR210CA
Parameter Symbol Min. Max. Units Remarks
STOP Setup Time t
Bus Free Time Between STOP and START
Glitch Pulse Reject t

4.6.2 SPI Slave Timing

The SPI Slave timing for the ATWINC3400-MR210CA module is provided in the following figures.
Figure 4-2. SPI Slave Clock Polarity and Clock Phase Timing
SUSTO
t
BUF
PR
40 - µs
Master Programming Option
0.6 -
µs
1.3 - -
0 50 ns -
-
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Draft Datasheet Preliminary
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