Microchip Technology TC850CLW, TC850ILW, TC850IJL, TC850CPL Datasheet

TC850

15-Bit, Fast Integrating CMOS A/D Converter

Features

• 15-bit Resolution Plus Sign Bit

• Up to 40 Conversions per Second

• IntegratingADC Technique

- Monotonic

- High Noise Immunity

- Auto Zeroed Amplifiers Eliminate Offset
Trimming

• Wide Dynamic Range: 96dB

• Low Input Bias Current: 30pA

• Low Input Noise: 30µV

P-P

• Sensitivity: 100µV

• Flexible Operational Control

• Continuous or On Demand Conversions

• Data Valid Output

• Bus Compatible, 3-State Data Outputs

-8-BitDataBus

-SimpleµP Interface

- Two Chip Enables

- Read ADC Result Like Memory

• ± 5V Power Supply Operation: 20mΩ

• 40-Pin Dual-in-Line or 44-Pin PLCC Packages

Applications

• Precision Analog Signal Processor

• PrecisionSensor Interface

• High Accuracy DC Measurements

Device Selection Table

Part Number Package

TC850CPL 40-Pin PDIP 0°Cto+70°C

TC850IJL 40-Pin CERDIP -25°Cto+85°C

TC850CLW 44-Pin PLCC 0°Cto+70°C

TC850ILW 44-Pin PLCC -25°Cto+85°C

Temperature

Range

Package Types

CS

CE

WR

RD

CONT/DEMAND

OVR/POL

L/H

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

BUSY

OSC

OSC

TEST

DGND

CONT/DEMAND

RD

6543 1442

OVR/POL

7

8

L/H

9

DB7

10

DB6

11

DB5

12

NC

13

DB4

DB3

DB2

DB1

DB0

18 19 20 21 23 24

BUSY

1

OSC

NC = No Internal Connection

40-Pin PDIP/CERDIP

1

2

3

4

5

6

7

TC850CPL

8

TC850IJL

9

10

11

12

13

14

15

16

17

1

18

2

19

20

44-Pin PLCC

WR

CE

CS

NC

VDDREF

43 42 41 40

TC850CLW

TC850ILW

DGND

25 26 27 28

NC

COMP

2

OSC

22

TEST

40

V

DD

REF1+

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

+

+

1

REF1

C

SS

OUT

V

INT

C

REF1

C

REF1

REF-

C

REF2

C

REF2

REF

+

2

IN+

IN­ANALOG
COMMON
C

INTB

C

INTA

C

BUFA

C

BUFB

BUFFER

INT

IN

INT

OUT

V

SS

COMP

-

REF1

C

REF-

39

38

37

36

35

34

33

3214

3115

3016

2917

IN

INT

BUFFER

+

-

-

+

C

REF2

C

REF2

REF

IN+

IN-

NC
ANALOG

COMMON
C

INTB

C

INTA

C

BUFA

C

BUFB

-

+

+

2



2002 Microchip TechnologyInc. DS21479B-page 1

TC850

General Description

The TC850 is a monolithic CMOS A/D converter (ADC)
with resolution of 15-bitsplus sign. It combines a chop­per-stabilized buffer and i ntegrator with a unique multi­ple-slope integration technique that increases
conversion speed. The result is 16 times improvement
in speed over previous 15-bit, monolithic integrating
ADCs (from 2.5 conversions per second up to 40 per
second). Faster conversion speed is especially wel­come in systems with human interface, such as digital
scales.

The TC850 incorporates an ADC and a µP-compatible
digital interface. Only a voltage reference and a few,
noncritical, passive components are required to form a
complete 15-bit plus sign ADC. CMOS processing pro­vides the TC850 with high-impedance, differential
inputs. Input bias current is typically only 30pA, permit­ting direct interface to sensors. Input sensitivity of
100µV per least significant bit (LSB) eliminates the

Functional Block Diagram

Pinout of 40-Pin Package

REF2+

+

REF

REF-

1

BUF

R

INT

INT IN

need for precision external amplifiers. The internal
amplifiers are auto zeroed, ensuring a zero digital out­put, with 0V analog input. Zero adjustment
potentiometers or calibrations are not required.

The TC850 outputsdataonan8-bit,3-statebus.Digital
inputs are CMOS compatible while outputs are TTL/
CMOS compatible.Chip-enable and byte-selectinputs,
combined with an end-of-conversion output, ensures
easy interfacing to a wide variety of microprocessors.
Conversions can be performed continuously or on
command. In continuous mode, data is read as three
consecutivebytes and manipulation of address lines i s
not required.

Operating from ±5V supplies, the TC850 dissipates
only 20mΩ. The TC850 i s packaged in a 40-pin plastic
or ceramic dual-in-line package (DIPs) and in a 44-pin
plastic leaded chip carrier (PLCC), surface-mount
package.

C

INT

INT OUT

+5V–5V

IN+

IN-

COMMON

-

32
31
30

Analog

Mux

A/D

Control

Sequencer

Clock
Oscillator

17 7

OSC

1

18

OSC

+

Buffer

÷4

53

CONT/

2

DEMAND

L/H6OVR/

POL

-

+

Integrator

TC850

Bus Interface

Decode Logic

4RD1CS2

WR

232425363439

CE

22 40

Comparator

+

-

6-Bit

Up/Down

Counter

Data Latch

Octal 2-Input Mux

3-State Data Bus

15 8

DB0

9-Bit

Up/Down

Counter

. . . .

DB7

DS21479B-page 2



2002 Microchip TechnologyInc.

TC850

1.0 ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings*

Positive Supply Voltage..........................................+6V

Negative Supply Voltage.......................................- 9V

Analog Input Voltage (IN+ pr IN-).............. V

DD

to V

SS

*Stresses above those listed under "Absolute Maximum Rat­ings"maycause permanentdamage to thedevice.These are
stress ratings only and functional operation of the device at
these or any other conditions above those indicated in the
operation sections of the specifications is not implied. E xpo­sure to Absolute Maximum R ating conditions for extended
periodsmay affectdevice reliability.

Voltage Reference Input:

(REF

+, REF1–, REF2+).................. VDDto V

1

SS

Logic Input Voltage.............VDD+0.3VtoGND–0.3V

Current Into Any Pin............................................10mA

While Operating ......................................100µA

Ambient Operating Temperature Range

C Device.......................................0°C to +70°C

I Device......................................-25°C to +85°C

Package Power Dissipation (T

≤ 70°C)

A

CerDIP .....................................................2.29Ω

Plastic DIP................................................1.23Ω

Plastic PLCC ...........................................1.23Ω

TC850 ELECTRICAL SPECIFICATIONS

Electrical Characteristics: VS=±5V;F

Symbol Parameter Min Typ Max Unit Test Conditions

ZeroScaleError ±0.25 ±0.5 LSB V
End PointLinearity Error — ±1 ±2 LSB -V
Differential Nonlinearity — ±0.1 ±0.5 LSB
InputLeakage Current — 30 75 pA VIN=0V,TA=25°C

I

IN

V

CommonMode Voltage Range VSS+1.5 — VSS– 1.5 V Over OperatingTemperatureRange

CMR

CMRR Common M ode Rejection Ratio — 80 — dB V

Full Scale Gain Temperature
Coefficient

Zero Scale Error
Temperature Coefficient

Full Scale Magnitude
Symmetry Error

InputNoise — 30 — µV

e

N

+ Positive Supply Current — 2 3.5 mA

I

S

– Negative Supply Current — 2 3.5 mA

I

S

Output High Voltage 3.5 4.9 — V IO=500µA

V

OH

Output Low Voltage — 0.15 0.4 V IO=1.6mA

V

OL

Output Leakage Current — 0.1 1 µA Pins 8 -15, High-Impedance State

I

OP

InputHighVoltage 3.5 2.3 — V Note 3

V

IH

Input Low Voltage — 2.1 1 V Note 3

V

IL

Input Pull-Up Current — 4 — µA Pins2,3,4,6,7;VIN=0V

I

PU

InputPull-Down Current — 14 — µA Pins1,5;VIN=5V

I

PD

I

C

Oscillator OutputCurrent — 140 — µAPin18,V

OSC

InputCapacitance — 1 — pF Pins 1 - 7, 17

C

IN

Output Capacitance — 15 — pF Pins 8 -15, High-Impedance State

OUT

Note 1: Demand mode, CONT/DEMAND

2: Continuous mode, CONT/DEMAND
3: Digital inputs have CMOS logic levels and internal pull-up/pull-down resistors. For TTL compatibility, external pull-up

resistors to V

are recommended.

DD

= 61.44kHz,VFS= 3.2768V, TA= 25°C, Figure 1-1, unless otherwise specified.

CLK

=0V

IN

≤ VIN≤ +V

FS

—1.13 nA-25°≤ T

=0V,VCM=±1V

IN

≤ +85°C

A

FS

— 2 5 ppm/°C External Ref. Temperature

Coefficient = 0 ppm/°C

=0V

IN

= ±3.275V

IN

≤ +70°C

A

≤ +70°C

A

OUT

=2.5V

0°C ≤ T

—0.32

µV/°C V

0°C ≤ T

—0.52LSBV

Not Exceeded 95% of Time

P-P

= LOW. Figure 8-5 timing diagram. CL= 100pF.

= HIGH. Figure 8-7 timing diagram.



2002 Microchip TechnologyInc. DS21479B-page 3

TC850

TC850 ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: VS=±5V;F

Symbol Parameter Min Typ Max Unit Test Conditions

T

Chip-Enable Access Time — 230 450 nsec CS or CE,RD=LOW(Note1)

CE

Read-Enable Access Time — 190 450 nsec CS = HIGH, CE =LOW,(Note1)

T

RE

T
T

Data Hold From CS or CE —250450nsecRD=LOW,(Note1)

DHC

Data Hold From RD —210450nsecCS=HIGH,CE=LOW,(Note1)

DHR

OVR/POL Data Access Time — 140 300 nsec CS = HIGH, CE =LOW,

T

OP

Low/High Byte Access Time — 140 300 nsec CS = HIGH, CE =LOW,

T

LH

ClockSetupTime 100 — — nsec Positive or NegativePulse Width
T
T

T

RD Minimum Pulse Width 450 230 — nsec CS= HIGH, CE =LOW,(Note2)

WRE

RD Minimum Delay Time 150 50 — nsec CS = HIGH, CE =LOW,(Note2)

WRD

WR Minimum Pulse Width 75 25 — nsec CS = HIGH, CE =LOW,(Note1)

WWD

Note 1: Demand mode, CONT/DEMAND

2: Continuous mode, CONT/DEMAND
3: Digital inputs have CMOS logic levels and internal pull-up/pull-down resistors. For TTL compatibility, external pull-up

resistors to V

are recommended.

DD

= 61.44kHz,VFS= 3.2768V, TA= 25°C, Figure 1-1, unless otherwise specified.

CLK

RD

=LOW,(Note1)

RD = LOW, (Note 1)

= LOW. Figure 8-5 timing diagram. CL= 100pF.

= HIGH. Figure 8-7 timing diagram.

DS21479B-page 4



2002 Microchip TechnologyInc.

FIGURE 1-1: STANDARD TEST CIRCUIT CONFIGURATION

TC850

+5V

20

V

DGND

DD

16

BUSY

8

DB7

9

DB6

10
11
12
13
14
15
1
2
3
4
5
6
7
17

18

21

0.1
µF

OSC

OSC

COMP

C

**

61.44 kHz

**

ANALOG COMMON
DB5
DB4

DB3
DB2
DB1
DB0
CS
CE
WR
RD
CONT/DEMAND
OVR/POL
L/H

TC850

1

2

C

INTBCBUFACBUFB

INTA

28 2729

0.1
µF

0.1
µF

-5V

2240

V

SS

REF

REF

REF-

C

REF1

C

REF1

C

REF2

C

REF2

BUFFER

INT

INT

OUT

TEST

0.1
µF

IN+

IN-

1

2

IN

26

+

+

+

­+

-

0.1
µF

32

31
30

39
33
36

38

37
34

35

120MkΩ

25

24

23

19

100MΩ

0.01µF Input

+1.6384V

+0.0256V

*

1µF

*

1µF

R

INT

0.1µF

C

INT

NC

NOTES: Unless otherwise specified, all 0.1µF capacitors are film dielectric.
Ceramic capacitors are not recommended.
NC = No Connection
*Polypropylene capacitors.
** 100pF Mica capacitors.



2002 Microchip TechnologyInc. DS21479B-page 5

TC850

2.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table .

TABLE 2-1: PIN FUNCTION TABLE

Pin Number

(40-Pin

PDIP/CERDIP)

1 2 CS Chip select, active HIGH. Logically ANDed, with CE

23CE
34WR

45RD

5 6 CONT/

67OVR/POL

78L/H

8 9 DB7 Most significant data bit output. When reading the A/D conversionresult, the

9-15 10-17 DB6-DB0 Data outputs DB6-DB0. 3-state, bus compatible.

16 18 BUSY A/D conversion status output. BUSY goes to a logic HIGH at the beginning of the

17 19 OSC
18 20 OSC
19 21 TEST For factory testing purposes only. Do not make external connectionto this pin.
20 22 DGND Digital groundconnection.
21 24 COMP Connection for comparator auto zero capacitor. Bypass to V
22 25 V
23 26 INT
24 27 INT
25 28 BUFFER Output of the input buffer.Connect to R
26 29 C
27 30 C
28 31 C
29 32 C
30 33 ANALOG

31 35 IN– Negative differential analog input.
32 36 I N+ Positive differentialanalog input.

Note 1: This pin incorporates a pull-down resistortoDGND.

2: This pin incorporatesa pull-upresistor to V
3: Pins 1, 23 and 34 (44-PLCC) package are NC “No Internal connection.

Pin Number

(44-Pin PLCC)

Symbol Description

inputs (Note 1).
Chip enable, active LOW (Note 2).
Writeinput,activeLOW.Whenchipisselected(CS=HIGHandCE= LOW) and

in demand mode (CONT/DEMAND
conversion (Note 1).

Read input,active LOW. When CS = HIGH and CE = LOW, a logic LOW on RD
enables the 3-state data outputs(Note 2).

Conversion control input. When CONT/DEMAND = LOW, conversionsareiniti-

DEMAND

ated by the WR
performed continuously (Note 1).

Overrange/polarity data-select input.Whenmakingconversionsin the demand
mode (CONT/DEMAND
whenthehigh-orderbyteisactive(Note2).

Low/high byte-select input. When CONT/DEMAND = LOW, this input controls
whetherlow-byte or high-byte data is enabled on DB0 through DB7 (Note 2).

polarity, overrange and DB7 data are output on this pin.

de-integratephase,thengoesLOWwhen conversion is complete.The falling
edge of BUSY can be used to generate a

Crystal oscillatorconnection or externaloscillator input.

1

Crystal oscillator connection.

2

SS

BUFB
BUFA

INTA
INTB

Negative power supply connection, typically -5V.
Outputof the integrator amplifier.Connect to C

OUT

Input to the integrator amplifier. Connect to summing node of R

IN

Connection for buffer auto zero capacitor. Bypass to VSSwith 0.1µF.
Connection to buffer auto zero capacitor. Bypass to VSSwith 0.1µF.
Connection for integrator auto zero capacitor. Bypass to VSSwith 0.1µF.
Connection for integrator auto zero capacitor. Bypass to VSSwith 0.1µF.
Analog common.

COMMON

.

DD

to enable read and write

=LOW),alogicLOWonWRstartsa

input. When CONT/DEMAND = HIGH, conversions are

= LOW), OVR/POL controlsthedataoutputonDB7

µP interrupt.

SS

.

INT

.

INT

with 0.1µF.

and C

INT

INT

.

DS21479B-page 6



2002 Microchip TechnologyInc.

TABLE 2-1: PIN FUNCTION TABLE (CONTINUED)

Pin Number

(40-Pin

PDIP/CERDIP)

33 37 REF2+ Positiveinputfor reference voltage V
34 38 C
35 39 C
36 40 REF– Negative input for reference voltages.
37 41 C
38 42 C
39 43 REF
40 44 V

Note 1: This pin incorporates a pull-down resistortoDGND.

2: This pin incorporatesa pull-upresistor to V
3: Pins 1, 23 and 34 (44-PLCC) package are NC “No Internal connection.

Pin Number

(44-Pin PLCC)

Symbol Description

+ Positive connection for V

REF2

– Negative connection for V

REF2

– Negative connection for V

REF1

+ Positive connection for V

REF1

+ Positiveinputfor V

1

DD

Positive power supply connection, typically +5V.

.

DD

REF1

reference capacitor.

REF2

reference capacitor.

REF2

reference capacitor.

REF1

reference capacitor.

REF1

.

REF2

.(V

REF2=VREF1

TC850

/64)



2002 Microchip TechnologyInc. DS21479B-page 7

TC850

3.0 DETAILED DESCRIPTION

The TC850 is a multiple-slope, integrating A/D con­verter ( ADC). The multiple-slope conversion process,
combined with chopper-stabilized amplifiers, results in
a significant increase in ADC speed, while maintaining
very high resolution and accuracy.

3.1 Dual Slope Conversion P rinciples

The conventional dual slope converter measurement
cycle (shown in Figure 3-1) has two distinct phases:

1. Input signal integration

2. Reference voltage integration (de-integration).

FIGURE 3-1: DUAL SLOPE ADC CYCLE

Signal De-integrate

Reference
De-integrate

End of Conversion

Integrator

Output

The input signal being converted is integrated for a
fixed time period, measured by counting clock pulses.
An opposite polarity constant reference voltage is then
de-integrateduntil the integrator output voltage returns
to zero. The reference integration time is directly
proportionalto the input signal.

In a simple dual slope converter, complete conversion
requires the i ntegrator output to "ramp-up" and "ramp­down." Most dual slope converters add a third phase,
auto zero. During auto zero, offset voltages of the input
buffer, integrator and comparator are nulled, thereby
eliminating the need for zero offset adjustments.

Dual slope converter accuracy is unrelated t o the inte­grating resistor and capacitor values, as long as they
are stable during a measurement cycle. By converting
the unknown analog input voltage into an easily mea­sured function of time, the dual slope converter
reduces the need for expensive, precision passive
components.

Noise immunity is an inherent benefit of the integrating
conversion method. Noise spikes are integrated, or
averaged, to zero during the integration period. I nte­grating ADCs are immune to t he large conversion
errors that plague successive approximation
converters in high-noise environments.

A simple mathematical equation relates the input sig­nal, reference voltage and integration time:

Auto
Zero

Time

0V

EQUATION 3-1:

where:

1

R

INTCINT

V

REF

T

INT

T

DEINT

T

INT

VIN(T)DT =

∫

0

= Reference voltage
= Signal integration time (fixed)
= Reference voltage integration time

(variable).

V

REFTDEINT

R

INTCINT

3.2 Multiple Slope Conversion
Principles

One limitation of the dual slope measurement tech­nique is conversion speed. In a typical dual slope
method, the auto zero and integrate times are each
one-half of the de-integrate time. For a 15-bit conver-

14+214+215

sion,2
for auto zero, integrate and de-integrate phases,
respectively. The large number of clock cycles effec­tively limits the conversion rate to about 2.5 conver­sions per second, when a typical analog CMOS
fabricationprocess is used.

The TC850 uses a multiple slope conversiontechnique
to increase conversion speed ( Figure 3-2). This tech­nique m akes use of a two-slope de-integration phase
and permits 15-bit resolution up to 40 conversions per
second.

During the TC850's de-integration phase, the integra­tion capacitor is rapidly dischargedto yield a resolution
of 9 bits. At this point, some charge will remain on the
capacitor. This remaining charge is then slowly de­integrated, producing an additional 6 bits of resolution.
The result is 15 bits of resolution achieved with only

9+26

2

(512 + 64, or 576) clock pulses for de­integration.A complete conversioncycle occupies only
1280 clock pulses.

In order to generate "fast-slow" de-integration phases,
two voltage references are required. The primary refer­ence (V
(typically V

) is set to one-half of the full scale voltage

REF1

REF1

secondaryvoltagereference (V
(typically 25.6 mV). To maintain 15-bit linearity, a toler­ance of 0.5% for V

(65,536)clockpulsesare required

= 1.6384V, and VFS= 3.2768V). The

is recommended.

REF2

)issettoV

REF2

REF1

/64

DS21479B-page 8



2002 Microchip TechnologyInc.