Microchip Technology TC835CPI, TC835CKW, TC835CBU Datasheet

TC835

Personal Computer Data Acquisition A/D Converter

Features

• Upgrade of Pin-Compatible TC7135, ICL7135

• 200kHz Operation

• Single 5V Operation With TC7660

• Multiplexed BCD Data Output

• UART and Microprocessor Interface

• Control Outputs for Auto-Ranging

• Input Sensitivity: 100µV

• No Sample and Hold Required

Applications

• Personal Computer Data Acquisition

• Scales, Panel Meters, Process Controls

• HP-IL Bus Instrumentation

Device Selection Table

Part Number Package Temperature Range

TC835CBU 64-PinPQFP 0°Cto+70°C

TC835CKW 44-Pin PQFP 0°Cto+70°C

TC835CPI 28-Pin PDI P 0°Cto+70°C

Note: Tape and Reel available for 44-Pin PQFP

package.

General Description

The TC835 is a low power, 4-1/2 digit (0.005%
resolution), BCD analog to digital converter (ADC) that
has been characterized for 200kHz clock rate opera­tion. The five conversions per second rate is nearly
twice as fast as the I CL7135 or TC7135. The TC835,
like the TC7135, does not use the external diode resis­tor rollover error compensation circuits required by the
ICL7135.

The multiplexed BCD data output is perfectforinterfac­ing to personal computers. The low cost, greater than
14-bit high-resolution and 100µV sensitivity makes the
TC835 exceptionally cost-effective.

Microprocessor-based data acquisition systems are
supported by the BUSY and STROBE
with the RUN/HOLD
OVERRANGE, UNDERRANGE, BUSY and RUN/
HOLD control functions, plus multiplexed BCD data
outputs, make the TC835 the ideal converter for µP­based scales, measurement systems and intelligent
panel meters.

The TC835 interfaces with full function LCD and LED
display decoder/drivers. The UNDERRANGE and
OVERRANGE outputs may be used to implement an
auto-ranging scheme or special display functions.

input of the TC835. The

outputs, along



2002 Microchip TechnologyInc. DS21478B-page 1

TC835

D

Package Type

V-

REF IN

ANALOG

COM

INT OUT

AZ IN

BUFF OUT

C

REF

C

REF

–INPUT

+INPUT

V+

(MSD) D5

(LSB) B1

B2

1

2

3

4

5

6

-

7

+

8

9

10

11

12

13

14

28-Pin PDIP

TC835CPI

UNDERRANGE

28

OVERRANGE

27

26

STROBE

RUN/HOLD

25

24

DIGTAL GND

23

POLARITY

22

CLOCK IN

21

BUSY

20

D1 (LSD)

19

D2

18

D3

17

D4

16

B8 (MSD)

15

B4

INT OUT

AZ IN

BUFF OUT

REF CAP–

REF CAP+

–INPUT

+INPUT

64-Pin PQFP

NCNCNC

44 43 42 41 39 3840

NC

1

2

3

4

5

6

7

8

V+

9

NC

10

NC

11

12 13 14 15 17 18

NC

NC

44-Pin PQFP

ANALOG

REF INV–UR

COMMON

TC835CKW

16

B2

B4

(LSB) B1

(MSD) D5

OR

STROBE

37 36 35 34

19 20 21 22

D4

D3

(MSB) B8

NC

NC

33

NC

32

NC

31

RUN/HOL

30

DGND

29

POLARITY

28

CLK IN

27

BUSY

26

NC

D1 (LSD)

25

D2

24

NC

23

NC

NC

OVERRANGE

UNDERRANGE

ANALOG COM

NOTES:

1. NC = No internal connection.

2. Pins 9, 25, 40 and 56 are connected to the die substrate. The potential at these pins is approximately V+.
No external connections should be made.

NC

NC
NC

NC

NC
NC

SUB

V–

REF IN

NC

NC

NC

NC

NCNCNC

NC

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

NC

61 60 59 58 57 56 55 545352 51 50 4964

63

62

NC

AZ IN

INT OUT

DGND

STROBE

RUN/HOLD

TC835CBU

NC

OUT

BUFF

BUF CAP–

POL

NC

SUB

SUB

D1

CLK IN

BUSY

NC

–INPUT

BUF CAP+

D2

NC

NC

NC

32

NC

+INPUT

NC

V+

48

NC

47

NC

46

NC

45

D3

44

D4

43

B3

42

B4

41

B2

40

SUB

39

B1

38

D5

37

NC

36

NC

35

NC

34

NC

33

NC

DS21478B-page 2



2002 Microchip TechnologyInc.

Typical Application

3

4

Address Bus

Control

Data Bus

TC835

+

5V

R 6522 P

PB0

Channel Selection

PA0
PA1
PA2

PA3
PA4
PA5
PA6
PA7
CA1
CA2

PB3PB2PB1

HCTS157

1Y
2Y
3Y

1B
2B
3B

1A
2A
3A

S

F

IN

V+ REF CAP

BUF

INPUT+

TC835

Analog

Common

F

IN

AZ

INT

V

Input

DGND

-

5V

POL
OR
UR
D5
B8
B4
B2

B1
D1
D2
D3
D4
STB
R/H

-15V

+15V

DG529

D

A

D

B

R

REF Voltage

WR

A1A0EN

Channel 1

Channel 2

Channel

Channel

Differential
Multiplexer



2002 Microchip TechnologyInc. DS21478B-page 3

TC835

1.0 ELECTRICAL
CHARACTERISTICS

Absolute Maximum Ratings*

Positive Supply Voltage......................................... +6V

*Stresses above those listed under "Absolute Maximum Rat­ings"maycause permanentdamage to the device.These are
stress ratings only and functional operation of the device at
these or any other conditions above t hose indicated in the
operation sections of the specifications is not implied. Expo­sure to Absolute Maximum R ating conditions for extended
periodsmay affectdevice reliability.

Negative Supply Voltage........................................-9V

Analog Input Voltage (Pin 9 or 10) ...V+ to V– (Note 2)

Reference Input Voltage (Pin 2) .....................V+ to V–

Clock Input Voltage ........................................ 0V to V

+

Operating Temperature Range................0°C to +70°C

StorageTemperature Range............. -65°C to +150°C

Package Power Dissipation (T

≤ 70°C)

A

28-Pin Plastic DIP ............................ 1.14Ω

44-Pin PQFP .................................... 1.00Ω

64-Pin PQFP .................................... 1.14Ω

TC835 ELECTRICAL SPECIFICATIONS

Electrical Characteristics: TA=+25°C,F
Symbol Parameter Min Typ Max Unit Test Conditions

Analog

Display Reading with Zero Volt Input -0.0000 ±0.0000 +0.0000 DisplayReading Note 3, Note 4
ZeroReading TemperatureCoefficient — 0.5 2 µV/°C VIN=0V,(Note 5)

TC

Z

Full-Scale Temperature Coefficient — — 5 ppm/°C VIN=2V;

TC

FS

NL Nonlinearity Error — 0.5 1 Count Note 7

DNL Differential Linearity Error — 0.01 — LSB Note 7

Display Reading in Ratiometric Operation +0.9996 +0.9998 +1.0000 Display Reading V

±FSE ± Full Scale Symmetry Error (Rollover Error) — 0.5 1 Count –V

Input Leakage Current — 1 10 pA Note 4

I

IN

Noise — 15 — µV

e

N

Digital

Input Low Current — 10 100 µAV

I

IL

Input High Current — 0.08 10 µAV

I

IH

Output Low Voltage — 0.2 0.4 V IOL=1.6mA

V

OL

Output High Voltage;

V

OH

f

CLK

Note 1: Functional operation is not implied.

2: Limit input current to under 100 µA if input voltages exceed supply voltage.
3: Full scale voltage = 2V.
4: V
5: 0°C ≤ T
6: Externalreference temperature coefficient less than 0.01ppm/°C.
7: -2V ≤ V
8: |V
9: Test circuit shown in Figure 1-1.
10: Specification relatedtoclock frequency range over which the TC835 correctly performs its various functions.Increased

B

1,B2,B4,B8,D1–D5

Busy, Polarity,Overrange,

Underrange, Strobe

ClockFrequency 0 200 1200 kHz Note 10

=0V.

IN

≤ +70°C.

A

≤ +2V. Error of readingfrom best fit straightline.

IN

| = 1.9959.

IN

errors result at higher operating frequencies.

= 200kHz, V+ = +5V, V-= -5V,unless otherwise specified.

CLOCK

2.4 4.4 5 V I

4.9 4.99 5 V I

P-P

(Note 5, Note 6

IN=VREF

Peak to Peak Value not
Exceeded 95% of Time

IN
IN

OH
OH

,(Note 3)

=+VIN, (Note 8)

IN

=0V
=+5V

=1mA
=10µA

DS21478B-page 4



2002 Microchip TechnologyInc.

TC835 ELECTRICAL S P EC IFICATIONS (CONTINUED)

TC835

Electrical Characteristics: TA=+25°C,F
Symbol Parameter Min Typ Max Unit Test Conditions

Power Supply

V+ Positive Supply Voltage 4 5 6 V
V– Negative SupplyVoltage -3 -5 -8 V

I+ PositiveSupply Current — 1 3 mA f
I– Negative Supply Current — 0.7 3 mA f

PD Power Dissipation — 8.5 30 mΩ f

Note 1: Functional operation is not implied.

2: Limit input current to under 100 µA if input voltages exceed supply voltage.
3: Full scale voltage = 2V.
4: V

=0V.

IN

5: 0°C ≤ T
6: Externalreference temperature coefficient less than 0.01ppm/°C.
7: -2V ≤ V
8: |V
9: Test circuit shown in Figure 1-1.
10: Specification relatedtoclock frequency range over which the TC835 correctly performs its various functions.Increased

errors result at higher operating frequencies.

≤ +70°C.

A

≤ +2V. Error of readingfrom best fit straightline.

IN

| = 1.9959.

IN

= 200kHz, V+ = +5V, V-= -5V,unless otherwise specified.

CLOCK

CLK
CLK
CLK

=0Hz
=0Hz
=0Hz



2002 Microchip TechnologyInc. DS21478B-page 5

TC835

2.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 2-1.

TABLE 2-1: PIN FUNCTION TABLE

Pin Number
28-Pin PDIP

1 V- Negative powersupply input.
2 REF IN External reference input.
3 ANALOG COMMON Reference point for REF IN.
4 INT OUT Integrator output. Integrator capacitor connection.
5 AZ IN Auto zero input. Auto zero capacitor connection.
6 BUFF OUT Analog input buffer output. Integrator resistor connection.
7C
8C
9 -INPUT Analog input. Analoginputnegative connection.

10 +INPUT Analog input. Analog input positive connection.

11 V+ Positive power supplyinput.
12 D5 Digit drive output.Most Significant Digit(MSD)
13 B1 Binary CodedDecimal (BCD) output.LeastSignificantBit(LSB)
14 B2 BCD output.
15 B4 BCD output.
16 B8 BCD output. Most Significant Bit (MSB)
17 D4 Digit drive output.
18 D3 Digit drive output.
19 D2 Digit drive output.
20 D1 Digit drive output. Least Significant Digit (LSD)
21 BUSY Busy output.At the beginning of the signal-integration phase,BUSYgoesHighand

22 CLOCK IN Clock input. Conversion clock connection.
23 POLARITY Polarity output.A positive input is indicatedby a logic High output.The polarity output is

24 DGND Digitallogic referenceinput.
25 RUN/HOLD

26 STROBE
27 OVERRANGE Over range output. A logic High indicates that the analog input exceeds the full scale input

28 UNDERRANGE Underrangeoutput. A logic High indicatesthatthe analog input is less than 9% of the full

Symbol Description

- Reference capacitor input. Reference capacitornegative connection.

REF

+ Reference capacitor input. Reference capacitor positive connection.

REF

remainsHighuntilthefirstclockpulseafter the integratorzerocrossing.

valid at the beginning of the reference integratephaseandremains valid until determined
duringthenext conversion.

Run / Hold input. When at a logic High,conversions are performed continuously. A logic
Low holds the current data as long as the Low condition exists.

Strobe output. The STROBE output pulses low in the center of the digit drive outputs.

range.

scaleinputrange.

DS21478B-page 6



2002 Microchip TechnologyInc.

TC835

3.0 DETAILED DESCRIPTION

(All Pin Designations Refer to 28-Pin DIP)

3.1 Dual Slope Conversion Principles

The TC835 is a dual slope, integrating analog to digital
converter. An understanding of the dual slope conver­sion technique will aid in following the detailed TC835
operational theory.

The conventional dual slope converter measurement
cycle has two distinct phases:

1. Input signal i ntegration

2. Referencevoltage integration (de-integration)
Theinputsignalbeingconvertedisintegratedforafixed

timeperiod,witht ime beingmeasuredby countingclock
pulses.An opposite polarity constantreference voltage
is then integrated until the integrator output voltage
returnstozero.Thereference integrationtimeisdirectly
proportional to the input signal.

In a simple dual slope converter, a complete
conversion requires the integrator output to "ramp-up"
and "ramp-down."

A simple mathematical equation relates the input sig­nal, reference voltage and integration time:

EQUATION 3-1:

where:

1

R

INTCINT

V

REF

T

INT

T

DEINT

T

INT

VIN(T)DT =

∫

0

= Reference voltage
= Signal integration time (fixed)
= Reference voltage integration time

(variable).

V

REFTDEINT

R

INTCINT

FIGURE 3-1: BASIC DUAL SLOPE

CONVERTER

Analog Input

Signal

REF

Voltage

Output

Integrator

Fixed

Signal

Integrate

Time

Integrator

-

+

Switch

Drive

Polarity Control

Display

Variable
Reference
Integrate
Time

Phase
Control

V

IN

V

IN

≈ V

REF

≈ 1/2 V

Comparator

-

+

Control

Logic

REF

Clock

Counter

3.2 TC835 Operational Theory

The TC835 incorporates a system zero phase and
integrator output voltage zero phase to the normal two
phase dual slope measurement cycle. Reduced sys­tem errors, fewer calibration steps and a shorter over­range recovery time result.

The TC835 measurement cycle contains four phases:

1. System zero

2. Analog input signal integration

3. Referencevoltage integration

4. Integrator output zero
Internal analog gate status for each phase is shown in

Table 3-1.

For a constant VIN:

EQUATION 3-2:

VIN=

V

REFTDEINT

t

INT

3.2.1 SYSTEM ZERO

During this phase, errors due to buffer, integrator and
comparator offset voltages are compensated for by
charging C
ing error voltage. With a zero input voltage the

(auto zero capacitor) with a compensat-

AZ

integrator output wi ll remain at zero.

The dual slope converter accuracy is unrelated to the
integrating resistor and capacitor values, as long as
they are stable during a measurement cycle. An
inherent benefit is noise immunity. Noise spikes are
integrated, or averaged, to zero during the integration
periods. Integrating ADCs are immune to the large
conversion errors that plague successive approxima­tion converters in high noise environments (see
Figure3-1).



2002 Microchip TechnologyInc. DS21478B-page 7

The externalinputsignal is disconnectedfromtheinter­nal circuitry by opening the two SW

switches. The

I

internal input points connect to ANALOG COMMON.
The reference capacitor charges to the reference
voltage potential through SW

. A feedback loop,

R

closed around the integrator and comparator, charges
the C

capacitor with a voltage to compensate for

AZ

buffer amplifier, integrator and comparator offset
voltages (see Figure 3-2).

TC835

A

FIGURE 3-2: SYSTEM Z ERO PHASE

Analog

SWRI+

C

REF

Input Buffer

SW

1

+

-

SWIZSW

SW

Z

C

R

INT

INT

C

SZ

Z

-

Comparator

+

+

-

Integrator

Switch Open
Switch Closed

To Digital
Section

+IN

REF

Analog
Common

–

SW

I

SWRI-

SW

R

IN

SW

Z

SWRI+SWRI-

SW

I

IN

3.2.2 ANALOG INP UT SIGNAL
INTEGRATION

The TC835 integrates the differential voltage between
the +INPUT and -INPUT pins. The differential voltage
mustbewithinthedeviceCommonmoderange(-1V
fromeithersupplyrail,typically). Theinputsignalpolarity
is determined at the end of this phase (see Figure 3-3).

FIGURE 3-3: INPUT SIGNAL

INTEGRATION PHASE

Analog

+IN

REF

nalog

Common

–

SW

I

SW

R

IN

SW

Z

SWRI+SWRI-

SW

I

IN

Input Buffer

+

SW

-

+SWRI-

RI

SW

SW

C

REF

IZ

SW

Z

SW

1

C

R

INT

INT

C

SZ

Z

-

Comparator

+

+

-

Integrator

Switch Open
Switch Closed

To
Digital
Section

3.2.3 REFERENCE VOLTAGE
INTEGRATION

FIGURE 3-4: REFERENCE VOLTAGE

INTEGRATION CYCLE

Analog

SWRI+

-

C

REF

+SWRI-

SW

1

Input Buffer

+

-

SW

IZ

SW

Z

C

R

INT

INT

C

SW

SZ

Z

-

Comparator

+

+

-

Integrator

Switch Open
Switch Closed

To Digital
Section

+IN

REF

Analog
Common

–

SW

I

SW

RI

SW

R

IN

SW

Z

SW

RI

SW

I

IN

3.2.4 INTEGRATOR OUTPUT ZERO

This phase guarantees the integrator output is at 0V
when the system zero phase is entered and that the
true system offset voltages are compensated for. This
phase normally lasts 100 to 200 clock cycles. If an
overrange condition exists, the phase is extended to
6200 clock cycles ( see Figure 3-5).

FIGURE 3-5: INTEGRATOR OU TPUT

ZERO PHASE

Analog

Input Buffer

SWRI+SWRI-

C

REF

SW

1

SW

R

+

-

SW

INTCINT

C

SW

IZ

Z

SZ

Z

-

+

Integrator

Switch Open
Switch Closed

Comparator

+

-

To Digital
Section

+

REF

Analog
Common

–

SW

I

IN

SW

R

IN

SW

Z

SWRI+SWRI-

SW

I

IN

The previously charged reference capacitor is con­nected with the proper polarity to ramp the integrator
outputbacktozero(see Figure 3-4). The digitalreading
displayed is:

Reading = 10,000

[Differential Input]

V

REF

TABLE 3-1: INTERNAL ANALOG GATE STATUS

Conversion Cycle Phase SWISWRI+SWRI-SWZSW

System Zero Closed Closed Closed Figure3-2
InputSignal Integration Closed Figure 3-3
Reference Voltage Integration Closed* Closed Figure3-4
Integrator OutputZero Closed Closed Figure3-5

*Note: Assumes a positive polarity input signal. SW

DS21478B-page 8

would be closed for a negative input signal.

RI

SW

R

SW

1



2002 Microchip TechnologyInc.

Reference Figures

IZ