Microchip Technology TC7650CPD, TC7650CPA Datasheet

TC7650

Chopper Stabilized Operational Amplifier

Features

• Low Input Offset Voltage: 0.7µV Typ

• Low Input Offset Voltage Drift: 0.05µV/°C Max

• Low Input Bias Current: 10pA Max

• High Impedance DifferentialCMOS Inputs: 10

12

• High Open Loop Voltage Gain:120dB Min.

• Low Input NoiseVoltage: 2.0µVp-p

• High Slew Rate: 2.5V/µsec.

• Low Power Operation:20mW

• Output Clamp Speeds Recovery Time

• Compensated Internally for Stable Unity Gain
Operation

• Direct Replacement for ICL7650

• Available in 8-Pin Plastic DIP and 14-Pin Plastic
DIP Packages

Applications

• Instrumentation

• Medical Instrumentation

• Embedded Control

• Temperature Sensor Amplifier

• Strain GageAmplifier

Package Type

8-Pin DIP

1

C

A

Ω

–

INPUT

+

INPUT

2

TC7650CPA

3

V

SS

4

14-Pin DIP

C

B

1

C

A

2

NC

3

–

INPUT

+

INPUT

V

NC

SS

4

TC7650CPD

5

6

7

8

C

B

V

7

DD

6

OUTPUT

OUTPUT CLAMP

5

14

INT/EXT

13

EXT CLK IN

12

INT CLK OUT

V

11

DD

10

OUTPUT

9

OUTPUT CLAMP

C

8

RETN

Device Selection Table

Part

Number

TC7650CPA 8-PinPDIP 0°C to +70°C 5µV
TC7650CPD 14-Pin PDIP 0°C to +70°C 5µV

Package

Temperature

Range

Max V

NC = NO INTERNAL CONNECTION

OS



2002 Microchip TechnologyInc. DS21463B-page 1

TC7650

General Description

The TC7650 CMOS chopper stabilized operational
amplifier practically removes offset voltage error terms
from system errorcalculations.The 5µVmaximum V

OS

specification, for example, represents a 15 times
improvement over the industry standard OP07E. The
50nV/°C offset drift specification is over25 times lower
than the OP07E. The increased performance elimi­nates V

trim procedures, periodic potentiometer

OS

adjustmentandthereliability problemscausedbydam­aged trimmers.

The TC7650 performance advantages are achieved
without the additional manufacturing complexity and
cost incurred with laser or "zener zap" V

trim tech-

OS

niques.

Functional Block Diagram

Output

Clamp

Inputs

Output Clamp

Circuit

Main
Amplifier

The TC7650 nulling scheme corrects both DC V

OS

errors and VOSdrift errors with temperature. A nulling
amplifieralternately correctsitsown V
main amplifier V

error. Offset nulling voltages are

OS

errorsandthe

OS

stored on two user supplied external capacitors. The
capacitors connect to the internal amplifier V

OS

null
points. The main amplifier input signal is never
switched. Switching spikes are not present at the
TC7650 output.

The 14-pin dual-in-line package (DIP) has an external
oscillatorinput to drive the nulling circuitry for optimum
noise performance. Both the 8 and 14-pin DIPs have
an output voltage clamp circuit to minimize overload
recoverytime.

14-Pin DIP Only

Oscillator

AB

INT/EXT
EXT CLK IN
CLK OUT

Output

NULL

Null
Amplifier

A

Null

*

For 8-Pin DIP, connect to V

Intermod

Compensation

BB

ss

BA

C

B

C

A

TC7650

*C

RETN

DS21463B-page 2



2002 Microchip TechnologyInc.

TC7650

1.0 ELECTRICAL
CHARACTERISTICS

*Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the dev ice.
These are stress ratingsonly and functional operation ofthe
device at these or any ot her conditions above those indi-

ABSOLUTE MAXIMUM RATINGS*

Total SupplyVoltage (VDDto VSS) .......................+18V

Input Voltage.................... (V

+0.3V)to (VSS–0.3V)

DD

cated in the operation sections of the specifications is not
implied. Exposure to Absolute Maximum Rating conditions
for ex tended periods my affect device reliability.

StorageTemperature Range..............-65°C to +150°C

Voltage on Oscillator Control Pins...............V

DD

to V

SS

Duration of Output Short Circuit.....................Indefinite

Current Into Any Pin............................................10mA

WhileOperating(Note 3)............................100µA

Package Power Dissipat ion (T

≤ 70°C)

A

8-Pin Plastic DIP.......................................730mW

14-Pin Plastic DIP.....................................800mW

Operating Temper ature Range

C Device .......................................... 0°C to +70°C

TC7652 ELECTRICAL SPECIFICATIONS

Electrical Characteristics: VDD=+5V,VSS=-5V,CA=CB=0.1µF, TA= +25°C, unless otherwise indicated.

Symbol Parameter Min. Typ Max Units Test Conditions

Input

V

OS

∆V

/∆T Input Offset Voltage A verage

OS

I

BIAS

I

OS

e

NP-P

I

N

R

IN

CMVR Common Mode Voltage Range -5 -5.2 to +2 +1.6 V
CMRR Common Mode Rejection Ratio 120 130 — dB CMVR = -5V to +1.5V

Output

A Large Signal Voltage Gain 120 130 — dB R
V

OUT

Dynamic

B

W

S

R

t

R

f

CH

Supply

V

DD,VSS

I

S

PSRR Power Supply Rejection Ratio 120 130 dB V
Note 1: See " Output Clamp" discussion.

Input Offset Voltage —

Temperature Coefficient
Offset Voltage vs. Time — 100 — nV/

Input Bias Current —

Input Offset Current — 0.5 — pA
Input Noise Voltage — 2 — µV
Input Noise Current —
Input Resistance — 10

Output Voltage Swing (Note 2)±4.7

Clamp ON Current 25 70 200 µAR
Clamp OFF Current — 1 — pA -4V < V

Unity Gain Bandwidth — 2.0 — MHz Unity Gain (+1)
Slew Rate — 2.5 — V/µsec CL= 50pF, RL= 10kΩ
Rise Time — 0.2 — µsec
Overshoot — 20 — %
Internal Chopping Frequency 120 200 375 Hz Pins 12–14 Open (DIP)

Operating Supply Range 4.5 — 16 V
Supply Current — 2 3.5 mA No Load

2: Output clamp not connected. See typical characteristics curves for output swing versus clamp current characteristics.
3: Limiting input current to 100µA is recommended to avoid latch-up problems.

—
— 0.01 0.05 µV/°C Operating Temperature Range

—
—

—

±0.7
±1.0

1.5
35

100

0.01

±4.85
±4.95

±5

—

10
150
400

12

—pA/√Hz f=10Hz

—
—

—µVTA= +25°C

Over Operating Temp Range

month

pA

TA= +25°C

pA

0°C ≤ T

pA

P-PRS

Ω

V
V

A

-25°C ≤ T

= 100Ω, 0 to 10Hz

=10kΩ

L

RL=10kΩ
R

= 100kΩ

L

= 100kΩ (Note 1)

L

OUT

=±3Vto±8V

S

≤ +70°C

A

≤ +85°C

<+4V(Note 1)



2002 Microchip TechnologyInc. DS21463B-page 3

TC7650

2.0 PIN DESCRIPTIONS

ThedescriptionsofthepinsarelistedinTable2-1.

TABLE 2-1: PIN FUNCTION TABLE

Pin Number

Symbol Description

8-pin DIP 14-pin DIP

1,8 2,1 C

A,CB

Nulling capacitor pins
2 4 -INPUT Inverting Input
3 5 +INPUT Non-inverting Input
47 V

SS

59OUTPUT

Negative Power Supply

Output VoltageClamp

CLAMP
6 10 OUTPUT Output
711 V

DD

Positive Power Supply
— 3,6 NC No internal connection
—8C

RETN

Capacitor current return pin
— 12 INT CLK OUT Internal Clock Output
— 13 EXT CLK IN External Clock Input
— 14 INT/EXT

Select Internal or External Clock

3.0 DETAILED DESCRIPTION

3.1 Theory of Operation

Figure 3-1 shows the major elements of the TC7650.
There are two amplifiers (the main amplifier and the
nulling amplifier), and both have offset null capability.
The main amplifier is connected full-time from the input
to the output. The nullingamplifier, underthe control of
the chopping frequency oscillator and clock circuit,
alternatelynulls itselfandthemainamplifier.Twoexter­nal capacitors provide the required storage of the null­ing potentials and the necessary nulling loop time
constants. The nulling arrangement operates over the
full common mode and power supply ranges, and is
also independentofthe output level, thus giving excep­tionally high CMRR, PSRR and A

Careful balancing of the input switches minimizes
chopper frequency charge injection at the input termi­nals, and the feed forward type injection into the com­pensationcapacitor that can cause outputspikes in this
type of circuit.

The circuit's offset voltage compensation is easily
shown. With the nulling inputs shorted, a voltage
almost identical to the nulling amplifier offset voltage is
stored on C

. The effective offset voltage at the null

A

amplifier input is:

EQUATION 3-1:

V

OSE

----------------- -V

=

AN1+

1

OSN

VOL

.

After the nulling amplifier is zeroed, the main amplifier
is zeroed; the A s witches open and B switches close.

The output voltage equation i s:

EQUATION 3-2:

V

OUT=AM[VOSM

+(V+-V-)+AN(V+-V-)+ANV

OSE

]

EQUATION 3-3:

V

+

OSMVOSN

V

OUTAMAN

V+V-–()

---------------- -------------------------- -+=
A

N

As desired, the device offset voltages are reduced by
the high open loop gai n of the nulling amplifier.

3.2 Output Stage/Loading

The output circuit is a high impedance stage (approxi­mately 18kΩ). With loads less than this, the chopper
amplifier behaves in some ways like a trans-conduc­tance amplifier whose open-loop gain isproportional to
load resistance. For example, the open loop gain will
be 17dB lower with a 1kΩ load than with a 10kΩ load.
If the amplifier is used strictly for DC, the lower gain is
of little consequence, since the DC gain is typically
greaterthan 120dB, even with a1kΩ load. In wideband
applications, the best frequency response will be
achieved with a load resistor of 10kΩ or higher. This
resultsin a s mooth 6dB/octave response from 0.1Hz to
2MHz, with phase shifts of less than 10° in the transi-

DS21463B-page 4



2002 Microchip TechnologyInc.

TC7650

tion region, where the main amplifier takes over from
the null amplifier. The clock frequency sets the transi­tion region.

ing sum and difference frequencies, and causing dis­turbances to the gain and phase versus frequency
characteristics near the chopping frequency. These
effects are substantially reduced in the TC7650 by

3.3 Intermodulation

Previous chopper stabilized amplifiers have suffered
from intermodulation effects between the chopper fre­quency and input signals. These arise because the
finite AC gain of the amplifier results in a small AC sig­nal at the input. This is seen by the zeroing circuit as an

feeding the nulling circuit with a dynamic current corre­sponding to the compensation capacitor current in such
a way as to cancel that portion of the input signal due
to a finite AC gain. The intermodulation and gain/phase
disturbances are held to very low values, and can gen­erally be ignored.

error signal, which is chopped and fed back, thus inject-

FIGURE 3-1: TC7650 CONTAI NS A NULLING AND MAIN AMPLIFIER. OFFSET CORRECTION

+

V

Analog Input

VOLTAGES ARE STORED ON TWO EXTERNAL CAPACITORS

+
Null

.

Main
Amplifier

-

-

V

B

A

TC7650

+

Null

-

B

A

Null

Gain = A

M

C

B

C

A

Amplifier

V

OUT

Gain = A

FIGURE 3-2: NULLING CAPACITOR

CONNECTION

2

-

TC7650

3

+

1

V

DD

7

6

4

C

B

8

C

A

V

SS

V

V

DD

SS

11

4

-

TC7650

5

+

2

14-PIN PACKAGE 8-PIN PACKAGE

CAC

7

10

1

8

B

3.4 Nulling Capacitor Connection

The offset voltage correction capacitors are connected
to C

and CB. The common capacitor connection is

A

made to V
capacitorreturn (C
The common connection should be made through a
separatePCtraceorwiretoavoidvoltagedrops.The
capacitorsoutside foil, if possible,shouldbe connected
to C

RETN

(Pin 4) on the 8-pin packages and to

SS

,Pin8)onthe14-pinpackages.

RETN

or VSS.

, Offset = V

N

OSN

3.5 Clock Operation

The internal oscillator is set for a 200Hz nominal chop­pingfrequencyonboththe8-and14-pinDIPs.Withthe
14-pin DIP TC7650, the 200 Hz internal chopping fre­quency is available at the internal clock output (Pin 12).
A 400Hz nominal signal will be present at the external
clockinput pin (Pin 13) with INT/EXT
is the internalclock signal before adivide-by-twooper­ation.

The 14-pin DIP device can be driven by an external
clock. The INT/EXT

input (Pin 14) hasan internal pull­up and may be l eft open for internal clock operation. If
an external clock is used, INT/EXT
(Pin 7) to disable the internal clock. Theexternal clock
signal is appliedto the external clock input (Pin 13).

The external clock amplitude should swing between
V

and ground for power supplies up to ±6V and

DD

between V

+

and V+-6V for higher supply voltages.

At low frequencies the external clock duty cycle is not
critical, since an internal divide-by-two gives the
desired 50% switching duty cycle. The offset storage
correction capacitorsare charged only whenthe exter­nal clock input is high. A 50% t o 80% external clock

highoropen. This

must be tied to V

SS



2002 Microchip TechnologyInc. DS21463B-page 5