Microchip Technology TC7135CPI, TC7135CLI, TC7135CBU Datasheet

z

4-1/2 Digit A/D Converter

TC7135

Features

• Low Rollover Error: ±1 Count Max

• Nonlinearity Error: ±1 Count Max

• Reading for 0V Input

• True Polarity Indication at Zero for Null Detection

• Multiplexed BCD Data Output

• TTL-Compatible Outputs

• Differential Input

• Control Signals Permit Interface to UARTs and
Microprocessors

• Blinking Display Visually Indicates Overrange
Condition

• Low Input Current: 1pA

• Low Zero Reading Drift: 2µV/°C

• Auto-Ranging Supported with Overrange and
Underrange Signals

• Available in PDIP and Surface-Mount Packages

Applications

• Precision Analog Signal Processor

• PrecisionSensor Interface

• High Accuracy DC Measurements

Device Selection Table

Part Number Package Temperature Range

TC7135CLI 28-Pin PLCC 0°Cto+70°C
TC7135CPI 28-PinPDIP 0°Cto+70°C
TC7135CBU 64-PinPQFP 0°Cto+70°C

General Description

The TC7135 4-1/2 digit A/D converter ( ADC) offers
50ppm (1 part in 20,000) resolution with a maximum
nonlinearity error of 1 count. An auto zero cycle
reduces zero error to below 10µV and zero drift to

0.5µV/°C. Source impedance errors are m inimized by
a 10pA maximum input current.Rollover error is limited
to ±1 count.

Microprocessorbased measurement systems are sup­ported by BUSY,STROBE

and RUN/HOLD control sig­nals. Remote data acquisition systems with data
transfer via UARTs are also possible. The additional
control pins and mul tiplexed BCD outputs make the
TC7135 the ideal converter for display or
microprocessorbased measurement systems.

Functional Block Diagram

SET V

REF

IN

V

REF

100kΩ

Analog GND

0.47µF

Signal
Input

+

5V

= 1V

100kΩ
100

kΩ

0.1µF

–5V

1µF

1µF

1

2

3

4

5
6

7
8
9

10
11
12

13

14

TC7135

V-

UNDERRANGE

REF IN
ANALOG

COMMON

INT OUT

AZ IN
BUFF OUT

C
C

-INPUT

+INPUT
V+
D5 (MSD)

B1 (LSB)

B2

REF

REF

­+

OVERRANGE

STROBE

RUN/HOLD

DIGTAL GND

POLARITY

CLOCK IN

BUSY

(LSD) D1

D2

D3

D4

(MSB) B8

B4

28

27

26

25

24

23

22

21

20

19

18

17

16

15

Clock
Input
120kH



2002 Microchip TechnologyInc. DS21460B-page 1

TC7135

Package Types

AZ IN

BUFF OUT

REF CAP–

REF CAP+

–INPUT

+INPUT

V+

OVERRANGE

UNDERRANGE

ANALOG COM

28-Pin PDIP

INT OUT

ANALOG

COM

4 3 2 1 27 2628

5

6

7

8

9

10

11

12 13 14 15 17 18

REF INV–URORSTROBE

TC7135

B2

(LSB) B1

(MSD) D5

NC

63 61 60 59 58 57 56 55 545352 51 50 4964

1

l

NC

2

NC

3

NC

4

NC

5

NC

6

NC

7

8

9

NC

10

V-

11

REF IN

12

13

NC

14

NC

15

NC

16

NC

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

NC

16

B4

(MSB) B8

NCNCNC

62

NC

AZ IN

INT OUT

D4

D3

STROBE

NC

25

RUN/HOLD

24

DIGTAL GND

23

POLARITY

22

CLOCK IN

21

BUSY

20

D1 (LSD)

19

D2

64-Pin PQFP

DGND

POLNCCLOCK IN

RUN/HOLD

TC7135

­NC

REF

C

BUFF OUT

NC

+

REF

C

BUSYD2D1

NC

–INPUT

NC

REF IN

ANALOG

INT OUT

BUFF OUT

C

– INPUT

+INPUT

(MSD) D5

(LSB) B1

NC

NC

NC

+INPUT

AZ IN

C

32

COM

REF

REF

NC

V+

V+

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

28-Pin PDIP

UNDERRANGE

1

V-

2

3

4

5

6

-

7

+

B2

NC

NC

NC

D3

D4

B8

B4

B2

NC

B1

D5

NC

NC

NC

NC

NC

TC7135

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

OVERRANGE

STROBE

RUN/HOLD

DIGTAL GND

POLARITY

CLOCK IN

BUSY

D1 (LSD)

D2

D3

D4

B8 (MSB)

B4

NOTE: NC = No internal connection.

DS21460B-page 2



2002 Microchip TechnologyInc.

TC7135

1.0 ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings*

Positive Supply Voltage..........................................+6V

Negative Supply Voltage.......................................- 9V

Analog Input Voltage (Pin 9 or 10)....V+ to V- (Note 2)

*Stresses above those listed under "Absolute Maximum Rat­ings"maycause permanentdamage to thedevice.These are
stress ratings only and functional operation of the device at
these or any other conditions above those indicated in the
operation sections of the specifications is not implied. E xpo­sure to Absolute Maximum R ating conditions for extended
periodsmay affectdevice reliability.

Reference Input Voltage (Pin 2)...................... V+ to V-

Clock Input Voltage........................................ 0V to V+

Operating Temperature Range ...............0°C to +70°C

StorageTemperature Range............– 65°C to +150°C

Package Power Dissipation;(T

≤ 70°C)

A

28-Pin PDIP ..................................... 1.14Ω

28-Pin PLCC .................................... 1.00Ω

64-Pin PQFP.....................................1.14Ω

TC7135 ELECTRICAL S PECIFICATIONS

Electrical Characteristics: TA=+25°C,F

(see Functional Block Diagram).

Symbol Parameter Min Typ Max Unit Test Conditions

Analog

Display Reading with Zero VoltInput -0.0000 ±0.0000 +0.0000 D isplay Reading Note 2 and Note 3
Zero Reading Temperature Coefficient — 0.5 2 µV/°C VIN=0V,(Note4)

TC

Z

TC

±FSE ± Full Scale Symmetry Error

Digital

Note 1: Limit input current to under 100µA if input voltages exceedsupply voltage.

Full ScaleTemperature Coefficient — — 5 ppm/°C VIN=2V,

FS

NL Nonlinearity Error — 0.5 1 Count Note 6

DNL Differential LinearityError — 0.01 — LSB Note 6

Display Reading in Ratiometric Operation +0.9996 +0.9999 +1.0000 Display Reading V

(Rollover Error)
Input Leakage Current — 1 10 pA Note 3

I

IN

Noise — 15 — µV

e

N

Input Low Current — 10 100 µAV

I

IL

Input High Current — 0.08 10 µAV

I

IH

OutputLowVol tage — 0.2 0.4 V IOL=1.6mA

V

OL

OutputHighVoltage;

V

OH

B

1,B2,B4,B8,D1–D5

Busy, Polarity,Overrange,

Underrange, Strobe

ClockFrequency 0 200 1200 kHz Note8

F

CLK

2: Full scalevoltage = 2V.

=0V.

3: V

IN

4: 30°C ≤ T
5: .External referencetemperaturecoefficientless than 0.01ppm/°C.
6: -2V ≤ V
7: IV

IN

8: Specification related to clock frequency range over which the TC7135 correctly performs its various functions. Increased

≤ +70°C

A

≤ +2V. Error of readingfrom best fit straightline.

IN

| = 1.9959.

errors result at higher operating frequencies.

= 120kHz, V+ = +5V, V- = -5V,unless otherwise specified

CLOCK

— 0.5 1 Count -V

2.4 4.4 5 V I

4.9 4.99 5 V I

P-P

(Note4andNote5)

=+V

(Note 2)

(Note 7)

IN,

IN=VREF,

IN

Peak-to-Peak Valuenot
Exceeded 95% of Time

=0V

IN

=+5V

IN

=1mA

OH

=10µA

OH



2002 Microchip TechnologyInc. DS21460B-page 3

TC7135

TC7135 ELECTRICAL S PECIFICATIONS (CONTINUED)

Electrical Characteristics: TA=+25°C,F

(see Functional Block Diagram).

Symbol Parameter Min Typ Max Unit Test Conditions
Power Supply

V+ Positive Supply Voltage 4 5 6 V

V- Negative Supply Voltage -3 -5 -8 V
I+ Positive Supply Current — 1 3 mA F

I- Negative Supply Current — 0.7 3 mA F

PD Power Dissipation — 8.5 30 mW F

Note 1: Limit input current to under 100µA if input voltages exceedsupply voltage.

2: Full scalevoltage = 2V.

=0V.

3: V

IN

4: 30°C ≤ T
5: .External referencetemperaturecoefficientless than 0.01ppm/°C.
6: -2V ≤ V
7: IV

IN

8: Specification related to clock frequency range over which the TC7135 correctly performs its various functions. Increased

errors result at higher operating frequencies.

≤ +70°C

A

≤ +2V. Error of readingfrom best fit straightline.

IN

| = 1.9959.

= 120kHz, V+ = +5V, V- = -5V,unless otherwise specified

CLOCK

CLK
CLK
CLK

=0Hz
=0Hz
=0Hz

DS21460B-page 4



2002 Microchip TechnologyInc.

2.0 PIN DESCRIPTIONS

The description of t he pins are listed in Table 2-1.

TABLE 2-1: PIN FUNCTION TABLE

TC7135

Pin Number
28-Pin PDIP

1 V- Negative power supplyinput.
2 REF IN External reference input.
3 ANALOG COMMON Reference point for REF IN.
4 INT OUT Integrator output. Integratorcapacitor connection.
5 AZ IN Auto zero inpt. Auto-zero capacitor connection.
6 BUFF OUT Analog input buffer output. Integrator resistor connection.
7C
8C

9 -INPUT Analoginput. Analog input negativeconnection.
10 +INPUT Analog input. Analog input positive connection.
11 V+ Positive power supplyinput.
12 D5 Digit drive output. Most Significant Digit (MSD)
13 B1 Binary Coded Decimal(BCD) output.LeastSignificantBit (LSB)
14 B2 BCD output.
15 B4 BCD output.
16 B8 BCD output. Most Significant Bit (MSB)
17 D4 Digit drive output.
18 D3 Digit drive output.
19 D2 Digit drive output.
20 D1 Digit drive output. Least Significant Digit (LSD)
21 BUSY Busy output.At the beginningof the signal-integration phase, BUSY goes High and

22 CLOCK IN Clock input. Conversion clock connection.
23 POLARITY Polarity output.A positive input is indicated by a logicHighoutput. The polarity outputis

24 DGND Digitallogicreference input.
25 RUN/HOLD

26 STROBE
27 OVERRANGE Over range output. A logic High indicates that the analog input exceeds the full scale input

28 UNDERRANGE Under range output.A logic High indicates that the analog input is less than 9% of the full

Symbol Description

- Reference capacitor input. Referencecapacitornegative connection.

REF

+ Reference capacitor input. Reference capacitorpositive connection.

REF

remainsHighuntilthefirstclockpulseafter the integratorzerocrossing.

valid at the beginning of the reference integrate phase andremains valid until determined
duringthenext conversion.

Run / Hold input. When at a logic High, conversions are performedcontinuously.A logic
Low holds the current data as long as the Low condition exists.

Strobe output. The STROBE output pulses low in the center of the digit drive outputs.

range.

scaleinputrange.



2002 Microchip TechnologyInc. DS21460B-page 5

TC7135

3.0 DETAILED DESCRIPTION

(All Pin Designations Refer to 28-Pin DIP)

3.1 Dual Slope Conversion P rinciples

The TC7135 is a dual slope, integrating A/ D converter.
An understanding of the dual slope conversion tech­nique will aid i n following the detailed TC7135
operational theory.

The conventional dual slope converter measurement
cycle has two distinct phases:

1. Input signal integration

2. Reference voltage integration ( de-integration)
The input signal being converted is integrated for a

fixed time period. Time is measured by counting clock
pulses.An opposite polarity constant referencevoltage
is then integrated until the integrator output voltage
returns to zero. The reference integration time is
directly proportional to the input signal.

In a simple dual slope converter, a complete conver­sion requires the integrator output to "ramp-up" and
"ramp-down."

A simple mathematical equation relates the input sig­nal, reference voltage, and integration time:

EQUATION 3-1:

T

1

R

INTCINT

INT

∫

0

VIN(T)DT =

where:

V
T
T

= Reference voltage

REF

= Signal integration time (fixed)

INT

= Reference voltage integration time

DEINT

(variable).

For a constant VIN:

EQUATION 3-2:

V

REFTDEINT

VIN=

The dual slope converter accuracy is unrelated to the
integrating resistor and capacitor values, as long as
they are stable during a measurement cycle. An inher-

T

INT

V

REFTDEINT

R

INTCINT

ent benefit is noise immunity. Noise spikes are inte­grated, or averaged, to zero during the integration
periods.

Integrating ADCs are immune to the large conversion
errors that plague successive approximation convert­ers in high-noise environments(see Figure 3-1).

FIGURE 3-1: BASIC DUAL SLOPE

CONVERTER

Analog Input

Signal

REF

Voltage

Output

Integrator

Fixed

Signal

Integrate

Time

Integrator

-

+

Switch

Drive

Polarity Control

Display

Variable
Reference
Integrate
Time

Phase
Control

V

IN

V

IN

≈ V

REF

≈ 1/2 V

Comparator

-

+

Control

Logic

REF

Clock

Counter

3.2 TC7135 Operational Theory

The TC7135 incorporates a system zero phase and
integratoroutputvoltage zero phase to the normal two­phase dual-slope measurement cycle. Reduced sys­tem errors, fewer calibration steps, and a shorter over­range recovery time result.

The TC7135 measurement cycle contains four phases:

1. System zero

2. Analog i nput signal integration

3. Reference voltage integration

4. Integrator output zero
Internal analog gate status for each phase is shown in

Figure 3-1.

TABLE 3-1: INTERNAL ANALOG GATE STATUS

Conversion Cycle Phase SWISWRI+SWRI-SWZSW

System Zero Closed Closed Closed Figure 3-2
InputSignal Integration Closed Figure 3-3
Reference Voltage Integration Closed* Closed Figure 3-4
Integrator OutputZero Closed Closed Figure 3-5

*Note: Assumes a positive polarity input signal. SW

DS21460B-page 6

would be closed for a negative input signal.

RI

SW

R

SW

1



2002 Microchip TechnologyInc.

Reference Figures

IZ

TC7135

A

A

3.2.1 SYSTEM ZERO

During this phase, errors due to buffer, integrator, and
comparator offset voltages are compensated for by
charging C

(auto zero capacitor) with a compensat-

AZ

ing error voltage. With a zero input voltage the integra­tor output will remain at zero.

The externalinputsignal is disconnectedfromtheinter­nal circuitry by opening the t wo SW

switches. The

I

internal input points connect to ANALOG COMMON.
The reference capacitor charges to the reference volt­age potential through SW
around the integrator and comparator, chargesthe C

. A feedback loop, closed

R

AZ

capacitorwithavoltage to compensate for bufferampli­fier, integrator, and comparator offset voltages (see
Figure 3-2).

FIGURE 3-2: SYSTEM ZERO PHASE

Analog

SWRI+

C

REF

Input Buffer

SW

1

+

-

SWIZSW

SW

Z

C

R

INT

INT

C

SZ

Z

-

Comparator

+

+

-

Integrator

Switch Open
Switch Closed

To Digital
Section

+IN

REF

Analog
Common

–

SW

I

SWRI-

SW

R

IN

SW

Z

SWRI+SWRI-

SW

I

IN

3.2.2 ANALOG INPUT SIGNAL
INTEGRATION

The TC7135 integratesthe differentialvoltage between
the +INPUT and -INPUT pins. The differential voltage
must be within the device Common mode range; - 1V
from either supply rail, typically. The input signal polar­ity is determined at the end of this phase.
SeeFigure2-3

FIGURE 3-3: INPUT SIGNAL

INTEGRATION PHASE

Analog

SW

Input Buffer

+

-

+SWRI-

RI

SW

SW

SW

IZ

SW

Z

1

C

REF

C

R

INT

INT

C

SZ

Z

-

Comparator

+

+

-

Integrator

Switch Open
Switch Closed

To
Digital
Section

nalog

Common

.

+IN

REF

–

SW

I

SW

R

IN

SW

Z

SWRI+SWRI-

SW

I

IN

3.2.3 REFERENCE VOLTAGE
INTEGRATION

The previously-charged reference capacitor is con­nected with the proper polarity to ramp the integrator
output back to zero

(see Figure 3-4). The digital

reading displayed is:

EQUATION 3-3:

Reading = 10,000

[Differential I nput]

V

REF

FIGURE 3-4: REFERENCE VOLTAGE

INTEGRATION CYCLE

Analog

SWRI+

-

C

REF

+SWRI-

Input Buffer

SW

1

C

R

INT

INT

+

-

SW

IZ

SW

Z

C

SW

SZ

Z

-

Comparator

+

+

-

Integrator

Switch Open
Switch Closed

To Digital
Section

+IN

REF

Analog
Common

–

SW

I

SW

RI

SW

R

IN

SW

Z

SW

RI

SW

I

IN

3.2.4 INTEGRATOR OUTPUT ZERO

This phase ensures the integrator output is at 0V when
the system zero phase is entered. It also ensures that
the true system offset voltages are compensated for.
This phase normally lasts 100 to 200 clockcycles. If an
overrange condition exists, t he phase is extended to
6200 clock cycles (see Figure 3-5).

FIGURE 3-5: INTEGRATOR OUTPUT

ZERO PHASE

Analog

Input Buffer

SWRI+SWRI-

C

REF

SW

1

SW

R

SW

INTCINT

C

SW

IZ

Z

SZ

Z

-

+

Integrator

Switch Open

Switch Closed

Comparator

+

-

To Digital
Section

+

-

+

IN

REF

IN

nalog

Common

–

IN

SW

SW

SW

SW

I

R

Z

SWRI+SWRI-

I



2002 Microchip TechnologyInc. DS21460B-page 7