• Direct LCD Driver for 4-1/2 D ig it s , Dec im al Po ints,
Low Battery Indicator, and Continuity Indicator
• Overrange and Underrange Outputs
• Range Select Input: 10:1
• High Common Mode Rejection Ratio: 110 dB
• External Phase Compensation Not Required
Applications
• Full-Featured Multimeters
• Digital Measu rem en t Dev ic es
Device Selection Table
Package
Code
TC7129CPLNormal40-Pin PDIP 0°C to +70°C
TC7129CKW Formed44-Pin PQFP 0°C to +70°C
TC7129CLW–44-Pin PLCC 0°C to +70°C
Pin
Layout
Package
Temperature
Range
General Description
The TC7129 is a 4-1/2 di git Analog-to-Dig ital Con verter
(ADC) that directly drives a multiplexed Liquid Crystal
Display (LCD). Fabricated in high-performance, lowpower CMOS, the TC7129 ADC is designed specifically for high-resolution, battery-powered digital multimeter applications. The traditional dual-slope method
of A/D conversion has been enhanced with a successive integration technique to produce readings accurate to better than 0.005% of full-scale and resolution
down to 10 µV per count.
The TC7129 includes f eatures impor tant to multimeter
applications. It detects and ind icat es l ow bat ter y con dition. A continuity outp ut drives an annunciator on the
display and can be used with an external driver to sound
an audible alarm. Overrange and underrange o utputs,
along with a range-ch ange input, provi de the ability to
create auto-ranging instruments. For snapshot readings, the TC7129 includes a latch-and-hold input to
freeze the present reading. This combination of features
makes the TC7129 the ideal choice for full-featured
multimeter and digital measurement applications.
Typical Application
Low Battery
20
27262524232221
*
0.1 µF
10 kΩ
+
9V
2004 Microchip Technology Inc.DS21459C-page 1
13141516171819
12
TC7129
29
28
+
1 µF
150 kΩ
9
1011
323130
–
Continuity
8
3534
36
20
kΩ
100 kΩ
*Note: RC network between pins 26 and 28 is not required.
+
0.1
µF
V
33
IN
39
3837
V+
5 pF
1234567
120 kHz
40
330 kΩ
10 pF
0.1 µF
V+
Page 2
TC7129
Package Types
ANNUNICATOR
B2, C2, LO BATT
Display
Output
Lines
B
, C1, CONT
1
A
F1, E1, DP
A
F2, E2, DP
B3, C
A
F3, E3, DP
B4, C
A4, G4, D
F4, E4, DP
OSC3
, G1, D
1
, G2, D
2
MINUS
3
,
, G3, D
3
4
V
DP4/OR
OSC1
BC
,
BP
BP
BP
DISP
40-Pin PDIP
1
2
3
4
5
1
6
1
7
8
2
9
2
10
11
3
12
3
13
5
14
4
15
4
16
3
17
2
18
1
19
20
TC7129CPL
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
OSC2
DP
1
DP
2
RANGE
DGND
REF LO
REF HI
IN HI
IN LO
BUFF
-
C
REF
C
+
REF
COMMON
CONTINUITY
INT OUT
INT IN
V+
V-
LATCH/HOLD
DP3/UR
, E1, DP
F
1
B2, C2, BATT
, G2, D
A
2
F2, E2, DP
B3, C
MINUS
3
,
A
, G3, D
3
F3, E3, DP
B4, C
A4, G4, D
F4, E4, DP
44-Pin QFP44-Pin PLCC
1
, D
, CONT
1
1
, G
, C
1
1
ANNUNCIATOR
OSC3
A
44 43 42 4139 3840
1
1
B
OSC1NCOSC2
2
3
2
4
2
5
NC
6
7
3
8
3
BC
9
4
5
,
10
4
11
4
12 13 14 1517 18
BP3BP
1
2
BP
TC7129CKW
16
/OR
4
DISP
V
DP
NC
/UR
3
DP
1DP2
DP
RANGE
37 36 35 34
19 20 21 22
V-
V+
DGND
33
32
31
30
29
28
27
26
25
24
23
INT IN
REF LO
REF HI
IN HI
IN LO
BUFF
NC
C
-
REF
C
+
REF
COMMON
CONTINUITY
INT OUT
F1, E1, DP
B2, C2, BATT
, G2, D
A
2
F2, E2, DP
B3, C
3
,
A
, G3, D
3
F3, E3, DP
B4, C
A4, G4, D
F4, E4, DP
MINUS
NC
BC
4
,
LATCH/HOLD
1
, D
, CONT
1
1
, G
, C
1
1
A
B
6543 1442
7
1
8
9
2
10
2
11
12
13
3
3
5
4
4
18 19 20 2123 24
3BP2
BP
ANNUNCIATOR
OSC3
OSC1NCOSC2
TC7129CLW
22
1
/OR
BP
DISP
4
V
DP
NC
/UR
3
DP
DP1DP2RANGE
43 42 41 40
25 26 27 28
V-
V+
LATCH/HOLD
DGND
39
38
37
36
35
34
33
3214
3115
3016
2917
INT IN
REF LO
REF HI
IN HI
IN LO
BUFF
NC
-
C
REF
C
+
REF
COMMON
CONTINUITY
INT OUT
DS21459C-page 2 2004 Microchip Technology Inc.
Page 3
TC7129
1.0ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings*
Supply Voltage (V+ to V-).......................................15V
*Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. These
are stress ratings only and functional operation of the device
at these or any other conditions above those indicated in the
operation sections of the specifications is not implied.
Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability.
Reference Voltage (REF HI or REF LO)........ V+ to V–
Input Voltage (IN HI or IN LO) (Note 1).......... V+ to V–
.......................................... V+ to (DGND – 0.3V)
V
DISP
Digital Input (Pins 1, 2, 19, 20,
21, 22, 27, 37, 39, 40).......................... DGND to V+
Analog Input (Pins 25, 29, 30) ....................... V+ to V–
Note 1:Input voltages may exceed supply voltages, provided input current is limited to ±400 µA. Currents above
this value may result in invalid display readings, but will not destroy the device if limited to ±1 mA.
Dissipation ratings assume device is mounted with all leads soldered to printed circuit board.
2004 Microchip Technology Inc.DS21459C-page 3
Page 4
TC7129
TC7129 ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrica l Characteristics: V+ to V– = 9V, V
Pin numbers refer to 40-pin DIP.
SymbolParameterMin TypMaxUnitTest Conditions
Power
V
COM
Common Voltage2.8 3.23.5VV+ to pin 28
Common Sink Current— 0.6—mA∆Common = +0.1V
Common Source Current— 10—µA∆Common = -0.1V
DGNDDigital Ground Voltage4.5 5.35.8VV+ to pin 36, V+ to V– = 9V
Sink Current— 1.2—mA∆DGND = +0.5V
Supply Voltage Range6 912VV+ to V–
I
S
Supply Current Excluding
Common Current
f
CLK
Clock Frequency— 120360kHz
Resistance— 50—kΩV
V
DISP
Low Battery Flag Activation
Voltage
Digital
Continuity Comparator Threshold
Voltages
Pull-down C urrent— 210µAPins 37, 38, 39
“Weak Output” Current
Sink/Source
Pin 22 Source Current—40—µA
Pin 22 Sink Current—3—µA
Note 1:Input voltages may exceed supply voltages, provided input current is limited to ±400 µA. Currents above
this value may result in invalid display readings, but will not destroy the device if limited to ±1 mA.
Dissipation ratings assume device is mounted with all leads soldered to printed circuit board.
= 1V, TA = +25°C, f
REF
= 120 kHz, unless otherwise indicated.
CLK
— 0.81.3mAV+ to V– = 9V
to V+
DISP
6.3 7.27.7VV+ to V–
100 200—mVV
— 200400mVV
pin 27 = High
OUT
pin 27 = Low
OUT
— 3/3—µAPins 20, 21 sink/sourc e
— 3/9—µAPin 27 sink/source
DS21459C-page 4 2004 Microchip Technology Inc.
Page 5
TC7129
2.0PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 2-1.
TABLE 2-1:PIN FUNCTION TABLE
Pin No.
40-Pin PDIP
1402OSC1Input to first clock inverter.
2413OSC3Output of second clock inverter.
3424ANNUNCIATOR Backplane square wave output for driving annunciators.
443 5B
544 6A
617F
728B
232026V–Negative power supply terminal.
242127V+Positive power supply terminal and positive rail for display
252228INT INInput to integrator amplifier.
262329INT OUTOutput of integrator amplifier.
272430CONTINUITYInput: When low, continuity flag on the display is off. When high,
282531COMMONSets common mode voltage of 3.2V below V+ for DE, 10X, etc.
292632C
302733C
312935BUFFEROutput of buffer amplifier.
323036IN LONegative input voltage terminal.
333137IN HIPositive input voltage terminal.
343238REF HIPositive reference voltage.
353339REF LONegative reference voltage
Pin No.
44-Pin PQFP
Pin No.
44-Pin PLCC
SymbolFunction
, C1, CONTOutput to display segments.
1
, G1, D
1
, E1, DP
1
, C2,
2
Output to display segments.
1
Output to display segments.
1
Output to display segments.
LO BATT
, G2, D
2
, E2, DP
2
, C3, MINUSO u tp ut to display se g m ents.
3
, G3, D
3
, E3, DP
3
, C4, BC
4
, D4, G
4
, E4, DP
4
3
2
1
DISP
/ORInput: When high, turns on most significant decimal point.
4
/URInput: Second-most significant decimal point on when high.
3
Output to display segments.
2
Output to display segments.
2
Output to display segments.
3
Output to display segments.
3
Output to display segments.
5
Output to display segments.
4
Output to display segments.
4
Backplane #3 output to display.
Backplane #2 output to display.
Backplane #1 output to display.
Negative rail for display drivers.
Output: Pulled high when result count exceeds ±19,999.
Output: Pulled high when result count is less than ±1000.
/HOLDInput: When floating, ADC operates in Free Run mode. When
pulled high, the last displayed reading is held. When pulled low,
the result counter contents are shown incrementing during the
de-integrate phase of cycle.
Output: Negative going edge occurs when the data latches are
updated. Can be used for converter status signal.
drivers.
continuity flag is on.
Output: High when voltage between inputs i s less than +200 mV .
Low when voltage between inputs is more than +200 mV.
Can be used as pre-regulator for external reference.
+Positive side of external reference capacitor.
REF
–Negative side of external reference capacitor.
REF
2004 Microchip Technology Inc.DS21459C-page 5
Page 6
TC7129
TABLE 2-1:PIN FUNCTION TABLE (CONTINUED)
Pin No.
40-Pin PDIP
363440DGNDInternal ground reference for digital section. See Section 4.2.1
373541RANGE3 µA pull-down for 200 mV scale. Pulled high externally for 2V
383642 DP
393743 DP
403844 OSC2Output of first clock inverter. Input of second clock inverter.
—6,17, 28, 3912, 23, 34, 1NCNo connection.
Pin No.
44-Pin PQFP
Pin No.
44-Pin PLCC
SymbolFunction
“±5V Power Supply”.
scale.
2
1
Internal 3 µA pull-down. When high, decimal point 2 will be on.
Internal 3 µA pull-down. When high, decimal point 1 will be on.
DS21459C-page 6 2004 Microchip Technology Inc.
Page 7
TC7129
3.0DETAILED DESCRIPTION
(All pin designations refer to 40-pin PDIP.)
The TC7129 is designed to be the heart of a high-
resolution analog measurement instrument. The only
additional components required are a few passive
elements: a voltage reference, a LCD and a power
source. Most component values are not critical;
substitutes can be chosen based on the information
given below.
The basic circuit for a digital multimeter application is
shown in Figure 3-1. See Section 4.0 “Typical Appli-cations”, for variations. Typical values for each
component are shown. The sections below give
component selection criteria.
3.1Oscillator (X
The primary criterion for selecting the crystal oscillator
is to choose a frequency tha t achieves maxim um rejection of line frequency noise. To do this, the integration
phase should last an integral number of line cycles.
The integration phase of the TC7129 is 10,000 clock
cycles on the 200 mV range and 1000 clock cycles on
the 2V range. One cl ock c yc le is eq ua l to tw o os cil la t or
cycles. For 60 Hz rejection, the oscillator frequency
should be chosen so that the period of one line cycle
equals the integration time for the 2V range.
, CO1, CO2, RO)
OSC
The resistor and cap acitor values are not crit ica l; those
shown work for most applications. In some situations,
the capacitor values may have to be adjusted to
compensate for parasitic capacitance in the circuit. The
capacitors can be low-cost ceramic devices.
Some applications can use a simple RC network
instead of a crystal oscillator. The RC oscillator has
more potential for jitter, especially in the least
significant digit. See Section 4.5 “RC Oscillator”.
3.2Integrating Resistor (R
The integrating resistor sets the charging current for
the integrating capacitor. Choo se a v alu e that provides
a current between 5 µA and 20 µA at 2V , the maxim um
full-scale input. The typical value chosen gives a
charging current of 13.3 µA:
INT
)
EQUATION 3-1:
I
CHARGE
Too high a value for R
noise pickup and increases errors due to leakage
current. Too low a value degrades the linearity of the
integration, leading to inaccurate readings.
2V
=
INT
13.3 µA
150 kΩ
increases the sensitivity to
EQUATION 3-1:
1/60 second = 16.7 msec =
1000 clock cycles *2 OSC cycles/ clock cycle
OSC Frequency
This equation gi ves an osc illa tor f requenc y of 120kHz.
A similar calculation gives an optimum frequency of
100 kHz for 50 Hz rejection.
2004 Microchip Technology Inc.DS21459C-page 7
Page 8
TC7129
Low Battery Continuity
V+
20
DP
4
/OR
DP
3
/UR
V
DISP
LATCH/
HOLD
V–
V+
+
INT IN
9V
13141516171819
Display Drive Outputs
CONTINUITY
COMMON
INT OUT
27262524232221
28
C
INT
0.1 µF
150 kΩ
10 kΩ
R
BIAS
12
TC7129
C
C
REF
REF
+
–
29
C
+
REF
1 µF
R
INT
9
1011
BUFF
IN LO
323130
– +
0.1
µF
C
V
IN HI
33
IF
IN
8
REF HI
R
IF
100 kΩ
REF LO
DGND
3534
36
R
REF
20
kΩ
ANNUNC
RANGE
DP
2
3837
D
REF
OSC3
DP
1
39
1234567
OSC1
OSC2
40
C
RF
0.1 µF
5 pF
120
kHz
330 kΩ
R
O
10 pF
V+
C
O1
Crystal
C
O2
Figure 3-1:Standard Circuit.
3.3Integrating Capacitor (C
The charge stored in the integrating capacitor during
the integrate phase is directly proportional to the input
voltage. The primary selection criterion for C
choose a value that gives the highest voltage swing
while remaining within the high-linearity portion of the
integrator output ran ge. An integrat or swing of 2V i s the
recommended value. The capacitor value can be
calculated using the following equation:
INT
)
is to
INT
EQUATION 3-1:
x I
t
INT
V
SWING
INT
Where t
C
=
INT
is the integration time.
INT
Using the values derived above (assuming 60 Hz
operation), the equation becomes:
EQUATION 3-2:
C
16.7 msec x 13.3 µA
=
INT
2V
= 0.1 µA
The capacitor should have low dielectric absorption to
ensure good integration linearity. Polypropylene and
Teflon® capacitors are usually suitable. A good
measurement of the dielectric absorption is to connect
the reference capacitor across the inputs by
connecting:
Pin-to-Pin:
20 → 33 (C
30 → 32 (C
+ to IN HI)
REF
– to IN LO)
REF
A reading between 10,000 and 9998 is acceptable;
anything lower indicates unacceptably high dielectric
absorption.
3.4Reference Capacitor (C
REF
)
The reference capacitor stores the reference voltage
during several phases of the measurement cycle. Low
leakage is the primary selection criterion for this component. The value must be high enough to offset the
effect of stray cap acit anc e at the c ap acito r terminals . A
value of at least 1 µF is recommended.
DS21459C-page 8 2004 Microchip Technology Inc.
Page 9
3.5Voltage Reference
(D
, R
REF
REF
, R
The reference potentiometer (R
BIAS
, CRF)
) provides an
REF
adjustment for adjusting the reference voltage; any
value above 20 kΩ is adequate. The bias resistor
) limits the current through D
(R
BIAS
150 µA. The reference filter capacitor (C
RC filter with R
to help eliminate noise.
BIAS
to less than
REF
) forms an
RF
3.6Input Filter (RIF, CIF)
For added stability, an RC input noise filter is usually
included in the circuit. The input filter resistor value
should not exceed 100 kΩ. A typical RC time constant
value is 16.7 msec to help reject line frequency noise.
The input filter capacitor should have low leakage for a
high-impedance input.
+5V
0.1 µF
0.1 µF
0.1 µF
36
DGND
TC7129
24
V+
REF HI
REF LO
COMMON
IN HI
IN LO
V–
23
TC7129
34
35
28
33
V
32
IN
+
–
3.7Battery
The typical circuit uses a 9V battery as a power so urce.
However , a ny v alue b etwee n 6V a nd 12V can b e use d.
For operation from batteries with voltages lower than
6V and for operation from power supplies, see
Section 4.2 “Powering the TC7129”.
4.0TYPICAL APPLICATIONS
4.1 TC7129 as a Replacement Part
The TC7129 is a direct pin-f or-pi n rep lac ement part for
the ICL7129. Note , howev er, that the ICL7129 require s
a capacitor an d resistor between pins 26 and 28 for
phase compensation. Since the TC7129 uses internal
phase compensat ion, these p art s are not requir ed and,
in fact, must be removed from the circuit for stable
operation.
4.2Powering the TC7129
While the most common power source for the TC7129
is a 9V battery, there are other possibilities. Some of
the more common ones are explained below.
4.2.1±5V Power Supply
Measurements are made with respect to power supply
ground. DGND (pin 36) is set intern ally to about 5V less
+ (pin 24); it is not inte nded to be a p ower su pply
than V
input and must not be tied directly to power supply
ground. It can be used as a refe rence for externa l logic,
as explaine d i n Section 4.3 “Connecting to ExternalLogic”, (see Figure 4-1).
-5V
Figure 4-1:Powering the TC7129 From
a ±5V Pow er Supply.
4.2.2Low Voltage Battery Source
A battery with voltage between 3.8V and 6V can be
used to power the TC7129 when used with a voltage
doubler circuit, as shown in Figure 4-2. The voltage
doubler uses the TC7660 DC-to-DC voltage converter
and two external capacitors.
24
+
3.8V
to
6V
8
TC7660
3
2
4
5
36
+
10 µF
+
V+
REF HI
DGND
REF LO
COMMON
TC7129
V–
10 µF
IN HI
IN LO
23
34
35
28
33
32
+
V
IN
–
Figure 4-2:Powering the TC7129 From
a Low-Voltage Battery.
2004 Microchip Technology Inc.DS21459C-page 9
Page 10
TC7129
–
4.2.3+5V Power Supply
Measurements are made with respect to power supply
ground. COMMON (pin 28) is connected to REF LO
(pin 35). A voltage doubler is needed, since the supply
voltage is less than the 6V minimum needed by the
TC7129. DGND (pin 36) must be isolated from power
supply ground (see Figure 4-3).
+5V
24
V+
0.1 µF
34
TC7129
35
36
8
V+
TC7660
GND
3
0.1 µF
2
4
5
10 µF
DGND
+
10 µF
+
28
33
32
V–
23
+
V
IN
+
V
24
External
Logic
I
LOGIC
36
TC7129
DGND
23
V-
Figure 4-4:Extern al Logi c Refere nc ed
Directly to DGND.
V+
24
External
Logic
TC7129
Figure 4-3:Powering the TC7129 From
a +5V Power Supply.
4.3Connecting to External Logic
External logic can be directly referenced to DGND
(pin 36), provided that the supply current of the externa l
logic does not exceed the sink current of DGND
(Figure 4-4). A safe value for DGND sink current is
1.2 mA. If the sink current is expected to exceed this
value, a buffer is recommended (see Figure4-5).
–
36
+
DGND
I
LOGIC
23
V–
Figure 4-5:Extern al Logi c Refere nc ed
to DGND with Buffer.
4.4Temperature Compensation
For most applications , V
directly to DGND (pin 36). For applications with a wide
temperature range, some LCDs require that the drive
levels vary with temperature to maintain good viewing
angle and display contrast. Figure 4-6 shows two
circuits that c an be adjus ted to give t emperat ure com pensation of about 10mV/°C between V+ (pin 24) and
. The diode between DGND and V
V
DISP
have a low turn-on voltage because V
exceed 0.3V below DGND.
(pin 19) can be conne cted
DISP
DISP
DISP
should
cannot
DS21459C-page 10 2004 Microchip Technology Inc.
Page 11
TC7129
V+
1N4148
39 kΩ
200 kΩ
24
TC7129
5 kΩ
75 kΩ
–
+
19
V
DISP
36
DGND
23
V–
Figure 4-6:Temperature Compensating Circuits.
4.5RC Oscillator
For applications in which 3-1/2 digit (100 µV) resolution
is sufficient, an RC oscillator is adequate. A recommended value for the capacitor is 51 pF. Other values
can be used as long as the y a re s ufficiently larger than
the circuit parasitic capacitance. The resistor value is
calculated as:
EQUATION 4-1:
0.45
R =
Freq * C
For 120 kHz frequency and C = 51 pF, the calculated
value of R is 75kΩ. The RC oscillator and the crystal
oscillator circuits are shown in Figu re 4-7.
TC7129
1 402
Ω
270 k
10 pF
V+
V+
5 pF
120 kHz
V+
20 kΩ
39 kΩ
2N2222
19
36
18 kΩ
24
TC7129
V
DISP
DGND
23
V–
4.6Measuring Techniques
Two im portant techn iques are used in the TC7129: successive integration and digital auto-zeroing. Successive integration is a refinement to the traditional dualslope conversion technique.
4.7Dual-Slope Conversion
A dual-slope conversion has two basic phases: integrate and de-integra te. During the integrate phase, th e
input signal is integrated for a fixed period of time; the
integrated volt age level is thus proporti onal to the inp ut
voltage. During the de-integrate phase, the integrated
voltage is ram pe d d ow n at a fixed slope, and a counter
counts the clock cycles until the integrator voltage
crosses zero . T he co un t is a me as u rem en t o f t he ti me
to ramp the integrated v oltag e to zero and i s, therefor e,
proportional to the input voltage being measured. This
count can then be sc aled an d disp layed as a mea surement of the input vol tage. F igure 4-8 shows the phases
of the dual-slope conversion.
Integrate
De-integrate
Zero
Crossing
TC7129
1 402
75 k
Ω
51 pF
Time
Figure 4-8:Dual-Slope Conversion.
The dual-slope method has a fundamental limitation.
The count can onl y stop on a c lock cycle, s o t hat me asurement accuracy is limited to the clock frequency. In
Figure 4-7:Oscillator Circuits.
addition, a delay in the zero-crossing comparator can
add to the inaccuracy. Figure 4-9 shows these errors in
an actual measurement.
2004 Microchip Technology Inc.DS21459C- page 11
Page 12
TC7129
r
Integrate
Time
De-integrate
Clock Pulses
Figure 4-9:Accuracy Errors in Dual-Slope Conversion.
Zero Integrate
and Latch
INT
1
Integrate
DE
1
De-integrate
REST X10
Overshoot due to zero-crossing between
clock pulses
Integrator Residue Voltage
Overshoot caused by comparato
delay of 1 clock pulse
DE
2
REST X10
DE
3
Zero Integrate
TC7129
Note: Shaded area greatly expanded in time and amplitude.
Figure 4-10:Integration Waveform.
Integrator
Residual Voltage
DS21459C-page 12 2004 Microchip Technology Inc.
Page 13
TC7129
4.8Successive Integration
The successive integration tech nique picks up where
dual-slope conversion ends. The overshoot voltage
shown in Figure 4-9 (called the “integrator residue
voltage”) is me asured to obtain a correction to the initial
count. Figure 4-10 shows the cycles in a successive
integration measurement.
The waveform shown is for a ne gative input s ignal. The
sequence of ev ents during the measure ment cycle is
shown in Table 4-1.
TABLE 4-1:MEASUREMENT CYCLE
SEQUENCE
PhaseDescription
INT
Input signal is integrated for fixed time (1000 clock
1
cycles on 2V scale, 10,000 on 200 mV).
Integrator voltage is ramped to zero. Counter
DE
1
counts up until zero-crossing to produce reading
accurate to 3-1/2 digits. Residue represents an
overshoot of the actual input voltage.
REST Rest; circuit settles.
X10Residue voltage is amplified 10 times and inverted.
Integrator voltage is ramped to zero. Counter
DE
2
counts down until zero-crossing to correct reading
to 4-1/2 digits. Residue represents an undershoot
of the actual input voltage.
REST Rest; circuit settles.
X10Residue voltage is amplified 10 times and inverted.
Integrator voltage is ramped to zero. Counter
DE
3
counts up until zero-crossing to correct reading to
5-1/2 digits. Residue is discarded.
4.9Digital Auto-Zeroing
To eliminate the effect of amplifier offset errors, the
TC7129 uses a digi tal auto-z eroing tech nique. Afte r the
input voltage is measured as described above, the
measurement is repeated with the inputs shorted
internally. The reading with inputs shorted is a
measurement of the internal errors and is subtracted
from the previous reading to obtain a corrected
measurement. Digit al auto -zeroing el iminates the need
for an external auto-zeroing capacitor used in other
ADCs.
4.10Inside the TC7129
Figure 4-11 shows a simplified block diagram of the
TC7129.
2004 Microchip Technology Inc.DS21459C- page 13
Page 14
TC7129
Low Battery Continuity
OSC1
OSC2
OSC3
RANGE
L/H
CONT
V–
DGND
V+
TC7129
Segment Drives
Latch, Decode Display Multiplexer
Up/Down Results Counter
Sequence Counter/Decoder
Control Logic
Analog Section
Backplane
Drives
Annunciator
Drive
V
DISP
DP
1
DP
2
UR/DP
OR/DP
REF HI
REF LO
INT OUT
INT IN
3
4
COMMONINHIIN
LO
Figure 4-11:TC7129 Functional Block Diagram.
IN HI
Common
IN LO
Continuity
INT
INT
1
INT
1
,
–
V
200 mV
REF HI
2
+
C
REF
REF LO
DE
DE
DE-DE+
DE+
DE–
INT
–
+
Continuity
Comparator
500 k
–
+
ZI, X10
REST
Ω
Buffer
R
INT
Figure 4-12:Integrator Block Diagram.
BUFF
C
INT
Integrator
–
+
100 pF
TC7129
X10
10
Comparator 1
pF
+
–
To Display Driver
To Digital
Section
Comparator 2
DS21459C-page 14 2004 Microchip Technology Inc.
Page 15
4.11Integrator Section
The integrator section includes the integrator, comparator, input buffer amplifier and analog switches (see
Table 4-2) used to change the circuit configuration
during the separate measurement phases described
earlier. (See Figure 4-12).
TABLE 4-2:SWITCH LEGENDS
LabelDescription
LabelMeaning.
DEOpen during all de-integrate phases.
DE–Closed during all de-integrate phases when
input voltage is negative.
DE+Closed during all de-integrate phases when
INT
INT
INTOpen during both integrate phases.
RESTClosed during the rest phase.
X10Closed during the X10 phase.
X10Open during the X10 phase.
The buffer amp li fier has a common mode inp ut vol t age
range from 1.5V above V– to 1V be low V+. The integrator amplifier can swing to within 0.3V of the rails.
However, for best linearity, the swing is usually limited
to within 1V. Both amplifiers can supply up to 80 µA of
output current, but should be limited to 20 µA for good
linearity.
input voltage is positive.
Closed during the first integrate phase
1
(measurement of the input voltage).
Closed during the second integrate phase
2
(measurement of the amplifier offset).
ZIClosed during the zero integrate phase.
TC7129
–
IN HI
COM
IN LO
CONT
200 mV
V
–
+
500 k
Ω
Figure 4-13:Continuity Indicator Circuit.
TC7129
DP4/OR, Pin 20
/UR, Pin 21
DP
LATCH/HOLD Pin 22
CONTINUITY, Pin 27
3
Figure 4-14:Input/Output Pin Schematic.
500 kΩ
+
Buffer
TC7129
To Display Driver
(Not Latched)
4.12Continuity Indicator
A comparator with a 200 mV threshold is connected
between IN HI (pin 33) and IN LO (pin 32). Whenever
the voltage between inputs is less than 200mV, the
CONTINUITY output (pin 27) will be pulled high,
activating the continuity annunciator on the display.
The continuity pin c an also be us ed as an input to drive
the continuity annunciator directly from an external
source (see Figure 4-13).
A schematic of the input/o utput nature of thi s pin is also
shown in Figure 4-14.
4.13Common and Digital Ground
The common and digital ground (DGND) outputs are
generated from internal zener diodes. The voltage
between V+ and DGND is the internal supply voltage
for the digital section of the TC7129. Common can
source approximately 12 µA; DGND has essentially no
source capability (se e Figure4-15).
2004 Microchip Technology Inc.DS21459C- page 15
Page 16
TC7129
24
V+
–
+
12 µA
N
Logic
Section
3.2V
COM
28
5V
36
P
DGND
TC7129
N
23
V–
Figure 4-15:Digital Ground (DGND) and
Common Outputs.
4.14Low Battery
The low battery annun ciato r turns o n whe n supp ly vo ltage between V– and V+ drop s below 6.8V. The internal
zener diode has a threshold of 6.3V. When the supply
voltage drop s below 6.8V, the transistor tied to V– turn s
off pulling the “Low Battery” point high.
4.15Sequence and Results Counter
A sequence counter and associated control logic provide signals that operate the analog switches in the
integrator section . The comparat or output from the integrator gates the res ults coun ter. The resul ts count er is
a six-sectio n up/down decade co unter that holds the
intermediate results from each successive integration.
4.16Overrange and Underrange
Outputs
When the results counter holds a value greater than
±19,999, the DP
When the results counter value is less than ±1000, the
DP3/UR output (Pin 21) is driven high. Both s ignal s are
valid on the falling edge of LATCH
not change until the end of the next conversion cycle.
The signals are upd ated a t the end o f each conv ersion,
unless the L
21 can also be used as inputs for external control of
decimal point s 3 a nd 4. Fig ure 4-14 shows a schematic
of the input/output nature of these pins.
/OR output (Pin 20) is driven high.
4
/HOLD (L/H) and do
/H input (Pin 22) is held high. Pins 20 and
4.17LATCH/Hold
The L/H output goes low during the last 100 cycles of
each conversion. This pulse latches the conversion
data into the display driv er secti on of the TC7129. Thi s
pin can also be used as an inp ut. When dr iven high, th e
display will not be updated; the previous reading is
displayed. When driven low, the display reading is not
latched; the sequence counter reading will be
displayed. Since the counter is counting much faster
than the backplanes are being updated, the reading
shown in this mode is somewhat erratic.
4.18Display Driver
The TC7129 drives a triplexed LCD with three backplanes. The LCD can include decimal points, polarity
sign and annunciators for continuity and low battery.
Figure 4-16 shows the assignment of the display
segments to the backplanes and segment drive lines.
The backplane drive frequency is obtained by dividing
the oscillator freq uency by 1200. Thi s result s in a b ackplane drive frequency of 100 Hz for 60 Hz operation
(120 kHz crystal) and 83.3 Hz for 50 Hz operation
(100 kHz crystal).
Backplane waveforms are shown in Figure 4-17.
These appear on outputs BP
and 18). They remain the s am e, re gard less of the segments being driven.
Other display output lines (pins 4 through 15) have
waveforms that vary depending on the displayed
values. Figure 4-18 shows a set of waveforms for the
A, G, D outputs (pins 5, 8, 11 and 14) for several
combinations of “ON” segments.
The ANNUNCIATOR DRIVE output (pin 3) is a square
wave, running at the backplane frequency (100 Hz or
83.3 H z) with a peak-to-peak voltage equal to DGND
voltage. Connec ting an an nunci ator to pin 3 turn s it on;
connecting it to its backplane turns it off.
, BP2, BP3 (pins 16, 17
1
DS21459C-page 16 2004 Microchip Technology Inc.
Page 17
TC7129
Low Battery
Continuity
BP
BP
1
2
Backplane
Connections
BP
3
Low BatteryContinuity
E
DP
F
4
4
4
,
,
G
D
A
4
4
4
,
,
C
BC
B
4
4
4
,
,
F
E
DP
3
3
3
,
,
G
D
A
3
3
3
,
,
C
MINUS
B
3
3
,
,
B
1
,
A
1
,
F
1
,
B
2
,
A
2
,
F
2
,
C
Continuity
1
,
G
D
1
,
E
DP
1
,
C
Low Battery
2
,
G
D
2
,
E
DP
2
,
1
1
2
2
Figure 4-16:Display Segment Assignments.
BP
1
BP
2
BP
3
Figure 4-17:Backplane Waveforms.
b Segment
Line
All Off
a Segment
On
d, g Off
a, g On
d Off
All On
Figure 4-18:Typical Display Output
Waveforms.
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DD
H
L
DISP
DD
H
L
DISP
DD
H
L
DISP
DD
H
L
DISP
2004 Microchip Technology Inc.DS21459C- page 17
Page 18
TC7129
5.0PACKAGING INFORMATION
5.1Package Marking Information
Package mar k ing data not available a this time.
5.2Taping Forms
Pin 1
User Direction of Feed
P, Pitch
Pin 1
W, Width
of Carrier
Tape
S tandard Reel Component Orientation
Component Taping Orientation for 44-Pin PQFP Devices
User Direction of Feed
Reverse Reel Component Orientation
PIN 1
W
P
Standard Reel Component Orientation
for TR Suffix Device
Carrier Tape, Number of Components Per Reel and Reel Size
Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size
44-Pin PQFP 24 mm 16 mm 500 13 in
Note: Drawing does not represent total number of pins.
DS21459C-page 18 2004 Microchip Technology Inc.
Page 19
40-Lead Plastic Dual In-line (P) – 600 mil Body (PDIP)
E1
D
TC7129
2
n
E
β
eB
Number of Pins
Pitch
Lead Thickness
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-011
Drawing No. C04-016
Lower Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-047
Drawing No. C04-048
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.Your local Microchip sales office
2.The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3.The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2004 Microchip Technology Inc.DS21459C-page 21
Page 24
TC7129
NOTES:
DS21459C-page 22 2004 Microchip Technology Inc.
Page 25
Note the following details of the code protection feature on Microchip devices:
•Microchip products meet the specification contained in their particular Microchip Data Sheet.
•Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•Microchip is willing to work with the customer who is concerned about the integrity of their code.
•Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are com mitted to continuously improving the code protect ion f eatures of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Mill ennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K
EELOQ, microID, MPLAB, PIC, PICmicro,
PICSTART, PRO MATE, PowerSmart, rfPIC, and
SmartShunt are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL,
SmartSensor and The Embedded Control Solutions Company
are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Migratable Memory, MPASM,
MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,
PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial,
SmartTel and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
®
8-bit MCUs, KEELOQ
®
code hopping
2004 Microchip Technology Inc.DS21459C-page 23
Page 26
WORLDWIDE SALESAND SERVICE
AMERICAS
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
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