Microchip Technology PIC32MX5XX, PIC32MX6XX, PIC32MX7XX Datasheet

EN: This Datasheet is present ed by the manufacturer.

Please visit our website for pricing and ava ilability at

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PIC32MX5XX/6XX/7XX

Family Data Sheet

High-Performance, USB, CAN and Ethernet

32-bit Flash Microcontrollers

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

ISBN: 978-1-60932-717-0

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and T empe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC devices, Serial EEPROMs, microperipherals, nonvolatile memo ry and analog products. In addition, Microchip’s quality system for the desig n and manufacture of development systems is ISO 9001:2000 certified.

®

MCUs and dsPIC® DSCs, KEELOQ

®

code hopping

PIC32MX5XX/6XX/7XX

High-Performance, USB, CAN and Ethernet

32-bit Flash Microcontrollers

High-Performance 32-bit RISC CPU:

• MIPS32® M4K® 32-bit core with 5-stage pipeline

• 80 MHz maximum frequency

• 1.56 DMIPS/MHz (Dhrystone 2.1) performance

at zero Wait state Flash access

• Single-cycle multiply and high-performance divide

unit

• MIPS16e

• Two sets of 32 core register files (32-bit) to reduce

interrupt latency

• Prefetch Cache module to speed execution from

Flash

®

mode for up to 40% smaller code size

Microcontroller Features:

• Operating voltage range of 2.3V to 3.6V

• 64K to 512K Flash memory (plus an

additional 12 KB of Boot Flash)

• 16K to 128K SRAM memory

• Pin-compatible with most PIC24/dsPIC

devices

• Multiple power management modes

• Multiple interrupt vectors with individually

programmable priority

• Fail-Safe Clock Monitor mode

• Configurable Watchdog Timer with on-chip

Low-Power RC oscillator for reliable operation

®

DSC

Peripheral Features:

• Atomic SET, CLEAR and INVERT operation on

select peripheral registers

• Up to 8-channels of hardware DMA with automatic

data size detection

• USB 2.0-compliant full-speed device and

On-The-Go (OTG) controller:

- Dedicated DMA channels

• 10/100 Mbps Ethernet MAC with MII and RMII

interface:

- Dedicated DMA channels

• CAN module:

- 2.0B Active with DeviceNet™ addressing support

- Dedicated DMA channels

• 3 MHz to 25 MHz crystal oscillator

Peripheral Features (Continued):

• Internal 8 MHz and 32 kHz oscillators

• Six UART modules with:

- RS-232, RS-485 and LIN support

-IrDA

• Up to four SPI modules

• Up to five I

• Separate PLLs for CPU and USB clocks

• Parallel Master and Slave Port (PMP/PSP) with 8-bit and 16-bit data, and up to 16 address lines

• Hardware Real-Time Clock and Calendar (RTCC)

• Five 16-bit Timers/Counters (two 16-bit pairs combine to create two 32-bit timers)

• Five Capture inputs

• Five Compare/PWM outputs

• Five external interrupt pins

• High-speed I/O pins capable of toggling at up to 80 MHz

• High-current sink/source (18 mA/18 mA) on all I/O pins

• Configurable open-drain output on digital I/O pins

®

with on-chip hardware encoder and

decoder

2

C™ modules

Debug Features:

• Two programming and debugging Interfaces:

- 2-wire interface with unintr u s ive access and

real-time data exchange with application

- 4-wire MIPS

Action Group (JTAG) interface

• Unintrusive hardware-based instruction trace

• IEEE Standard 1149.2 compatible (JTAG) boundary scan

®

standard enhanced Joint Test

Analog Features:

• Up to 16-channel, 10-bit Analog-to-Digital Converter:

- 1 Msps conversion rate

- Conversion available during Sleep and Idle

• Two Analog Comparators

PIC32MX5XX/6XX/7XX

TABLE 1: PIC32 USB AND CAN – FEATURES

USB and CAN

Device

Pins

Program Memory (KB)

PIC32MX534F064H 64 64 + 12

PIC32MX564F064H 64 64 + 12

PIC32MX564F128H 64 128 + 12

PIC32MX575F256H 64 256 + 12

PIC32MX575F512H 64 512 + 12

PIC32MX534F064L 100 64 + 12

PIC32MX564F064L 100 64 + 12

PIC32MX564F128L 100 128 + 12

PIC32MX575F256L 100 256 + 12

PIC32MX575F512L 100 512 + 12

(1)

USB

CAN

DMA Channels

Data Memory (KB)

(Programmable/

Timers/Capture/Compare

16 1 1 5/5/5 4/4 6 3 4 16 2 Yes Yes No

32 1 1 5/5/5 4/4 6 3 4 16 2 Yes Yes No

64 1 1 5/5/5 8/4 6 3 4 16 2 Yes Yes No

16 1 1 5/5/5 4/4 6 4 5 16 2 Yes Yes Yes

32 1 1 5/5/5 4/4 6 4 5 16 2 Yes Yes Yes

64 1 1 5/5/5 8/4 6 4 5 16 2 Yes Yes Yes

Legend: PF, PT = TQFP MR = QFN BG = XBGA Note 1: This device features 12 KB boot Flash memory.

2: CTS and RTS pins may not be available for all UART modules. Refer to the “

information.

3: Some pins between the UART, SPI and I

2

C modules may be shared. Refer to the “

information.

4: Refer to

32.0 “Packaging Information” for more information.

Dedicated)

(4)

Trace

Packages

(3)

SPI

(3)

2

C™ I

(Channels)

JTAG

PMP/PSP

Comparators

(2,3)

UART

10-bit 1 Msps ADC

PT, MR

PT, PF, BG

Pin Diagrams” section for more

TABLE 2: PIC32 USB AND ETHERNET – FEATURES

USB and Ethernet

PIC32MX5XX/6XX/7XX

Device

Pins

Program Memory (KB)

PIC32MX664F064H 64 64 + 12

PIC32MX664F128H 64 128 + 12

PIC32MX675F256H 64 256 + 12

PIC32MX675F512H 64 512 + 12

PIC32MX695F512H 64 512 + 12

PIC32MX664F064L 100 64 + 12

PIC32MX664F128L 100 128 + 12

PIC32MX675F256L 100 256 + 12

PIC32MX675F512L 100 512 + 12

PIC32MX695F512L 100

512 + 12

(1)

USB

Ethernet

DMA Channels

Data Memory (KB)

(Programmable/

Timers/Capture/Compare

32 1 1 5/5/5 4/4 6 3 4 16 2 Yes Yes No

64 1 1 5/5/5 8/4 6 3 4 16 2 Yes Yes No

128 1 1 5/5/5 8/4 6 3 4 16 2 Yes Yes No

32 1 1 5/5/5 4/4 6 4 5 16 2 Yes Yes Yes

64 1 1 5/5/5 8/4 6 4 5 16 2 Yes Yes Yes

128 1 1 5/5/5 8/4 6 4 5 16 2 Yes Yes Yes

Legend: PF, PT = TQFP MR = QFN BG = XBGA Note 1: This device features 12 KB boot Flash memory.

2: CTS and RTS pins may not be available for all UART modules. Refer to the “

information.

3: Some pins between the UART, SPI and I

2

C modules may be shared. Refer to the “

information.

4: Refer to

32.0 “Packaging Information” for more information.

(4)

Trace

Packages

(3)

SPI

(3)

2

C™ I

(Channels)

Comparators

JTAG

PMP/PSP

(2,3)

UART

Dedicated)

10-bit 1 Msps ADC

PT, MR

PT, PF, BG

Pin Diagrams” section for more

PIC32MX5XX/6XX/7XX

TABLE 3: PIC32 USB, ETHERNET AND CAN – FEATURES

USB, Ethernet and CAN

Device

Pins

Program Memory (KB)

PIC32MX764F128H 64 128 + 12

PIC32MX775F256H 64 256 + 12

PIC32MX775F512H 64 512 + 12

PIC32MX795F512H 64 512 + 12

PIC32MX764F128L 100 128 + 12

PIC32MX775F256L 100 256 + 12

PIC32MX775F512L 100 512 + 12

PIC32MX795F512L 100 512 + 12

(1)

USB

Data Memory (KB)

CAN

Ethernet

DMA Channels

Timers/Capture/Compare

32 1 1 1 5/5/5 4/6 6 3 4 16 2 Yes Yes No

64 1 1 2 5/5/5 8/8 6 3 4 16 2 Yes Yes No

128 1 1 2 5/5/5 8/8 6 3 4 16 2 Yes Yes No

32 1 1 1 5/5/5 4/6 6 4 5 16 2 Yes Yes Yes

64 1 1 2 5/5/5 8/8 6 4 5 16 2 Yes Yes Yes

128 1 1 2 5/5/5 8/8 6 4 5 16 2 Yes Yes Yes

Legend: PF, PT = TQFP MR = QFN BG = XBGA Note 1: This device features 12 KB boot Flash memory.

2: CTS and RTS pins may not be available for all UART modules. Refer to the “

information.

3: Some pins between the UART, SPI and I

2

C modules may be shared. Refer to the “

information.

4: Refer to

32.0 “Packaging Information” for more information.

(4)

Trace

Packages

(3)

SPI

(3)

2

C™ I

10-bit 1 Msps ADC

(Channels)

JTAG

PMP/PSP

Comparators

(2,3)

UART

Dedicated)

(Programmable/

PT, MR

PT, PF, BG

Pin Diagrams” section for more

Pin Diagrams

64-Pin QFN

(1)

= Pins are up to 5V tolerant

Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be

connected to VSS externally.

PIC32MX575F256H

PMD5/RE5 PMD6/RE6 PMD7/RE7

SCK2/U6TX/U3RTS

/PMA5/CN8/RG6

VDD

AN5/C1IN+/VBUSON/CN7/RB5

AN4/C1IN-/CN6/RB4

AN3/C2IN+/CN5/RB3

AN2/C2IN-/CN4/RB2

SDA4/SDI2/U3RX/PMA4/CN9/RG7

SCL4/SDO2/U3TX/PMA3/CN10/RG8

PGEC1/AN1/V

REF-/CVREF-/CN3/RB1

PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0

SS2

/U6RX/U3CTS/PMA2/CN11/RG9

MCLR

VSS

64 63 6261 60 59 58 57 56 55

22 23 24 25 26 27 2829 30 31

3

40 39 38 37 36 35 34 33

4 5

7 8

9 10 11

1

2

42 41

6

32

43

54

14 15 16

12 13

17

18 19 20 21

45 44

47 46

48

53

52 51 5049

AVDD

AN8/SS4

/U5RX/U2CTS/C1OUT/RB8

AN9/C2OUT/PMA7/RB9

TMS/AN10/CVREFOUT/PMA13/RB10

TDO/AN11/PMA12/RB11

VDD

PGEC2/AN6/OCFA/RB6

PGED2/AN7/RB7

AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5

AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4

TCK/AN12/PMA11/RB12

TDI/AN13/PMA10/RB13

AN14/SCK4/U5TX/U2RTS

/PMALH/PMA1/RB14

AN15/OCFB/PMALL/PMA0/CN12/RB15

VSS

AVSS

CN15/RD6

PMRD/CN14/RD5

OC5/IC5/PMWR/CN13/RD4

SCL3/SDO3/U1TX/OC4/RD3

SDA3/SDI3/U1RX/OC3/RD2

SCK3/U4TX/U1RTS

/OC2/RD1

PMD4/RE4

PMD3/RE3

PMD2/RE2

PMD1/RE1

C1RX/RF0

VCAP/VCORE

PMD0/RE0

C1TX/RF1

CN16/RD7

V

DD

SOSCI/CN1/RC13 OC1/INT0/RD0

SCL1/IC3/PMCS2/PMA15/INT3/RD10 SS3

/U4RX/U1CTS/SDA1/IC2/INT2/RD9

RTCC/IC1/INT1/RD8

IC4/PMCS1/PMA14/INT4/RD11

OSC2/CLKO/RC15 OSC1/CLKI/RC12 V

DD

D+/RG2

VUSB VBUS USBID/RF3

D-/RG3

SOSCO/T1CK/CN0/RC14

Vss

PIC32MX575F512H

PIC32MX534F064H PIC32MX564F064H PIC32MX564F128H

PIC32MX5XX/6XX/7XX

64-Pin QFN

(1)

= Pins are up to 5V tolerant

PIC32MX675F512H PIC32MX695F512H

PIC32MX675F256H

22 23 24 25 26 27 28 29 30 31

40 39 38 37 36 35 34 33

42 41

32

43

17 18 19 20 21

45 44

47 46

48

AV

DD

AN8/SS4/U5RX/U2CTS/C1OUT/RB8

AN9/C2OUT/PMA7/RB9

TMS/AN10/CV

REFOUT

/PMA13/RB10

TDO/AN11/PM A12/RB11

V

DD

PGEC2/AN6/OCFA /RB6

PGED2/AN7/RB7

SCL5/SDO4/U2TX/PMA8/CN18/RF5

SDA5/SDI4/U2RX/PMA9/CN17/RF4

TCK/AN12/PMA1 1/RB12

TDI/AN13/PMA10/RB13

AN14/SCK4/U5TX/U2RTSU2R TS

/PMALH/PMA1/RB14

AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15

V

SS

AV

SS

SOSCI/CN1/RC13 OC1/INT0/RD0

ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10 AERXD0/ETXD2/SS3

/U4RX/U1CTS/SDA1/IC2/INT2/RD9

RTCC/AERXD1/ETXD3/IC1/INT1/RD8

ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11

OSC2/CLKO/RC15 OSC1/CLKI/RC12 V

DD

D+/RG2

V

USB

V

BUS

USBID/RF3

D-/RG3

SOSCO/T1CK/CN0/RC14

Vss

ETXEN/PMD5/RE5

ETXD0/PMD6/RE6 ETXD1/PMD7/RE7

SCK2/U6TX/U3RTS

/PMA5/CN8/RG6

V

DD

AN5/C1IN+/V

BUSON

/CN7/RB5

AN4/C1IN-/CN6/RB4

AN3/C2IN+/CN5/RB3

AN2/C2IN-/CN4/RB2

SDA4/SDI2/U3RX/PMA4/CN9/RG7

SCL4/SDO2/U3TX/PMA3/CN10/RG8

PGEC1/AN1/V

REF

-/CV

REF

-/CN3/RB1

PGED1/AN0/V

REF

+/CV

REF

+/PMA6/CN2/RB0

SS2

/U6RX/U3CTS/PMA2/ CN11/RG9

MCLR

V

SS

64 63 62 61 60 59 58 57 56 55

3 4 5

7 8

9 10 11

1

2

6

54

14 15 16

12 13

53 52 51 50 49

AETXEN/ETXERR/CN15/RD6

PMRD/CN14/RD5

OC5/IC5/PMWR/CN13/RD4

SCL3/SDO3/U1TX/OC4/RD3

SDA3/SDI3/U1RX/OC3/RD2

EMDIO/AEMDIO/SCK3/U4TX/U1RTS

/OC2/RD1

ERXERR/PMD4/RE4

ERXCLK/EREFCLK/PMD3/RE3

ERXDV/ECRSDV/PMD2/RE2

ERXD0/PMD1/RE1

AETXD1/ERXD3/RF0

V

CAP

/V

CORE

ERXD1/PMD0/RE0

AETXD0/ERXD2/RF1

ETXCLK/AERXERR/CN16/RD7

V

DD

Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be

connected to VSS externally.

PIC32MX664F064H PIC32MX664F128H

Pin Diagrams (Continued)

64-Pin QFN

(1)

= Pins are up to 5V tolerant

ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7

SCK2/U6TX/U3RTS

/PMA5/CN8/RG6

V

DD

AN5/C1IN+/V

BUSON

/CN7/RB5

AN4/C1IN-/CN6/RB4

AN3/C2IN+/CN5/RB3

AN2/C2IN-/CN4/RB2

SDA4/SDI2/U3RX/PMA4/CN9/RG7

SCL4/SDO2/U3TX/PMA3/CN10/RG8

PGEC1/AN1/V

REF

-/CV

REF

-/CN3/RB1

PGED1/AN0/V

REF

+/CV

REF

+/PMA6/CN2/RB0

SS2

/U6RX/U3CTS/PMA2/CN11/RG9

MCLR

V

SS

64 63 62 61 60 59 58 57 56 55

3

4

5

7

8

9 10 11

1

2

6

54

14 15 16

12 13

53 52 51 50 49

AETXEN/ETXERR/CN15/RD6

PMRD/CN14/RD5

OC5/IC5/PMWR/CN13/RD4

SCL3/SDO3/U1TX/OC4/RD3

SDA3/SDI3/U1RX/OC3/RD2

EMDIO/AEMDIO/SCK3/U4TX/U1RTS

/OC2/RD1

ERXERR/PMD4/RE4

ERXCLK/EREFCLKPMD3/RE3

ERXDV/ECRSDV/PMD2/RE2

ERXD0/PMD1/RE1

C1RX/AETXD1/ERXD3/RF0

V

CAP

/V

CORE

ERXD1/PMD0/RE0

C1TX/AETXD0/ERXD2/RF1

ETXCLK/AERXERR/CN16/RD7

V

DD

PIC32MX795F512H

PIC32MX775F256H PIC32MX775F512H

22 23 24 25 26 27 28 29 30 31

40 39 38 37 36 35 34

33

42 41

32

43

17 18 19 20 21

45 44

47 46

48

AV

DD

AN8/C2TX/SS4/U5RX/U2CTS/C1OUT/RB8

AN9/C2OUT/PMA7/RB9

TMS/AN10/CV

REFOUT

/PMA13/RB10

TDO/AN11/PMA12/RB11

V

DD

PGEC2/AN6/OCFA/RB6

PGED2/AN7/RB7

AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5

AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4

TCK/AN12/PMA11/RB12

TDI/AN13/PMA10/RB13

AN14/C2RX/SCK4/U5TX/U2RTS

/PMALH/PMA1/RB14

AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15

V

SS

AV

SS

SOSCI/CN1/RC13 OC1/INT0/RD0

ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10 AERXD0/ETXD2/SS3

/U4RX/U1CTS/SDA1/IC2/INT2/RD9

RTCC/AERXD1/ETXD3/IC1/INT1/RD8

ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11

OSC2/CLKO/RC15 OSC1/CLKI/RC12 V

DD

D+/RG2

V

USB

V

BUS

USBID/RF3

D-/RG3

SOSCO/T1CK/CN0/RC14

Vss

Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be

connected to VSS externally.

PIC32MX5XX/6XX/7XX

64-Pin QFN

(1)

= Pins are up to 5V tolerant

ETXEN/PMD5/RE5

ETXD0/PMD6/RE6 ETXD1/PMD7/RE7

SCK2/U6TX/U3RTS

/PMA5/CN8/RG6

V

DD

AN5/C1IN+/V

BUSON

/CN7/RB5

AN4/C1IN-/CN6/RB4

AN3/C2IN+/CN5/RB3

AN2/C2IN-/CN4/RB2

SDA4/SDI2/U3RX/PMA4/CN9/RG7

SCL4/SDO2/U3TX/PMA3/CN10/RG8

PGEC1/AN1/V

REF

-/CV

REF

-/CN3/RB1

PGED1/AN0/V

REF

+/CV

REF

+/PMA6/CN2/RB0

SS2

/U6RX/U3CTS/PMA2/CN11/RG9

MCLR

V

SS

64 63 62 61 60 59 58 57 56 55

3 4 5

7 8

9 10 11

1

2

6

54

14 15 16

12 13

53 52 51 50 49

AETXEN/ETXERR/CN15/RD6

PMRD/CN14/RD5

OC5/IC5/PMWR/CN13/RD4

SCL3/SDO3/U1TX/OC4/RD3

SDA3/SDI3/U1RX/OC3/RD2

EMDIO/AEMDIO/SCK3/U4TX/U1RT S

/OC2/RD1

ERXERR/PMD4/RE4

ERXCLK/EREFCLKPMD3/RE3

ERXDV/ECRSDV/PMD2/RE2

ERXD0/PMD1/RE1

C1RX/AETXD1/ERXD3/RF0

V

CAP

/V

CORE

ERXD1/PMD0/RE0

C1TX/AETXD0/ERXD2/RF1

ETXCLK/AERXERR/CN16/RD7

V

DD

PIC32MX764F128H

22 23 24 25 26 27 28 29 30 31

40 39 38 37 36 35 34

33

42 41

32

43

17 18 19 20 21

45 44

47 46

48

AV

DD

AN8/SS4/U5RX/U2CTS/C1OUT/RB8

AN9/C2OUT/PMA7/RB9

TMS/AN10/CV

REFOUT

/PMA13/RB10

TDO/AN11/PMA12/RB11

V

DD

PGEC2/AN6/OCFA /RB6

PGED2/AN7/RB7

AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5

AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4

TCK/AN12/PMA1 1/RB12

TDI/AN13/PMA10/RB13

AN14/SCK4/U5TX/U2RTS

/PMALH/PMA1/RB14

AN15/EMDC/AEMDC/OCFB/PMALL/PM A0/C N12/RB15

V

SS

AV

SS

SOSCI/CN1/RC13 OC1/INT0/RD0

ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10 AERXD0/ETXD2/SS3

/U4RX/U1CTS/SDA1/IC2/INT2/RD9

RTCC/AERXD1/ETXD3/IC1/INT1/RD8

ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11

OSC2/CLKO/RC15 OSC1/CLKI/RC12 V

DD

D+/RG2

V

USB

V

BUS

USBID/RF3

D-/RG3

SOSCO/T1CK/CN0/RC14

Vss

Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be

connected to VSS externally.

Pin Diagrams (Continued)

64-Pin TQFP

= Pins are up to 5V tolerant

PIC32MX575F256H

PMD5/RE5 PMD6/RE6 PMD7/RE7

SCK2/U6TX/U3RTS

/PMA5/CN8/RG6

V

DD

AN5/C1IN+/V

BUSON

/CN7/RB5

AN4/C1IN-/CN6/RB4

AN3/C2IN+/CN5/RB3

AN2/C2IN-/CN4/RB2

SDA4/SDI2/U3RX/PMA4/CN9/RG7

SCL4/SDO2/U3TX/PMA3/CN10/RG8

PGEC1/AN1/V

REF

-/CV

REF

-/CN3/RB1

PGED1/AN0/V

REF

+/CV

REF

+/PMA6/CN2/RB0

SS2

/U6RX/U3CTS/PMA2/CN11/RG9

MCLR

V

SS

64 63 62 61 60 59 58 57 56 55

22 23 24 25 26 27 28 29 30 31

3

40 39 38 37 36 35 34 33

4 5

7 8

9 10 11

1

2

42 41

6

32

43

54

14 15 16

12 13

17

18 19 20 21

45 44

47 46

48

53

52 51 50 49

AV

DD

AN8/SS4/U5RX/U2CTS/C1OUT/RB8

AN9/C2OUT/PMA7/RB9

TMS/AN10/CV

REFOUT

/PMA13/RB10

TDO/AN11/PMA12/RB11

V

DD

PGEC2/AN6/OCFA/RB6

PGED2/AN7/RB7

AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5

AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4

TCK/AN12/PMA11/RB12

TDI/AN13/PMA10/RB13

AN14/SCK4/U5TX/U2RTS

/PMALH/PMA1/RB14

AN15/OCFB/PMALL/PMA0/CN12/RB15

V

SS

AV

SS

CN15/RD6

PMRD/CN14/RD5

OC5/IC5/PMWR/CN13/RD4

SCL3/SDO3/U1TX/OC4/RD3

SDA3/SDI3/U1RX/OC3/RD2

SCK3/U4TX/U1RTS

/OC2/RD1

PMD4/RE4

PMD3/RE3

PMD2/RE2

PMD1/RE1

C1RX/RF0

V

CAP

/V

CORE

PMD0/RE0

C1TX/RF1

CN16/RD7

V

DD

SOSCI/CN1/RC13 OC1/INT0/RD0

SCL1/IC3/PMCS2/PMA15/INT3/RD10 SS3

/U4RX/U1CTS/SDA1/IC2/INT2/RD9

RTCC/IC1/INT1/RD8

IC4/PMCS1/PMA14/INT4/RD11

OSC2/CLKO/RC15 OSC1/CLKI/RC12 V

DD

D+/RG2

V

USB

V

BUS

USBID/RF3

D-/RG3

SOSCO/T1CK/CN0/RC14

Vss

PIC32MX575F512H

PIC32MX534F064H PIC32MX564F064H PIC32MX564F128H

PIC32MX5XX/6XX/7XX

64-Pin TQFP

= Pins are up to 5V tolerant

PIC32MX675F512H PIC32MX695F512H

PIC32MX675F256H

ETXEN/PMD5/RE5

ETXD0/PMD6/RE6 ETXD1/PMD7/RE7

SCK2/U6TX/U3RTS

/PMA5/CN8/RG6

V

DD

AN5/C1IN+/V

BUSON

/CN7/RB5

AN4/C1IN-/CN6/RB4

AN3/C2IN+/CN5/RB3

AN2/C2IN-/CN4/RB2

SDA4/SDI2/U3RX/PMA4/CN9/RG7

SCL4/SDO2/U3TX/PMA3/CN10/RG8

PGEC1/AN1/V

REF

-/CV

REF

-/CN3/RB1

PGED1/AN0/V

REF

+/CV

REF

+/PMA6/CN2/RB0

SS2

/U6RX/U3CTS/PMA2/CN11/RG9

MCLR

V

SS

64 63 62 61 60 59 58 57 56 55

3 4 5

7 8

9 10 11

1

2

6

54

14 15 16

12 13

53 52 51 50 49

AETXEN/ETXERR/CN15/RD6

PMRD/CN14/RD5

OC5/IC5/PMWR/CN13/RD4

SCL3/SDO3/U1TX/OC4/RD3

SDA3/SDI3/U1RX/OC3/RD2

EMDIO/AEMDIO/SCK3/U4TX/U1RTS

/OC2/RD1

ERXERR/PMD4/RE4

ERXCLK/EREFCLK/PMD3/RE3

ERXDV/ECRSDV/PMD2/RE2

ERXD0/PMD1/RE1

AETXD1/ERXD3/RF0

V

CAP

/V

CORE

ERXD1/PMD0/RE0

AETXD0/ERXD2/RF1

ETXCLK/AERXERR/CN16/RD7

V

DD

22 23 24 25 26 27 28 29 30 31

40 39 38 37 36 35 34 33

42 41

32

43

17 18 19 20 21

45 44

47 46

48

AV

DD

AN8/SS4/U5RX/U2CTS/C1OUT/RB8

AN9/C2OUT/PMA7/RB9

TMS/AN10/CV

REFOUT

/PMA13/RB10

TDO/AN11/PMA12/RB11

V

DD

PGEC2/AN6/OCFA/R B6

PGED2/AN7/RB7

SCL5/SDO4/U2TX/PMA8/CN18/RF5

SDA5/SDI4/U2RX/PMA9/CN17/RF4

TCK/AN12/PMA11/RB12

TDI/AN13/PMA10/RB13

AN14/SCK4/U5TX/U2RTS

/PMALH/PMA1/RB14

AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN 12/RB 15

V

SS

AV

SS

SOSCI/CN1/RC13 OC1/INT0/RD0

ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10 AERXD0/ETXD2/SS3

/U4RX/U1CTS/SDA1/IC2/INT2/RD9

RTCC/AERXD1/ETXD3/IC1/INT1/RD8

ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11

OSC2/CLKO/RC15 OSC1/CLKI/RC12 V

DD

D+/RG2

V

USB

V

BUS

USBID/RF3

D-/RG3

SOSCO/T1CK/CN0/RC14

Vss

PIC32MX664F064H PIC32MX664F128H

Pin Diagrams (Continued)

64-Pin TQFP

= Pins are up to 5V tolerant

PIC32MX795F512H

PIC32MX775F256H PIC32MX775F512H

ETXEN/PMD5/RE5

ETXD0/PMD6/RE6 ETXD1/PMD7/RE7

SCK2/U6TX/U3RTS

/PMA5/CN8/RG6

V

DD

AN5/C1IN+/V

BUSON

/CN7/RB5

AN4/C1IN-/CN6/RB4

AN3/C2IN+/CN5/RB3

AN2/C2IN-/CN4/RB2

SDA4/SDI2/U3RX/PMA4/CN9/RG7

SCL4/SDO2/U3TX/PMA3/CN10/RG8

PGEC1/AN1/V

REF

-/CV

REF

-/CN3/RB1

PGED1/AN0/V

REF

+/CV

REF

+/PMA6/CN2/RB0

SS2

/U6RX/U3CTS/PMA2/CN11/RG9

MCLR

V

SS

64 63 62 61 60 59 58 57 56 55

3

4

5

7

8

9 10 11

1

2

6

54

14 15 16

12 13

53

52 51 50 49

AETXEN/ETXERR/CN15/RD6

PMRD/CN14/RD5

OC5/IC5/PMWR/CN13/RD4

SCL3/SDO3/U1TX/OC4/RD3

SDA3/SDI3/U1RX/OC3/RD2

EMDIO/AEMDIO/SCK3/U4TX/U1RTS

/OC2/RD1

ERXERR/PMD4/RE4

ERXCLK/EREFCLK/PMD3/RE3

ERXDV/ECRSDV/PMD2/RE2

ERXD0/PMD1/RE1

C1RX/AETXD1/ERXD3/RF0

V

CAP

/V

CORE

ERXD1/PMD0/RE0

C1TX/AETXD0/ERXD2/RF1

ETXCLK/AERXERR/CN16/RD7

V

DD

22 23 24 25 26 27 28 29 30 31

40 39 38 37 36 35 34 33

42 41

32

43

17

18 19 20 21

45 44

47 46

48

AV

DD

AN8/C2TX/SS4/U5RX/U2CTS/C1OU T/RB8

AN9/C2OUT/PMA7/RB9

TMS/AN10/CV

REFOUT

/PMA13/RB10

TDO/AN11/PMA12/RB11

V

DD

PGEC2/AN6/OCFA /RB6

PGED2/AN7/RB7

AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5

AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4

TCK/AN12/PMA11/RB12

TDI/AN13/PMA10/RB13

AN14/C2RX/SCK4/U5TX/U2RTS

/PMALH/PMA1/RB14

AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15

V

SS

AV

SS

SOSCI/CN1/RC13 OC1/INT0/RD0

ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10 AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT 2/RD9 RTCC/AERXD1/ETXD3/IC1/INT1/RD8

ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11

OSC2/CLKO/RC15 OSC1/CLKI/RC12 V

DD

D+/RG2

V

USB

V

BUS

USBID/RF3

D-/RG3

SOSCO/T1CK/CN0/RC14

Vss

PIC32MX5XX/6XX/7XX

64-Pin TQFP

= Pins are up to 5V tolerant

PIC32MX764F128H

ETXEN/PMD5/RE5

ETXD0/PMD6/RE6 ETXD1/PMD7/RE7

SCK2/U6TX/U3RTS

/PMA5/CN8/RG6

V

DD

AN5/C1IN+/V

BUSON

/CN7/RB5

AN4/C1IN-/CN6/RB4

AN3/C2IN+/CN5/RB3

AN2/C2IN-/CN4/RB2

SDA4/SDI2/U3RX/PMA4/CN9/RG7

SCL4/SDO2/U3TX/PMA3/CN10/RG8

PGEC1/AN1/V

REF

-/CV

REF

-/CN3/RB1

PGED1/AN0/V

REF

+/CV

REF

+/PMA6/CN2/RB0

SS2

/U6RX/U3CTS/PMA2/CN11/RG9

MCLR

V

SS

64 63 62 61 60 59 58 57 56 55

3

4

5

7

8

9 10 11

1

2

6

54

14 15 16

12 13

53 52 51 50 49

AETXEN/ETXERR/CN15/RD6

PMRD/CN14/RD5

OC5/IC5/PMWR/CN13/RD4

SCL3/SDO3/U1TX/OC4/RD3

SDA3/SDI3/U1RXU1RX/OC3/RD2

EMDIO/AEMDIO/SCK3/U4TX/U1RTS

/OC2/RD1

ERXERR/PMD4/RE4

ERXCLK/EREFCLK/PMD3/RE3

ERXDV/ECRSDV/PMD2/RE2

ERXD0/PMD1/RE1

C1RX/AETXD1/ERXD3/RF0

V

CAP

/V

CORE

ERXD1/PMD0/RE0

C1TX/AETXD0/ERXD2/RF1

ETXCLK/AERXERR/CN16/RD7

V

DD

22 23 24 25 26 27 28 29 30 31

40 39 38 37 36 35 34 33

42 41

32

43

17 18 19 20 21

45 44

47 46

48

AV

DD

AN8/SS4/U5RX/U2CTS/C1OUT/RB8

AN9/C2OUT/PMA7/RB9

TMS/AN10/CV

REFOUT

/PMA13/RB10

TDO/AN11/PMA12/RB11

V

DD

PGEC2/AN6/OCFA/RB6

PGED2/AN7/RB7

AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5

AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4

TCK/AN12/PMA1 1/RB 12

TDI/AN13/PMA10/RB13

AN14/SCK4/U5TX/U2RTS

/PMALH/PMA1/RB14

AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15

V

SS

AV

SS

SOSCI/CN1/RC13 OC1/INT0/RD0

ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10 AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT 2/RD9 RTCC/AERXD1/ETXD3/IC1/INT1/RD8

ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11

OSC2/CLKO/RC15 OSC1/CLKI/RC12 V

DD

D+/RG2

V

USB

V

BUS

USBID/RF3

D-/RG3

SOSCO/T1CK/CN0/RC14

Vss

Pin Diagrams (Continued)

PMRD/CN14/RD5

OC5/PMWR/CN13/RD4

PMD13/CN19/RD13

IC5/PMD12/RD12

OC4/RD3

OC3/RD2

OC2/RD1

TRD3/RA7

TRCLK/RA6

PMD2/RE2

TRD0/RG13

TRD1/RG12

TRD2/RG14

PMD1/RE1

PMD0/RE0

PMD8/RG0

PMD4/RE4

PMD3/RE3

C1RX/PMD11/RF0

SOSCI/CN1/RC13 SDO1/OC1/INT0/RD0

SCK1/IC3/PMCS2/PMA15/RD10 SS1/

IC2

/RD9

RTCC/IC1/RD8

IC4/PMCS1/PMA14/RD11

SDA1/INT4/RA15 SCL1/INT3/RA14

OSC2/CLKO/RC15 OSC1/CLKI/RC12 V

DD

D+/RG2

V

USB

V

BUS

SCL3/SDO3/U1TX/RF8

D-/RG3

SDA3/SDI3/U1RX/RF2 USBID/RF3

V

SS

SOSCO/T1CK/CN0/RC14

V

REF

+/CV

REF

+/PMA6/RA10

V

REF

-/CV

REF

-/PMA7/RA9

AV

DD

AV

SS

AN8/C1OUT/RB8

AN9/C2OUT/RB9

AN10/CV

REFOUT

/PMA13/RB10

AN11/PMA12/RB11

V

DD

AC1RX/SS4/U5RX/U2CTS/RF12

AC1TX/SCK4/U5TX/U2RTS

/RF13

SS3

/U4RX/U1CTS/CN20/RD14

SCK3/U4TX/U1RTS

/CN21/RD15

V

DD

V

SS

PGEC2/AN6/OCFA/RB6

PGED2/AN7/RB7

SCL5/SDO4/U2TX/PMA8/CN18/RF5

SDA5/SDI4/U2RX/PMA9/CN17/RF4

PMD5/RE5 PMD6/RE6 PMD7/RE7

T2CK/RC1 T3CK/RC2 T4CK/RC3

T5CK/SDI1/RC4

SCK2/U6TX/U3RTS

/PMA5/CN8/RG6

V

DD

TMS/RA0 INT1/RE8 INT2/RE9

AN5/C1IN+/V

BUSON

/CN7/RB5

AN4/C1IN-/CN6/RB4

AN3/C2IN+/CN5/RB3

AN2/C2IN-/CN4/RB2

SDA4/SDI2/U3RX/PMA4/CN9/RG7 SCL4/SDO2/U3TX/PMA3/CN10/RG8

PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0

V

DD

RG15

SS2/U6RX/U3CTS

/PMA2/CN11/RG9

MCLR

AN12/PMA11/RB12

AN13/PMA10/RB13

AN14/PMALH/PMA1/RB14

AN15/OCFB/PMALL/PMA0/CN12/RB15

PMD9/RG1

C1TX/PMD10/RF1

V

DD

PMD14/CN15/RD6

TDO/RA5

SDA2/RA3 SCL2/RA2

V

SS

V

SS

V

SS

V

CAP

/V

CORE

TDI/RA4

TCK/RA1

100-Pin TQFP

PMD15/CN16/RD7

= Pins are up to 5V tolerant

20

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

65 64 63 62 61 60 59

56

45

44

43

42

41

40

39

2829303132333435363738

17 18 19

21

22

1

72 71 70 69 68 67 66

75 74 73

58 57

24

23

25

27

464748

49

55 54 53 52 51

50

26

PIC32MX575F512L

92949391908988878685848382818079789576

77

969897

99

100

PIC32MX575F256L

PIC32MX534F064L PIC32MX564F064L PIC32MX564F128L

PIC32MX5XX/6XX/7XX

100-Pin TQFP

PIC32MX675F512L PIC32MX695F512L

PIC32MX675F256L

= Pins are up to 5V tolerant

PMRD/CN14/RD5

OC5/PMWR/CN13/RD 4

ETXD3/PMD13/CN19/RD13

ETXD2/IC5/PMD12/RD12

OC4/RD3

OC3/RD2

OC2/RD1

TRD3/RA7

TRCLK/RA6

PMD2/RE2

TRD0/RG13

TRD1/RG12

TRD2/RG14

PMD1/RE1

PMD0/RE0

PMD8/RG0

PMD4/RE4

PMD3/RE3

ETXD1/PMD11/RF0

PMD5/RE5 PMD6/RE6 PMD7/RE7

T2CK/RC1 T3CK/RC2 T4CK/RC3

T5CK/SDI1/RC4

ECOL/SCK2/U6TX/U3RTS

/PMA5/CN8/RG6

V

DD

TMS/RA0 AERXD0/INT1/RE8 AERXD1/INT2/RE9

AN5/C1IN+/V

BUSON

/CN7/RB5

AN4/C1IN-/CN6/RB4

AN3/C2IN+/CN5/RB3

AN2/C2IN-/CN4/RB2

ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7

ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/U3TX/PMA3/CN10/RG8

PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0

V

DD

AERXERR/RG15

ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CT S/PMA2/CN11/RG9

MCLR

ETXERR/PMD9/RG1

ETXD0/PMD10/RF1

VDDETXEN/PMD14/CN15/RD6

V

SS

V

CAP

/V

DDCORE

ETXCLK/PMD15/CN16/RD7

20

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

21 22

1

24

23

25

92949391908988878685848382818079789576

77

969897

99

100

SOSCI/CN1/RC13 SDO1/OC1/INT0/RD0

SS1/

IC2/RD9

RTCC/EMDIO/AEMDIO/IC1/RD8

EMDC/AEMDC/IC4/PMCS1/PMA14/RD1 1

AETXEN/SDA1/INT4/RA1 5 AETXCLK/SCL1/INT3/RA14

OSC2/CLKO/RC15 OSC1/CLKI/RC12 V

DD

D+/RG2

V

USB

V

BUS

SCL3/SDO3/U1TX/RF8

D-/RG3

SDA3/SDI3/U1RX/RF2 USBID/RF3

V

SS

SOSCO/T1CK/CN0/RC14

V

REF

+/CV

REF

+/AERXD3/PMA6/RA10

V

REF

-/CV

REF

-/AERXD2/PMA7/RA9

AV

DD

AV

SS

AN8/C1OUT/RB8

AN9/C2OUT/RB9

AN10/CV

REFOUT

/PMA13/RB10

AN11/ERXERR/AETXERR/PMA12/RB11

V

DD

SS4/U5RX/U2CTS/RF12

SCK4/U5TX/U2RTS

/RF13

AETXD0/SS3

/U4RX/U1CTS/CN20/RD14

AETXD1/SCK3/U4TX/U1RTS

/CN21/RD15

V

DD

V

SS

PGED2/AN7/RB7

SCL5/SDO4/U2TX/PMA8/CN18/RF5

SDA5/SDI4/U2RX/PMA9/CN17/RF4

AN12/ERXD0/AECRS/PMA11/RB12

AN13/ERXD1/AECOL/PMA10/RB13

AN14/ERXD2/AETXD3/PMALH/PMA1/RB14

AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15

TDO/RA5

SDA2/RA3 SCL2/RA2

V

SS

V

SS

TDI/RA4

TCK/RA1

65 64 63 62 61 60 59

56

45

44

43

42

41

40

39

2829303132333435363738

72 71 70 69 68 67 66

75 74 73

58 57

27

464748

49

55 54 53 52 51

50

SCK1/IC3/PMCS2/PMA15/RD10

PIC32MX664F064L PIC32MX664F128L

PGEC2/AN6/OCFA/RB6

26

Pin Diagrams (Continued)

PIC32MX5XX/6XX/7XX

100-Pin TQFP

= Pins are up to 5V tolerant

PIC32MX795F512L

PIC32MX775F256L PIC32MX775F512L

PMRD/CN14/RD5

OC5/PMWR/CN13/RD4

ETXD3/PMD13/CN19/RD13

ETXD2/IC5/PMD12/RD12

OC4/RD3

OC3/RD2

OC2/RD1

TRD3/RA7

TRCLK/RA6

PMD2/RE2

TRD0/RG13

TRD1/RG12

TRD2/RG14

PMD1/RE1

PMD0/RE0

C2RX/PMD8/RG0

PMD4/RE4

PMD3/RE3

C1RX/ETXD1/PMD11/RF0

PMD5/RE5 PMD6/RE6 PMD7/RE7

T2CK/RC1 T3CK/AC2TX/RC2 T4CK/AC2RX/RC3

T5CK/SDI1/RC4

ECOL/SCK2/U6TX/U3RTS

/PMA5/CN8/RG6

V

DD

TMS/RA0 AERXD0/INT1/RE8 AERXD1/INT2/RE9

AN5/C1IN+/V

BUSON

/CN7/RB5

AN4/C1IN-/CN6/RB4

AN3/C2IN+/CN5/RB3

AN2/C2IN-/CN4/RB2

ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7

ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/U3TX/PMA3/CN10/RG8

PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0

V

DD

AERXERR/RG15

ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CTS/PMA2/CN1 1/R G9

MCLR

C2TX/ETXERR/PMD9/RG1

C1TX/ETXD0/PMD10/RF1

VDDETXEN/PMD14/CN15/RD6

V

SS

V

CAP

/V

DDCORE

ETXCLK/PMD15/CN16/RD7

20

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

21 22

1

24

23

25

92949391908988878685848382818079789576

77

969897

99

100

SOSCI/CN1/RC13 SDO1/OC1/INT0/R D0

SCK1/IC3/PMCS2/PMA15/RD10 SS1/

IC2/RD9

RTCC/EMDIO/AE MDIO/IC1 /RD8

EMDC/AEMD C/IC4 /PMCS 1/PMA 14/RD 1

AETXEN/SDA1/INT4/RA15 AETXCLK/SCL1/INT3/R A14

OSC2/CLKO/RC15 OSC1/CLKI/RC12 V

DD

D+/RG2

V

USB

V

BUS

SCL3/SDO3/U1TX/RF8

D-/RG3

SDA3/SDI3/U1RX/RF2 USBID/RF3

V

SS

SOSCO/T1CK/CN0/RC14

V

REF

+/CV

REF

+/AERXD3/PMA6/RA10

V

REF

-/CV

REF

-/AERXD2/PMA7/RA9

AV

DD

AV

SS

AN8/C1OUT/RB8

AN9/C2OUT/RB9

AN10/CV

REFOUT

/PMA13/RB10

AN11/ERXERR/AETXERR/PMA12/RB11

V

DD

AC1RX/SS4/U5RX/U2CTS/RF12

AC1TX/SCK4/U5TX/U2RTS

/RF13

AETXD0/SS3

/U4RX/U1CTS/CN20/RD14

AETXD1/SCK3/U4TX/U1RTS/CN21/RD15

V

DD

V

SS

PGEC2/AN6/OCFA/RB6

PGED2/AN7/RB7

SCL5/SDO4/U2TX/PMA8/CN18/RF5

SDA5/SDI4/U2RX/PMA9/CN17/RF4

AN12/ERXD0/AECRS/P MA11/RB12

AN13/ERXD1/AECOL/PM A10/RB1 3

AN14/ERXD2/AETXD3/PMALH/PMA1/RB14

AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15

TDO/RA5

SDA2/RA3 SCL2/RA2

V

SS

V

SS

TDI/RA4

TCK/RA1

65 64 63 62 61 60 59

56

45

44

43

42

41

40

39

2829303132333435363738

72 71 70 69 68 67 66

75 74 73

58 57

27

464748

49

55 54 53 52 51

50

26

Pin Diagrams (Continued)

PIC32MX5XX/6XX/7XX

100-Pin TQFP

= Pins are up to 5V tolerant

PIC32MX764F128L

PMRD/CN14/RD5

OC5/PMWR/CN13/RD4

ETXD3/PMD13/CN19/RD13

ETXD2/IC5/PMD12/RD12

OC4/RD3

OC3/RD2

OC2/RD1

TRD3/RA7

TRCLK/RA6

PMD2/RE2

TRD0/RG13

TRD1/RG12

TRD2/RG14

PMD1/RE1

PMD0/RE0

PMD8/RG0

PMD4/RE4

PMD3/RE3

C1RX/ETXD1/PMD11/RF0

PMD5/RE5 PMD6/RE6 PMD7/RE7

T2CK/RC1 T3CK/RC2 T4CK/RC3

T5CK/SDI1/RC4

ECOL/SCK2/U6TX/U3RTS

/PMA5/CN8/RG6

V

DD

TMS/RA0 AERXD0/INT1/RE8 AERXD1/INT2/RE9

AN5/C1IN+/V

BUSON

/CN7/RB5

AN4/C1IN-/CN6/RB4

AN3/C2IN+/CN5/RB3

AN2/C2IN-/CN4/RB2

ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7

ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/U3TX/PMA3/CN10/RG8

PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0

V

DD

AERXERR/RG15

ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CTS/PMA2/CN1 1/RG 9

MCLR

ETXERR/PMD9/RG1

C1TX/ETXD0/PMD10/R F1

VDDETXEN/PMD14/CN15/RD6

V

SS

V

CAP

/V

DDCORE

ETXCLK/PMD15/CN16/RD7

20

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19

21

22

1

24

23

25

92949391908988878685848382818079789576

77

969897

99

100

SOSCI/CN1/RC13 SDO1/OC1/INT0/R D0

SCK1/IC3/PMCS2/PMA15/RD10 SS1/

IC2/RD9

RTCC/EMDIO/AE MDIO/IC1 /RD8

EMDC/AEMD C/IC4 /PMCS 1/PMA 14/RD 1

AETXEN/SDA1/INT4/RA15 AETXCLK/SCL1/INT3/R A14

OSC2/CLKO/RC15 OSC1/CLKI/RC12 V

DD

D+/RG2

V

USB

V

BUS

SCL3/SDO3/U1TX/RF8

D-/RG3

SDA3/SDI3/U1RX/RF2 USBID/RF3

V

SS

SOSCO/T1CK/CN0/RC14

V

REF

+/CV

REF

+/AERXD3/PMA6/RA10

V

REF

-/CV

REF

-/AERXD2/PMA7/RA9

AV

DD

AV

SS

AN8/C1OUT/RB8

AN9/C2OUT/RB9

AN10/CV

REFOUT

/PMA13/RB10

AN11/ERXERR/AETXERR/PMA12/RB11

V

DD

AC1RX/SS4/U5RX/U2C TS /R F1 2

AC1TX/SCK4/U5TX/U2RTS

/RF13

AETXD0/SS3

/U4RX/U1CTS/CN20/RD14

AETXD1/SCK3/U4TX/U1RTS/CN21/RD15

V

DD

V

SS

PGEC2/AN6/OCFA/RB6

PGED2/AN7/RB7

SCL5/SDO4/U2TX/PMA 8/CN18/R F5

SDA5/SDI4/U2RX/PMA9/CN17/RF4

AN12/ERXD0/AECRS/PMA11/RB12

AN13/ERXD1/AECOL/PMA10/RB13

AN14/ERXD2/AETXD3/PMALH/PMA1/RB14

AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15

TDO/RA5

SDA2/RA3 SCL2/RA2

V

SS

V

SS

TDI/RA4

TCK/RA1

65 64 63 62 61 60 59

56

45

44

43

42

41

40

39

2829303132333435363738

72 71 70 69 68 67 66

75 74 73

58 57

27

464748

49

55 54 53 52 51

50

26

Pin Diagrams (Continued)

PIC32MX5XX/6XX/7XX

Pin Diagrams (Continued)

121-Pin XBGA

(1)

1234567891011

A

RE4 RE3 RG13 RE0 RG0 RF1 VDD VSS RD12 RD2 RD1

B

NC RG15 RE2 RE1 RA7 RF0 VCAP/

VCORE

RD5 RD3 VSS RC14

C

RE6 VDD RG12 RG14 RA6 NC RD7 RD4 V DD RC13 RD11

D

RC1 RE7 RE5 VSS VSS NC RD6 RD13 RD0 NC RD10

E

RC4 RC3 RG6 RC2 VDD RG1 VSS RA15 RD8 RD9 RA14

F

MCLR

RG8 RG9 RG7 VSS NC NC VDD RC12 VSS RC15

G

RE8 RE9 RA0 NC VDD VSS VSS NC RA5 RA3 RA4

H

RB5 RB4 VSS VDD NC VDD NC VBUS VUSB RG2 RA2

J

RB3 RB2 RB7 AVDD RB11 RA1 RB12 NC NC RF8 RG3

K

RB1 RB0 RA10 RB8 NC RF12 RB14 VDD RD15 RF3 RF2

L

RB6 RA9 AVSS RB9 RB10

RF13

RB13 RB15 RD14 RF4 RF5

PIC32MX575F256L

Note 1: Refer to

Table 4, Table 5 and Table 6 for full pin names.

= Pins are up to 5V tolerant

PIC32MX795F512L

PIC32MX575F512L PIC32MX675F512L PIC32MX695F512L

PIC32MX675F256L PIC32MX775F256L

PIC32MX775F512L

PIC32MX534F064L PIC32MX564F064L

PIC32MX564F128L

PIC32MX664F064L PIC32MX664F128L

PIC32MX764F128L

PIC32MX5XX/6XX/7XX

TABLE 4: PIN NAMES: PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L,

PIC32MX575F256L AND PIC32MX575F512L DEVICES

Number

A1 PMD4/RE4 E8 SDA1/INT4/RA15 A2 PMD3/RE3 E9 RTCC/IC1/RD8 A3 TRD0/RG13 E10 SS1 A4 PMD0/RE0 E11 SCL1/INT3/RA14

A5 PMD8/RG0 F1 MCLR A6 C1TX/PMD10/RF1 F2 SCL4/SDO2/U3TX/PMA3/CN10/RG8

A7 VDD F3 SS2 A8 VSS F4 SDA4/SDI2/U3RX/PMA4/CN9/RG7

A9 IC5/PMD12/RD12 F5 VSS A10 OC3/RD2 F6 No Connect (NC) A11 OC2/RD1 F7 No Connect (NC)

B1 No Connect (NC) F8 VDD

B2 RG15 F9 OSC1/CLKI/RC12

B3 PMD2/RE2 F10 VSS

B4 PMD1/RE1 F11 OSC2/CLKO/RC15

B5 TRD3/RA7 G1 INT1/RE8

B6 C1RX/PMD11/RF0 G2 INT2/RE9

B7 VCAP/VCORE G3 TMS/RA0

B8 PMRD/CN14/RD5 G4 No Connect (NC)

B9 OC4/RD3 G5 VDD B10 VSS G6 VSS B11 SOSCO/T1CK/CN0/RC14 G7 VSS

C1 PMD6/RE6 G8 No Connect (NC)

C2 VDD G9 TDO/RA5

C3 TRD1/RG12 G10 SDA2/RA3

C4 TRD2/RG14 G11 TDI/RA4

C5 TRCLK/RA6 H1 AN5/C1IN+/VBUSON/CN7/RB5

C6 No Connect (NC) H2 AN4/C1IN-/CN6/RB4

C7 PMD15/CN16/RD7 H3 VSS

C8 OC5/PMWR/CN13/RD4 H4 VDD

C9 VDD H5 No Connect (NC) C10 SOSCI/CN1/RC13 H6 VDD C11 IC4/PMCS1/PMA14/RD11 H7 No Connect (NC)

D1 T2CK/RC1 H8 VBUS

D2 PMD7/RE7 H9 VUSB

D3 PMD5/RE5 H10 D+/RG2

D4 VSS H11 SCL2/RA2

D5 VSS J1 AN3/C2IN+/CN5/RB3

D6 No Connect (NC) J2 AN2/C2IN-/CN4/RB2

D7 PMD14/CN15/RD6 J3 PGED2/AN7/RB7

D8 PMD13/CN19/RD13 J4 AVDD

D9 SDO1/OC1/INT0/RD0 J5 AN11/PMA12/RB11 D10 No Connect (NC) J6 TCK/RA1 D11 SCK1/IC3/PMCS2/PMA15/RD10 J7 A N12/PMA11/RB12

E1 T5CK/SDI1/RC4 J8 No Connect (NC)

E2 T4CK/RC3 J9 No Connect (NC)

E3 SCK2/U6TXU6TX/U3RTS

E4 T3CK/RC2 J11 D-/RG3

E5 VDD K1 PGEC1/AN1/CN3/RB1

E6 PMD9/RG1 K2 PGED1/AN0/CN2/RB0

E7 VSS K3 VREF+/CVREF+/PMA6/RA10

Full Pin Name

/PMA5/CN8/RG6 J10 SCL3/SDO3/U1TX/RF8

Number

Full Pin Name

/IC2/RD9

/U6RX/U3CTS/PMA2/CN11/RG9

PIC32MX5XX/6XX/7XX

TABLE 4: PIN NAMES: PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L,

PIC32MX575F256L AND PIC32MX575F512L DEVICES (CONTINUED)

Number

K4 AN8/C1OUT/RB8 L3 AVSS K5 No Connect (NC) L4 AN9/C2OUT/RB9

K6 AC1RX/SS4 K7 AN14/PMALH/PMA1/RB14 L6 AC1TX/SCK4/U5TX/U2RTS K8 VDD L7 AN13/PMA10/RB13 K9 SCK3/U4TX/U1RTS

K10 USBID/RF3 L9 SS3/U4RX/U1CTS/CN20/RD14

K11 SDA3/SDI3/U1RX/RF2 L10 SDA5/SDI4/U2RX/PMA9/CN17/RF4

L1 PGEC2/AN6/OCFA/RB6 L11 SCL5/SDO4/U2TX/PMA8/CN18/RF5 L2 VREF-/CVREF-/PMA7/RA9

Full Pin Name

/U5RX/U2CTS/RF12 L5 AN10/CVREFOUT/PMA13/RB10

/CN21/RD15 L8 AN15/OCFB/PMALL/PMA0/CN12/RB15

Number

Full Pin Name

/RF13

PIC32MX5XX/6XX/7XX

TABLE 5: PIN NAMES: PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L,

PIC32MX675F512L AND PIC32MX695F512L DEVICES

Number

A1 PMD4/RE4 E8 AETXEN/SDA1/INT4/RA15 A2 PMD3/RE3 E9 RTCC/EMDIO/AEMDIO/IC1/RD8

A3 TRD0/RG13 E10 SS1 A4 PMD0/RE0 E11 AETXCLK/SCL1/INT3/RA14

A5 PMD8/RG0 F1 MCLR A6 ETXD0/PMD10/RF1 F2 ERXDV/AERXDV/ECRSDV/AECRSDV//SCL4/SDO2/

A7 VDD F3 ERXCLK/AERXCLK/EREFCLK/AEREFCLK//SS2

A8 VSS F4 ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7 A9 ETXD2/IC5/PMD12/RD12 F5 VSS

A10 OC3/RD2 F6 No Connect (NC) A11 OC2/RD1 F7 No Connect (NC)

B1 No Connect (NC) F8 V B2 AERXERR/RG15 F9 OSC1/CLKI/RC12 B3 PMD2/RE2 F10 VSS B4 PMD1/RE1 F11 OSC2/CLKO/RC15 B5 TRD3/RA7 G1 AERXD0/INT1/RE8 B6 ETXD1/PMD11/RF0 G2 AERXD1/INT2/RE9

CAP/VCORE G3 TMS/RA0

B7 V B8 PMRD/CN14/RD5 G4 No Connect (NC) B9 OC4/RD3 G5 VDD

B10 VSS G6 VSS B11 SOSCO/T1CK/CN0/RC14 G7 VSS

C1 PMD6/RE6 G8 No Connect (NC) C2 VDD G9 TDO/RA5 C3 TRD1/RG12 G10 SDA2/RA3 C4 TRD2/RG14 G11 TDI/RA4 C5 TRCLK/RA6 H1 AN5/C1IN+/V C6 No Connect (NC) H2 AN4/C1IN-/CN6/RB4 C7 ETXCLK/PMD15/CN16/RD7 H3 VSS C8 OC5/PMWR/CN13/RD4 H4 VDD C9 VDD H5 No Connect (NC)

C10 SOSCI/CN1/RC13 H6 VDD

C11 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11 H7 No Connect (NC)

D1 T2CK/RC1 H8 VBUS D2 PMD7/RE7 H9 VUSB D3 PMD5/RE5 H10 D+/RG2 D4 VSS H11 SCL2/RA2 D5 VSS J1 AN3/C2IN+/CN5/RB3 D6 No Connect (NC) J2 AN2/C2IN-/CN4/RB2 D7 ETXEN/PMD14/CN15/RD6 J3 PGED2/AN7/RB7 D8 ETXD3/PMD13/CN19/RD13 J4 AV D9 SDO1/OC1/INT0/RD0 J5 AN11/ERXERR/AETXERR/PMA12/RB11

D10 No Connect (NC) J6 TCK/RA1

D11 SCK1/IC3/PMCS2/PMA15/RD10 J7 AN12/ERXD0/AECRS/PMA11/RB12

E1 T5CK/SDI1/RC4 J8 No Connect (NC) E2 T4CK/RC3 J9 No Connect (NC) E3 ECOL/SCK2/U6TX/U3RTS E4 T3CK/RC2 J11 D-/RG3

DD K1 PGEC1/AN1/CN3/RB1

E5 V E6 ETXERR/PMD9/RG1 K2 PGED1/AN0/CN2/RB0 E7 VSS K3 VREF+/CVREF+/AERXD3/PMA6/RA10

Full Pin Name

/PMA5/CN8/RG6 J10 SCL3/SDO3/U1TX/RF8

Number

/IC2/RD9

U3TX/PMA3/CN10/RG8

/PMA2/CN11/RG9

U3CTS

DD

BUSON/CN7/RB5

DD

Full Pin Name

/U6RX/

PIC32MX5XX/6XX/7XX

TABLE 5: PIN NAMES: PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L,

PIC32MX675F512L AND PIC32MX695F512L DEVICES (CONTINUED)

Number

K4 AN8/C1OUT/RB8 L3 AVSS K5 No Connect (NC) L4 AN9/C2OUT/RB9 K6 SS4 K7 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 L6 SCK4/U5TX/U2RTS K8 VDD L7 AN13/ERXD1/AECOL/PMA10/RB13 K9 AETXD1/SCK3/U4TX/U1RTS/CN21/RD15 L8 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15

K10 USBID/RF3 L9 AETXD0/SS3 K11 SDA3/SDI3/U1RX/RF2 L10 SDA5/SDI4/U2RX/PMA9/CN17/RF4

L1 PGEC2/AN6/OCFA/RB6 L11 SCL5/SDO4/U2TX/PMA8/CN18/RF5 L2 V

/U5RX/U2CTS/RF12 L5 AN10/CVREFOUT/PMA13/RB10

REF-/CVREF-/AERXD2/PMA7/RA9

Full Pin Name

Number

Full Pin Name

/RF13

/U4RX/U1CTS/CN20/RD14

PIC32MX5XX/6XX/7XX

T ABLE 6: PIN NAMES: PIC32MX775F256L, PIC32MX775F512L AND

PIC32MX795F512L DEVICES

Number

A1 PMD4/RE4 E8 AETXEN/SDA1/INT4/RA15 A2 PMD3/RE3 E9 RTCC/EMDIO/AEMDIO/IC1/RD8 A3 TRD0/RG13 E10 SS1 A4 PMD0/RE0 E11 AETXCLK/SCL1/INT3/RA14

A5 C2RX/PMD8/RG0 F1 MCLR A6 C1TX/ETXD0/PMD10/RF1 F2 ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/

A7 VDD F3 ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2

A8 VSS F4 ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7

A9 ETXD2/IC5/PMD12/RD12 F5 VSS A10 OC3/RD2 F6 No Connect (NC) A11 OC2/RD1 F7 No Connect (NC)

B1 No Connect (NC) F8 V

B2 AERXERR/RG15 F9 OSC1/CLKI/RC12

B3 PMD2/RE2 F10 VSS

B4 PMD1/RE1 F11 OSC2/CLKO/RC15

B5 TRD3/RA7 G1 AERXD0/INT1/RE8

B6 C1RX/ETXD1/PMD11/RF0 G2 AERXD1/INT2/RE9

B7 VCAP/VCORE G3 TMS/RA0

B8 PMRD/CN14/RD5 G4 No Connect (NC)

B9 OC4/RD3 G5 V B10 VSS G6 VSS B11 SOSCO/T1CK/CN0/RC14 G7 VSS

C1 PMD6/RE6 G8 No Connect (NC)

C2 VDD G9 TDO/RA5

C3 TRD1/RG12 G10 SDA2/RA3

C4 TRD2/RG14 G11 T D I/R A4

C5 TRCLK/RA6 H1 AN5/C1IN+/VBUSON/CN7/RB5

C6 No Connect (NC) H2 AN4/C1IN-/CN6/RB4

C7 ETXCLK/PMD15/CN16/RD7 H3 V

C8 OC5/PMWR/CN13/RD4 H4 VDD

C9 VDD H5 No Connect (NC) C10 SOSCI/CN 1/RC13 H6 VDD C11 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11 H7 No Connect (NC)

D1 T2CK/RC1 H8 VBUS

D2 PMD7/RE7 H9 VUSB

D3 PMD5/RE5 H10 D+/RG2

D4 VSS H 11 SCL2/RA2

D5 VSS J1 AN3/C2IN+/CN5/R B3

D6 No Connect (NC) J2 AN2/C2IN-/CN4/RB2

D7 ETXEN/PMD14/CN15/RD6 J3 PGED2/AN7/RB7

D8 ETXD3/PMD13/CN19/RD13 J4 AVDD

D9 SDO1/OC1/INT0/RD0 J5 AN11/ERXERR/AETXERR/PMA12/RB11 D10 N o Connect (NC) J6 TCK/RA1 D11 SCK1/IC3/PMCS2/PMA15/RD10 J7 AN12/ERXD0/AECRS/PMA11/RB12

E1 T5CK/SDI1/RC4 J8 No Connect (NC)

E2 T4CK/AC2RX/RC3 J9 No Connect (NC)

E3 ECOL/SCK2/U6TX/U3RTS

E4 T3CK/AC2TX/RC2 J11 D-/RG3

E5 VDD K1 PGEC1/AN1/CN3/RB1

E6 C2TX/ETXERR/PMD9/RG1 K2 PGED1/AN0/CN2/RB0

E7 VSS K3 VREF+/CVREF+/AERXD3/PMA6/RA10

Full Pin Name

/PMA5/CN8/RG6 J10 SCL3/SDO3/U1TX/RF8

Number

/IC2/RD9

U3TX/PMA3/CN10/RG8

/PMA2/CN11/RG9

U3CTS

DD

SS

Full Pin Name

/U6RX/

PIC32MX5XX/6XX/7XX

T ABLE 6: PIN NAMES: PIC32MX775F256L, PIC32MX775F512L AND

PIC32MX795F512L DEVICES (CONTINUED)

Number

K4 AN8/C1OUT/RB8 L3 AVSS K5 No Connect (NC) L4 AN9/C2OUT/RB9 K6 AC1RX/SS4 K7 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 L6 AC1TX/SCK4/U5TX/U2RTS K8 VDD L7 AN13/ERXD1/AECOL/PMA10/RB13 K9 AETXD1/SCK3/U4TX/U1RTS/CN21/RD15 L8 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15

K10 USBID/RF3 L9 AETXD0/SS3 K11 SDA3/SDI3/U1RX/RF2 L10 SDA5/SDI4/U2RX/PMA9/CN17/RF4

L1 PGEC2/AN6/OCFA/RB6 L11 SCL5/SDO4/U2TX/PMA8/CN18/RF5

REF-/CVREF-/AERXD2/PMA7/RA9

L2 V

Full Pin Name

/U5RX/U2CTS/RF12 L5 AN10/CVREFOUT/PMA13/RB10

Number

Full Pin Name

/RF13

/U4RX/U1CTS/CN20/RD14

PIC32MX5XX/6XX/7XX

TABLE 7: PIN NAME: PIC32MX764F128L DEVICE

Number

A1 PMD4/RE4 E8 AETXEN/SDA1/INT4/RA15

A2 PMD3/RE3 E9 RTCC/EMDIO/AEMDIO/IC1/RD8

A3 TRD0/RG13 E10 SS1

A4 PMD0/RE0 E11 AETXCLK/SCL1/INT3/RA14

A5 PMD8/RG0 F1 MCLR

A6 C1TX/ETXD0/PMD10/RF1 F2 ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/

A7 VDD F3 ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2

A8 VSS F4 ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7

A9 ETXD2/IC5/PMD12/RD12 F5 VSS A10 OC3/RD2 F6 No Connect (NC) A11 OC2/RD1 F7 No Connect (NC)

B1 No Connect (NC) F8 VDD

B2 AERXERR/RG15 F9 OSC1/CLKI/RC12

B3 PMD2/RE2 F10 VSS

B4 PMD1/RE1 F11 OSC2/CLKO/RC15

B5 TRD3/RA7 G1 AERXD0/INT1/RE8

B6 C1RX/ETXD1/PMD11/RF0 G2 AERXD1/INT2/RE9

B7 VCAP/VCORE G3 TMS/RA0

B8 PMRD/CN14/RD5 G4 No Connect (NC)

B9 OC4/RD3 G5 V B10 VSS G6 VSS B11 SOSCO/T1CK/CN0/RC14 G7 VSS

C1 PMD6/RE6 G8 No Connect (NC)

C2 VDD G9 TDO/RA5

C3 TRD1/RG12 G10 SDA2/RA3

C4 TRD2/RG14 G11 T D I/R A4

C5 TRCLK/RA6 H1 AN5/C1IN+/V

C6 No Connect (NC) H2 AN4/C1IN-/CN6/RB4

C7 ETXCLK/PMD15/CN16/RD7 H3 VSS

C8 OC5/PMWR/CN13/RD4 H4 VDD

C9 VDD H5 No Connect (NC) C10 SOSCI/CN 1/RC13 H6 VDD C11 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11 H7 No Connect (NC)

D1 T2CK/RC1 H8 VBUS

D2 PMD7/RE7 H9 VUSB

D3 PMD5/RE5 H10 D+/RG2

D4 VSS H 11 SCL2/RA2

D5 VSS J1 AN3/C2IN+/CN5/R B3

D6 No Connect (NC) J2 AN2/C2IN-/CN4/RB2

D7 ETXEN/PMD14/CN15/RD6 J3 PGED2/AN7/RB7

D8 ETXD3/PMD13/CN19/RD13 J4 AV

D9 SDO1/OC1/INT0/RD0 J5 AN11/ERXERR/AETXERR/PMA12/RB11 D10 N o Connect (NC) J6 TCK/RA1 D11 SCK1/IC3/PMCS2/PMA15/RD10 J7 AN12/ERXD0/AECRS/PMA11/RB12

E1 T5CK/SDI1/RC4 J8 No Connect (NC)

E2 T4CK/RC3 J9 No Connect (NC)

E3 ECOL/SCK2/U6TX/U3RTS

E4 T3CK/RC2 J11 D-/RG3

E5 VDD K1 PGEC1/AN1/CN3/RB1

E6 ETXERR/PMD9/RG1 K2 PGED1/AN0/CN2/RB0

SS K3 VREF+/CVREF+/AERXD3/PMA6/RA10

E7 V

Full Pin Name

/PMA5/CN8/RG6 J10 SCL3/SDO3/U1TX/RF8

Number

/IC2/RD9

U3TX/PMA3/CN10/RG8

/PMA2/CN11/RG9

U3CTS

DD

BUSON/CN7/RB5

DD

Full Pin Name

/U6RX/

PIC32MX5XX/6XX/7XX

TABLE 7: PIN NAME: PIC32MX764F128L DEVICE (CONTINUED)

Number

K4 AN8/C1OUT/RB8 L3 AVSS K5 No Connect (NC) L4 AN9/C2OUT/RB9

K6 AC1RX/SS4 K7 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 L6 AC1TX/SCK4/U5TX/U2RTS K8 VDD L7 AN13/ERXD1/AECOL/PMA10/RB13

K9 AETXD1/SCK3/U4TX/U1RTS K10 USBID/RF3 L9 AETXD0/SS3 K11 SDA3/SDI3/U1RX/RF2 L10 SDA5/SDI4/U2RX/PMA9/CN17/RF4

L1 PGEC2/AN6/OCFA/RB6 L11 SCL5/SDO4/U2TX/PMA8/CN18/RF5

REF-/CVREF-/AERXD2/PMA7/RA9

L2 V

Full Pin Name

/U5RX/U2CTS/RF12 L5 AN10/CVREFOUT/PMA13/RB10

/CN21/RD15 L8 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15

Number

Full Pin Name

/U4RX/U1CTS/CN20/RD14

/RF13

PIC32MX5XX/6XX/7XX

Table of Contents

1.0 Device Overview........................................................................................................................................................................ 31

2.0 Guidelines for Getting Started with 32-bit Microcontrollers........................................................................................................ 41

3.0 PIC32 MCU ................................................................................................................................................................................ 45

4.0 Memory Organization .................................................................................................................................................................51

5.0 Flash Program Memory............................................................................................................................................................ 113

6.0 Resets ...................................................................................................................................................................................... 115

7.0 Interrupt Controller................................................................................................................................................................... 117

8.0 Oscillator Configuration ............................................................................................................................................................121

9.0 Prefetch Cache......................................................................................................................................................................... 123

10.0 Direct Memory Access (DMA) Controller ................................................................................................................................. 125

11.0 USB On-The-Go (OTG)............................................................................................................................................................ 127

12.0 I/O Ports................................................................................................................................................................................... 129

13.0 Timer1 ...................................................................................................................................................................................... 131

14.0 Timer2/3, Timer4/5................................................................................................................................................................... 133

15.0 Input Capture............................................................................................................................................................................ 135

16.0 Output Compare....................................................................................................................................................................... 137

17.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 139

18.0 Inter-Integrated Circuit (I

19.0 Universal Asynchronous Receiver Transmitter (UART)........................................................................................................... 143

20.0 Parallel Master Port (PMP)....................................................................................................................................................... 145

21.0 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 147

22.0 10-bit Analog-to-Digital Converter (ADC)................................................................................................................................. 149

23.0 Controller Area Network (CAN)................................................................................................................................................ 151

24.0 Ethernet Controller ................................................................................................................................................................... 153

25.0 Comparator .............................................................................................................................................................................. 155

26.0 Comparator Voltage Reference (CV

27.0 Power-Saving Features ........................................................................................................................................................... 159

28.0 Special Features ...................................................................................................................................................................... 161

29.0 Instruction Set .......................................................................................................................................................................... 175

30.0 Development Support............................................................................................................................................................... 177

31.0 Electrical Characteristics.......................................................................................................................................................... 181

32.0 Packaging Information.............................................................................................................................................................. 225

Appendix A: Migrating from PIC32MX3XX/4XX to PIC32MX5XX/6XX/7XX Devices ........................................................................ 239

Appendix B: Revision History............................................................................................................................................................. 240

The Microchip Web Site..................................................................................................................................................................... 251

Customer Change Notification Service.............................................................................................................................................. 251

Customer Support.............................................................................................................................................................................. 251

Reader Response.............................................................................................................................................................................. 252

Product Identification System............................................................................................................................................................. 253

2

C™) ................................................................................................................................................. 141

REF).................................................................................................................................. 157

PIC32MX5XX/6XX/7XX

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at sheet to (480) 792-4150. We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

Y ou can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site;

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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using.

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http://www.microchip.com

Customer Notification System

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www.microchip.com to receive the most current information on all of our products.

PIC32MX5XX/6XX/7XX

NOTES:

PIC32MX5XX/6XX/7XX

Note 1: Some features are not available on all device variant s.

2: BOR functionality is provided when the on-board voltage regulator is enabled.

UART1-6

Comparators

PORTA

PORTD

PORTE

PORTF

PORTG

PORTB

CN1-22

JTAG

Priority

DMAC

ICD

MIPS32® M4K

®

IS DS

EJTAG INT

Bus Matrix

Prefetch

Data RAM

Peripheral Bridge

128

128-bit Wide

Flash

32

32 32

32

Peripheral Bus Clocked by PBCLK

Program Flash Memory

Controller

32

Module

32

Interrupt

Controller

BSCAN

PORTC

PMP

I2C1-5

SPI1-4

IC1-5

PWM

OC1-5

OSC1/CLKI

OSC2/CLKO

VDD, VSS

Timing

Generation

MCLR

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Precision

Reference

Band Gap

FRC/LPRC

Oscillators

Regulator

Voltage

VCAP/VCORE

OSC/SOSC

Oscillators

PLL

Dividers

SYSCLK PBCLK

Peripheral Bus Clocked by SYSCLK

USB

PLL-USB

USBCLK

32

RTCC

10-bit ADC

Timer1-5

32

CAN1, CAN2

ETHERNET

32

CPU Core

1.0 DEVICE OVERVIEW

Note 1: This data sheet summarizes the features

of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (

www.microchip.com/PIC32).

2: Some registers and associated bits

described in this section may not be available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register and bit information.

FIGURE 1-1: BLOCK DIAGRAM

(1,2)

This document contains device-specific information for PIC32MX5XX/6XX/7XX devices.

Figure 1-1 illustrates a general block diagram of the

core and peripheral modules in the PIC32MX5XX/6XX/7XX family of devices.

Table 1-1 lists the functions of the various pins shown

in the pinout diagrams.

PIC32MX5XX/6XX/7XX

TABLE 1-1: PINOUT I/O DESCRIPTIONS

Pin Number

Pin Name

AN0 16 25 K2 I Analog Analog input channels. AN1 15 24 K1 I Analog AN2 14 23 J2 I Analog AN3 13 22 J1 I Analog AN4 12 21 H2 I Analog AN5 11 20 H1 I Analog AN6 17 26 L1 I Analog AN7 18 27 J3 I Analog AN8 21 32 K4 I Analog AN9 22 33 L4 I Analog AN10 23 34 L5 I Analog AN11 24 35 J5 I Analog AN12 27 41 J7 I Analog AN13 28 42 L7 I Analog AN14 29 43 K7 I Analog AN15 30 44 L8 I Analog CLKI 39 63 F9 I ST/CMOS External clock source input. Always associated

CLKO 40 64 F11 O — Oscillator cryst al output. Connects to crystal or

OSC1 39 63 F9 I ST/CMOS Oscillator crystal input. ST buffer when

OSC2 40 64 F1 1 I/O — Oscillator crystal output. Connects to crystal or

SOSCI 47 73 C10 I ST/CMOS 32.768 kHz low-powe r oscillator crystal input;

SOSCO 48 74 B11 O — 32.768 kHz low-power oscillator crystal output.

Legend: CMOS = CMOS comp atible input or output Analog = Analog input P = Power

Note 1: Pin numbers are provided for reference only. See the “

2: See

64-Pin

QFN/TQFP

ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer

Section 24.0 “Ethernet Controller” for more information.

100-Pin

TQFP

(1)

121-Pin

XBGA

Type

Buffer

Type

with OSC1 pin function.

resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function.

configured in RC mode; CMOS otherwise.

resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes.

CMOS otherwise.

Pin Diagrams” section for device pin availability.

Description

PIC32MX5XX/6XX/7XX

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

CN0 48 74 B11 I ST Change notification inputs. CN1 47 73 C10 I ST CN2 16 25 K2 I ST CN3 15 24 K1 I ST CN4 14 23 J2 I ST CN5 13 22 J1 I ST CN6 12 21 H2 I ST CN7 11 20 H1 I ST CN8 4 10 E3 I ST CN9 5 11 F4 I ST CN10 6 12 F2 I ST CN11 8 14 F3 I ST CN12 30 44 L8 I ST CN13 52 81 C8 I ST CN14 53 82 B8 I ST CN15 54 83 D7 I ST CN16 55 84 C7 I ST CN17 31 49 L10 I ST CN18 32 50 L11 I ST CN19 — 80 D8 I ST CN20 — 47 L9 I ST CN21 — 48 K9 I ST IC1 42 68 E9 I ST Capture Inputs 1-5 IC2 43 69 E10 I ST IC3 44 70 D11 I ST IC4 45 71 C11 I ST IC5 52 79 A9 I ST OCFA 17 26 L1 I ST Output Compare Fault A Input OC1 46 72 D9 O — Output Compare Output 1 OC2 49 76 A11 O — Output Compare Output 2 OC3 50 77 A10 O — Output Compare Output 3 OC4 51 78 B9 O — Output Compare Output 4 OC5 52 81 C8 O — Output Compare Output 5 OCFB 30 44 L8 I ST Output Compare Fault B Input INT0 46 72 D9 I ST External Interrupt 0 INT1 42 18 G1 I ST External Interrupt 1 INT2 43 19 G2 I ST External Interrupt 2 INT3 44 66 E11 I ST External Interrupt 3 INT4 45 67 E8 I ST External Interrupt 4

Legend: CMOS = CMOS comp atible input or output Analog = Analog input P = Power

Note 1: Pin numbers are provided for reference only. See the “

2: See Section 24.0 “Ethernet Controller” for more information.

64-Pin

QFN/TQFP

ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer

100-Pin

TQFP

(1)

121-Pin

XBGA

Type

Buffer

Type

Can be software programmed for internal weak pull-ups on all inputs.

Pin Diagrams” section for device pin availability.

Description

PIC32MX5XX/6XX/7XX

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RA0 — 17 G3 I/O ST PORTA is a bidirectional I/O port RA1 — 38 J6 I/O ST RA2 — 58 H11 I/O ST RA3 — 59 G10 I/O ST RA4 — 60 G11 I/O ST RA5 — 61 G9 I/O ST RA6 — 91 C5 I/O ST RA7 — 92 B5 I/O ST RA9 — 28 L2 I/O ST RA10 — 29 K3 I/O ST RA14 — 66 E11 I/O ST RA15 — 67 E8 I/O ST RB0 16 25 K2 I/O ST PORTB is a bidirectional I/O port RB1 15 24 K1 I/O ST RB2 14 23 J2 I/O ST RB3 13 22 J1 I/O ST RB4 12 21 H2 I/O ST RB5 11 20 H1 I/O ST RB6 17 26 L1 I/O ST RB7 18 27 J3 I/O ST RB8 21 32 K4 I/O ST RB9 22 33 L4 I/O ST RB10 23 34 L5 I/O ST RB11 24 35 J5 I/O ST RB12 27 41 J7 I/O ST RB13 28 42 L7 I/O ST RB14 29 43 K7 I/O ST RB15 30 44 L8 I/O ST RC1 — 6 D1 I/O ST PORTC is a bidirectional I/O port RC2 — 7 E4 I/O ST RC3 — 8 E2 I/O ST RC4 — 9 E1 I/O ST RC12 39 63 F9 I/O ST RC13 47 73 C10 I/O ST RC14 48 74 B11 I/O ST RC15 40 64 F11 I/O ST

Legend: CMOS = CMOS comp atible input or output Analog = Analog input P = Power

Note 1: Pin numbers are provided for reference only. See the “

2: See Section 24.0 “Ethernet Controller” for more information.

64-Pin

QFN/TQFP

ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer

100-Pin

TQFP

(1)

121-Pin

XBGA

Type

Buffer

Type

Pin Diagrams” section for device pin availability.

Description

PIC32MX5XX/6XX/7XX

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RD0 46 72 D9 I/O ST PORTD is a bidirectional I/O port RD1 49 76 A11 I/O ST RD2 50 77 A10 I/O ST RD3 51 78 B9 I/O ST RD4 52 81 C8 I/O ST RD5 53 82 B8 I/O ST RD6 54 83 D7 I/O ST RD7 55 84 C7 I/O ST RD8 42 68 E9 I/O ST RD9 43 69 E10 I/O ST RD10 44 70 D11 I/O ST RD11 45 71 C11 I/O ST RD12 — 79 A9 I/O ST RD13 — 80 D8 I/O ST RD14 — 47 L9 I/O ST RD15 — 48 K9 I/O ST RE0 60 93 A4 I/O ST PORTE is a bidirectional I/O port RE1 61 94 B4 I/O ST RE2 62 98 B3 I/O ST RE3 63 99 A2 I/O ST RE4 64 100 A1 I/O ST RE5 1 3 D3 I/O ST RE6 2 4 C1 I/O ST RE7 3 5 D2 I/O ST RE8 — 18 G1 I/O ST RE9 — 19 G2 I/O ST RF0 58 87 B6 I/O ST PORTF is a bidirectional I/O port RF1 59 88 A6 I/O ST RF2 — 52 K11 I/O ST RF3 33 51 K10 I/O ST RF4 31 49 L10 I/O ST RF5 32 50 L11 I/O ST RF8 — 53 J10 I/O ST RF12 — 40 K6 I/O ST RF13 — 39 L6 I/O ST

Legend: CMOS = CMOS comp atible input or output Analog = Analog input P = Power

Note 1: Pin numbers are provided for reference only. See the “

2: See Section 24.0 “Ethernet Controller” for more information.

64-Pin

QFN/TQFP

ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer

100-Pin

TQFP

(1)

121-Pin

XBGA

Type

Buffer

Type

Pin Diagrams” section for device pin availability.

Description

PIC32MX5XX/6XX/7XX

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

RG0 — 90 A5 I/O ST PORTG is a bidirectional I/O port RG1 — 89 E6 I/O ST RG6 4 10 E3 I/O ST RG7 5 11 F4 I/O ST RG8 6 12 F2 I/O ST RG9 8 14 F3 I/O ST RG12 — 96 C3 I/O ST RG13 — 97 A3 I/O ST RG14 — 95 C4 I/O ST RG15 — 1 B2 I/O ST RG2 37 57 H10 I ST PORTG input pins RG3 36 56 J11 I ST T1CK 48 74 B11 I ST Timer1 external clock input T2CK — 6 D1 I ST Timer2 external clock input T3CK — 7 E4 I ST Timer3 external clock input T4CK — 8 E2 I ST Timer4 external clock input T5CK — 9 E1 I ST Timer5 external clock input U1CTS

U1RTS U1RX U1TX U3CTS U3RTS

U3RX U3TX

U2CTS U2RTS U2RX U2TX U4RX U4TX U6RX U6TX U5RX U5TX

SCK1 — 70 D11 I/O ST Synchronous serial clock input/output for SPI1 SDI1 — 9 E1 I ST SPI1 data in SDO1 — 72 D9 O — SPI1 data out

SS1

Legend: CMOS = CMOS comp atible input or output Analog = Analog input P = Power

Note 1: Pin numbers are provided for reference only. See the “

2: See

64-Pin

QFN/TQFP

43 47 L9 I ST UART1 clear to send 49 48 K9 O — UART1 ready to send

50 52 K11 51 53 J10

8 14 F3 I ST UART3 clear to send 4 10 E3 O — UART3 ready to send 511F4

612F2

21 40 K6 I ST UART2 clear to send 29 39 L6 O — UART2 ready to send

31 49 L10 32 50 L11 43 47 L9 49 48 K9

814F3

410E3 21 40 K6 29 39 L6

— 69 E10 I/O ST SPI1 slave synchronization or frame pulse I/O

ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer

Section 24.0 “Ethernet Controller” for more information.

100-Pin

TQFP

(1)

121-Pin

XBGA

Type

Buffer

Type

I ST UART1 receive

O — UART1 transmit

I ST UART3 receive

O — UART3 transmit

I ST UART2 receive

O — UART2 transmit

I ST UART4 receive

O — UART4 transmit

I ST UART6 receive

O — UART6 transmit

I ST UART5 receive

O — UART5 transmit

Pin Diagrams” section for device pin availability.

Description

PIC32MX5XX/6XX/7XX

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

SCK3 49 48 K9 I/O ST Synchronous serial clock input/output for SPI3 SDI3 50 52 K11 I ST SPI3 data in SDO3 51 53 J10 O — SPI3 data out SS3 SCK2 4 10 E3 I/O ST Synchronous serial clock input/output for SPI2 SDI2 5 11 F4 I ST SPI2 data in SDO2 6 12 F2 O — SPI2 data out

SS2 SCK4 29 39 L6 I/O ST Synchronous serial clock input/output for SPI4 SDI4 31 49 L10 I ST SPI4 data in SDO4 32 50 L11 O — SPI4 data out

SS4 SCL1 44 66 E11 I/O ST Synchronous serial clock input/output for I2C1 SDA1 43 67 E8 I/O ST Synchronous serial data input/output for I2C1 SCL3 51 53 J10 I/O ST Synchronous serial clock input/output for I2C3 SDA3 50 52 K11 I/O ST Synchronous serial data input/output for I2C3 SCL2 — 58 H11 I/O ST Synchronous serial clock input/output for I2C2 SDA2 — 59 G10 I/O ST Synchronous serial data input/output for I2C2 SCL4 6 12 F2 I/O ST Synchronous serial clock input/output for I2C4 SDA4 5 11 F4 I/O ST Synchronous serial data input/output for I2C4 SCL5 32 50 L11 I/O ST Synchronous serial clock input/output for I2C5 SDA5 31 49 L10 I/O ST Synchronous serial data input/output for I2C5 TMS 23 17 G3 I ST JTAG Test mode select pin TCK 27 38 J6 I ST JTAG test clock input pin TDI 28 60 G11 I ST JTAG test data input pin TDO 24 61 G9 O — JTAG test data output pin RTCC 42 68 E9 O — Real-Time Clock alarm output

REF- 15 28 L2 I Analog Comparator Voltage Reference (low)

CV CVREF+ 16 29 K3 I Analog Comparator Voltage Reference (high) CVREFOUT 23 34 L5 O Ana log C omparator Voltage Reference output C1IN- 12 21 H2 I Analog Comparator 1 negative input C1IN+ 11 20 H1 I Analog Comparator 1 positive input C1OUT 21 32 K4 O — Comparator 1 output C2IN- 14 23 J2 I Analog Comparator 2 negative input C2IN+ 13 22 J1 I Analog Comparator 2 positive input C2OUT 22 33 L4 O — Comparator 2 output PMA0 30 44 L8 I/O TTL/ST Parallel Master Port Address bit 0 input

PMA1 29 43 K7 I/O TTL/ST Parallel Master Port Address bit 1 input

Legend: CMOS = CMOS comp atible input or output Analog = Analog input P = Power

Note 1: Pin numbers are provided for reference only. See the “

2: See

64-Pin

QFN/TQFP

43 47 L9 I/O ST SPI3 slave synchronization or frame pulse I/O

8 14 F3 I/O ST SPI2 slave synchronization or frame pulse I/O

21 40 K6 I/O ST SPI4 slave synchronization or frame pulse I/O

ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer

Section 24.0 “Ethernet Controller” for more information.

100-Pin

TQFP

(1)

121-Pin

XBGA

Type

Buffer

Type

(Buffered Slave modes) and output (Master modes)

Pin Diagrams” section for device pin availability.

Description

PIC32MX5XX/6XX/7XX

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

PMA2 8 14 F3 O — Parallel Master Port address (Demultiplexed PMA3 6 12 F2 O — PMA4 5 11 F4 O — PMA5 4 10 E3 O — PMA6 16 29 K3 O — PMA7 22 28 L2 O — PMA8 32 50 L11 O — PMA9 31 49 L10 O — PMA10 28 42 L7 O — PMA11 27 41 J7 O — PMA12 24 35 J5 O — PMA13 23 34 L5 O — PMA14 45 71 C11 O — PMA15 44 70 D11 O — PMCS1 45 71 C11 O — Parallel Master Port Chip Select 1 strobe PMCS2 44 70 D11 O — Parallel Master Port Chip Select 2 strobe PMD0 60 93 A4 I/O TTL/ST Parallel Master Port data (Demultiplexed PMD1 61 94 B4 I/O TTL/ST PMD2 62 98 B3 I/O TTL/ST PMD3 63 99 A2 I/O TTL/ST PMD4 64 100 A1 I/O TTL/ST PMD5 1 3 D3 I/O TTL/ST PMD6 2 4 C1 I/O TTL/ST PMD7 3 5 D2 I/O TTL/ST PMD8 — 90 A5 I/O TTL/ST PMD9 — 89 E6 I/O TTL/ST PMD10 — 88 A6 I/O TTL/ST PMD11 — 87 B6 I/O TTL/ST PMD12 — 79 A9 I/O TTL/ST PMD13 — 80 D8 I/O TTL/ST PMD14 — 83 D7 I/O TTL/ST PMD15 — 84 C7 I/O TTL/ST PMALL 30 44 L8 O — Parallel Master Port address latch enable

PMALH 29 43 K7 O — Parallel Master Port address latch enable

PMRD 53 82 B8 O — Parallel Master Port read strobe PMWR 52 81 C8 O — Parallel Master Port write strobe

BUS 34 54 H8 I Analog USB bus power monitor

V VUSB 35 55 H9 P — USB internal transceiver supply VBUSON 11 20 H1 O — USB Host and OTG bus power control output

Legend: CMOS = CMOS comp atible input or output Analog = Analog input P = Power

Note 1: Pin numbers are provided for reference only. See the “

2: See

64-Pin

QFN/TQFP

ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer

Section 24.0 “Ethernet Controller” for more information.

100-Pin

TQFP

(1)

121-Pin

XBGA

Type

Buffer

Type

Master modes)

Master mode) or address/data (Multiplexed Master modes)

low byte (Multiplexed Master modes)

high byte (Multiplexed Master modes)

Pin Diagrams” section for device pin availability.

Description

PIC32MX5XX/6XX/7XX

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

64-Pin

QFN/TQFP

100-Pin

TQFP

D+ 37 57 H10 I/O Analog USB D+ D- 36 56 J11 I/O Analog USB DUSBID 33 51 K10 I ST USB OTG ID detect C1RX 58 87 B6 I ST CAN1 bus receive pin C1TX 59 88 A6 O — CAN1 bus transmit pin AC1RX 32 40 K6 I ST Alternate CAN1 bus receive pin AC1TX 31 39 L6 O — Alternate CAN1 bus transmit pin C2RX 29 90 A5 I ST CAN2 bus receive pin C2TX 21 89 E6 O — CAN2 bus transmit pin AC2RX — 8 E2 1 ST Alternate CAN2 bus receive pin AC2TX — 7 E4 O — Alternate CAN2 bus transmit pin ERXD0 61 41 J7 I ST Ethernet Receive Data 0 ERXD1 60 42 L7 I ST Ethernet Receive Data 1 ERXD2 59 43 K7 I ST Ethernet Receive Data 2

ERXD3 58 44 L8 I ST Ethernet Receive Data 3 ERXERR 64 35 J5 I ST Ethernet receive error input ERXDV 62 12 F2 I ST Ethernet receive data valid ECRSDV 62 12 F2 I ST Ethernet carrier sense data valid ERXCLK 63 14 F3 I ST Ethernet receive clock EREFCLK 63 14 F3 I ST Ethernet reference clock ETXD0 2 88 A6 O — Ethernet Transmit Data 0 ETXD1 3 87 B6 O — Ethernet Transmit Data 1 ETXD2 43 79 A9 O — Ethernet Transmit Dat a 2 ETXD3 42 80 D8 O — Ethernet Transmit Data 3 ETXERR 54 89 E6 O — Ethernet transmit error ETXEN 1 83 D7 O — Ethernet transmit enable ETXCLK 55 84 C7 I ST Ethernet transmit clock ECOL 44 10 E3 I ST Ethernet collision detect ECRS 45 11 F4 I ST Ethernet carrier sense EMDC 30 71 C11 O — Ethernet management data clock EMDIO 49 68 E9 I/O — Ethernet management data AERXD0 43 18 G1 I ST Alternate Ethernet Receive Data 0 AERXD1 42 19 G2 I ST Alternate Ethernet Receive Data 1 AERXD2 — 28 L2 I ST Alternate Ethernet Receive Data 2 AERXD3 — 29 K3 I ST Alternate Ethernet Receive Data 3 AERXERR 55 1 B2 I ST Alternate Ethernet receive error input AERXDV — 12 F2 I ST Alternate Ethernet receive data valid AECRSDV 44 12 F2 I ST Alternate Ethernet carrier sense data valid AERXCLK — 14 F3 I ST Alternate Ethernet receive clock AEREFCLK 45 14 F3 I ST Alternate Ethernet reference clock AETXD0 59 47 L9 O — Alternate Ethernet Transmit Data 0 Legend: CMOS = CMOS comp atible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer

Note 1: Pin numbers are provided for reference only. See the “

2: See

Section 24.0 “Ethernet Controller” for more information.

(1)

121-Pin

XBGA

Type

Buffer

Type

Description

(2) (2) (2)

(2)

(2) (2) (2) (2)

(2)

Pin Diagrams” section for device pin availability.

(2)

(2) (2) (2) (2)

(2)

PIC32MX5XX/6XX/7XX

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

64-Pin

QFN/TQFP

100-Pin

TQFP

AETXD1 58 48 K9 O — Alternate Ethernet Transmit Data 1 AETXD2 — 44 L8 O — Alternate Ethernet Transmit Data 2 AETXD3 — 43 K7 O — Alternate Ethernet Transmit Data 3 AETXERR — 35 J5 O — Alternate Ethernet transmit error AETXEN 54 67 E8 O — Alternate Ethernet transmi t enable AETXCLK — 66 E11 I ST Alternate Ethernet transmit clock AECOL — 42 L7 I ST Alternate Ethernet collision detect AECRS — 41 J7 I ST Alternate Ethernet carrier sense AEMDC 30 71 C11 O — Alternate Ethernet Management Data clock AEMDIO 49 68 E9 I/O — Alternate Ethernet Management Data TRCLK — 91 C5 O — Trace clock

TRD0 — 97 A3 O — Trace Data Bits 0-3 TRD1 — 96 C3 O — TRD2 — 95 C4 O — TRD3 — 92 B5 O — PGED1 16 25 K2 I/O ST Data I/O pin for Programming/Debugging

PGEC1 15 24 K1 I ST Clock input pin for Programming/Debugging

PGED2 18 27 J3 I/O ST Data I/O pin for Programming/Debugging

PGEC2 17 26 L1 I ST Clock input pin for Programming/Debugging

MCLR

7 13 F1 I/P ST Master Clear (Reset) input. This pin is an

AVDD 19 30 J4 P P Positive supply for analog modules. This pin

AVSS 20 31 L3 P P Ground reference for analog modules VDD 10, 26, 38, 572, 16, 37,

46, 62, 86

CAP/VCORE 56 85 B7 P — CPU logic filter capacitor connection

V VSS 9, 25, 41 15, 36, 45,

65, 75

VREF+ 16 29 K3 I Analog Analog voltage reference (high) input VREF- 15 28 L2 I Analog Analog vo ltage reference (low) input Legend: CMOS = CMOS comp atible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer

Note 1: Pin numbers are provided for reference only. See the “

2: See Section 24.0 “Ethernet Controller” for more information.

(1)

121-Pin

XBGA

A7, C2, C9, E5, K8, F8,

G5, H4, H6

A8, B10,

D4, D5, E7, F5,

F10, G6,

G7, H3

Type

Buffer

Type

Description

(2) (2) (2)

(2)

Communication Channel 1

Communication Channel 2

active-low Reset to the device.

must be connected at all times.

P — Positive supply for peripheral logic and I/O pins

P — Ground reference for logic and I/O pins. This

pin must be connected at all times.

Pin Diagrams” section for device pin availability.

(2)

PIC32MX5XX/6XX/7XX

2.0 GUIDELINES FOR GETTING STARTED WITH 32-BIT MICROCONTROLLERS

Note 1: This data sheet summarizes the features

of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (

www.microchip.com/PIC32).

2: Some registers and associated bits

described in this section may not be available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register and bit information.

2.1 Basic Connection Requirements

Getting started with the PIC32MX5XX/6XX/7XX family of 32-bit Microcontrollers (MCUs) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected:

• All VDD and VSS pins

Section 2.2 “Decoupling Capacitors” )

(see

• All AV

• VCAP/VCORE pin

• MCLR pin

• PGECx/PGEDx pins–used for In-Circuit Serial

• OSC1 and OSC2 pins–when external oscillator

The following pin may be required, as well: V

for ADC module is implemented

DD and AVSS pins–even if the ADC module

is not used

(see

Section 2.2 “Decoupling Capacitors” )

Section 2.3 “Capacitor on Internal

(see

Vo ltage Regulator (VCAP/VCORE)”

Section 2.4 “Master Clear (MCLR) Pin”)

(see

Programming (ICSP™) and debugging purposes

(see

Section 2.5 “ICSP Pins”)

source is used

Section 2.8 “External Oscillator Pins”)

(see

REF+/VREF- pins – used when external voltage reference

Note: The AV

connected, regardless of ADC use and the ADC voltage reference source.

DD and AVSS pins must be

)

2.2 Decoupling Capacitors

The use of decoupling capacitors on power supply pins, such as VDD, VSS, AVDD and AVSS is required. See

Figure 2-1.

Consider the following criteria when using decoupling capacitors:

• Value and type of capacitor: A value of 0.1 µF (100 nF), 10-20V is recommended. The capacitor should be a low Equivalent Series Resistance (low-ESR) capacitor and have resonance frequency in the range of 20 MHz and higher. It is further recommended that ceramic capacitors be used.

• Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended that the capacitors be placed on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within onequarter inch (6 mm) in length.

• Handling high frequency noise: If the board is experiencing high frequency noise, upward of tens of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 µF to 0.001 µF. Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. For example, 0.1 µF in parallel with 0.001 µF.

• Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum thereby reducing PCB track inductance.

PIC32MX5XX/6XX/7XX

PIC32

VDD

VSS

VDD

VSS

VDD

AVDD

AVSS

VDD

VSS

C

R

VDD

MCLR

0.1 µF Ceramic

VCAP/VCORE

10 Ω

R1

CBP

0.1 µF Ceramic CBP

CEFC

Note 1: R ≤ 10 kΩ is recommended. A suggested start-

ing value is 10 kΩ. Ensure that the MCLR

VIH and VIL specifications are met.

2: R1 ≤ 470Ω will limit any current flowing into

MCLR

from the external capacitor C, in the

event of MCLR

pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR

VIH and VIL specifications are met.

3: The capacitor can be sized to prevent uninten-

tional Resets from brief glitches or to extend the device Reset period during POR.

C

R1

R

VDD

MCLR

PIC32

JP

FIGURE 2-1: RECOMMENDED

MINIMUM CONNECTION

2.2.1 BULK CAPACITORS

The use of a bulk capacitor is recommended to improve power supply stability. T ypical values range from 4.7 µF to 47 µF. This capacitor should be located as close to the device as possible.

2.4 Master Clear (MCLR

The MCLR

pin provides for two specific device

) Pin

functions:

• Device Reset

• Device programming and debugging Pulling The MCLR

pin low generates a device Reset.

Figure 2-2 illustrates a typical MCLR circuit. During

device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR

pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R and C will need to be adjusted based on the application and PCB requirements.

For example, as illustrated in

Figure 2-2, it is

recommended that the capacitor C, be isolated from the MCLR

pin during programming and debugging

operations. Place the components illustrated in

one-quarter inch (6 mm) from the MCLR

FIGURE 2-2: EXAMPLE OF MCLR

Figure 2-2 within

pin.

CONNECTIONS

2.3 Capacitor on Internal Voltage Regulator (VCAP/VCORE)

2.3.1 INTERNAL REGULATOR MODE

A low-ESR (1 ohm) capacitor is required on the VCAP/VCORE pin, which is used to stabilize the internal voltage regulator output. The VCAP/VCORE pin must not be connected to VDD, and must have a CEFC capacitor, with at least a 6V rating, connected to ground. The type can be ceramic or tantal um. Refer to

“Electrical Characteristics”

on CEFC specifications.

for additional information

Section 31.0

PIC32MX5XX/6XX/7XX

2.5 ICSP Pins

The PGECx and PGEDx pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms.

Pull-up resistors, series diodes and capacitors on the PGECx and PGEDx pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming spe cification for information on capacitive loading limits and pin input voltage high

IH) and input low (VIL) requirements.

(V Ensure that the “Communication Channel Select” (i.e.,

PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to

®

MPLAB For more information on ICD 2, ICD 3 and REAL ICE

connection requirements, refer to the following documents that are available on the Microchip web site.

• “MPLAB

• “Using MPLAB

• “MPLAB

• “Using MPLAB

• “MPLAB® ICD 3 Design Advisory” DS51764

• “MPLAB

• “Using MPLAB

ICD 2, MPLAB ICD 3 or MPLAB REAL ICE™.

®

ICD 2 In-Circuit Debugger User’s

Guide” DS51331

User’s Guide” DS51616

DS51749

®

ICD 2” (poster) DS51265

ICD 2 Design Advisory” DS51566

®

ICD 3” (poster) DS51765

REAL ICE™ In-Circuit Debugger

®

REAL ICE™ Emulator” (poster)

2.6 JTAG

The TMS, TDO, TDI and TCK pins are used for testing and debugging according to the Joint Test Action Group (JTAG) st andard. It is recommended to keep the trace length between the JTAG connector and the JTAG pins on the device as short as possible. If the JTAG connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms.

Pull-up resistors, series diodes and capacitors on the TMS, TDO, TDI and TCK pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (V

IH) and input low (VIL) requirements.

2.7 Trace

The trace pins can be connected to a hardware-traceenabled programmer to provide a compress real time instruction trace. When used for trace the TRD3, TRD2, TRD1, TRD0 and TRCLK pins should be dedicated for this use. The trace hardware requires a22Ω series resistor between the trace pins and the trace connector.

PIC32MX5XX/6XX/7XX

Main Oscillator

Guard Ring

Guard Trace

Secondary

Oscillator

2.8 External Oscillator Pins

Many MCUs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to

Configuration”

The oscillator circuit shoul d be placed on the same side of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested layout is illustrated in

for details).

FIGURE 2-3: SUGGESTED OSCILLATOR

CIRCUIT PLACEMENT

Section 8.0 “Oscillator

Figure 2-3.

2.9 Configuration of Analog and Digital Pins During ICSP Operations

If MPLAB ICD 2, ICD 3 or REAL ICE is selected as a debugger, it automatically initializes all of the A/D input pins (ANx) as “digital” pins by setting all bits in the ADPCFG register.

The bits in this register that correspond to the A/D pins that are initialized by MPLAB ICD 2, ICD 3 or REAL ICE, must not be cleared by the user application firmware; otherwise, communication errors will result between the debugger and the device.

If your application needs to use certain A/D pins as analog input pins during the debug session, the user application must clear the corresponding bits in the ADPCFG register during initialization of the ADC module.

When MPLAB ICD 2, ICD 3 or REAL ICE is used as a programmer, the user application firmware must correctly configure the ADPCFG register. Automatic initialization of this register is only done during debugger operation. Failure to correctly configure the register(s) will result in all A/D pins being recognized as analog input pins, resulting in the port value being read as a logic ‘0’, which may affect user application functionality.

2.10 Unused I/Os

Unused I/O pins should not be allowed to float as inputs. They can be configured as outputs and driven to a logic-low state.

Alternatively, inputs can be reserved by connecting the pin to V the pin as an input.

SS through a 1k to 10k resistor and configuring

PIC32MX5XX/6XX/7XX

Dual Bus I/F

System

Coprocessor

MDU

FMT

TAP

EJTAG

Power

Management

Off-Chip

Debug I/F

Execution

Core

(RF/ALU/Shift)

Bus Matrix

Trace

Trace I/F

Bus Interface

MCU

3.0 PIC32 MCU

Note 1: This data sheet summarizes the features

of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 2. “MCU” (DS61113) in the “PIC32 Family Reference Manual”, which is available from the Microchip website (

chip.com/PIC32

MIPS32 available at

2: Some registers and associated bits

described in this section may not be available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register and bit information.

The MCU module is the heart of the PIC32MX5XX/6XX/7XX family processor. The MCU fetches instructions, decodes each instruction, fetches source operands, executes each instruction and writes the results of instruction execution to the proper destinations.

®

). Resources for the

M4K® Processor Core are

http://www.mips.com.

3.1 Features

• 5-stage pipeline

• 32-bit address and data paths

• MIPS32 Enhanced Architecture (Rele a se 2)

- Multiply-accumulate and multiply-subtract instructions

- Targeted multiply instruction

- Zero/One detect instructions

- WAIT instruction

- Conditional move instructions (MOVN, MOVZ)

- Vectored interrupts

- Programmable exception vector base

www.micro-

- Atomic interrupt enable/disable

- GPR shadow registers to minimize latency for interrupt handlers

- Bit field manipulation instructions

• MIPS16e

- 16-bit encoding of 32-bit instructions to

- Special PC-relative instructions for efficient

- SAVE and RESTORE macro instructions for

- Improved support for handling 8 and 16-bit

• Simple Fixed Mapping Translation (FMT) mechanism

• Simple dual bus interface

- Independent 32-bit address and data busses

- Transactions can be aborted to improve

• Autonomous multiply/divide unit

- Maximum issue rate of one 32x16 multiply

- Maximum issue rate of one 32x32 multiply

- Early-in iterative divide. Minimum 11 and

• Power control

- Minimum frequency: 0 MHz

- Low-Power mode (triggered by WAIT

- Extensive use of local gated clocks

• EJT AG debug and instruction trace

- Support for single stepping

- Virtual instruction and data address/value

- Breakpoints

- PC tracing with trace compression

®

code compression

improve code density

loading of addresses and constants

setting up and tearing down stack frames within subroutines

data types

interrupt latency

per clock

every other clock

maximum 33 clock latency (dividend (rs) sign extension-dependent)

instruction)

FIGURE 3-1: MCU BLOCK DIAGRAM

PIC32MX5XX/6XX/7XX

3.2 Architecture Overview

The PIC32MX5XX/6XX/7XX family core contains several logic blocks working together in parallel, providing an efficient high-performance computing engine. The following blocks are included with the core:

• Execution Unit

• Multiply/Divide Unit (MDU)

• System Control Coprocessor (CP0)

• Fixed Mapping Translation (FMT)

• Dual Internal Bus interfaces

• Power Management

• MIPS16e Support

• Enhanced JTAG (EJTAG) Controller

3.2.1 EXECUTION UNIT

The PIC32MX5XX/6XX/7XX family core execution unit implements a load/store architecture with single-cycle ALU operations (logical, shift, add, subtract) and an autonomous multiply/divide unit. The core contains thirty-two 32-bit General Purpose Registers (GPRs) used for integer operations and address calculation. One additional register file shadow set (containing thirty-two registers) is added to minimize context switching overhead during interrupt/exception processing. The register file consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline.

The execution unit includes:

• 32-bit adder used for calculating the data address

• Address unit for calculating the next instruction address

• Logic for branch determination and branch target address calculation

• Load aligner

• Bypass multiplexers used to avoid stalls when executing instruction streams where data producing instructions are followed closely by consumers of their results

• Leading Zero/One detect unit for implementing the CLZ and CLO instructions

• Arithmetic Logic Unit (ALU) for performing bitwise logical operations

• Shifter and store alig ner

3.2.2 MULTIPLY/DIVIDE UNIT (MDU)

The PIC32MX5XX/6XX/7XX family core includes a Multiply/Divide Unit (MDU) that contains a separate pipeline for multiply and divide operations. This pipeline operates in parallel with the Integer Unit (IU) pipeline and does not stall when the IU pipeline stalls. This allows MDU operations to be partially masked by system stalls and/or other integer unit instructions.

The high-performance MDU consists of a 32x16 booth recoded multiplier, result/accumulation registers (HI and LO), a divide state machine, and the necessary multiplexers and control logic. The first number shown (‘32’ of 32x16) represents the rs operand. The second number (‘16’ of 32x16) represents the rt operand. The PIC32 core only checks the value of the latter (rt) operand to determine how many times the operation must pass through the multiplier. The 16x16 and 32x16 operations pass through the multiplier once. A 32x32 operation passes through the multiplier twice.

The MDU supports execution of one 16x16 or 32x16 multiply operation every clock cycle; 32x32 multiply operations can be issued every other clock cycle. Appropriate interlocks are implemented to stall the issuance of back-to-back 32x32 multiply operations. The multiply operand size is automatically determined by logic built into the MDU.

Divide operations are implemented with a simple 1 bit per clock iterative algorithm. An early-in detection checks the sign extension of the dividend (rs) operand. If rs is 8 bits wide, 23 iterations are skipped. For a 16-bit wide rs, 15 iterations are skipped and for a 24-bit wide rs, 7 iterations are skipped. Any attempt to issue a subsequent MDU instruction while a divide is still active causes an IU pipeline stall until the divide operation is completed.

Table 3-1 lists the repeat rate (peak issue rate of cycles

until the operation can be reissued) and latency (number of cycles until a result is available) for the PIC32 core multiply and divide instructions. The approximate latency and repeat rates are listed in terms of pipeline clocks.

PIC32MX5XX/6XX/7XX

TABLE 3-1: PIC32MX5XX/6XX/7XX FAMILY CORE HIGH-PERFORMANCE INTEGER

MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES

Opcode Operand Size (mul rt) (div rs) Latency Repeat Rate

MULT/MULTU, MADD/MADDU, MSUB/MSUBU

MUL 16 bits 2 1

DIV/DIVU 8 bits 12 11

16 bits 1 1 32 bits 2 2

32 bits 3 2

16 bits 19 18 24 bits 26 25 32 bits 33 32

The MIPS architecture defines that the result of a multiply or divide operation be placed in the HI and LO registers. Using the Move-From-HI (MFHI) and MoveFrom-LO (MFLO) instructions, these values can be transferred to the General Purpose Register file.

In addition to the HI/LO targeted operations, the MIPS32 architecture also defines a multiply instruction, MUL, which places the least significant results in the primary register file instead of the HI/LO register pair. By avoiding the explicit MFLO instruction required when using the LO register, and by supporting multiple destination registers, the throughput of multiply-intensive operations is increased.

Two other instructions, Multiply-Add (MADD) and Multiply-Subtract (MSUB), are used to perform the multiply-accumulate and multiply-subtract operations. The MADD instruction multiplies two numbers and then adds the product to the current contents of the HI and LO registers. Similarly, the MSUB instruction multiplies two operands and then subtracts the product from the HI and LO registers. The MADD and MSUB operations are commonly used in DSP algorithms.

3.2.3 SYSTEM CONTROL COPROCESSOR (CP0)

In the MIPS architecture, CP0 is responsible for the virtual-to-physical address translation, the exception control system, the processor’s diagnostics capability, the operating modes (Kernel, User and Debug) and whether interrupts are enabled or disabled. Configuration information, such as presence of options like MIPS16e, is also available by accessing the CP0 registers, listed in

Table 3-2.

PIC32MX5XX/6XX/7XX

TABLE 3-2: COPROCESSOR 0 REGISTERS

Register

Number

0-6 Reserved Reserved in the PIC32MX5XX/6XX/7XX family core.

7 HWREna Enables access via the RDHWR instruction to selected hardware registers. 8 BadVAddr

9 Count 10 Reserved Reserved in the PIC32MX5XX/6XX/7XX family core. 11 Compare 12 Status 12 IntCtl 12 SRSCtl 12 SRSMap 13 Cause 14 EPC 15 PRId Processor identification and revision. 15 EBASE Exception vector base register. 16 Config Configuration register. 16 Config1 Configuration Register 1. 16 Config2 Configuration Register 2. 16 Config3 Configuration Register 3.

17-22 Reserved Reserved in the PIC32MX5XX/6XX/7XX family core.

23 Debug 24 DEPC

25-29 Reserved Reserved in the PIC32MX5XX/6XX/7XX family core.

30 ErrorEPC 31 DESAVE

Note 1: Registers used in exception processing.

2: Registers used during debug.

Register

Name

(1)

(2)

(1)

(2)

Function

Reports the address for the most recent address-related exception. Processor cycle count.

Timer interrupt control. Processor status and control. Interrupt system status and control. Shadow register set status and control. Provides mapping from vectored interrupt to a shadow set. Cause of last general exception. Program counter at last exception.

Debug control and exception status. Program counter at last debug exception.

Program counter at last error. Debug handler scratchpad register.

PIC32MX5XX/6XX/7XX

Coprocessor 0 also contains the logic for identifying and managing exceptions. Exceptions can be caused by a variety of sources, including alignment errors in data, external events or program errors. the exception types in order of priority.

TABLE 3-3: PIC32MX5XX/6XX/7XX FAMILY CORE EXCEPTION TYPES

Exception Description

Table 3-3 lists

Reset Assertion MCLR DSS EJTAG debug single step. DINT EJTAG debug interrupt. Caused by the assertion of the external EJ_DINT input or by setting the

EjtagBrk bit in the ECR register. NMI Assertion of NMI signal. Interrupt Assertion of unmasked hardware or software interrupt signal. DIB EJTAG debug hardware instruction break matched. AdEL Fetch address alignment error.

Fetch reference to protected address. IBE Instruction fetch bus error. DBp EJTAG breakpoint (execution of SDBBP instruction). Sys Execution of SYSCALL instruction. Bp Execution of BREAK instruction. RI Execution of a reserved instruction. CpU Execution of a coprocessor instruction for a coprocessor that is not enabled. CEU Execution of a CorExtend instruction when CorExtend is not enabled. Ov Execution of an arithmetic instruction that overflowed. Tr Execution of a trap (when trap condition is true). DDBL/DDBS EJTAG Data Address Break (address only) or EJTA G data value break on store (address + value). AdEL Load address alignment error.

Load reference to protected address. AdES Store address alignment error.

Store to protected address. DBE Load or store bus error. DDBL EJTAG data hardware breakpoint matched in load data compare.

or a Power-on Reset (POR).

PIC32MX5XX/6XX/7XX

3.3 Power Management

The PIC32MX5XX/6XX/7XX family core of fers a number of power management features, including low-power design, active power management and power-down modes of operation. The core is a static design that supports slowing or Halting the clocks, which reduces system power consumption during Idle periods.

3.3.1 INSTRUCTION-CONTROLLED POWER MANAGEMENT

The mechanism for invoking Power-Down mode is through execution of the WAIT instruction. For more information on power management, see

“Power-Saving Features”

.

3.3.2 LOCAL CLOCK GATING

The majority of the power consumed by the PIC32MX5XX/6XX/7XX family core is in the clock tree and clocking registers. The PIC32 family uses extensive use of local gated clocks to reduce this dynamic power consumption.

Section 27.0

3.4 EJTAG Debug Support

The PIC32MX5XX/6XX/7XX family core provides for an Enhanced JTAG (EJTAG) interface for use in the software debug of application and kernel code. In addition to standard User mode and Kernel modes of operation, the PIC32MX5XX/6XX/7XX family core provides a Debug mode that is entered after a debug exception (derived from a hardware breakpoint, singlestep exception, etc.) is taken and continues until a Debug Exception Return (DERET) instruction is executed. During this time, the processor executes the debug exception handler routine.

The EJTAG interface operates through the Test Access Port (T AP), a serial communication port used for transferring test data in and out of the PIC32MX5XX/6XX/7XX family core. In addition to the standard JTAG instructions, special instructions defined in the EJTAG specification define which registers are selected and how they are used.

PIC32MX5XX/6XX/7XX

4.0 MEMORY ORGANIZATION

Note: This data sheet summarizes the features

of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source.For detailed information, refer to Section 3. “Memory Organization” (DS61115) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (

PIC32MX5XX/6XX/7XX microcontrollers provide 4 GB of unified virtual memory address space. All memory regions, including program, data memory, SFRs and Configuration registers, reside in this address space at their respective unique addresses. The program and data memories can be optionally partitioned into user and kernel memories. In addition, the data memory can be made executable, allowing PIC32MX5XX/6XX/7XX devices to execute from data memory.

Key features include:

• 32-bit native data width

• Separate User (KUSEG) and Kernel (KSEG0/KSEG1) mode address space

• Flexible program Flash memory partitioning

• Flexible data RAM partitioning for data and program space

• Separate boot Flash memo ry for protected code

• Robust bus exception handling to intercept runaway code

• Simple memory mapping with Fixed Mapping Translation (FMT) unit

• Cacheable (KSEG0) and non-cacheable (KSEG1) address regions

www.microchip.com/PIC32).

4.1 PIC32MX5XX/6XX/7XX Memory Layout

PIC32MX5XX/6XX/7XX microcontrollers implement two address schemes: virtual and physical. All hardware resources, such as program memory, data memory and peripherals, are located at their respective physical addresses. Virtual addresses are exclusively used by the CPU to fetch and execute instructions as well as access peripherals. Physical addresses are used by bus master peripherals, such as DMA and the Flash controller, that access memory independently of the CPU.

The memory maps for the PIC32MX5XX/6XX/7XX devices are illustrated in

4.1.1 PERIPHERAL REGISTERS

LOCATIONS

Table 4-1 through Table 4-44 contain the peripheral

address maps for the PIC32MX5XX/6XX/7XX devices. Peripherals located on the PB bus are mapped to 512-byte boundaries. Peripherals on the FPB bus are mapped to 4-Kbyte boundaries.

Figure 4-1 through Figure 4-6.

PIC32MX5XX/6XX/7XX

Virtual

Memory Map

Physical

Memory Map

0xFFFFFFFF

Reserved

0xFFFFFFFF

0xBFC03000

0xBFC02FFF

Device

Configuration

Registers

0xBFC02FF0 0xBFC02FEF

Boot Flash

0xBFC00000

Reserved

0xBF900000

0xBF8FFFFF

SFRs

0xBF800000

Reserved

0xBD010000

0xBD00FFFF

Program Flash

(2)

0xBD000000

Reserved

0xA0008000

0xA0007FFF

RAM

(2)

0xA0000000 0x1FC03000

Reserved

Device

Configuration

Registers

0x1FC02FFF

0x9FC03000

0x9FC02FFF Device

Configuration

Registers

0x1FC02FF0

Boot Flash

0x1FC02FEF

0x9FC02FF0

0x9FC02FEF

Boot Flash

0x1FC00000

Reserved

0x9FC00000 0x1F900000

Reserved SFRs

0x1F8FFFFF

0x9D010000 0x1F800000

0x9D00FFFF

Program Flash

(2)

Reserved

0x9D000000 0x1D010000

Reserved

Program Flash

(2)

0x1D00FFFF

0x80008000

0x80007FFF

RAM

(2)

0x1D000000

Reserved

0x80000000 0x00008000

Reserved RAM

(2)

0x00007FFF

0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”

(DS61115)) and can be changed by initialization code provided by en d user development tools (refer to the specific development tool documentation for information).

KSEG1KSEG0

FIGURE 4-1: MEMORY MAP ON RESET FOR PIC32MX564F064H, PIC32MX564F064L,

PIC32MX664F064H AND PIC32MX664F064L DEVICES

(1)

PIC32MX5XX/6XX/7XX

Virtual

Memory Map

Physical

Memory Map

0xFFFFFFFF

Reserved

0xFFFFFFFF

0xBFC03000

0xBFC02FFF

Device

Configuration

Registers

0xBFC02FF0 0xBFC02FEF

Boot Flash

0xBFC00000

Reserved

0xBF900000

0xBF8FFFFF

SFRs

0xBF800000

Reserved

0xBD010000

0xBD00FFFF

Program Flash

(2)

0xBD000000

Reserved

0xA0004000

0xA0003FFF

RAM

(2)

0xA0000000 0x1FC03000

Reserved

Device

Configuration

Registers

0x1FC02FFF

0x9FC03000

0x9FC02FFF Device

Configuration

Registers

0x1FC02FF0

Boot Flash

0x1FC02FEF

0x9FC02FF0

0x9FC02FEF

Boot Flash

0x1FC00000

Reserved

0x9FC00000 0x1F900000

Reserved SFRs

0x1F8FFFFF

0x9D010000 0x1F800000

0x9D00FFFF

Program Flash

(2)

Reserved

0x9D000000 0x1D010000

Reserved

Program Flash

(2)

0x1D00FFFF

0x80004000

0x80003FFF

RAM

(2)

0x1D000000

Reserved

0x80000000 0x00004000

Reserved RAM

(2)

0x00003FFF

0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”

(DS61115)) and can be changed by initialization code provided by en d user development tools (refer to the specific development tool documentation for information).

KSEG1KSEG0

FIGURE 4-2: MEMORY MAP ON RESET FOR PIC32MX534F064H AND PIC32MX534F064L

(1)

DEVICES

PIC32MX5XX/6XX/7XX

Virtual

Memory Map

Physical

Memory Map

0xFFFFFFFF

Reserved

0xFFFFFFFF

0xBFC03000

0xBFC02FFF

Device

Configuration

Registers

0xBFC02FF0 0xBFC02FEF

Boot Flash

0xBFC00000

Reserved

0xBF900000

0xBF8FFFFF

SFRs

0xBF800000

Reserved

0xBD020000

0xBD01FFFF

Program Flash

(2)

0xBD000000

Reserved

0xA0008000

0xA0007FFF

RAM

(2)

0xA0000000 0x1FC03000

Reserved

Device

Configuration

Registers

0x1FC02FFF

0x9FC03000

0x9FC02FFF Device

Configuration

Registers

0x1FC02FF0

Boot Flash

0x1FC02FEF

0x9FC02FF0

0x9FC02FEF

Boot Flash

0x1FC00000

Reserved

0x9FC00000 0x1F900000

Reserved SFRs

0x1F8FFFFF

0x9D020000 0x1F800000

0x9D01FFFF

Program Flash

(2)

Reserved

0x9D000000 0x1D020000

Reserved

Program Flash

(2)

0x1D01FFFF

0x80008000

0x80007FFF

RAM

(2)

0x1D000000

Reserved

0x80000000 0x00008000

Reserved RAM

(2)

0x00007FFF

0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”

(DS61115)) and can be changed by initialization code provided by en d user development tools (refer to the specific development tool documentation for information).

KSEG1KSEG0

FIGURE 4-3: MEMORY MAP ON RESET FOR PIC32MX564F128H, PIC32MX564F128L,

PIC32MX664F128H, PIC32MX664F128L, PIC32MX764F128H AND PIC32MX764F128L DEVICES

(1)

PIC32MX5XX/6XX/7XX

Virtual

Memory Map

Physical

Memory Map

0xFFFFFFFF

Reserved

0xFFFFFFFF

0xBFC03000

0xBFC02FFF

Device

Configuration

Registers

0xBFC02FF0 0xBFC02FEF

Boot Flash

0xBFC00000

Reserved

0xBF900000

0xBF8FFFFF

SFRs

0xBF800000

Reserved

0xBD040000

0xBD03FFFF

Program Flash

(2)

0xBD000000

Reserved

0xA0010000

0xA000FFFF

RAM

(2)

0xA0000000 0x1FC03000

Reserved

Device

Configuration

Registers

0x1FC02FFF

0x9FC03000

0x9FC02FFF Device

Configuration

Registers

0x1FC02FF0

Boot Flash

0x1FC02FEF

0x9FC02FF0

0x9FC02FEF

Boot Flash

0x1FC00000

Reserved

0x9FC00000 0x1F900000

Reserved SFRs

0x1F8FFFFF

0x9D040000 0x1F800000

0x9D03FFFF

Program Flash

(2)

Reserved

0x9D000000 0x1D040000

Reserved

Program Flash

(2)

0x1D03FFFF

0x80008000

0x80007FFF

RAM

(2)

0x1D000000

Reserved

0x80000000 0x00010000

Reserved RAM

(2)

0x0000FFFF

0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”

(DS61115)) and can be changed by initialization code provided by en d user development tools (refer to the specific development tool documentation for information).

KSEG1KSEG0

FIGURE 4-4: MEMORY MAP ON RESET FOR PIC32MX575F256H, PIC32MX575F256L,

PIC32MX675F256H, PIC32MX675F256L, PIC32MX775F256H AND PIC32MX775F256L DEVICES

(1)

PIC32MX5XX/6XX/7XX

Virtual

Memory Map

Physical

Memory Map

0xFFFFFFFF

Reserved

0xFFFFFFFF

0xBFC03000

0xBFC02FFF

Device

Configuration

Registers

0xBFC02FF0

0xBFC02FEF

Boot Flash

0xBFC00000

Reserved

0xBF900000

0xBF8FFFFF

SFRs

0xBF800000

Reserved

0xBD080000

0xBD07FFFF

Program Flash

(2)

0xBD000000

Reserved

0xA0010000

0xA000FFFF

RAM

(2)

0xA0000000 0x1FC03000

Reserved

Device

Configuration

Registers

0x1FC02FFF

0x9FC03000

0x9FC02FFF Device

Configuration

Registers

0x1FC02FF0

Boot Flash

0x1FC02FEF

0x9FC02FF0

0x9FC02FEF

Boot Flash

0x1FC00000

Reserved

0x9FC00000 0x1F900000

Reserved SFRs

0x1F8FFFFF

0x9D080000 0x1F800000

0x9D07FFFF

Program Flash

(2)

Reserved

0x9D000000 0x1D080000

Reserved

Program Flash

(2)

0x1D07FFFF

0x80010000

0x8000FFFF

RAM

(2)

0x1D000000

Reserved

0x80000000 0x00010000

Reserved RAM

(2)

0x0000FFFF

0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”

(DS61115)) and can be changed by initialization code provid ed by end user development tools (refer to the specific development tool documentation for information).

KSEG1KSEG0

FIGURE 4-5: MEMORY MAP ON RESET FOR PIC32MX575F512H, PIC32MX575F512L,

PIC32MX675F512H, PIC32MX675F512L, PIC32MX775F512H AND PIC32MX775F512L DEVICES

PIC32MX5XX/6XX/7XX

Virtual

Memory Map

Physical

Memory Map

0xFFFFFFFF

Reserved

0xFFFFFFFF

0xBFC03000

0xBFC02FFF

Device

Configuration

Registers

0xBFC02FF0

0xBFC02FEF

Boot Flash

0xBFC00000

Reserved

0xBF900000

0xBF8FFFFF

SFRs

0xBF800000

Reserved

0xBD080000

0xBD07FFFF

Program Flash

(2)

0xBD000000

Reserved

0xA0020000

0xA001FFFF

RAM

(2)

0xA0000000 0x1FC03000

Reserved

Device

Configuration

Registers

0x1FC02FFF

0x9FC03000

0x9FC02FFF Device

Configuration

Registers

0x1FC02FF0

Boot Flash

0x1FC02FEF

0x9FC02FF0

0x9FC02FEF

Boot Flash

0x1FC00000

Reserved

0x9FC00000 0x1F900000

Reserved SFRs

0x1F8FFFFF

0x9D080000 0x1F800000

0x9D07FFFF

Program Flash

(2)

Reserved

0x9D000000 0x1D080000

Reserved

Program Flash

(2)

0x1D07FFFF

0x80020000

0x8001FFFF

RAM

(2)

0x1D000000

Reserved

0x80000000 0x00020000

Reserved RAM

(2)

0x0001FFFF

0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”

(DS61115)) and can be changed by initialization code provid ed by end user development tools (refer to the specific development tool documentation for information).

KSEG1KSEG0

FIGURE 4-6: MEMORY MAP ON RESET FOR PIC32MX695F512H, PIC32MX695F512L,

PIC32MX795F512H AND PIC32MX795F512L DEVICES

TABLE 4-1: BUS MATRIX REGISTER MAP

PIC32MX5XX/6XX/7XX

Bits

Name

Register

(BF88_#)

Virtual Address

2000 BMXCON

2010 BMXDKPBA

2020 BMXDUDBA

2030 BMXDUPBA

2040 BMXDRMSZ

2050 BMXPUPBA

2060 BMXPFMSZ

2070 BMXBOOTSZ

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.

(1)

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

Bit Range

31:16 — — — — — BMXCHEDMA — — — — — BMXERRIXI BMXERRICD BMXERRDMA BMXERRDS BMXERRIS 001F

15:0 — — — — — — — — —BMXWSDRM — — — BMXARB<2:0> 0041

— — — — — — — — — — — — — — — — 0000