Microchip Technology PIC24FV16KM204 FAMILY Datasheet

PIC24FV16KM204 FAMILY

General Purpose, 16-Bit Flash Microcontroller

with XLP Technology Data Sheet

Analog Peripheral Features

• Up to Two 8-Bit Digital-to-Analog Converters
(DAC):

- Soft Reset disable function allows DAC to

retain its output value through non-V
Resets

- Support for Idle mode

- Support for left and right-justified input data

• Two Operational Amplifiers (Op Amps):

- Differential inputs

- Selectable power/speed levels:

- Low power/low speed

- High power/high speed

• Up to 22-Channel, 10/12-Bit Analog-to-Digital
Converter:

- 100k samples/second at 12-bit conversion

rate (single Sample-and-Hold)

- Auto-scan with Threshold Detect

- Can operate during Sleep

- Dedicated band gap reference and

temperature sensor input

• Up to Three Rail-to-Rail Analog Comparators:

- Programmable reference voltage for

comparators

- Band gap reference input

- Flexible input multiplexing

- Low-power or high-speed selection options

• Charge Time Measurement Unit (CTMU):

- Capacitive measurement, up to 22 channels

- Time measurement down to 200 ps

resolution

- Up to 16 external Trigger pairs

• Internal Temperature Sensor with Dedicated A/D
Converter Input

DD

Multiple/Single Capture Compare Peripheral (MCCP/SCCP) Features

• 16 or 32-Bit Time Base

• 16 or 32-Bit Capture

- 4-Deep Capture Buffer

• 16 or 32-Bit Compare:

- Single Edge Compare modes

- Dual Edge Compare/PWM modes

- Center-Aligned Compare mode

- Variable Frequency Pulse mode

• Fully Asynchronous Operation, Available in
Sleep modes

• Single Output Steerable mode (MCCP only)

• Brush DC Forward and Reverse modes
(MCCP only)

• Half-Bridge with Dead-Time Delay (MCCP only)

• Push-Pull PWM mode (MCCP only)

• Auto-Shutdown with Programmable Source and
Shutdown State

• Programmable Output Polarity

 2013 Microchip Technology Inc. Advance Information DS33030A-page 1

PIC24FV16KM204 FAMILY

Memory

Peripherals

Device

FV16KM204 44 16K 2K 512 2.0-5.5 1 3/2 2 2 22 2 2 3 Yes Yes 2 3

FV16KM202 28 16K 2K 512 2.0-5.5 1 3/2 2 2 19 2 2 3 Yes Yes 2 3

FV08KM204 44 8K 2K 512 2.0-5.5 1 3/2 2 2 22 2 2 3 Yes Yes 2 3

FV08KM202 28 8K 2K 512 2.0-5.5 1 3/2 2 2 19 2 2 3 Yes Yes 2 3

FV16KM104 44 16K 1K 512 2.0-5.5 1 1/1 1 1 22 — — 1 Yes — 1 3

FV16KM102 28 16K 1K 512 2.0-5.5 1 1/1 1 1 19 — — 1 Yes — 1 3

FV08KM102 28 8K 1K 512 2.0-5.5 1 1/1 1 1 19 — — 1 Yes — 1 3

FV08KM101 20 8K 1K 512 2.0-5.5 1 1/1 1 1 16 — — 1 Yes — 1 3

F16KM204 44 16K 2K 512 1.8-3.6 1 3/2 2 2 22 2 2 3 Yes Yes 2 3

F16KM202 28 16K 2K 512 1.8-3.6 1 3/2 2 2 19 2 2 3 Yes Yes 2 3

F08KM204 44 8K 2K 512 1.8-3.6 1 3/2 2 2 22 2 2 3 Yes Yes 2 3

F08KM202 28 8K 2K 512 1.8-3.6 1 3/2 2 2 19 2 2 3 Yes Yes 2 3

F16KM104 44 16K 1K 512 1.8-3.6 1 1/1 1 1 22 — — 1 Yes — 1 3

F16KM102 28 16K 1K 512 1.8-3.6 1 1/1 1 1 19 — — 1 Yes — 1 3

F08KM102 28 8K 1K 512 1.8-3.6 1 1/1 1 1 19 — — 1 Yes — 1 3

F08KM101 20 8K 1K 512 1.8-3.6 1 1/1 1 1 16 — — 1 Yes — 1 3

Pins

Flash Program (bytes)

SRAM (bytes)

MSSP

UART

16-Bit Timer

EE Data (bytes)

Voltage Range (V)

16-Bit MCCP/SCCP

5V Devices

3V Devices

12-Bit A/D Channels

Op Amp

8-Bit DAC

CTMU

Comparators

RTCC

CLC

ICD BRKPT

DS33030A-page 2 Advance Information  2013 Microchip Technology Inc.

PIC24FV16KM204 FAMILY

Special Microcontroller Features

• Wide Operating Voltage Range Options:

- 1.8V to 3.6V (PIC24F devices)

- 2.0V to 5.0V (PIC24FV devices)

• Selectable Power Management modes:

- Idle: CPU shuts down, allowing for significant
power reduction

- Sleep: CPU and peripherals shut down for
substantial power reduction and fast wake-up

- Retention Sleep mode: PIC24FV devices can
enter Sleep mode, employing the
retention regulator, further reducing power
consumption

- Doze: CPU can run at a lower frequency than
peripherals, a user-programmable feature

- Alternate Clock modes allow on-the-fly
switching to a lower clock speed for selective
power reduction

• Fail-Safe Clock Monitor:

- Detects clock failure and switches to on-chip,
low-power RC oscillator

• Ultra Low-Power Wake-up Pin Provides an
External Trigger for Wake from Sleep

• 10,000 Erase/Write Cycle Endurance Flash
Program Memory, Typical

• 100,000 Erase/Write Cycle Endurance
Data EEPROM, Typical

• Flash and Data EEPROM Data Retention: 20 Years
Minimum

• Self-Programmable under Software Control

• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)

• Watchdog Timer (WDT) with its Own On-Chip
RC Oscillator for Reliable Operation

• On-Chip Regulator for 5V Operation

• Selectable Windowed WDT Feature

• Selectable Oscillator Options including:

- 4x Phase Locked Loop (PLL)

• 8 MHz (FRC) Internal RC Oscillator:

- HS/EC, high-speed crystal/resonator

oscillator or external clock

• In-Circuit Serial Programming™ (ICSP™) and
In-Circuit Emulation (ICE) – via Two Pins

• In-Circuit Debugging

• Programmable High/Low-Voltage
Detect (HLVD) module

• Programmable Brown-out Reset (BOR):

- Software enable feature

- Configurable shutdown in Sleep

- Auto-configures power mode and sensitivity

based on device operating speed

- LPBOR available for re-arming of the POR

High-Performance RISC CPU

• Modified Harvard Architecture

• Operating Speed:

- DC – 32 MHz clock input

- 16 MIPS at 32 MHz clock input

• 8 MHz Internal Oscillator:

- 4x PLL option

- Multiple clock divide options

- Fast start-up

• 17-Bit x 17-Bit Single-Cycle Hardware
Fractional/Integer Multiplier

• 32-Bit by 16-Bit Hardware Divider

• 16 x 16-Bit Working Register Array

• C Compiler Optimized Instruction Set Architecture

• 24-Bit-Wide Instructions

• 16-Bit-Wide Data Path

• Linear Program Memory Addressing, up to
6 Mbytes

• Linear Data Memory Addressing, up to 64 Kbytes

• Two Address Generation Units (AGUs) for Separate
Read and Write Addressing of Data Memory

Peripheral Features

• High-Current Sink/Source, 18 mA/18 mA All Ports

• Independent Ultra Low-Power, 32 kHz
Timer Oscillator

• Up to Two Master Synchronous Serial Ports
(MSSPs) with SPI and I

In SPI mode:

- User-configurable SCKx and SDOx pin outputs

- Daisy-chaining of SPI slave devices

2

In I

C mode:

- Serial clock synchronization (clock stretching)

- Bus collision detection and will arbitrate

accordingly

- Support for 16-bit read/write interface

• Up to Two Enhanced Addressable UARTs:

- LIN/J2602 bus support (auto-wake-up,

Auto-Baud Detect, Break character support)

- High and low speed (SCI)

®

-IrDA

• Two External Interrupt Pins

• Hardware Real-Time Clock and Calendar (RTCC)

• Configurable Reference Clock Output (REFO)

• Two Configurable Logic Cells (CLC)

• Up to Two Single Output Capture/Compare/PWM
(SCCP) modules and up to Three Multiple Output
Capture/Compare/PWM (MCCP) modules

mode (hardware encoder/decoder

function)

2

C™ modes:

 2013 Microchip Technology Inc. Advance Information DS33030A-page 3

PIC24FV16KM204 FAMILY

Pin

Pin Features

PIC24F08KM101 PIC24FVKM08KM101

1MCLR

/VPP/RA5

2PGC2/CV

REF+/VREF+/AN0/CN2/RA0

3PGD2/CV

REF-/VREF-/AN1/CN3/RA1

4 PGD1/AN2/CTCMP/ULPWU/C1IND/OC2A/CN4/RB0

5 PGC1/AN3/C1INC/CTED12/CN5/RB1

6 AN4/U1RX/TCKIB/CTED13/CN6/RB2

7 OSCI/CLKI/AN13/C1INB/CN30/RA2

8 OSCO/CLKO/AN14/C1INA/CN29/RA3

9 PGD3/SOSCI/AN15/CLCINA/CN1/RB4

10 PGC3/SOSCO/SCLKI/AN16/PWRLCLK/CLCINB/CN0/RA4

11 AN19/U1TX/CTED1/INT0/CN23/RB7 AN19/U1TX/IC1/OC1A/CTED1/INT0/CN23/RB7

12 AN20/SCL1/U1CTS

/OC1B/CTED10/CN22/RB8

13 AN21/SDA1/T1CK/U1RTS

/U1BCLK/IC2/CLC1O/CTED4/CN21/RB9

14 IC1/OC1A/INT2/CN8/RA6 V

CAP OR VDDCORE

15 AN12/HLVDIN/SCK1/OC1C/CTED2/CN14/RB12 AN12/HLVDIN/SCK1/OC1C/CTED2/INT2/CN14/RB12

16 AN11/SDO1/OCFB/OC1D/CTPLS/CN13/RB13

17 CV

REF/AN10/SDI1/C1OUT/OCFA/CTED5/INT1/CN12/RB14

18 AN9/REFO/SS1

/TCKIA/CTED6/CN11/RB15

19 V

SS/AVSS

20 VDD/AVDD

20-Pin SPDIP/SSOP/SOIC

PIC24F08KM101

RA5

RA3

RA0
RA1

V

DD

VSS

RB0

RB7

RA4

RB4

RB8

RA2

RB2

RB1

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

RB15
RB14
RB13

RB9

RA6

OR VDDCORE

RB12

Pin Diagrams

DS33030A-page 4 Advance Information  2013 Microchip Technology Inc.

Pin Diagrams (Continued)

20-Pin QFN

Pin

Pin Features

PIC24F08KM101 PIC24FV08KM101

1 PGD1/AN2/CTCMP/ULPWU/C1IND/OC2A/CN4/RB0

2 PGC1/AN3/C1INC/CTED12/CN5/RB1

3 AN4/U1RX/TCKIB/CTED13/CN6/RB2

4 OSCI/CLKI/AN13/C1INB/CN30/RA2

5 OSCO/CLKO/AN14/C1INA/CN29/RA3

6 PGD3/SOSCI/AN15/CLCINA/CN1/RB4

7 PGC3/SOSCO/SCLKI/AN16/PWRLCLK/CLCINB/CN0/RA4

8 AN19/U1TX/CTED1/INT0/CN23/RB7 AN19/U1TX/IC1/OC1A/CTED1/INT0/CN23/RB7

9 AN20/SCL1/U1CTS

/OC1B/CTED10/CN22/RB8

10 AN21/SDA1/T1CK/U1RTS

/U1BCLK/IC2/CLC1O/CTED4/CN21/RB9

11 IC1/OC1A/INT2/CN8/RA6 V

CAP OR VDDCORE

12 AN12/HLVDIN/SCK1/OC1C/CTED2/CN14/RB12 AN12/HLVDIN/SCK1/OC1C/CTED2/INT2/CN14/RB12

13 AN11/SDO1/OCFB/OC1D/CTPLS/CN13/RB13

14 CV

REF/AN10/SDI1/C1OUT/OCFA/CTED5/INT1/CN12/RB14

15 AN9/REFO/SS1

/TCKIA/CTED6/CN11/RB15

16 V

SS/AVSS

17 VDD/AVDD

18 MCLR/VPP/RA5 MCLR/VPP/RA5

19 PGC2/CV

REF+ /VREF+/AN0/CN2/RA0 PGC2/CVREF+ /VREF+/AN0/CN2/RA0

20 PGD2/CV

REF-/VREF-/AN1/CN3/RA1 PGD2/CVREF-/VREF-/AN1/CN3/RA1

PIC24F08KM101

2

3

1

5

4

678910

11

12

13

14

15

16

17

18

19

20

RB0

RB1

RB2

RA2

RA3

RB7

RB9

RA4

RB4

RB8

RA6 or VDDCORE

RB12

RB13

RB14

RB15

CVREF-

CV

REF+

RA5

RA0

RA1

PIC24FV16KM204 FAMILY

 2013 Microchip Technology Inc. Advance Information DS33030A-page 5

PIC24FV16KM204 FAMILY

Pin

Pin Features

PIC24FXXKMX02 PIC24FVXXKMX02

1MCLR

/VPP/RA5

2CV

REF+/VREF+/DAC1REF+/AN0/C3INC/CN2/RA0

3CV

REF-/VREF-/AN1/CN3/RA1 CVREF-/VREF-/AN1/RA1

4 PGD1/AN2/CTCMP/ULPWU/C1IND/C2INB/C3IND/U2TX/CN4/RB0

5PGC1/OA1INA/OA2INA/AN3/C1INC/C2INA/U2RX/CTED12/CN5/RB1

6 OA1INB/OA2INB/AN4/C1INB/C2IND/SDA2/U1RX/TCKIB/CTED13/CN6/RB2

7 OA1OUT/AN5/C1INA/C2INC/SCL2/CN7/RB3

8V

SS

9 OSCI/CLKI/AN13/CN30/RA2

10 OSCO/CLKO/AN14/CN29/RA3

11 SOSCI/AN15/U2RTS

/U2BCLK/CN1/RB4

12 SOSCO/SCLKI/AN16/PWRLCLK/U2CTS

/CN0/RA4

13 V

DD

14 PGD3/AN17/ASDA1/SCK2/IC4/OC1E/CLCINA/CN27/RB5

15 PGC3/AN18/ASCL1/SDO2/IC5/OC1F/CLCINB/CN24/RB6

16 AN19/U1TX/INT0/CN23/RB7 AN19/U1TX/C2OUT/OC1A/INT0/CN23/RB7

17 AN20/SCL1/U1CTS

/C3OUT/OC1B/CTED10/CN22/RB8

18 AN21/SDA1/T1CK/U1RTS

/U1BCLK/IC2/OC4/CLC1O/CTED4/CN21/RB9

19 SDI2/IC1/OC5/CLC2O/CTED3/CN9/RA7

20 C2OUT/OC1A/CTED1/INT2/CN8/RA6 V

CAP OR VDDCORE

21 PGD2/SDI1/OC3A/OC1C/CTED11/CN16/RB10

22 PGC2/SCK1/OC2A/CTED9/CN15/RB11

23 DAC1OUT/AN12/HLVDIN/SS2

/IC3/OC2B/CTED2/CN14/RB12 DAC1OUT/AN12/HLVDIN/SS2/IC3/OC2B/CTED2/INT2/CN14/

RB12

24 OA1INC/OA2INC/AN11/SDO1/OCFB/OC3B/OC1D/CTPLS/CN13/RB13

25 DAC2OUT/CV

REF/OA1IND/OA2IND/AN10/C3INB/RTCC/C1OUT/OCFA/CTED5/INT1/CN12/RB14

26 DAC2REF+/OA2OUT/AN9/C3INA/REFO/SS1

/TCKIA/CTED6/CN11/RB15

27 V

SS/AVSS

28 VDD/AVDD

28-Pin SPDIP/SSOP/SOIC

PIC24F16KMX02

MCLR/RA5

V

SS

RA0
RA1

AV

DD

AVSS

RB0

RA7

RA3

RA2

RA6 or V

DDCORE

RB3

RB2

RB1

1
2
3
4
5
6
7
8
9
10

28
27
26
25
24
23
22
21
20
19

RB15
RB14
RB13

RB10

RB11

RB12

RA4

RB6

RB5

V

DD

RB7

11
12
13
14

18
17
16
15

RB8

RB9

RB4

Legend: Values in red indicate pin function differences between PIC24F(V)XXKM202 and PIC24F(V)XXKM102 devices.

Pin Diagrams (Continued)

DS33030A-page 6 Advance Information  2013 Microchip Technology Inc.

Pin Diagrams (Continued)

Legend: Values in red indicate pin function differences between PIC24F(V)XXKM202 and PIC24F(V)XXKM102 devices.

Note 1: Exposed pad on underside of device is connected to V

SS.

28-Pin QFN

(1)

10 11

2
3

6

1

18

19

20

21

22

12 13 14

15

8

7

16

17

232425262728

9

PIC24F16KMX02

5

4

MCLR/RA5

VSS

VDD

RA0

RA1

VDD

VSS

RB0

RB6

RA4

RB4

RA7

RA3

RA2

RA6

OR VDDCORE

RB7

RB9

RB8

RB3

RB2

RB1

RB15

RB14

RB13
RB12

RB10

RB11

RB5

Pin

Pin Features Pin Features

PIC24FXXKMX02 PIC24FVXXKMX02

1 PGD1/AN2/CTCMP/ULPWU/C1IND/C2INB/C3IND/U2TX/CN4/RB0

2PGC1/OA1INA/OA2INA/AN3/C1INC/C2INA/U2RX/CTED12/CN5/RB1

3 OA1INB/OA2INB/AN4/C1INB/C2IND/SDA2/U1RX/TCKIB/CTED13/CN6/RB2

4 OA1OUT/AN5/C1INA/C2INC/SCL2/CN7/RB3

5V

SS

6 OSCI/CLKI/AN13/CN30/RA2

7 OSCO/CLKO/AN14/CN29/RA3

8 SOSCI/AN15/U2RTS

/U2BCLK/CN1/RB4

9 SOSCO/SCLKI/AN16/PWRLCLK/U2CTS

/CN0/RA4

10 V

DD

11 PGD3/AN17/ASDA1/SCK2/IC4/OC1E/CLCINA/CN27/RB5

12 PGC3/AN18/ASCL1/SDO2/IC5/OC1F/CLCINB/CN24/RB6

13 AN19/U1TX/INT0/CN23/RB7 AN19/U1TX/C2OUT/OC1A/INT0/CN23/RB7

14 AN20/SCL1/U1CTS

/C3OUT/OC1B/CTED10/CN22/RB8

15 AN21/SDA1/T1CK/U1RTS

/U1BCLK/IC2/OC4/CLC1O/CTED4/CN21/RB9

16 SDI2/IC1/OC5/CLC2O/CTED3/CN9/RA7

17 C2OUT/OC1A/CTED1/INT2/CN8/RA6 V

DDCORE/VCAP

18 PGD2/SDI1/OC3A/OC1C/CTED11/CN16/RB10

19 PGC2/SCK1/OC2A/CTED9/CN15/RB11

20 DAC1OUT/AN12/HLVDIN/SS2

/IC3/OC2B/CTED2/CN14/RB12 DAC1OUT/AN12/HLVDIN/SS2/IC3/OC2B/CTED2/INT2/CN14/RB12

21 OA1INC/OA2INC/AN11/SDO1/OCFB/OC3B/OC1D/CTPLS/CN13/RB13

22 DAC2OUT/CV

REF/OA1IND/OA2IND/AN10/C3INB/RTCC/C1OUT/OCFA/CTED5/INT1/CN12/RB14

23 DAC2REF+/OA2OUT/AN9/C3INA/REFO/SS1

/TCKIA/CTED6/CN11/RB15

24 V

SS

25 VDD

26 MCLR/VPP/RA5

27 CV

REF+/VREF+/DAC1REF+/AN0/C3INC/CN2/RA0 CVREF+/VREF+/DAC1REF+/AN0/C3INC/CTED1/CN2/RA0

28 CV

REF-/VREF-/AN1/CN3/RA1 CVREF-/VREF-/AN1/CN3/RA1

PIC24FV16KM204 FAMILY

 2013 Microchip Technology Inc. Advance Information DS33030A-page 7

PIC24FV16KM204 FAMILY

Legend: Values in red indicate pin

function differences between
PIC24F(V)XXKM202 and
PIC24F(V)XXKM102 devices.

Note 1: Exposed pad on underside of

device is connected to V

SS.

Pin

Pin Features

PIC24FXXKMX04 PIC24FVXXKMX04

1

AN21/SDA1/T1CK/U1RTS/U1BCLK/IC2/OC4/CLC1O/CTED4/CN21/RB9

2

U1RX/OC2C/CN18/RC6

3

U1TX/OC2D/CN17/RC7

4

OC2E/CN20/RC8

5

IC4/OC2F/CTED7/CN19/RC9

6

IC1/OC5/CLC2O/CTED3/CN9/RA7

7

C2OUT/OC1A/CTED1/INT2/CN8/RA6 V

CAP

or V

DDCORE

8

PGD2/SDI1/OC1C/CTED11/CN16/RB10

9

PGC2/SCK1/OC2A/CTED9/CN15/RB11

10

DAC1OUT/AN12/HLVDIN/OC2B/CTED2/

CN14/RB12

DAC1OUT/AN12/HLVDIN/OC2B/CTED2/INT2/

CN14/RB12

11

OA1INC/OA2INC/AN11/SDO1/OC1D/CTPLS/CN13/RB13

12

IC5/OC3A/CN35/RA10

13

IC3/OC3B/CTED8/CN36/RA11

14

DAC2OUT/CV

REF

/OA1IND/OA2IND/AN10/C3INB/RTCC/C1OUT/OCFA/CTED5/INT1/CN12/

RB14

15

DAC2REF+/OA2OUT/AN9/C3INA/REFO/SS1/TCKIA/CTED6/CN11/RB15

16

AV

SS

17

AV

DD

18

MCLR/VPP/RA5

19

CV

REF

+/V

REF

+/DAC1REF+/AN0/C3INC/CN2/

RA0

CV

REF

+/V

REF

+/DAC1REF+/AN0/C3INC/

CTED1/CN2/RA0

20

CV

REF

-/V

REF

-/AN1/CN3/RA1

21

PGD1/AN2/CTCMP/ULPWU/C1IND/C2INB/C3IND/U2TX/CN4/RB0

22

PGC1/OA1INA/OA2INA/AN3/C1INC/C2INA/

U2RX/CTED12/CN5//RB1

OA1INA/OA2INA/AN3/C1INC/C2INA/U2RX/

CTED12/CN5/RB1

23

OA1INB/OA2INB/AN4/C1INB/C2IND/SDA2/TCKIB/CTED13/CN6/RB2

24

OA1OUT/AN5/C1INA/C2INC/SCL2/CN7/RB3

25

AN6/CN32/RC0

26

AN7/CN31/RC1

27

AN8/CN10/RC2

28

V

DD

29

V

SS

30

OSCI/CLKI/AN13/CN30/RA2

31

OSCO/CLKO/AN14/CN29/RA3

32

OCFB/CN33/RA8

33

SOSCI/AN15/U2RTS/U2BCLK/CN1/RB4

34

SOSCO/SCLKI/AN16/PWRLCLK/U2CTS/CN0/RA4

35

SS2/CN34/RA9

36

SDI2/CN28/RC3

37

SDO2/CN25/RC4

38

SCK2/CN26/RC5

39

V

SS

40

V

DD

41

PGD3/AN17/ASDA1/OC1E/CLCINA/CN27/RB5

42

PGC3/AN18/ASCL1/OC1F/CLCINB/CN24/RB6

43

AN19/INT0/CN23/RB7 AN19/C2OUT/OC1A/INT0/CN23/RB7

44

AN20/SCL1/U1CTS/C3OUT/OC1B/CTED10/CN22/RB8

10
11

2
3
4
5
6

1

1819202122

121314

15

38

8

7

4443424140

39

16

17

29

30

31

32

33

23

24

25

26

27

28

363435

9

PIC24FXXKMX04

37

RB8

RB7

RB6

RB5

V

DD

VSS

RC5

RC4

RC3

RA9

RA4

RB4
RA8
RA3
RA2
V

SS

VDD
RC2
RC1
RC0
RB3
RB2

RB9
RC6
RC7
RC8
RC9
RA7
RA6
RB10
RB11
RB12
RB13

RB1

RB0

RA1

RA0

MCLR

/RA5

AV

DD

AVSS

RB15

RB14

RA11

RA10

44-Pin TQFP/QFN

(1)

Pin Diagrams (Continued)

DS33030A-page 8 Advance Information  2013 Microchip Technology Inc.

Pin Diagrams (Continued)

Pin

Pin Features

PIC24FXXKMX04 PIC24FVXXKMX04

1

AN21/SDA1/T1CK/U1RTS/U1BCLK/IC2/OC4/CLC1O/CTED4/CN21/RB9

2

U1RX/OC2C/CN18/RC6

3

U1TX/OC2D/CN17/RC7

4

OC2/CN20/RC8

5

IC4/OC2F/CTED7/CN19/RC9

6

IC1/OC5/CLC2O/CTED3/CN9/RA7

7VDDCORE or VCAP C2OUT/OC1A/CTED1/INT2/CN8/RA6

8n/c n/c

9

PGD2/SDI1/OC1C/CTED11/CN16/RB10

10

PGC2/SCK1/OC2A/CTED9/CN15/RB11

11

DAC1OUT/AN12/HLVDIN/OC2B/CTED2/

CN14/RB12

DAC1OUT/AN12/HLVDIN/OC2B/CTED2/

INT2/CN14/RB12

12

OA1INC/OA2INC/AN11/SDO1/OC1D/CTPLS/CN13/RB13

13

IC5/OC3A/CN35/RA10

14

IC3/OC3B/CTED8/CN36/RA11

15

DAC2OUT/CV

REF

/OA1IND/OA2IND/AN10/C3INB/RTCC/C1OUT/OCFA/CTED5/INT1/

CN12/RB14

16

DAC2REF+/OA2OUT/AN9/C3INA/REFO/SS1/TCKIA/CTED6/CN11/RB15

17 VSS/AVSS

18 VDD/AVDD

19 MCLR/VPP/RA5

20 n/c

21

CV

REF

+/V

REF

+/DAC1REF+/AN0/C3INC/

CN2/RA0

CV

REF

+/V

REF

+/DAC1REF+/AN0/C3INC/

CTED1/CN2/RA0

22

CV

REF

-/V

REF

-/AN1/CN3/RA1 CV

REF

-/V

REF

-/AN1/CN3/RA1

23

PGD1/AN2/CTCMP/ULPWU/C1IND/C2INB/C3IND/U2TX/CN4/RB0

24

PGC1/OA1INA/OA2INA/AN3/C1INC/C2INA/U2RX/CTED12/CN5/RB1

25

OA1INB/OA2INB/AN4/C1INB/C2IND/SDA2/

TCKIB/CTED13/CN6/RB2

AN4/C1INB/C2IND/SDA2/T5CK/
T4CK/CTED13/CN6/RB2

26

OA1OUT/AN5/C1INA/C2INC/SCL2/CN7/RB3

27

AN6/CN32/RC0

28

AN7/CN31/RC1

29

AN8/CN10/RC2

30 VDD

31 VSS

32 n/c

33

OSCI/AN13/CLKI/CN30/RA2

34

OSCO/CLKO/AN14/CN29/RA3

35

OCFB/CN33/RA8

36

SOSCI/AN15/U2RTS/U2BCLK/CN1/RB4

37

SOSCO/SCLKI/AN16/PWRLCLK/U2CTS/CN0/RA4

38

SS2/CN34/RA9

39

SDI2/CN28/RC3

40

SDO2/CN25/RC4

41

SCK2/CN26/RC5

42 VSS

43 VDD

44 n/c

45

PGD3/AN17/ASDA1/OC1E/CLCINA/CN27/RB5

46

PGC3/AN18/ASCL1/OC1F/CLCINB/CN24/RB6

47

AN19/C2OUT/INT0/CN23/RB7 AN19/OC1A/INT0/CN23/RB7

48

AN20/SCL1/U1CTS/C3OUT/OC1B/CTED10/CN22/RB8

48-Pin UQFN

(1)

R

B

8

R

B

7

R

B

6

R

B

5

n

/

c

V

D

D

V

S

S

R

C

5

R

C

4

R

C

3

R

A

9

R

A

4

4

8

4

7

4

6

4

5

4

4

4

3

4

2

4

1

4

0

3

9

3

8

3

7

RB9

1

36

RB4

RC6

2

35

RA8

RC7

3

34

RA3

RC8

4

33

RA2

RC9

5

32

n/c

RA7

6

PIC24FXXKMX04

31

V

SS

RA6

7

30

V

DD

n/c

8

29

RC2

RB10

9

28

RC1

RB11

10

27

RC0

RB12

11

26

RB3

RB13

12

25

RB2

1

3

1

4

1

5

1

6

1

7

1

8

1

9

2

0

2

1

2

2

2

3

2

4

R

A

1

0

R

A

1

1

R

B

1

4

R

B

1

5

V

S

S

/

A

V

S

S

V

D

D

/

A

V

D

D

n

/

c

R

A

0

R

A

1

R

B

0

R

B

1

PIC24FVXXKMX04

M

C

L

R

/

R

A

5

Legend: Values in red indicate pin

function differences between
PIC24F(V)XXKM202 and
PIC24F(V)XXKM102 devices.

Note 1: Exposed pad on underside of

device is connected to V

SS.

PIC24FV16KM204 FAMILY

 2013 Microchip Technology Inc. Advance Information DS33030A-page 9

PIC24FV16KM204 FAMILY

Table of Contents

1.0 Device Overview ........................................................................................................................................................................ 13

2.0 Guidelines for Getting Started with 16-Bit Microcontrollers........................................................................................................ 29

3.0 CPU ........................................................................................................................................................................................... 35

4.0 Memory Organization ................................................................................................................................................................. 41

5.0 Flash Program Memory.............................................................................................................................................................. 67

6.0 Data EEPROM Memory ............................................................................................................................................................. 73

7.0 Resets ........................................................................................................................................................................................ 79

8.0 Interrupt Controller ..................................................................................................................................................................... 85

9.0 Oscillator Configuration ............................................................................................................................................................ 121

10.0 Power-Saving Features............................................................................................................................................................ 131

11.0 I/O Ports ................................................................................................................................................................................... 137

12.0 Timer1 ..................................................................................................................................................................................... 141

13.0 Capture/Compare/PWM/Timer Modules (MCCP and SCCP) .................................................................................................. 143

14.0 Master Synchronous Serial Port (MSSP) ................................................................................................................................. 159

15.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 173

16.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 181

17.0 Configurable Logic Cell (CLC).................................................................................................................................................. 195

18.0 High/Low-Voltage Detect (HLVD) ............................................................................................................................................. 207

19.0 12-Bit A/D Converter with Threshold Detect ............................................................................................................................ 209

20.0 8-Bit Digital-to-Analog Converter (DAC)................................................................................................................................... 229

21.0 Dual Operational Amplifier Module ........................................................................................................................................... 233

22.0 Comparator Module.................................................................................................................................................................. 235

23.0 Comparator Voltage Reference ................................................................................................................................................ 239

24.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 241

25.0 Special Features ...................................................................................................................................................................... 249

26.0 Development Support............................................................................................................................................................... 261

27.0 Electrical Characteristics .......................................................................................................................................................... 265

28.0 Packaging Information.............................................................................................................................................................. 297

Appendix A: Revision History............................................................................................................................................................. 323

Index ................................................................................................................................................................................................. 325

The Microchip Web Site..................................................................................................................................................................... 331

Customer Change Notification Service .............................................................................................................................................. 331

Customer Support .............................................................................................................................................................................. 331

Reader Response .............................................................................................................................................................................. 332

Product Identification System............................................................................................................................................................. 333

DS33030A-page 10 Advance Information  2013 Microchip Technology Inc.

PIC24FV16KM204 FAMILY

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at [e-mail] or fax the Reader Response Form in the back of this data sheet to [phone]. We
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Most Current Data Sheet

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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

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Register on our web site at www.microchip.com to receive the most current information on all of our products.

 2013 Microchip Technology Inc. Advance Information DS33030A-page 11

PIC24FV16KM204 FAMILY

NOTES:

DS33030A-page 12 Advance Information  2013 Microchip Technology Inc.

PIC24FV16KM204 FAMILY

1.0 DEVICE OVERVIEW

This document contains device-specific information for
the following devices:

• PIC24FV08KM101 • PIC24F08KM101

• PIC24FV08KM102 • PIC24F08KM102

• PIC24FV16KM102 • PIC24F16KM102

• PIC24FV16KM104 • PIC24F16KM104

• PIC24FV08KM202 • PIC24F08KM202

• PIC24FV08KM204 • PIC24F08KM204

• PIC24FV16KM202 • PIC24F16KM202

• PIC24FV16KM204 • PIC24F16KM204

The PIC24FV16KM204 family introduces many new
analog features to the extreme low-power Microchip
devices. This is a 16-bit microcontroller family with a
broad peripheral feature set and enhanced computa­tional performance. This family also offers a new
migration option for those high-performance applica­tions which may be outgrowing their 8-bit platforms, but
do not require the numerical processing power of a
Digital Signal Processor (DSC).

1.1 Core Features

1.1.1 16-BIT ARCHITECTURE

Central to all PIC24F devices is the 16-bit modified
Harvard architecture, first introduced with Microchip’s
dsPIC® Digital Signal Controllers. The PIC24F CPU
core offers a wide range of enhancements, such as:

• 16-bit data and 24-bit address paths with the
ability to move information between data and
memory spaces

• Linear addressing of up to 16 Mbytes (program
space) and 16 Kbytes (data)

• A 16-element working register array with built-in
software stack support

• A 17 x 17 hardware multiplier with support for
integer math

• Hardware support for 32-bit by 16-bit division

• An instruction set that supports multiple address­ing modes and is optimized for high-level
languages, such as C

• Operational performance up to 16 MIPS

1.1.2 POWER-SAVING TECHNOLOGY

All of the devices in the PIC24FV16KM204 family incor­porate a range of features that can significantly reduce
power consumption during operation. Key features
include:

• On-the-Fly Clock Switching, to allow the device
clock to be changed under software control to the
Timer1 source or the internal, low-power RC
oscillator during operation, allowing users to
incorporate power-saving ideas into their software
designs.

• Doze Mode Operation, when timing-sensitive
applications, such as serial communications,
require the uninterrupted operation of peripherals,
the CPU clock speed can be selectively reduced,
allowing incremental power savings without
missing a beat.

• Instruction-Based Power-Saving Modes, to allow
the microcontroller to suspend all operations or
selectively shut down its core while leaving its
peripherals active with a single instruction in
software.

1.1.3 OSCILLATOR OPTIONS AND

FEATURES

The PIC24FV16KM204 family offers five different oscil­lator options, allowing users a range of choices in
developing application hardware. These include:

• Two Crystal modes using crystals or ceramic
resonators.

• Two External Clock modes offering the option of a
divide-by-2 clock output.

• Two Fast Internal oscillators (FRCs), one with a
nominal 8 MHz output and the other with a
nominal 500 kHz output. These outputs can also
be divided under software control to provide clock
speed as low as 31 kHz or 2 kHz.

• A Phase Locked Loop (PLL) frequency multiplier,
available to the external oscillator modes and the
8 MHz FRC oscillator, which allows clock speeds
of up to 32 MHz.

• A separate internal RC oscillator (LPRC) with a
fixed 31 kHz output, which provides a low-power
option for timing-insensitive applications.

The internal oscillator block also provides a stable ref­erence source for the Fail-Safe Clock Monitor (FSCM).
This option constantly monitors the main clock source
against a reference signal provided by the internal
oscillator and enables the controller to switch to the
internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.

 2013 Microchip Technology Inc. Advance Information DS33030A-page 13

PIC24FV16KM204 FAMILY

1.1.4 EASY MIGRATION

The PIC24FV16KM204 family devices have two
variants. The KM20X variant provides the full feature set
of the device, while the KM10X offers a reduced periph­eral set, allowing for the balance of features and cost
(refer to Ta bl e 1- 1 ). Both variants allow for a smooth
migration path as applications grow and evolve.

The consistent pinout scheme used throughout the entire
family also helps in migrating to the next larger device.
This is true when moving between devices with the same
pin count, different die variants, or even moving from
20-pin or 28-pin devices to 44-pin/48-pin devices.

The PIC24F family is pin compatible with devices in the
dsPIC33 family, and shares some compatibility with the
pinout schema for PIC18 and dsPIC30. This extends
the ability of applications to grow from the relatively
simple to the powerful and complex, yet still selecting a
Microchip device.

1.2 Other Special Features

• Communications: The PIC24FV16KM204 family
incorporates a range of serial communication
peripherals to handle a range of application
requirements. There is an MSSP module which
implements both SPI and I2C™ protocols, and
supports both Master and Slave modes of
operation for each. Devices also include one of
two UARTs with built-in IrDA

• Analog Features: Select members of the
PIC24FV16KM204 family include two 8-bit
Digital-to-Analog Converters which offer support
in Idle mode, and left and right-justified input data,
as well as up to two operational amplifiers with
selectable power and speed modes.

• Real-Time Clock/Calendar (RTCC): This module
implements a full-featured clock and calendar with
alarm functions in hardware, freeing up timer
resources and program memory space for use of
the core application.

• 12-Bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period and
faster sampling speed. The 16-deep result buffer
can be used either in Sleep, to reduce power, or in
Active mode to improve throughput.

• Charge Time Measurement Unit (CTMU) Interface:
The PIC24FV16KM204 family includes the new
CTMU interface module, which can be used for
capacitive touch sensing, proximity sensing, and
also for precision time measurement and pulse
generation. The CTMU can also be connected to
the operational amplifiers to provide active guard­ing, which provides increased robustness in the
presence of noise in capacitive touch applications.

®

encoders/decoders.

1.3 Details on Individual Family Members

Devices in the PIC24FV16KM204 family are available
in 20-pin, 28-pin, 44-pin and 48-pin packages. The
general block diagram for all devices is shown in

Figure 1-1.

Members of the PIC24FV16KM204 family are available
as both standard and high-voltage devices. High-voltage
devices, designated with an “FV” in the part number
(such as PIC24FV16KM204), accommodate an operat-

DD range of 2.0V to 5.5V and have an on-board

ing V
voltage regulator that powers the core. Peripherals
operate at V

Standard devices, designated by “F” (such as
PIC24F16KM204), function over a lower VDD range of

1.8V to 3.6V. These parts do not have an internal regu-

lator, and both the core and peripherals operate directly
from V

The PIC24FV16KM204 family may be thought of as
two different device groups, both offering slightly differ­ent sets of features. These differ from each other in
multiple ways:

• The size of the Flash program memory

• The number of external analog channels available

• The number of Digital-to-Analog Converters

• The number of operational amplifiers

• The number of analog comparators

• The presence of a Real-Time Clock and Calendar

(RTCC)

• The number and type of CCP modules (i.e.,

MCCP vs. SCCP)

• The number of serial communication modules

(both MSSPs and UARTs)

• The number of Configurable Logic

Cell (CLC) modules.

The general differences between the different
sub-families are shown in Ta bl e 1- 1 and Ta bl e 1- 2.

A list of the pin features available on the
PIC24FV16KM204 family devices, sorted by function,
is provided in Table 1-5.

DD.

DD.

DS33030A-page 14 Advance Information  2013 Microchip Technology Inc.

PIC24FV16KM204 FAMILY

TABLE 1-1: DEVICE FEATURES FOR THE PIC24F16KM204 FAMILY

Features

PIC24F16KM204

Operating Frequency DC-32 MHz

Program Memory (bytes) 16K 8K 16K 8K

Program Memory (instructions) 5632 2816 5632 2816

Data Memory (bytes) 2048

Data EEPROM Memory (bytes) 512

Interrupt Sources (soft vectors/NMI traps) 40 (36/4)

Voltage Range 1.8-3.6V

I/O Ports PORTA<11:0>

PORTB<15:0>

PORTC<9:0>

Total I/O Pins 38 24

Timers 11

(One 16-Bit Timer, five MCCP/SCCP with up to two 16/32 timers each)

Capture/Compare/PWM modules
MCCP
SCCP

Serial Communications
MSSP
UART

Input Change Notification Interrupt 37 23

12-Bit Analog-to-Digital Module
(input channels)

Analog Comparators 3

8-Bit Digital-to-Analog Converters 2

Operational Amplifiers 2

Charge Time Measurement Unit (CTMU) Yes

Real-Time Clock and Calendar (RTCC) Yes

Configurable Logic Cell (CLC) 2

Resets (and delays) POR, BOR, RESET Instruction, MCLR

Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations

Packages 44-Pin QFN/TQFP,

22 22 19 19

REPEAT Instruction, Hardware Traps, Configuration Word Mismatch

48-Pin UQFN

PIC24F08KM204

3
2

2
2

(PWRT, OST, PLL Lock)

PIC24F16KM202

, WDT, Illegal Opcode,

SPDIP/SSOP/SOIC/QFN

PIC24F08KM202

PORTA<7:0>

PORTB<15:0>

28-Pin

 2013 Microchip Technology Inc. Advance Information DS33030A-page 15

PIC24FV16KM204 FAMILY

TABLE 1-2: DEVICE FEATURES FOR THE PIC24F16KM104 FAMILY

Features

PIC24F16KM104

Operating Frequency DC-32 MHz

Program Memory (bytes) 16K 16K 8K 8K

Program Memory (instructions) 5632 5632 2816 2816

Data Memory (bytes) 1024

Data EEPROM Memory (bytes) 512

Interrupt Sources (soft vectors/NMI traps) 25 (21/4)

Voltage Range 1.8-3.6V

I/O Ports PORTA<11:0>

PORTB<15:0>

PORTC<9:0>

Total I/O Pins 38 24 18

Timers 5

(One 16-Bit Timer, two MCCP/SCCP with up to two 16/32 timers each)

Capture/Compare/PWM modules
MCCP
SCCP

Serial Communications
MSSP
UART

Input Change Notification Interrupt 37 23 17

12-Bit Analog-to-Digital Module
(input channels)

Analog Comparators 1

8-Bit Digital-to-Analog Converters

Operational Amplifiers —

Charge Time Measurement Unit (CTMU) Yes

Real-Time Clock and Calendar (RTCC) —

Configurable Logic Cell (CLC) 1

Resets (and delays) POR, BOR, RESET Instruction, MCLR

Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations

Packages 44-Pin

22 19 16

REPEAT Instruction, Hardware Traps, Configuration Word Mismatch

QFN/TQFP,

48-Pin UQFN

PIC24F16KM102

PORTA<7:0>

PORTB<15:0>

1
1

1
1

—

(PWRT, OST, PLL Lock)

28-Pin

SPDIP/SSOP/SOIC/QFN

PIC24F08KM102

, WDT, Illegal Opcode,

PIC24F08KM101

PORTA<6:0>

PORTB<15:12,9:7,

4,2:0>

20-Pin

SOIC/SSOP/SPDIP

DS33030A-page 16 Advance Information  2013 Microchip Technology Inc.

PIC24FV16KM204 FAMILY

TABLE 1-3: DEVICE FEATURES FOR THE PIC24FV16KM204 FAMILY

Features

PIC24FV16KM204

Operating Frequency DC-32 MHz

Program Memory (bytes) 16K 8K 16K 8K

Program Memory (instructions) 5632 2816 5632 2816

Data Memory (bytes) 2048

Data EEPROM Memory (bytes) 512

Interrupt Sources (soft vectors/NMI traps) 40 (36/4)

Voltage Range 2.0-5.5V

I/O Ports PORTA<11:7,5:0>

PORTB<15:0>

PORTC<9:0>

Total I/O Pins 37 23

Timers 11

(One 16-Bit Timer, five MCCP/SCCP with up to two 16/32 timers each)

Capture/Compare/PWM modules
MCCP
SCCP

Serial Communications
MSSP
UART

Input Change Notification Interrupt 36 22

12-Bit Analog-to-Digital Module
(input channels)

Analog Comparators 3

8-Bit Digital-to-Analog Converters

Operational Amplifiers 2

Charge Time Measurement Unit (CTMU) Yes

Real-Time Clock and Calendar (RTCC) Yes

Configurable Logic Cell (CLC) 2

Resets (and delays) POR, BOR, RESET Instruction, MCLR

REPEAT Instruction, Hardware Traps, Configuration Word Mismatch

Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations

Packages 44-Pin QFN/TQFP,

22 19

48-Pin UQFN

PIC24FV08KM204

3
2

2
2

2

(PWRT, OST, PLL Lock)

PIC24FV16KM202

PORTA<7,5:0>

, WDT, Illegal Opcode,

SPDIP/SSOP/SOIC/QFN

PIC24FV08KM202

PORTB<15:0>

28-Pin

 2013 Microchip Technology Inc. Advance Information DS33030A-page 17

PIC24FV16KM204 FAMILY

TABLE 1-4: DEVICE FEATURES FOR THE PIC24FV16KM104 FAMILY

Features

PIC24FV16KM104

Operating Frequency DC-32 MHz

Program Memory (bytes) 16K 16K 8K 8K

Program Memory (instructions) 5632 5632 2816 2816

Data Memory (bytes) 1024

Data EEPROM Memory (bytes) 512

Interrupt Sources (soft vectors/NMI traps) 25 (21/4)

Voltage Range 2.0-5.5V

I/O Ports PORTA<11:7,5:0>

PORTB<15:0>

PORTC<9:0>

Total I/O Pins 37 23 17

Timers 5

(One 16-Bit Timer, two MCCP/SCCP with up to two 16/32 timers each)

Capture/Compare/PWM modules
MCCP
SCCP

Serial Communications
MSSP
UART

Input Change Notification Interrupt 36 22 16

12-Bit Analog-to-Digital Module
(input channels)

Analog Comparators 1

8-Bit Digital-to-Analog Converters

Operational Amplifiers —

Charge Time Measurement Unit (CTMU) Yes

Real-Time Clock and Calendar (RTCC) —

Configurable Logic Cell (CLC) 1

Resets (and delays) POR, BOR, RESET Instruction, MCLR

Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations

Packages 44-Pin

22 19 16

REPEAT Instruction, Hardware Traps, Configuration Word Mismatch

QFN/TQFP,

48-Pin UQFN

PIC24FV16KM102

PORTA<7,5:0>

PORTB<15:0>

1
1

1
1

—

(PWRT, OST, PLL Lock)

28-Pin

SPDIP/SSOP/SOIC/QFN

PIC24FV08KM102

, WDT, Illegal Opcode,

PIC24FV08KM101

PORTA<5:0>

PORTB<15:12,9:7,

4,2:0>

20-Pin

SOIC/SSOP/SPDIP

DS33030A-page 18 Advance Information  2013 Microchip Technology Inc.

PIC24FV16KM204 FAMILY

Instruction

Decode and

Control

16

PCH

16

Program Counter

23

24

Data Bus

16

Divide

Support

16

16

16

8

Interrupt

Controller

PSV and Table

Data Access

Control Block

Repeat
Control

Logic

Data Latch

Data RAM

Address

Latch

Address Latch

Program Memory

Data Latch

16

Address Bus

Literal Data

23

Control Signals

16

16

16 x 16

W Reg Array

Multiplier

17x17

PORTA

(1)

RA<0:7>

PORTB

(1)

RB<0:15>

Note 1: All pins or features are not implemented on all device pinout configurations. See Table 1-5 for I/O port

pin descriptions.

Comparators

MCCP1-3 CTMU

Op Amp

A/D

12-Bit

DAC1/2

MSSP1/2

CLC1/2

CN1-36

(1)

UART1/2

Data EEPROM

OSCI/CLKI

OSCO/CLKO

V

DD

, V

SS

Timi ng

Generation

MCLR

Power-up

Time r

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Time r

BOR

FRC/LPRC
Oscillators

DSWDT

Timer1RTCC

REFO

HLVD

PORTC

(1)

RC<9:0>

Precision

Reference

Band Gap

Voltage

V

CAP

Regulator

SCCP4/5

(I2C™, SPI)

1/2

PCL

Stac k

Control

Logic

Read AGU
Write AGU

EA MUX

Inst Latch

Inst Register

16-Bit ALU

FIGURE 1-1: PIC24FV16KM204 FAMILY GENERAL BLOCK DIAGRAMS

 2013 Microchip Technology Inc. Advance Information DS33030A-page 19

DS33030A-page 20 Advance Information  2013 Microchip Technology Inc.

TABLE 1-5: PIC24FV16KM204 FAMILY PINOUT DESCRIPTION

FFV

Pin Number Pin Number

Function

AN0 2 2 27 19 21 2 2 27 19 21 I ANA A/D Analog Inputs

AN1 3 3 28 20 22 3 3 28 20 22 I ANA A/D Analog Inputs

AN2 4 4 1 21 23 4 4 1 21 23 I ANA A/D Analog Inputs

AN3 5 5 2 22 24 5 5 2 22 24 I ANA A/D Analog Inputs

AN4 6 6 3 23 25 6 6 3 23 25 I ANA A/D Analog Inputs

AN5 — 7 4 24 26 — 7 4 24 26 I ANA A/D Analog Inputs

AN6 — — — 25 27 — — — 25 27 I ANA A/D Analog Inputs

AN7 — — — 26 28 — — — 26 28 I ANA A/D Analog Inputs

AN8 — — — 27 29 — — — 27 29 I ANA A/D Analog Inputs

AN9 18 26 23 15 16 18 26 23 15 16 I ANA A/D Analog Inputs

AN10 17 25 22 14 15 17 25 22 14 15 I ANA A/D Analog Inputs

AN11 16 24 21 11 12 16 24 21 11 12 I ANA A/D Analog Inputs

AN12 15 23 20 10 11 15 23 20 10 11 I ANA A/D Analog Inputs

AN13 7 9 6 30 33 7 9 6 30 33 I ANA A/D Analog Inputs

AN14 8 10 7 31 34 8 10 7 31 34 I ANA A/D Analog Inputs

AN15 9 11 8 33 36 9 11 8 33 36 I ANA A/D Analog Inputs

AN16 10 12 9 34 37 10 12 9 34 37 I ANA A/D Analog Inputs

AN17 — 14 11 41 45 — 14 11 41 45 I ANA A/D Analog Inputs

AN18 — 15 12 42 46 — 15 12 42 46 I ANA A/D Analog Inputs

AN19 11 16 13 43 47 11 16 13 43 47 I ANA A/D Analog Inputs

AN20 12 17 14 44 48 12 17 14 44 48 I ANA A/D Analog Inputs

AN21 13 18 15 1 1 13 18 15 1 1 I ANA A/D Analog Inputs

ASCL1 — 15 12 42 46 — 15 12 42 46 I/O I

ASDA1 — 14 11 41 45 — 14 11 41 45 I/O I

DD 20 28 25 17 18 20 28 25 17 18 P — A/D Supply Pins

AV

SS 19 27 24 16 17 19 27 24 16 17 P — A/D Supply Pins

AV

C1INA 8 7 4 24 26 8 7 4 24 26 I ANA Comparator 1 Input A (+)

C1INB 7 6 3 23 25 7 6 3 23 25 I ANA Comparator 1 Input B (-)

C1INC 5 5 2 22 24 5 5 2 22 24 I ANA Comparator 1 Input C (+)

C1IND 4 4 1 21 23 4 4 1 21 23 I ANA Comparator 1 Input D (-)

Legend: ANA = Analog level input/output, ST = Schmitt Trigger input buffer, I

20-Pin

PDIP/

SSOP/

SOIC

28-Pin

PDIP/

SSOP/

SOIC

28-Pin

QFN

44-Pin

QFN/

TQFP

48-Pin

UQFN

20-Pin

PDIP/

SSOP/

SOIC

28-Pin

PDIP/

SSOP/

SOIC

2

C™ = I2C/SMBus input buffer

28-Pin

QFN

44-Pin

QFN/

TQFP

48-Pin
UQFN

I/O Buffer Description

2

C™ Alternate I2C1 Clock Input/Output

2

C Alternate I2C1 Data Input/Output

PIC24FV16KM204 FAMILY

 2013 Microchip Technology Inc. Advance Information DS33030A-page 21

TABLE 1-5: PIC24FV16KM204 FAMILY PINOUT DESCRIPTION (CONTINUED)

FFV

Pin Number Pin Number

Function

C1OUT 17 25 22 14 15 17 25 22 14 15 O — Comparator 1 Output

C2INA — 5 2 22 24 — 5 2 22 24 I ANA Comparator 2 Input A (+)

C2INB — 4 1 21 23 — 4 1 21 23 I ANA Comparator 2 Input B (-)

C2INC — 7 4 24 26 — 7 4 24 26 I ANA Comparator 2 Input C (+)

C2IND — 6 3 23 25 — 6 3 23 25 I ANA Comparator 2 Input D (-)

C2OUT — 20 17 7 7 — 16 13 43 47 O — Comparator 2 Output

C3INA — 26 23 15 16 — 26 23 15 16 I ANA Comparator 3 Input A (+)

C3INB — 25 22 14 15 — 25 22 14 15 I ANA Comparator 3 Input B (-)

C3INC —2271921—2271921IANAComparator 3 Input C (+)

C3IND — 4 1 21 23 — 4 1 21 23 I ANA Comparator 3 Input D (-)

C3OUT — 17 14 44 48 — 17 14 44 48 O — Comparator 3 Output

CLC1O 131815 1 1 131815 1 1O—CLC 1 Output

CLC2O — 19 16 6 6 — 19 16 6 6 O — CLC 2 Output

CLCINA 9 14 11 41 45 9 14 11 41 45 I ST CLC External Input A

CLCINB 10 15 12 42 46 10 15 12 42 46 I ST CLC External Input B

CLKI 7 9 6 30 33 7 9 6 30 33 I ANA Primary Clock Input

CLKO 8 10 7 31 34 8 10 7 31 34 O — System Clock Output

CN0 10 12 9 34 37 10 12 9 34 37 I ST Interrupt-on-Change Inputs

CN1 9 11 8 33 36 9 11 8 33 36 I ST Interrupt-on-Change Inputs

CN2 2 2 27 19 21 2 2 27 19 21 I ST Interrupt-on-Change Inputs

CN3 3 3 28 20 22 3 3 28 20 22 I ST Interrupt-on-Change Inputs

CN4 4 4 1 21 23 4 4 1 21 23 I ST Interrupt-on-Change Inputs

CN5 5 5 2 22 24 5 5 2 22 24 I ST Interrupt-on-Change Inputs

CN6 6 6 3 23 25 6 6 3 23 25 I ST Interrupt-on-Change Inputs

CN7 — 7 4 24 26 — 7 4 24 26 I ST Interrupt-on-Change Inputs

CN8 14 20 17 7 7 — — — — — I ST Interrupt-on-Change Inputs

CN9 — 19 16 6 6 — 19 16 6 6 I ST Interrupt-on-Change Inputs

CN10 — — — 27 29 — — — 27 29 I ST Interrupt-on-Change Inputs

CN11 18 26 23 15 16 18 26 23 15 16 I ST Interrupt-on-Change Inputs

CN12 17 25 22 14 15 17 25 22 14 15 I ST Interrupt-on-Change Inputs

Legend: ANA = Analog level input/output, ST = Schmitt Trigger input buffer, I

20-Pin

PDIP/

SSOP/

SOIC

28-Pin

PDIP/

SSOP/

SOIC

28-Pin

QFN

44-Pin

QFN/

TQFP

48-Pin

UQFN

20-Pin

PDIP/

SSOP/

SOIC

28-Pin

PDIP/

SSOP/

SOIC

2

C™ = I2C/SMBus input buffer

28-Pin

QFN

44-Pin

QFN/

TQFP

48-Pin
UQFN

I/O Buffer Description

PIC24FV16KM204 FAMILY

DS33030A-page 22 Advance Information  2013 Microchip Technology Inc.

TABLE 1-5: PIC24FV16KM204 FAMILY PINOUT DESCRIPTION (CONTINUED)

FFV

Pin Number Pin Number

Function

CN13 16 24 21 11 12 16 24 21 11 12 I ST Interrupt-on-Change Inputs

CN14 15 23 20 10 11 15 23 20 10 11 I ST Interrupt-on-Change Inputs

CN15 — 22 19 9 10 — 22 19 9 10 I ST Interrupt-on-Change Inputs

CN16 — 21 18 8 9 — 21 18 8 9 I ST Interrupt-on-Change Inputs

CN17 — — — 3 3 — — — 3 3 I ST Interrupt-on-Change Inputs

CN18 — — — 2 2 — — — 2 2 I ST Interrupt-on-Change Inputs

CN19 — — — 5 5 — — — 5 5 I ST Interrupt-on-Change Inputs

CN20 — — — 4 4 — — — 4 4 I ST Interrupt-on-Change Inputs

CN21 13 18 15 1 1 13 18 15 1 1 I ST Interrupt-on-Change Inputs

CN22 12 17 14 44 48 12 17 14 44 48 I ST Interrupt-on-Change Inputs

CN23 11 16 13 43 47 11 16 13 43 47 I ST Interrupt-on-Change Inputs

CN24 — 15 12 42 46 — 15 12 42 46 I ST Interrupt-on-Change Inputs

CN25 — — — 37 40 — — — 37 40 I ST Interrupt-on-Change Inputs

CN26 — — — 38 41 — — — 38 41 I ST Interrupt-on-Change Inputs

CN27 — 14 11 41 45 — 14 11 41 45 I ST Interrupt-on-Change Inputs

CN28 — — — 36 39 — — — 36 39 I ST Interrupt-on-Change Inputs

CN29 8 10 7 31 34 8 10 7 31 34 I ST Interrupt-on-Change Inputs

CN30 7 9 6 30 33 7 9 6 30 33 I ST Interrupt-on-Change Inputs

CN31 — — — 26 28 — — — 26 28 I ST Interrupt-on-Change Inputs

CN32 — — — 25 27 — — — 25 27 I ST Interrupt-on-Change Inputs

CN33 — — — 32 35 — — — 32 35 I ST Interrupt-on-Change Inputs

CN34 — — — 35 38 — — — 35 38 I ST Interrupt-on-Change Inputs

CN35 — — — 12 13 — — — 12 13 I ST Interrupt-on-Change Inputs

CN36 — — — 13 14 — — — 13 14 I ST Interrupt-on-Change Inputs

CTCMP 4 4 1 21 23 4 4 1 21 23 I ANA CTMU Comparator Input

Legend: ANA = Analog level input/output, ST = Schmitt Trigger input buffer, I

20-Pin

PDIP/

SSOP/

SOIC

28-Pin

PDIP/

SSOP/

SOIC

28-Pin

QFN

44-Pin

QFN/

TQFP

48-Pin

UQFN

20-Pin

PDIP/

SSOP/

SOIC

28-Pin

PDIP/

SSOP/

SOIC

2

C™ = I2C/SMBus input buffer

28-Pin

QFN

44-Pin

QFN/

TQFP

48-Pin
UQFN

I/O Buffer Description

PIC24FV16KM204 FAMILY

 2013 Microchip Technology Inc. Advance Information DS33030A-page 23

TABLE 1-5: PIC24FV16KM204 FAMILY PINOUT DESCRIPTION (CONTINUED)

FFV

Pin Number Pin Number

Function

CTED1 11 20 17 7 7 11 2 27 19 21 I ST CTMU Trigger Edge Inputs

CTED2 15 23 20 10 11 15 23 20 10 11 I ST CTMU Trigger Edge Inputs

CTED3 — 19 16 6 6 — 19 16 6 6 I ST CTMU Trigger Edge Inputs

CTED4 13 18 15 1 1 13 18 15 1 1 I ST CTMU Trigger Edge Inputs

CTED5 17 25 22 14 15 17 25 22 14 15 I ST CTMU Trigger Edge Inputs

CTED6 18 26 23 15 16 18 26 23 15 16 I ST CTMU Trigger Edge Inputs

CTED7 — — — 5 5 — — — 5 5 I ST CTMU Trigger Edge Inputs

CTED8 — — — 13 14 — — — 13 14 I ST CTMU Trigger Edge Inputs

CTED9 — 22 19 9 10 — 22 19 9 10 I ST CTMU Trigger Edge Inputs

CTED10 12 17 14 44 48 12 17 14 44 48 I ST CTMU Trigger Edge Inputs

CTED11 — 21 18 8 9 — 21 18 8 9 I ST CTMU Trigger Edge Inputs

CTED12 5 5 2 22 24 5 5 2 22 24 I ST CTMU Trigger Edge Inputs

CTED13 6 6 3 23 25 6 6 3 23 25 I ST CTMU Trigger Edge Inputs

CTPLS 16 24 21 11 12 16 24 21 11 12 O — CTMU Pulse Output

REF 17 25 22 14 15 17 25 22 14 15 O ANA Comparator Voltage Reference Output

CV

REF+ 2 2 27 19 21 2 2 27 19 21 I ANA Comparator Voltage Reference Positive Input

CV

REF- 3 3 28 20 22 3 3 28 20 22 I ANA Comparator Voltage Reference Negative Input

CV

DAC1OUT — 23 20 10 11 — 23 20 10 11 O ANA DAC1 Output

DAC1REF+ — 2 27 19 21 — 2 27 19 21 I ANA DAC1 Positive Voltage Reference Input

DAC2OUT — 25 22 14 15 — 25 22 14 15 O ANA DAC2 Output

DAC2REF+ — 26 23 15 16 — 26 23 15 16 I ANA DAC2 Positive Voltage Reference Input

HLVDIN 15 23 20 10 11 15 23 20 10 11 I ANA External High/Low-Voltage Detect Input

IC1 14 19 16 6 6 11 19 16 6 6 I ST MCCP1 Input Capture Input

IC2 13 18 15 1 1 13 18 15 1 1 I ST MCCP2 Input Capture Input

IC3 — 23 20 13 14 — 23 20 13 14 I ST MCCP3 Input Capture Input

IC4 — 14 11 5 5 — 14 11 5 5 I ST SCCP4 Input Capture Input

IC5 — 15 12 12 13 — 15 12 12 13 I ST SCCP5 Input Capture Input

INT0 11 16 13 43 47 11 16 13 43 47 I ST External Interrupt 0 Input

INT1 17 25 22 14 15 17 25 22 14 15 I ST External Interrupt 1 Input

INT2 14 20 17 7 7 15 23 20 10 11 I ST External Interrupt 2 Input

Legend: ANA = Analog level input/output, ST = Schmitt Trigger input buffer, I

20-Pin

PDIP/

SSOP/

SOIC

28-Pin

PDIP/

SSOP/

SOIC

28-Pin

QFN

44-Pin

QFN/

TQFP

48-Pin

UQFN

20-Pin

PDIP/

SSOP/

SOIC

28-Pin

PDIP/

SSOP/

SOIC

2

C™ = I2C/SMBus input buffer

28-Pin

QFN

44-Pin

QFN/

TQFP

48-Pin
UQFN

I/O Buffer Description

PIC24FV16KM204 FAMILY

DS33030A-page 24 Advance Information  2013 Microchip Technology Inc.

TABLE 1-5: PIC24FV16KM204 FAMILY PINOUT DESCRIPTION (CONTINUED)

FFV

Pin Number Pin Number

Function

MCLR 1 1 26 18 19 1 1 26 18 19 I ST Master Clear (Device Reset) Input (active-low)

OA1INA — 5 2 22 24 — 5 2 22 24 I ANA Op Amp 1 Input A

OA1INB — 6 3 23 25 — 6 3 23 25 I ANA Op Amp 1 Input B

OA1INC — 24 21 11 12 — 24 21 11 12 I ANA Op Amp 1 Input C

OA1IND — 25 22 14 15 — 25 22 14 15 I ANA Op Amp 1 Input D

OA1OUT — 7 4 24 26 — 7 4 24 26 O ANA Op Amp 1 Analog Output

OA2INA — 5 2 22 24 — 5 2 22 24 I ANA Op Amp 2 Input A

OA2INB — 6 3 23 25 — 6 3 23 25 I ANA Op Amp 2 Input B

OA2INC — 24 21 11 12 — 24 21 11 12 I ANA Op Amp 2 Input C

OA2IND — 25 22 14 15 — 25 22 14 15 I ANA Op Amp 2 Input D

OA2OUT — 26 23 15 16 — 26 23 15 16 O ANA Op Amp 2 Analog Output

OC1A 14 20 17 7 7 11 16 13 43 47 O — MCCP1 Output Compare A

OC1B 12 17 14 44 48 12 17 14 44 48 O — MCCP1 Output Compare B

OC1C 15 21 18 8 9 15 21 18 8 9 O — MCCP1 Output Compare C

OC1D 16 24 21 11 12 16 24 21 11 12 O — MCCP1 Output Compare D

OC1E — 14 11 41 45 — 14 11 41 45 O — MCCP1 Output Compare E

OC1F — 15 12 42 46 — 15 12 42 46 O — MCCP1 Output Compare F

OC2A 4 22 19 9 10 4 22 19 9 10 O — MCCP2 Output Compare A

OC2B — 23 20 10 11 — 23 20 10 11 O — MCCP2 Output Compare B

OC2C — — — 2 2 — — — 2 2 O — MCCP2 Output Compare C

OC2D — — — 3 3 — — — 3 3 O — MCCP2 Output Compare D

OC2E — — — 4 4 — — — 4 4 O — MCCP2 Output Compare E

OC2F — — — 5 5 — — — 5 5 O — MCCP2 Output Compare F

OC3A — 21 18 12 13 — 21 18 12 13 O — MCCP3 Output Compare A

OC3B — 24 21 13 14 — 24 21 13 14 O — MCCP3 Output Compare B

OC4 — 18 15 1 1 — 18 15 1 1 O — SCCP4 Output Compare

OC5 — 19 16 6 6 — 19 16 6 6 O — SCCP5 Output Compare

OCFA 17 25 22 14 15 17 25 22 14 15 I ST MCCP/SCCP Output Compare Fault Input A

OCFB 16 24 21 32 35 16 24 21 32 35 I ST MCCP/SCCP Output Compare Fault Input B

Legend: ANA = Analog level input/output, ST = Schmitt Trigger input buffer, I

20-Pin

PDIP/

SSOP/

SOIC

28-Pin

PDIP/

SSOP/

SOIC

28-Pin

QFN

44-Pin

QFN/

TQFP

48-Pin

UQFN

20-Pin

PDIP/

SSOP/

SOIC

28-Pin

PDIP/

SSOP/

SOIC

2

C™ = I2C/SMBus input buffer

28-Pin

QFN

44-Pin

QFN/

TQFP

48-Pin
UQFN

I/O Buffer Description

PIC24FV16KM204 FAMILY

 2013 Microchip Technology Inc. Advance Information DS33030A-page 25

TABLE 1-5: PIC24FV16KM204 FAMILY PINOUT DESCRIPTION (CONTINUED)

FFV

Pin Number Pin Number

Function

OSCI 7 9 6 30 33 7 9 6 30 33 I ANA Primary Oscillator Input

OSCO 8 10 7 31 34 8 10 7 31 34 O ANA Primary Oscillator Output

PGC1 5 5 2 22 24 5 5 2 22 24 I/O ST ICSP Clock 1

PGD1 4 4 1 21 23 4 4 1 21 23 I/O ST ICSP Data 1

PGC2 2 22 19 9 10 2 22 19 9 10 I/O ST ICSP Clock 2

PGD2 3 21 18 8 9 3 21 18 8 9 I/O ST ICSP Data 2

PGC3 10 15 12 42 46 10 15 12 42 46 I/O ST ICSP Clock 3

PGD3 9 14 11 41 45 9 14 11 41 45 I/O ST ICSP Data 3

PWRLCLK 10 12 9 34 37 10 12 9 34 37 I ST RTCC Power Line Clock Input

RA0 2 2 27 19 21 2 2 27 19 21 I/O ST PORTA Pins

RA1 3 3 28 20 22 3 3 28 20 22 I/O ST PORTA Pins

RA2 7 9 6 30 33 7 9 6 30 33 I/O ST PORTA Pins

RA3 8107 313481073134I/OSTPORTA Pins

RA4 10 12 9 34 37 10 12 9 34 37 I/O ST PORTA Pins

RA5 1 1 26 18 19 1 1 26 18 19 I/O ST PORTA Pins

RA6 14 20 17 7 7 — — — — — I/O ST PORTA Pins

RA7 — 19 16 6 6 — 19 16 6 6 I/O ST PORTA Pins

RA8 — — — 32 35 — — — 32 35 I/O ST PORTA Pins

RA9 — — — 35 38 — — — 35 38 I/O ST PORTA Pins

RA10 — — — 12 13 — — — 12 13 I/O ST PORTA Pins

RA11 — — — 13 14 — — — 13 14 I/O ST PORTA Pins

RB0 4 4 1 21 23 4 4 1 21 23 I/O ST PORTB Pins

RB1 5 5 2 22 24 5 5 2 22 24 I/O ST PORTB Pins

RB2 6 6 3 23 25 6 6 3 23 25 I/O ST PORTB Pins

RB3 — 7 4 24 26 — 7 4 24 26 I/O ST PORTB Pins

RB4 9118333691183336I/OSTPORTB Pins

RB5 — 14 11 41 45 — 14 11 41 45 I/O ST PORTB Pins

RB6 — 15 12 42 46 — 15 12 42 46 I/O ST PORTB Pins

RB7 11 16 13 43 47 11 16 13 43 47 I/O ST PORTB Pins

RB8 12 17 14 44 48 12 17 14 44 48 I/O ST PORTB Pins

Legend: ANA = Analog level input/output, ST = Schmitt Trigger input buffer, I

20-Pin

PDIP/

SSOP/

SOIC

28-Pin

PDIP/

SSOP/

SOIC

28-Pin

QFN

44-Pin

QFN/

TQFP

48-Pin

UQFN

20-Pin

PDIP/

SSOP/

SOIC

28-Pin

PDIP/

SSOP/

SOIC

2

C™ = I2C/SMBus input buffer

28-Pin

QFN

44-Pin

QFN/

TQFP

48-Pin
UQFN

I/O Buffer Description

PIC24FV16KM204 FAMILY

DS33030A-page 26 Advance Information  2013 Microchip Technology Inc.

TABLE 1-5: PIC24FV16KM204 FAMILY PINOUT DESCRIPTION (CONTINUED)

FFV

Pin Number Pin Number

Function

RB9 13 18 15 1 1 13 18 15 1 1 I/O ST PORTB Pins

RB10 — 21 18 8 9 — 21 18 8 9 I/O ST PORTB Pins

RB11 — 22 19 9 10 — 22 19 9 10 I/O ST PORTB Pins

RB12 15 23 20 10 11 15 23 20 10 11 I/O ST PORTB Pins

RB13 16 24 21 11 12 16 24 21 11 12 I/O ST PORTB Pins

RB14 17 25 22 14 15 17 25 22 14 15 I/O ST PORTB Pins

RB15 18 26 23 15 16 18 26 23 15 16 I/O ST PORTB Pins

RC0 — — — 25 27 — — — 25 27 I/O ST PORTC Pins

RC1 — — — 26 28 — — — 26 28 I/O ST PORTC Pins

RC2 — — — 27 29 — — — 27 29 I/O ST PORTC Pins

RC3 — — — 36 39 — — — 36 39 I/O ST PORTC Pins

RC4 — — — 37 40 — — — 37 40 I/O ST PORTC Pins

RC5 — — — 38 41 — — — 38 41 I/O ST PORTC Pins

RC6 — — — 2 2 — — — 2 2 I/O ST PORTC Pins

RC7 — — — 3 3 — — — 3 3 I/O ST PORTC Pins

RC8 — — — 4 4 — — — 4 4 I/O ST PORTC Pins

RC9 — — — 5 5 — — — 5 5 I/O ST PORTC Pins

REFO 18 26 23 15 16 18 26 23 15 16 O — Reference Clock Output

RTCC — 25 22 14 15 — 25 22 14 15 O — Real-Time Clock/Calendar Output

SCK1 15 22 19 9 10 15 22 19 9 10 I/O ST MSSP1 SPI Clock

SDI1 17 21 18 8 9 17 21 18 8 9 I ST MSSP1 SPI Data Input

SDO1 16 24 21 11 12 16 24 21 11 12 O — MSSP1 SPI Data Output

SS1 18 26 23 15 16 18 26 23 15 16 I ST MSSP1 SPI Slave Select Input

SCK2 — 14 11 38 41 — 14 11 38 41 I/O ST MSSP2 SPI Clock

SDI2 — 19 16 36 39 — 19 16 36 39 I ST MSSP2 SPI Data Input

SDO2 — 15 12 37 40 — 15 12 37 40 O — MSSP2 SPI Data Output

SS2 — 23 20 35 38 — 23 20 35 38 I ST MSSP2 SPI Slave Select Input

Legend: ANA = Analog level input/output, ST = Schmitt Trigger input buffer, I

20-Pin

PDIP/

SSOP/

SOIC

28-Pin

PDIP/

SSOP/

SOIC

28-Pin

QFN

44-Pin

QFN/

TQFP

48-Pin

UQFN

20-Pin

PDIP/

SSOP/

SOIC

28-Pin

PDIP/

SSOP/

SOIC

2

C™ = I2C/SMBus input buffer

28-Pin

QFN

44-Pin

QFN/

TQFP

48-Pin
UQFN

I/O Buffer Description

PIC24FV16KM204 FAMILY

 2013 Microchip Technology Inc. Advance Information DS33030A-page 27

TABLE 1-5: PIC24FV16KM204 FAMILY PINOUT DESCRIPTION (CONTINUED)

FFV

Pin Number Pin Number

Function

SCL1 12 17 14 44 48 12 17 14 44 48 I/O I2C MSSP1 I2C Clock

SDA1 13 18 15 1 1 13 18 15 1 1 I/O I2C MSSP1 I

SCL2 — 7 4 24 26 — 7 4 24 26 I/O I2C MSSP2 I

SDA2 — 6 3 23 25 — 6 3 23 25 I/O I2C MSSP2 I

SCLKI 10 12 9 34 37 10 12 9 34 37 I ST Secondary Clock Digital Input

SOSCI 9 11 8 33 36 9 11 8 33 36 I ANA Secondary Oscillator Input

SOSCO 10 12 9 34 37 10 12 9 34 37 I ANA Secondary Oscillator Output

T1CK 13 18 15 1 1 13 18 15 1 1 I ST Timer1 Digital Input Cock

TCKIA 18 26 23 15 16 18 26 23 15 16 I ST MCCP/SCCP Time Base Clock Input A

TCKIB 6 6 3 23 25 6 6 3 23 25 I ST MCCP/SCCP Time Base Clock Input B

U1CTSN 12 17 14 44 48 12 17 14 44 48 I ST UART1 Clear-to-Send Input

U1RTS 13 18 15 1 1 13 18 15 1 1 O — UART1 Request-to-Send Output

U1BCLK 13 18 15 1 1 13 18 15 1 1 O — UART1 16x Baud Rate Clock Output

U1RX 6 6 3 2 2 6 6 3 2 2 I ST UART1 Receive

U1TX 11 16 13 3 3 11 16 13 3 3 O — UART1 Transmit

U2CTSN - 12 9 34 37 - 12 9 34 37 I ST UART2 Clear-to-Send Input

U2RTS - 11 8 33 36 - 11 8 33 36 O - UART2 Request-to-Send Output

U2BCLK 13 18 15 1 1 13 18 15 1 1 O - UART2 16x Baud Rate Clock Output

U2RX - 5 2 22 24 - 5 2 22 24 I ST UART2 Receive

U2TX - 4 1 21 23 - 4 1 21 23 O - UART2 Transmit

ULPWU 4 4 1 21 23 4 4 1 21 23 I ANA Ultra Low-Power Wake-up Input

VCAP - - - - - 14 20 17 7 7 P - Regulator External Filter Capacitor Connection

DD 20 28 25 17,28,28 18,30,30 20 28 25 17,28,28 18,30,30 P - Device Positive Supply Voltage

V

DDCORE - - - - - 14 20 17 7 7 P - Microcontroller Core Supply Voltage

V

VPP 1 1 26 18 19 1 1 26 18 19 P - High-Voltage Programming Pin

REF+ 2 2 27 19 21 2 2 27 19 21 I ANA A/D Reference Voltage Positive Input

V

V

REF- 3 3 28 20 22 3 3 28 20 22 I ANA A/D Reference Voltage Negative Input

SS 19 27 24 16,29,29 17,31,31 19 27 24 16,29,29 17,31,31 P - Device Ground Return Voltage

V

Legend: ANA = Analog level input/output, ST = Schmitt Trigger input buffer, I

20-Pin

PDIP/

SSOP/

SOIC

28-Pin

PDIP/

SSOP/

SOIC

28-Pin

QFN

44-Pin

QFN/

TQFP

48-Pin

UQFN

20-Pin

PDIP/

SSOP/

SOIC

28-Pin

PDIP/

SSOP/

SOIC

2

C™ = I2C/SMBus input buffer

28-Pin

QFN

44-Pin

QFN/

TQFP

48-Pin
UQFN

I/O Buffer Description

2

C Data

2

C Clock

2

C Data

PIC24FV16KM204 FAMILY

PIC24FV16KM204 FAMILY

NOTES:

DS33030A-page 28 Advance Information  2013 Microchip Technology Inc.

PIC24FV16KM204 FAMILY

PIC24FV16KM204

VDD

VSS

VDD

VSS

VSS

VDD

AVDD

AVSS

VDD

VSS

C1

R1

V

DD

MCLR

VCAP

R2

C7

C2

(2)

C3

(2)

C4

(2)

C5

(2)

C6

(2)

Key (all values are recommendations):

C1 through C6: 0.1 µF, 20V ceramic

C7: 10 µF, 16V tantalum or ceramic

R1: 10 kΩ

R2: 100Ω to 470Ω

Note 1: See Section 2.4 “Voltage Regulator Pin

(V

CAP)” for an explanation of VCAP pin

connections.

2: The example shown is for a PIC24F device

with five V

DD/VSS and AVDD/AVSS pairs.

Other devices may have more or less
pairs; adjust the number of decoupling
capacitors appropriately.

(1)

2.0 GUIDELINES FOR GETTING
STARTED WITH 16-BIT

FIGURE 2-1: RECOMMENDED

MINIMUM CONNECTIONS

MICROCONTROLLERS

2.1 Basic Connection Requirements

Getting started with the PIC24FV16KM204 family of
16-bit microcontrollers requires attention to a minimal
set of device pin connections before proceeding with
development.

The following pins must always be connected:

DD and VSS pins

•All V

(see Section 2.2 “Power Supply Pins”)

•All AV

•MCLR

•V

These pins must also be connected if they are being
used in the end application:

• PGECx/PGEDx pins used for In-Circuit Serial

• OSCI and OSCO pins when an external oscillator

Additionally, the following pins may be required:

•V

The minimum mandatory connections are shown in

Figure 2-1.

DD and AVSS pins, regardless of whether or

not the analog device features are used
(see Section 2.2 “Power Supply Pins”)

pin

(see Section 2.3 “Master Clear (MCLR) Pin”)

CAP pins

(see Section 2.4 “Voltage Regulator Pin (V

CAP)”)

Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)

source is used
(see Section 2.6 “External Oscillator Pins”)

REF+/VREF- pins are used when external voltage

reference for analog modules is implemented

Note: The AVDD and AVSS pins must always be

connected, regardless of whether any of
the analog modules are being used.

 2013 Microchip Technology Inc. Advance Information DS33030A-page 29

PIC24FV16KM204 FAMILY

Note 1: R1  10 k is recommended. A suggested

starting value is 10 k. Ensure that the
MCLR

pin VIH and VIL specifications are met.

2: R2  470 will limit any current flowing into

MCLR

from the external capacitor, C, in the

event of MCLR

pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR

pin

V

IH and VIL specifications are met.

C1

R2

R1

V

DD

MCLR

PIC24FXXKXX

JP

2.2 Power Supply Pins

2.2.1 DECOUPLING CAPACITORS

The use of decoupling capacitors on every pair of
power supply pins, such as V

SS, is required.

AV

Consider the following criteria when using decoupling
capacitors:

• Value and type of capacitor: A 0.1
10-20V capacitor is recommended. The capacitor
should be a low-ESR device, with a resonance
frequency in the range of 200 MHz and higher.
Ceramic capacitors are recommended.

• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is no greater
than 0.25 inch (6 mm).

• Handling high-frequency noise: If the board is
experiencing high-frequency noise (upward of
tens of MHz), add a second ceramic type capaci­tor in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01

µF to 0.001 µF. Place this

second capacitor next to each primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible
(e.g., 0.1

µF in parallel with 0.001 µF).

• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB trace
inductance.

DD, VSS, AVDD and

µF (100 nF),

2.3 Master Clear (MCLR) Pin

The MCLR pin provides two specific device
functions: device Reset, and device programming
and debugging. If programming and debugging are
not required in the end application, a direct
connection to V
addition of other components, to help increase the
application’s resistance to spurious Resets from
voltage sags, may be beneficial. A typical
configuration is shown in Figure 2-1. Other circuit
designs may be implemented, depending on the
application’s requirements.

During programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR
levels (V
not be adversely affected. Therefore, specific values
of R1 and C1 will need to be adjusted based on the
application and PCB requirements. For example, it is
recommended that the capacitor, C1, be isolated
from the MCLR
debugging operations by using a jumper (Figure 2-2).
The jumper is replaced for normal run-time
operations.

Any components associated with the MCLR
should be placed within 0.25 inch (6 mm) of the pin.

FIGURE 2-2: EXAMPLE OF MCLR PIN

DD may be all that is required. The

pin. Consequently, specific voltage

IH and VIL) and fast signal transitions must

pin during programming and

pin

CONNECTIONS

2.2.2 TANK CAPACITORS

On boards with power traces running longer than
six inches in length, it is suggested to use a tank capac­itor for integrated circuits, including microcontrollers, to
supply a local power source. The value of the tank
capacitor should be determined based on the trace
resistance that connects the power supply source to
the device, and the maximum current drawn by the
device in the application. In other words, select the tank
capacitor so that it meets the acceptable voltage sag at
the device. Typical values range from 4.7

DS33030A-page 30 Advance Information  2013 Microchip Technology Inc.

µF to 47 µF.