Section 66. 16-Bit Sigma-Delta A/D Converter
HIGHLIGHTS
66
16-Bit Sigma-De lt a
A/D Converter
This section of the manual contains the following major topics:
66.1 Introduction.................................................................................................................66-2
66.2 Registers.....................................................................................................................66-4
66.3 SD A/D Module Configuration.....................................................................................66-8
66.4 Interrupt Modes.........................................................................................................66-14
66.5 Offset Calibration......................................................................................................66-14
66.6 Gain Error Calibration...............................................................................................66-15
66.7 Operation During Sleep and Idle Modes ...................................................................66-21
66.8 Effects of a Reset......................................................................................................66-21
66.9 Register Map............................................... ..............................................................66-22
66.10 Design Tips...............................................................................................................66-23
66.11 Related Application Notes.........................................................................................66-24
66.12 Revision History........................................................................................................66-25
© 2013 Microchip Technology Inc. DS30687A-page 66-1
PIC24F Family Reference Manual
66.1 INTRODUCTION
The PIC24F 16-bit Sigma-Delta Analog-to-Digital (SD A/D) Converter has the following key
features:
• Sigma-Delta Conversion
• Programmable Data Rate up to 62.5 ksps
• Differential inputs with Gain Settings
• Dithering Option and Adjustable Oversampling Ratios
• Independent Module Reset Option
The SD A/D Converter module accepts the analog signal and converts it to a corresponding
digital value. The 16-bit SD A/D Converter can have up to eight differential analog inputs
(channels). Some of the channels can be configured as single-ended inputs or can be used for
the external voltage reference connection. The actual number of analog inputs and the external
voltage reference input configuration c an vary with the device. For mo re information on th e actual
number and type of channels available in the device, refer to the specific device data sheet.
The SD A/D Converter contains the following sections:
• Analog Input Selection
• Output Buffer
• Timing and Control Functions
The 16-bit SD A/D Converter samples an input signal less than Nyquist Frequency. The analog
input multiplexer selects the signal to be converted from multiple analog input pins. The
differential analog input signal can be positive or negative (i.e., bipolar). The sampled voltage is
converted to a digital value, which represents the ratio of input voltage to a reference voltage.
The reference voltages can be configured to either external references or SV
The input signal can be amplified up to 32 times using the gain settings. Dithering averages the
nonlinearity of the Digital-to-Analog Converter (DAC) and thereby reduces harmonic distortion.
The bandwidth of the input amplifier can be selected using the power level option.
A simplified block diagram for the SD A/D Converter is shown in Figure 66-1.
Note: The Nyquist Frequency is half the sampling frequency of the SD A/D Converter.
DD and SVSS.
DS30687A-page 66-2 © 2013 Microchip Technology Inc.
Section 66. 16-Bit Sigma-Delta A/D Converter
CH1+
CHn+
Clock
Generation
SINC
3
PGA
Modulator
SV
REF-
V
REF-
-
Filter/Sample
Control and
Interrupt Logic
SDAxIF
SDxRESH
SDxRESL
Low-Pass
Primary OSC
FRC
Fc
Y
DITHER<1:0>
SDGAIN<2:0>
SDDIV<2:0>
SDCS<1:0>
FILTDIS
SDINT<1:0>
SDWM<1:0>
RNDRES<1:0>
Filter
CH0CH1-
CHn-
V
REF-
SDCH<2:0>
(1)
SVSS
SDREFN
SVREF+
SVDD
VREF+
SDREFP
CH0+
V
REF+
Note 1: Refer to the specific device data sheet for more information on the actual number and type of channels available.
—
—
–
+
Figure 66-1: 16-Bit Sigma-Delta A/D Converter Block Diagram
66
16-Bit Sigma-De lt a
A/D Converter
© 2013 Microchip Technology Inc. DS30687A-page 66-3
PIC24F Family Reference Manual
66.2 REGISTERS
The 16-bit SD A/D Converter uses five registers for its operation:
• SDxCON1: SD A/Dx Control Register 1
• SDxCON2: SD A/Dx Control Register 2
• SDxCON3: SD A/Dx Control Register 3
• SDxRESH: SD A/Dx Result Register High Word
• SDxRESL: SD A/Dx Result Register Low Word
All registers are mapped in the data memory space. The SDxCON1, SDxCON2 and SDxCON3
registers (Register 66-1, Register 66-2 and Register 66-3) control the ove rall operation of the SD
A/D module. This includes enabling the module, configuring the conversion clock and voltage
reference source s, se ttin g dithering scheme, ga in of the input amplifier, ov er s am pl ing fre que nc y
and so on.
DS30687A-page 66-4 © 2013 Microchip Technology Inc.
Section 66. 16-Bit Sigma-Delta A/D Converter
Register 66-1: SDxCON1: SD A/Dx Control Register 1
R/W-0 U-0 R/W-0 R/W-0 r-0 R/W-0 R/W-0 R/W-0
SDON — SDSIDL SDRST r SDGAIN2 SDGAIN1 SDGAIN0
bit 15 bit 8
R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
DITHER1 DITHER0 —VOSCAL— SDREFN SDREFP PWRLVL
bit 7 bit 0
Legend: r = Reserved bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 SDON: SD A/D Module Enable bit
1 = Sigma-Delta A/D module is enabled
0 = Sigma-Delta A/D module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 SDSIDL: SD A/D Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12 SDRST: SD A/D Reset bit
1 = Resets all SD A/D module circuitry (analog section remains in Reset as long as SDRST bit is set)
0 = Releases from Reset (Run mode)
bit 11 Reserved: Always maintain as ‘0’ for proper A/D operation
bit 10-8 SDGAIN<2:0>: SD A/D Gain Control bits
11x = Reserved ; do not use
101 = 1:32
100 = 1:16
011 = 1:8
010 = 1:4
001 = 1:2
000 = 1:1
bit 7-6 DITHER<1:0>: Dithering Mode Select bits
11 = High Dither mode (preferred with higher Oversampling Ratio (OSR) and positive reference
below SV
10 = Medium Dither mode (preferred for low-to-medium OSR and positive reference below SV
01 = Low Dither mode (preferred when the positive reference is at or near SV
00 = No Dither mode
bit 5 Unimplemented: Read as ‘ 0’
bit 4 VOSCAL: Internal Offset Measurement Enable bit
1 = Converter is configured to sample its own internal offset error
0 = Converter is configured for normal operation
bit 3 Unimplemented: Read as ‘ 0’
bit 2 SDREFN: SD A/D Negative Voltage Reference Configuration bit
REF- pin
1 = SV
SS
0 = SV
bit 1 SDREFP: SD A/D Positive Voltage Reference Configuration bit
1 = SVREF+ pin
DD
0 = SV
bit 0 PWRLVL: Analog Amplifier Bandwidth Select bit
1 = 2x bandwidth (higher po wer consumption compared to normal bandwidth)
0 = Normal ba ndwidth
DD)
DD)
DD)
66
16-Bit Sigma-De lt a
A/D Converter
© 2013 Microchip Technology Inc. DS30687A-page 66-5
PIC24F Family Reference Manual
Register 66-2: SDxCON2: SD A/Dx Control Register 2
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0
CHOP1 CHOP0 SDINT1 SDINT0
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0 HS/C-0
— — — RNDRES1 RNDRES0 — — SDRDY
bit 7 bit 0
Legend: HS = Hardware Settable bit C = Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 CHOP<1:0>: Amplifier Chopping Enable bits
11 = Chopping is enabled
10 = Reserved
01 = Reserved
00 = Chopping is disabled
bit 13-12 SDINT<1:0>: SD A/D Interrupt Event Generation Select bits
11 = Interrupt on every data output
10 = Interrupt on every fifth data output
01 = Interrupt when the new result is less than the old result
00 = Interrupt when the new result is greater than the old result
bit 11-10 Unimplemented: Read as ‘0’
bit 9-8 SDWM<1:0>: SD A/D Output Result Register Write Mode bits
11 = Reserved ; do not use
10 = SDxRESH/SDxRESL are never updated (used for > or < threshold compare)
01 = SDxRESH/SDxRESL are updated on every interrupt
00 = SDxRESH/SDxRESL are upda ted on ev ery interrupt a fter SDRDY is cleare d to ‘0’ by the soft ware
bit 7-5 Unimplemented: Read as ‘0’
bit 4-3 RNDRES<1:0>: Round Data Control bits
11 = Round result to 8 bits
10 = Round result to 16 bits
01 = Round result to 24 bits
00 = No Rounding (32 bits)
bit 2-1 Unimplemented: Read as ‘0’
bit 0 SDRDY: SD A/D Filter Data Ready bit (set by hardware)
1 = SINC filter delay is satisfied (clear this bit in software)
0 = SINC filter delay is not satisfied
— —SDWM1SDWM0
DS30687A-page 66-6 © 2013 Microchip Technology Inc.
Section 66. 16-Bit Sigma-Delta A/D Converter
Register 66-3: SDxCON3: SD A/Dx Control Register 3
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
(1)
SDDIV2
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — SDCH2
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
SDDIV1
(1)
SDDIV0
(1)
SDOSR2 SDOSR1 SDOSR0 SDCS1 SDCS0
(3)
SDCH1
(3)
SDCH0
(3)
66
16-Bit Sigma-De lt a
A/D Converter
bit 15-13 SDDIV<2:0>: SD A/D Input Clock Divider/Postscaler Ratio bits
111 = Reserved
110 = 64
101 = 32
100 = 16
011 = 8
010 = 4
001 = 2
000 = 1 (No divider, clock selected by SDCS<1:0> is provided directly to A/D)
bit 12-10 SDOSR<2:0>: SD A/D Oversampling Ratio (OSR) Selection bits
111 = Reserved
110 = 16 (fastest conversion results, low quality)
101 = 32
100 = 64
011 = 128
010 = 256
001 = 512
000 = 1024 (slowest conversion results, best quality)
bit 9-8 SDCS<1:0>: SD A/D Clock Source Select bits
11 = Reserved
10 = Primary Oscillator (OSCI/CLKI)
01 = FRC (8 MHz)
00 = System clock (FOSC/2)
bit 7-3 Unimplemented: Read as ‘0’
bit 2-0 SDCH<2:0>: SD A/D Analog Channel Input Select bits
(2)
(3)
(1)
Note 1: To avoid overclocking or underclocking the module, set SDDIV<2:0> to obtain an A/D clock frequency
(input frequency selected by SDCS<1:0> is divided by the SDDIVx postscaler) at or between 1 MHz and
4 MHz.
2: The 8 MHz FRC output is used directly, prior to the FRCDIV<2:0> postscaler.
3: Refer to the specific device data sheet for more information on the actual number and type of channels
available.
© 2013 Microchip Technology Inc. DS30687A-page 66-7
PIC24F Family Reference Manual
66.3 SD A/D MODULE CONFIGURATION
All of the registers d escribed in the p revious section must be configu red for the module o peration.
The various configuration and control functions of the module are distributed throughout the
module’s thre e co ntr o l r e gi ste r s. Control fun ct ion s ca n b e so r ted i n to fou r g rou ps: in pu t , t i mi ng ,
conversion and output. Table 66-1 shows the location of the control or status bits by register.
Table 66-1: SD A/D Module Functions by Registers and Bits
SD A/D
Function
Input SDxCON1 PWRLVL, SDREFP, SDREFN, VOSCAL, DITHER<1:0>,
Timing SDxCON3 SDCS<1:0>, SDDIV<2:0>
Conversion SDxCON1 SDON, SDSIDL
Output SDxCON2 RNDRES<1:0>, SDWM<1:0>
The following steps should be followed for performing an SD A/D conversion.
1. Configure the SD A/D module:
a) Select the power l evel
b) Select the volta ge reference sou rce to match th e expected rang e on the ana log inputs
c) Set the dither value
d) Set the gain
e) Select the output resolution
f) Select the Data Overwrite mode
g) Select the Chopping Clock mode
h) Select the input channel
i) Select the SD A/D module clock source
j) Select the desired output data rate
k) Select the sampling frequency
2. Configure the SD A/D interrupt (if required):
a) Select the Interrupt mode
b) Clear the SDAxIF bit
c) Select the SD A/D interrupt priority
3. Turn on the SD A/D module.
The options for each co nfiguratio n step are des cribed in th e subseque nt section s. Example 66-1
shows the possible initialization sequence.
Register(s) Specific Bits
SDGAIN<2:0>
SDxCON2 CHOP<1:0>
SDxCON3 SDCH<2:0>
SDxCON2 SDINT<1:0>
SDxCON3 SDOSR<2:0>
DS30687A-page 66-8 © 2013 Microchip Technology Inc.
Section 66. 16-Bit Sigma-Delta A/D Converter
signed short int count;
signed short int result;
// Configure the SD A/D module
SD1CON1bits.PWRLVL = 0; // Low power, normal bandwidth
SD1CON1bits.SDREFP = 0; // Positive Voltage Reference is SVDD
SD1CON1bits.SDREFN = 0; // Negative Voltage Reference is SVSS
SD1CON1bits.VOSCAL = 0; // Internal Offset Measurement is disabled
SD1CON1bits.DITHER = 1; // Low Dither
SD1CON1bits.SDGAIN = 0; // Gain is 1:1
SD1CON2bits.RNDRES = 2; // Round result to 16-bit
SD1CON2bits.SDWM = 1; // SDxRESH/SDxRESL updated on every Interrupt
SD1CON2bits.CHOP = 3; // Chopping should be enabled
SD1CON3bits.SDCH = 0; // Channel 0 (see the specific device data sheet)
SD1CON3bits.SDCS = 1; // Clock Source is a 8 MHz FRC
SD1CON3bits.SDOSR = 0; // Oversampling Ratio (OSR) is 1024 (best quality)
SD1CON3bits.SDDIV = 1; // Input Clock Divider is 2 (SD ADC clock is 4MHz)
// Configure SD A/D interrupt
SD1CON2bits.SDINT
= 3; // Interrupt on every data output
IFS6bits.SDA1IF
= 0; // Clear interrupt flag
// Turn on the SD A/D module
SD1CON1bits.SDON = 1;
// Wait for a minimum of five interrupts to be generated. Need to throw at least
// the first four away when using interrupt every period option, since the
// low pass SINC filter needs to be flushed with new data when we change
// ADC channel or initialize the ADC.
for(count=0; count<8; count++)
{
//Clear interrupt flag.
IFS6bits.SDA1IF = 0;
//Wait for the result ready.
while(IFS6bits.SDA1IF == 0);
}
// Channel #0 conversion result.
result = SD1RESH;
Example 66-1: Channel Measurement
66
16-Bit Sigma-De lt a
A/D Converter
66.3.1 Selecting the Voltage Reference Source
The voltage references for SD A/D conversions are selected using the SDREFN and SDREFP
control bits (SDx CON1 <2:1 >). T he upper voltage refe ren ce (V
applied on the SV
applied on the SV
© 2013 Microchip Technology Inc. DS30687A-page 66-9
REF+ pin. The lower voltage reference (VREF-) can be SVSS or the voltage
REF- pin.
REF+) can be SVDD or the voltag e
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