Note the following details of the code protection feature on Microchip devices:
•Microchip products meet the specification contained in their particular Microchip Data Sheet.
•Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•Microchip is willing to work with the customer who is concerned about the integrity of their code.
•Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K
EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PRO MATE, rfPIC and SmartShunt are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
logo, PowerCal, PowerInfo,
PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
10.0 Data EEPROM and Flash Program Memory Control ............................................................................................................... 119
14.0 Special Features of the CPU.................................................................................................................................................... 197
15.0 Instruction Set Summary.......................................................................................................................................................... 217
16.0 Development Support............................................................................................................................................................... 227
18.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 259
Appendix A: Data Sheet Revision History .......................................................................................................................................... 293
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of
silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
The PIC16F631/677/685/687/689/690 has a 13-bit
program counter capable of addressing an 8K x 14
program memory space. Only the first 1K x 14
(0000h-03FFh) is physically implemented for the
PIC16F631, the first 2K x 14 (0000h-07FFh) for the
PIC16F677/PIC16F687, and the first 4K x 14
(0000h-0FFFh) for the PIC16F685/PIC16F689/
PIC16F690. Accessing a location above these
boundaries will cause a wraparound. The Reset vector
is at 0000h and the interrupt vector is at 0004h (see
Figures 2-1 through 2-3).
The data memory (see Figures 2-6 through 2-8) is
partitioned into four banks which contain the General
Purpose Registers (GPR) and the Special Function
Registers (SFR). The Special Function Registers are
located in the first 32 locations of each bank. The
General Purpose Registers, implemented as static
RAM, are located in the last 96 locations of each Bank.
Register locations F0h-FFh in Bank 1, 170h-17Fh in
Bank 2 and 1F0h-1FFh in Bank 3 point to addresses
70h-7Fh in Bank 0. The actual number of General
Purpose Resisters (GPR) in each Bank depends on the
device. Details are shown in Figures 2-4 through 2-8.
All other RAM is unimplemented and returns ‘0’ when
read. RP<1:0> of the STATUS register are the bank
select bits:
RP1
RP0
00→Bank 0 is selected
01→Bank 1 is selected
10→Bank 2 is selected
11→Bank 3 is selected
2.2.1GENERAL PURPOSE REGISTER
FILE
The register file is organized as 128 x 8 in the
PIC16F687 and 256 x 8 in the
PIC16F685/PIC16F689/PIC16F690. Each register is
accessed, either directly or indirectly, through the File
Select Register (FSR) (see Section 2.4 “IndirectAddressing, INDF and FSR Registers”).
2.2.2SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Tables 2-1
through 2-4). These registers are static RAM.
The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
associated with the “core” are described in this section.
Registers related to the operation of peripheral features
are described in the section of that peripheral feature.
Legend:– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1:MCLR
and WDT Reset do not affect the previous value data latch. The RABIF bit will be cleared upon Reset but will set again if the
mismatch exists.
2:PIC16F687/PIC16F689/PIC16F690 only.
3:PIC16F685/PIC16F690 only.
4:PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only.
5:PIC16F677/PIC16F687/PIC16F689/PIC16F690 only.
6:When SSPCON register bits SSPM<3:0> = 1001, any reads or writes to the SSPADD SFR address are accessed through the SSPMSK
register. See Registers 13-2 and 13-3 for more detail.
7:Port pins with analog functions controlled by the ANSEL and ANSELH registers will read ‘0’ immediately after a Reset even though the
data latches are either undefined (POR) or unchanged (other Resets).
Legend:– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1:MCLR
and WDT Reset do not affect the previous value data latch. The RABIF bit will be cleared upon Reset but will set again if the
mismatch exists.
2:PIC16F687/PIC16F689/PIC16F690 only.
3:PIC16F685/PIC16F690 only.
4:PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only.
5:PIC16F677/PIC16F687/PIC16F689/PIC16F690 only.
6:RA3 pull-up is enabled when pin is configured as MCLR
in Configuration Word.
7:Accessible only when SSPCON register bits SSPM<3:0> = 1001.
2:PIC16F685/PIC16F689/PIC16F690 only.
3:PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only.
4:Port pins with analog functions controlled by the ANSEL and ANSELH registers will read ‘0’ immediately after a Reset even though the
data latches are either undefined (POR) or unchanged (other Resets).
——RA5RA4RA3RA2RA1RA0--xx xxxx59,205
RB7RB6RB5RB4————xxxx ----69,205
RC7RC6RC5RC4RC3RC2RC1RC0xxxx xxxx76,205
———Write Buffer for the upper 5 bits of the Program Counter---0 000044,205
The STATUS register, shown in Register 2-1, contains:
• the arithmetic status of the ALU
• the Reset status
• the bank select bits for data memory (GPR and
SFR)
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
and PD bits are not
For example, CLRF STATUS, will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not affecting any Status bits, see Section 15.0 “Instruction Set
Summary”
Note 1: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
REGISTER 2-1:STATUS: STATUS REGISTER
R/W-0R/W-0R/W-0R-1R-1R/W-xR/W-xR/W-x
IRPRP1RP0TO
bit 7bit 0
Legend:
R = Readable bitW = Writable bitU = Unimplemented bit, read as ‘0’
-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown
PDZDC
(1)
(1)
C
bit 7IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h-1FFh)
0 = Bank 0, 1 (00h-FFh)
bit 6-5RP<1:0>: Register Bank Select bits (used for direct addressing)
00 = Bank 0 (00h-7Fh)
01 = Bank 1 (80h-FFh)
10 = Bank 2 (100h-17Fh)
11 = Bank 3 (180h-1FFh)
bit 4TO
bit 3PD
bit 2Z: Zero bit
bit 1DC: Digit Carry/Borrow
bit 0C: Carry/Borrow
: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
(1)
bit
(ADDWF, ADDLW, SUBLW, SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
(1)
(1)
Note 1: For Borrow
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.
The INTCON register, shown in Register 2-3, is a
readable and writable register, which contains the various
enable and flag bits for TMR0 register overflow, PORTA
change and external RA2/AN2/T0CKI/INT/C1OUT pin
interrupts.
Note:Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
REGISTER 2-3:INTCON: INTERRUPT CONTROL REGISTER
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-x
GIEPEIET0IEINTERABIE
bit 7bit 0
Legend:
R = Readable bitW = Writable bitU = Unimplemented bit, read as ‘0’
-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown
bit 7GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5T0IE: Timer0 Overflow Interrupt Enable bit
1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
bit 4INTE: RA2/INT External Interrupt Enable bit
1 = Enables the RA2/INT external interrupt
0 = Disables the RA2/INT external interrupt
bit 3RABIE: PORTA/PORTB Change Interrupt Enable bit
1 = Enables the PORTA/PORTB change interrupt
0 = Disables the PORTA/PORTB change interrupt
bit 2T0IF: Timer0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1INTF: RA2/INT External Interrupt Flag bit
1 = The RA2/INT external interrupt occurred (must be cleared in software)
0 = The RA2/INT external interrupt did not occur
bit 0RABIF: PORTA/PORTB Change Interrupt Flag bit
1 = When at least one of the PORTA or PORTB general purpose I/O pins changed state (must be
cleared in software)
0 = None of the PORTA or PORTB general purpose I/O pins have changed state
(2)
(1,3)
(1,3)
T0IF
(2)
INTFRABIF
Note 1: IOCA or IOCB register must also be enabled.
2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before
Note:Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
R = Readable bitW = Writable bitU = Unimplemented bit, read as ‘0’
-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown
bit 7OSFIF: Oscillator Fail Interrupt Flag bit
1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0 = System clock operating
bit 6C2IF: Comparator C2 Interrupt Flag bit
1 = Comparator output (C2OUT bit) has changed (must be cleared in software)
0 = Comparator output (C2OUT bit) has not changed
bit 5C1IF: Comparator C1 Interrupt Flag bit
1 = Comparator output (C1OUT bit) has changed (must be cleared in software)
0 = Comparator output (C1OUT bit) has not changed
bit 4EEIF: EE Write Operation Interrupt Flag bit
1 = Write operation completed (must be cleared in software)
0 = Write operation has not completed or has not started
bit 3-0Unimplemented: Read as ‘0’
Note:Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
The Program Counter (PC) is 13 bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<12:8>) is not directly
readable or writable and comes from PCLATH. On any
Reset, the PC is cleared. Figure 2-9 shows the two
situations for the loading of the PC. The upper example
in Figure 2-9 shows how the PC is loaded on a write to
PCL (PCLATH<4:0> → PCH). The lower example in
Figure 2-9 shows how the PC is loaded during a CALL or
GOTO instruction (PCLATH<4:3> → PCH).
FIGURE 2-9:LOADING OF PC IN
DIFFERENT SITUATIONS
PCHPCL
128 70
PC
PCLATH<4:0>
5
PCLATH
PCHPCL
12 11 100
PC
2
87
PCLATH<4:3>
PCLATH
8
11
2.3.1MODIFYING PCL
Executing any instruction with the PCL register as the
destination simultaneously causes the Program
Counter PC<12:8> bits (PCH) to be replaced by the
contents of the PCLATH register. This allows the entire
contents of the program counter to be changed by
writing the desired upper 5 bits to the PCLATH register.
When the lower 8 bits are written to the PCL register, all
13 bits of the program counter will change to the values
contained in the PCLATH register and those being
written to the PCL register.
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). Care should be
exercised when jumping into a look-up table or
program branch table (computed GOTO) by modifying
the PCL register. Assuming that PCLATH is set to the
table start address, if the table length is greater than
255 instructions or if the lower 8 bits of the memory
address rolls over from 0xFF to 0x00 in the middle of
the table, then PCLATH must be incremented for each
address rollover that occurs between the table
beginning and the target location within the table.
For more information refer to Application Note AN556,
“Implementing a Table Read” (DS00556).
Instruction with
PCL as
Destination
ALU Result
GOTO, CALL
OPCODE<10:0>
2.3.2STACK
The PIC16F631/677/685/687/689/690 devices have an
8-level x 13-bit wide hardware stack (see Figures 2-2
and 2-3). The stack space is not part of either program
or data space and the Stack Pointer is not readable or
writable. The PC is PUSHed onto the stack when a
CALL instruction is executed or an interrupt causes a
branch. The stack is POPed in the event of a RETURN,RETLW or a RETFIE instruction execution. PCLATH is
not affected by a PUSH or POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
Note 1: There are no Status bits to indicate stack
overflow or stack underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions or the vectoring to an
interrupt address.
2.4Indirect Addressing, INDF and
FSR Registers
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF
register. Any instruction using the INDF register actually
accesses data pointed to by the File Select Register
(FSR). Reading INDF itself indirectly will produce 00h.
Writing to the INDF register indirectly results in a no
operation (although Status bits may be affected). An
effective 9-bit address is obtained by concatenating the
8-bit FSR and the IRP bit of the STATUS register, as
shown in Figure 2-10.
A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 2-1.
EXAMPLE 2-1:INDIRECT ADDRESSING
MOVLW0x20;initialize pointer
MOVWFFSR;to RAM
NEXTCLRFINDF;clear INDF register
INCFFSR;inc pointer
BTFSSFSR,4;all done?
GOTONEXT;no clear next
The Oscillator module has a wide variety of clock
sources and selection features that allow it to be used
in a wide range of applications while maximizing performance and minimizing power consumption. Figure 3-1
illustrates a block diagram of the Oscillator module.
Clock sources can be configured from external
oscillators, quartz crystal resonators, ceramic resonators
and Resistor-Capacitor (RC) circuits. In addition, the
system clock source can be configured from one of two
internal oscillators, with a choice of speeds selectable via
software. Additional clock features include:
• Selectable system clock source between external
or internal via software.
• Two-Speed Start-up mode, which minimizes
latency between external oscillator start-up and
code execution.
• Fail-Safe Clock Monitor (FSCM) designed to
detect a failure of the external clock source (LP,
XT, HS, EC or RC modes) and switch
automatically to the internal oscillator.
The Oscillator module can be configured in one of eight
clock modes.
1. EC – External clock with I/O on OSC2/CLKOUT.
2. LP – 32 kHz Low-Power Crystal mode.
3.XT – Medium Gain Crystal or Ceramic Resonator
Oscillator mode.
4.HS – High Gain Crystal or Ceramic Resonator
mode.
5. RC – External Resistor-Capacitor (RC) with
OSC/4 output on OSC2/CLKOUT.
F
6. RCIO – External Resistor-Capacitor (RC) with
I/O on OSC2/CLKOUT.
7. INTOSC – Internal oscillator with F
OSC/4 output
on OSC2 and I/O on OSC1/CLKIN.
8. INTOSCIO – Internal oscillator with I/O on
OSC1/CLKIN and OSC2/CLKOUT.
Clock Source modes are configured by the FOSC<2:0>
bits in the Configuration Word register (CONFIG). The
internal clock can be generated from two internal
oscillators. The HFINTOSC is a calibrated highfrequency oscillator. The LFINTOSC is an uncalibrated
low-frequency oscillator.
The Oscillator Control (OSCCON) register (Figure 3-1)
controls the system clock and frequency selection
options. The OSCCON register contains the following
bits:
• Frequency selection bits (IRCF)
• Frequency Status bits (HTS, LTS)
• System clock control bits (OSTS, SCS)
REGISTER 3-1:OSCCON: OSCILLATOR CONTROL REGISTER
U-0R/W-1R/W-1R/W-0R-1R-0R-0R/W-0
(1)
(1)
HTSLTSSCS
—IRCF2IRCF1IRCF0OSTS
bit 7bit 0
Legend:
R = Readable bitW = Writable bitU = Unimplemented bit, read as ‘0’
-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown
bit 7Unimplemented: Read as ‘0’
bit 6-4IRCF<2:0>: Internal Oscillator Frequency Select bits
bit 3OSTS: Oscillator Start-up Time-out Status bit
1 = Device is running from the clock defined by FOSC<2:0> of the CONFIG register
0 = Device is running from the internal oscillator (HFINTOSC or LFINTOSC)
bit 2HTS: HFINTOSC Status bit (High Frequency – 8 MHz to 125 kHz)
1 = HFINTOSC is stable
0 = HFINTOSC is not stable
bit 1LTS: LFINTOSC Stable bit (Low Frequency – 31 kHz)
1 = LFINTOSC is stable
0 = LFINTOSC is not stable
bit 0SCS: System Clock Select bit
1 = Internal oscillator is used for system clock
0 = Clock source defined by FOSC<2:0> of the CONFIG register
Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe
Clock Source modes can be classified as external or
internal.
• External Clock modes rely on external circuitry for
the clock source. Examples are: Oscillator modules (EC mode), quartz crystal resonators or
ceramic resonators (LP, XT and HS modes) and
Resistor-Capacitor (RC) mode circuits.
• Internal clock sources are contained internally
within the Oscillator module. The Oscillator
module has two internal oscillators: the 8 MHz
High-Frequency Internal Oscillator (HFINTOSC)
and the 31 kHz Low-Frequency Internal Oscillator
(LFINTOSC).
The system clock can be selected between external or
internal clock sources via the System Clock Select
(SCS) bit of the OSCCON register. See Section 3.6
“Clock Switching” for additional information.
3.4External Clock Modes
3.4.1OSCILLATOR START-UP TIMER (OST)
If the Oscillator module is configured for LP, XT or HS
modes, the Oscillator Start-up Timer (OST) counts
1024 oscillations from OSC1. This occurs following a
Power-on Reset (POR) and when the Power-up Timer
(PWRT) has expired (if configured), or a wake-up from
Sleep. During this time, the program counter does not
increment and program execution is suspended. The
OST ensures that the oscillator circuit, using a quartz
crystal resonator or ceramic resonator, has started and
is providing a stable system clock to the Oscillator
module. When switching between clock sources, a
delay is required to allow the new clock to stabilize.
These oscillator delays are shown in Table 3-1.
In order to minimize latency between external oscillator
start-up and code execution, the Two-Speed Clock
Start-up mode can be selected (see Section 3.7 “Two-
Speed Clock Start-up Mode”).
TABLE 3-1:OSCILLATOR DELAY EXAMPLES
Switch FromSwitch ToFrequencyOscillator Delay
Sleep/POR
Sleep/POREC, RCDC – 20 MHz2 cycles
LFINTOSC (31 kHz)EC, RCDC – 20 MHz1 cycle of each
Sleep/PORLP, XT, HS32 kHz to 20 MHz1024 Clock Cycles (OST)
LFINTOSC (31 kHz)HFINTOSC125 kHz to 8 MHz1 μs (approx.)
LFINTOSC
HFINTOSC
31 kHz
125 kHz to 8 MHz
Oscillator Warm-up Delay (T
WARM)
3.4.2EC MODE
The External Clock (EC) mode allows an externally
generated logic level as the system clock source. When
operating in this mode, an external clock source is
connected to the OSC1 input and the OSC2 is available
for general purpose I/O. Figure 3-2 shows the pin
connections for EC mode.
The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
operation after a Power-on Reset (POR) or wake-up
from Sleep. Because the PIC
static, stopping the external clock input will have the
effect of halting the device while leaving all data intact.
Upon restarting the external clock, the device will
resume operation as if no time had elapsed.
The LP, XT and HS modes support the use of quartz
crystal resonators or ceramic resonators connected to
OSC1 and OSC2 (Figure 3-3). The mode selects a low,
medium or high gain setting of the internal inverteramplifier to support various resonator types and speed.
LP Oscillator mode selects the lowest gain setting of the
internal inverter-amplifier. LP mode current consumption
is the least of the three modes. This mode is designed to
drive only 32.768 kHz tuning-fork type crystals (watch
crystals).
XT Oscillator mode selects the intermediate gain
setting of the internal inverter-amplifier. XT mode
current consumption is the medium of the three modes.
This mode is best suited to drive resonators with a
medium drive level specification.
HS Oscillator mode selects the highest gain setting of the
internal inverter-amplifier. HS mode current consumption
is the highest of the three modes. This mode is best
suited for resonators that require a high drive setting.
Figure 3-3 and Figure 3-4 show typical circuits for
quartz crystal and ceramic resonators, respectively.
FIGURE 3-3:QUARTZ CRYSTAL
OPERATION (LP, XT OR
HS MODE)
PIC® MCU
OSC1/CLKIN
C1
Quartz
Crystal
C2
Note 1: A series resistor (RS) may be required for
2: The value of R
(1)
R
S
quartz crystals with low drive level.
selected (typically between 2 MΩ to 10 MΩ).
(2)
RF
OSC2/CLKOUT
F varies with the Oscillator mode
To Internal
Logic
Sleep
Note 1: Quartz crystal characteristics vary according
to type, package and manufacturer. The
user should consult the manufacturer data
sheets for specifications and recommended
application.
2: Always verify oscillator performance over
DD and temperature range that is
the V
expected for the application.
3: For oscillator design assistance, reference
the following Microchip Applications Notes:
• AN826, “Crystal Oscillator Basics and
Crystal Selection for rfPIC
®
and PIC®
Devices” (DS00826)
®
• AN849, “Basic PIC
Oscillator Design”
(DS00849)
®
• AN943, “Practical PIC
Oscillator
Analysis and Design” (DS00943)
• AN949, “Making Your Oscillator Work”
(DS00949)
FIGURE 3-4:CERAMIC RESONATOR
OPERATION
(XT OR HS MODE)
PIC® MCU
OSC1/CLKIN
C1
(3)
RP
C2
Ceramic
Resonator
Note 1: A series resistor (RS) may be required for
ceramic resonators with low drive level.
2: The value of R
selected (typically between 2 MΩ to 10 MΩ).
3: An additional parallel feedback resistor (R
may be required for proper ceramic resonator
operation.
The external Resistor-Capacitor (RC) modes support
the use of an external RC circuit. This allows the
designer maximum flexibility in frequency choice while
keeping costs to a minimum when clock accuracy is not
required. There are two modes: RC and RCIO.
In RC mode, the RC circuit connects to OSC1. OSC2/
CLKOUT outputs the RC oscillator frequency divided
by 4. This signal may be used to provide a clock for
external circuitry, synchronization, calibration, test or
other application requirements. Figure 3-5 shows the
external RC mode connections.
FIGURE 3-5:EXTERNAL RC MODES
VDD
REXT
OSC1/CLKIN
CEXT
VSS
OSC/4 or
F
(2)
I/O
Recommended values: 10 kΩ ≤ REXT ≤ 100 kΩ, <3V
Note 1:Alternate pin functions are listed in the
2:Output depends upon RC or RCIO Clock
OSC2/CLKOUT
Section 1.0 “Device Overview”.
mode.
In RCIO mode, the RC circuit is connected to OSC1.
OSC2 becomes an additional general purpose I/O pin.
The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacitor (CEXT) values
and the operating temperature. Other factors affecting
the oscillator frequency are:
• threshold voltage variation
• component tolerances
• packaging variations in capacitance
The user also needs to take into account variation due
to tolerance of external RC components used.
PIC® MCU
(1)
3 kΩ ≤ R
C
EXT≤ 100 kΩ, 3-5V
EXT > 20 pF, 2-5V
Internal
Clock
3.5Internal Clock Modes
The Oscillator module has two independent, internal
oscillators that can be configured or selected as the
system clock source.
1. The HFINTOSC (High-Frequency Internal
Oscillator) is factory calibrated and operates at
8 MHz. The frequency of the HFINTOSC can be
user-adjusted via software using the OSCTUNE
register (Register 3-2).
2. The LFINTOSC (Low-Frequency Internal
Oscillator) is uncalibrated and operates at
31 kHz.
The system clock speed can be selected via software
using the Internal Oscillator Frequency Select bits
IRCF<2:0> of the OSCCON register.
The system clock can be selected between external or
internal clock sources via the System Clock Selection
(SCS) bit of the OSCCON register. See Section 3.6“Clock Switching” for more information.
3.5.1INTOSC AND INTOSCIO MODES
The INTOSC and INTOSCIO modes configure the
internal oscillators as the system clock source when
the device is programmed using the oscillator selection
or the FOSC<2:0> bits in the Configuration Word
register (CONFIG).
In INTOSC mode, OSC1/CLKIN is available for general
purpose I/O. OSC2/CLKOUT outputs the selected
internal oscillator frequency divided by 4. The CLKOUT
signal may be used to provide a clock for external
circuitry, synchronization, calibration, test or other
application requirements.
In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT
are available for general purpose I/O.
3.5.2HFINTOSC
The High-Frequency Internal Oscillator (HFINTOSC) is
a factory calibrated 8 MHz internal clock source. The
frequency of the HFINTOSC can be altered via
software using the OSCTUNE register (Register 3-2).
The output of the HFINTOSC connects to a postscaler
and multiplexer (see Figure 3-1). One of seven
frequencies can be selected via software using the
IRCF<2:0> bits of the OSCCON register. See
Section 3.5.4 “Frequency Select Bits (IRCF)” for
more information.
The HFINTOSC is enabled by selecting any frequency
between 8 MHz and 125 kHz by setting the IRCF<2:0>
bits of the OSCCON register ≠ 000. Then, set the
System Clock Source (SCS) bit of the OSCCON
register to ‘1’ or enable Two-Speed Start-up by setting
the IESO bit in the Configuration Word register
(CONFIG) to ‘1’.
The HF Internal Oscillator (HTS) bit of the OSCCON
register indicates whether the HFINTOSC is stable or not.
The HFINTOSC is factory calibrated but can be
adjusted in software by writing to the OSCTUNE
register (Register 3-2).
The default value of the OSCTUNE register is ‘0’. The
value is a 5-bit two’s complement number.
When the OSCTUNE register is modified, the
HFINTOSC frequency will begin shifting to the new
frequency. Code execution continues during this shift.
There is no indication that the shift has occurred.
OSCTUNE does not affect the LFINTOSC frequency.
Operation of features that depend on the LFINTOSC
clock source frequency, such as the Power-up Timer
(PWRT), Watchdog Timer (WDT), Fail-Safe Clock
Monitor (FSCM) and peripherals, are not affected by the
change in frequency.
REGISTER 3-2:OSCTUNE: OSCILLATOR TUNING REGISTER
U-0U-0U-0R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
———TUN4TUN3TUN2TUN1TUN0
bit 7bit 0
Legend:
R = Readable bitW = Writable bitU = Unimplemented bit, read as ‘0’
-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown
bit 7-5Unimplemented: Read as ‘0’
bit 4-0TUN<4:0>: Frequency Tuning bits
01111 = Maximum frequency
01110 =
•
•
•
00001 =
00000 = Oscillator module is running at the factory-calibrated frequency.
11111 =
The Low-Frequency Internal Oscillator (LFINTOSC) is
an uncalibrated 31 kHz internal clock source.
The output of the LFINTOSC connects to a postscaler
and multiplexer (see Figure 3-1). Select 31 kHz, via
software, using the IRCF<2:0> bits of the OSCCON
register. See Section 3.5.4 “Frequency Select Bits(IRCF)” for more information. The LFINTOSC is also the
frequency for the Power-up Timer (PWRT), Watchdog
Timer (WDT) and Fail-Safe Clock Monitor (FSCM).
The LFINTOSC is enabled by selecting 31 kHz
(IRCF<2:0> bits of the OSCCON register = 000) as the
system clock source (SCS bit of the OSCCON
register = 1), or when any of the following are enabled:
• Two-Speed Start-up IESO bit of the Configuration
Word register = 1 and IRCF<2:0> bits of the
OSCCON register = 000
• Power-up Timer (PWRT)
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor (FSCM)
The LF Internal Oscillator (LTS) bit of the OSCCON
register indicates whether the LFINTOSC is stable or
not.
3.5.4FREQUENCY SELECT BITS (IRCF)
The output of the 8 MHz HFINTOSC and 31 kHz
LFINTOSC connects to a postscaler and multiplexer
(see Figure 3-1). The Internal Oscillator Frequency
Select bits IRCF<2:0> of the OSCCON register select
the frequency output of the internal oscillators. One of
eight frequencies can be selected via software:
•8 MHz
• 4 MHz (Default after Reset)
•2 MHz
•1 MHz
• 500 kHz
• 250 kHz
• 125 kHz
• 31 kHz (LFINTOSC)
Note:Following any Reset, the IRCF<2:0> bits of
the OSCCON register are set to ‘110’ and
the frequency selection is set to 4 MHz.
The user can modify the IRCF bits to
select a different frequency.
3.5.5HFINTOSC AND LFINTOSC CLOCK
SWITCH TIMING
When switching between the LFINTOSC and the
HFINTOSC, the new oscillator may already be shut
down to save power (see Figure 3-6). If this is the case,
there is a delay after the IRCF<2:0> bits of the
OSCCON register are modified before the frequency
selection takes place. The LTS and HTS bits of the
OSCCON register will reflect the current active status
of the LFINTOSC and HFINTOSC oscillators. The
timing of a frequency selection is as follows:
1.IRCF<2:0> bits of the OSCCON register are
modified.
2. If the new clock is shut down, a clock start-up
delay is started.
3.Clock switch circuitry waits for a falling edge of
the current clock.
4. CLKOUT is held low and the clock switch
circuitry waits for a rising edge in the new clock.
5. CLKOUT is now connected with the new clock.
LTS and HTS bits of the OSCCON register are
updated as required.
6.Clock switch is complete.
See Figure 3-1 for more details.
If the internal oscillator speed selected is between
8 MHz and 125 kHz, there is no start-up delay before
the new frequency is selected. This is because the old
and new frequencies are derived from the HFINTOSC
via the postscaler and multiplexer.
Start-up delay specifications are located in the
oscillator tables of Section 17.0 “ElectricalSpecifications”.
The system clock source can be switched between
external and internal clock sources via software using
the System Clock Select (SCS) bit of the OSCCON
register.
3.6.1SYSTEM CLOCK SELECT (SCS) BIT
The System Clock Select (SCS) bit of the OSCCON
register selects the system clock source that is used for
the CPU and peripherals.
• When the SCS bit of the OSCCON register = 0,
the system clock source is determined by
configuration of the FOSC<2:0> bits in the
Configuration Word register (CONFIG).
• When the SCS bit of the OSCCON register = 1,
the system clock source is chosen by the internal
oscillator frequency selected by the IRCF<2:0>
bits of the OSCCON register. After a Reset, the
SCS bit of the OSCCON register is always
cleared.
Note:Any automatic clock switch, which may
occur from Two-Speed Start-up or Fail-Safe
Clock Monitor, does not update the SCS bit
of the OSCCON register. The user can
monitor the OSTS bit of the OSCCON
register to determine the current system
clock source.
3.6.2OSCILLATOR START-UP TIME-OUT
STATUS (OSTS) BIT
The Oscillator Start-up Time-out Status (OSTS) bit of
the OSCCON register indicates whether the system
clock is running from the external clock source, as
defined by the FOSC<2:0> bits in the Configuration
Word register (CONFIG), or from the internal clock
source. In particular, OSTS indicates that the Oscillator
Start-up Timer (OST) has timed out for LP, XT or HS
modes.
3.7Two-Speed Clock Start-up Mode
Two-Speed Start-up mode provides additional power
savings by minimizing the latency between external
oscillator start-up and code execution. In applications
that make heavy use of the Sleep mode, Two-Speed
Start-up will remove the external oscillator start-up
time from the time spent awake and can reduce the
overall power consumption of the device.
This mode allows the application to wake-up from
Sleep, perform a few instructions using the INTOSC
as the clock source and go back to Sleep without
waiting for the primary oscillator to become stable.
When the Oscillator module is configured for LP, XT or
HS modes, the Oscillator Start-up Timer (OST) is
enabled (see Section 3.4.1 “Oscillator Start-up Timer(OST)”). The OST will suspend program execution until
1024 oscillations are counted. Two-Speed Start-up
mode minimizes the delay in code execution by
operating from the internal oscillator as the OST is
counting. When the OST count reaches 1024 and the
OSTS bit of the OSCCON register is set, program
execution switches to the external oscillator.
3.7.1TWO-SPEED START-UP MODE
CONFIGURATION
Two-Speed Start-up mode is configured by the
following settings:
• IESO (of the Configuration Word register) = 1;
Internal/External Switchover bit (Two-Speed Startup mode enabled).
• SCS (of the OSCCON register) = 0.
• FOSC<2:0> bits in the Configuration Word
register (CONFIG) configured for LP, XT or HS
mode.
Two-Speed Start-up mode is entered after:
• Power-on Reset (POR) and, if enabled, after
Power-up Timer (PWRT) has expired, or
• Wake-up from Sleep.
If the external clock oscillator is configured to be
anything other than LP, XT or HS mode, then Twospeed Start-up is disabled. This is because the external
clock oscillator does not require any stabilization time
after POR or an exit from Sleep.
3.7.2TWO-SPEED START-UP
SEQUENCE
1. Wake-up from Power-on Reset or Sleep.
2. Instructions begin execution by the internal
oscillator at the frequency set in the IRCF<2:0>
bits of the OSCCON register.
3. OST enabled to count 1024 clock cycles.
4. OST timed out, wait for falling edge of the
internal oscillator.
5. OSTS is set.
6. System clock held low until the next falling edge
of new clock (LP, XT or HS mode).
7. System clock is switched to external clock
source.
Note:Executing a SLEEP instruction will abort
the oscillator start-up time and will cause
the OSTS bit of the OSCCON register to
remain clear.
Checking the state of the OSTS bit of the OSCCON
register will confirm if the microcontroller is running
from the external clock source, as defined by the
FOSC<2:0> bits in the Configuration Word register
(CONFIG), or the internal oscillator.
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue operating should the external oscillator fail.
The FSCM can detect oscillator failure any time after
the Oscillator Start-up Timer (OST) has expired. The
FSCM is enabled by setting the FCMEN bit in the
Configuration Word register (CONFIG). The FSCM is
applicable to all external Oscillator modes (LP, XT, HS,
EC, RC and RCIO).
FIGURE 3-8:FSCM BLOCK DIAGRAM
Clock Monitor
External
Clock
LFINTOSC
Oscillator
31 kHz
(~32 μs)
Sample Clock
÷ 64
488 Hz
(~2 ms)
3.8.1FAIL-SAFE DETECTION
The FSCM module detects a failed oscillator by
comparing the external oscillator to the FSCM sample
clock. The sample clock is generated by dividing the
LFINTOSC by 64. See Figure 3-8. Inside the fail
detector block is a latch. The external clock sets the
latch on each falling edge of the external clock. The
sample clock clears the latch on each rising edge of the
sample clock. A failure is detected when an entire halfcycle of the sample clock elapses before the primary
clock goes low.
Latch
S
R
Q
Q
Clock
Failure
Detected
3.8.3FAIL-SAFE CONDITION CLEARING
The Fail-Safe condition is cleared after a Reset,
executing a SLEEP instruction or toggling the SCS bit
of the OSCCON register. When the SCS bit is toggled,
the OST is restarted. While the OST is running, the
device continues to operate from the INTOSC selected
in OSCCON. When the OST times out, the Fail-Safe
condition is cleared and the device will be operating
from the external clock source. The Fail-Safe condition
must be cleared before the OSFIF flag can be cleared.
3.8.4RESET OR WAKE-UP FROM SLEEP
The FSCM is designed to detect an oscillator failure
after the Oscillator Start-up Timer (OST) has expired.
The OST is used after waking up from Sleep and after
any type of Reset. The OST is not used with the EC or
RC Clock modes so that the FSCM will be active as
soon as the Reset or wake-up has completed. When
the FSCM is enabled, the Two-Speed Start-up is also
enabled. Therefore, the device will always be executing
code while the OST is operating.
Note:Due to the wide range of oscillator start-up
times, the Fail-Safe circuit is not active
during oscillator start-up (i.e., after exiting
Reset or Sleep). After an appropriate
amount of time, the user should check the
OSTS bit of the OSCCON register to verify
the oscillator start-up and that the system
clock switchover has successfully
completed.
3.8.2FAIL-SAFE OPERATION
When the external clock fails, the FSCM switches the
device clock to an internal clock source and sets the bit
flag OSFIF of the PIR2 register. Setting this flag will
generate an interrupt if the OSFIE bit of the PIE2
register is also set. The device firmware can then take
steps to mitigate the problems that may arise from a
failed clock. The system clock will continue to be
sourced from the internal clock source until the device
firmware successfully restarts the external oscillator
and switches back to external operation.
The internal clock source chosen by the FSCM is
determined by the IRCF<2:0> bits of the OSCCON
register. This allows the internal oscillator to be
configured before a failure occurs.
Note:The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
Oscillator
Failure
Failure
Detected
TestTest
TABLE 3-2:SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
NameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
CONFIG
OSCCON
OSCTUNE
PIE1
PIR1
Legend:x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.
Note 1:Other (non Power-up) Resets include MCLR
(2)
2:See Configuration Word register (Register 14-1) for operation of all register bits.
There are as many as eighteen general purpose I/O
pins available. Depending on which peripherals are
enabled, some or all of the pins may not be available as
general purpose I/O. In general, when a peripheral is
enabled, the associated pin may not be used as a
general purpose I/O pin.
4.1PORTA and the TRISA Registers
PORTA is a 6-bit wide, bidirectional port. The
corresponding data direction register is TRISA
(Register 4-2). Setting a TRISA bit (= 1) will make the
corresponding PORTA pin an input (i.e., disable the
output driver). Clearing a TRISA bit (= 0) will make the
corresponding PORTA pin an output (i.e., enables
output driver and puts the contents of the output latch
on the selected pin). The exception is RA3, which is
input only and its TRIS bit will always read as ‘1’.
Example 4-1 shows how to initialize PORTA.
Reading the PORTA register (Register 4-1) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then
written to the PORT data latch. RA3 reads ‘0’ when
MCLRE = 1.
The TRISA register controls the PORTA pin output
drivers, even when they are being used as analog
inputs. The user should ensure the bits in the TRISA
register are maintained set when using them as analog
inputs. I/O pins configured as analog input always read
‘0’.
Note:The ANSEL register must be initialized to
configure an analog channel as a digital
input. Pins configured as analog inputs will
read ‘0’.
EXAMPLE 4-1:INITIALIZING PORTA
BCFSTATUS,RP0 ;Bank 0
BCFSTATUS,RP1 ;
CLRFPORTA;Init PORTA
BSFSTATUS,RP1 ;Bank 2
CLRF ANSEL;digital I/O
BSFSTATUS,RP0 ;Bank 1
BCFSTATUS,RP1 ;
MOVLW 0Ch;Set RA<3:2> as inputs
MOVWF TRISA;and set RA<5:4,1:0>
;as outputs
BCFSTATUS,RP0 ;Bank 0
REGISTER 4-1:PORTA: PORTA REGISTER
U-0U-0R/W-xR/W-xR-xR/W-xR/W-xR/W-x
——RA5RA4RA3RA2RA1RA0
bit 7bit 0
Legend:
R = Readable bitW = Writable bitU = Unimplemented bit, read as ‘0’
-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown
bit 7-6Unimplemented: Read as ‘0’
bit 5-0RA<5:0>: PORTA I/O Pin bit
1 = Port pin is > V
0 = Port pin is < VIL
IH
REGISTER 4-2:TRISA: PORTA TRI-STATE REGISTER
U-0U-0R/W-1R/W-1R-1R/W-1R/W-1R/W-1
——TRISA5TRISA4TRISA3TRISA2TRISA1TRISA0
bit 7bit 0
Legend:
R = Readable bitW = Writable bitU = Unimplemented bit, read as ‘0’
-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown
bit 7-6Unimplemented: Read as ‘0’
bit 5-0TRISA<5:0>: PORTA Tri-State Control bit
Note 1:TRISA<3> always reads ‘1’.
2:TRISA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
PIC16F631/677/685/687/689/690
4.2Additional Pin Functions
Every PORTA pin on this device family has an
interrupt-on-change option and a weak pull-up option.
RA0 also has an Ultra Low-Power Wake-up option. The
next three sections describe these functions.
4.2.1ANSEL AND ANSELH REGISTERS
The ANSEL and ANSELH registers are used to disable
the input buffers of I/O pins, which allow analog voltages
to be applied to those pins without causing excessive
current. Setting the ANSx bit of a corresponding pin will
cause all digital reads of that pin to return ‘0’ and also
permit analog functions of that pin to operate correctly.
The state of the ANSx bit has no effect on the digital
output function of its corresponding pin. A pin with the
TRISx bit clear and ANSx bit set will operate as a digital
output, together with the analog input function of that
pin. Pins with the ANSx bit set always read ‘0’, which
can cause unexpected behavior when executing read
or write operations on the port due to the
read-modify-write sequence of all such operations.
4.2.2WEAK PULL-UPS
Each of the PORTA pins, except RA3, has an
individually configurable internal weak pull-up. Control
bits WPUAx enable or disable each pull-up. Refer to
Register 4-4. Each weak pull-up is automatically turned
off when the port pin is configured as an output. The
pull-ups are disabled on a Power-on Reset by the
RABPU
automatically enabled for RA3 when configured as
MCLR
software control of the MCLR
bit of the OPTION register. A weak pull-up is
and disabled when RA3 is an I/O. There is no
pull-up.
4.2.3INTERRUPT-ON-CHANGE
Each PORTA pin is individually configurable as an
interrupt-on-change pin. Control bits IOCAx enable or
disable the interrupt function for each pin. Refer to
Register 4-6. The interrupt-on-change is disabled on a
Power-on Reset.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
PORTA. The ‘mismatch’ outputs of the last read are
OR’d together to set the PORTA Change Interrupt Flag
bit (RABIF) in the INTCON register (Register 2-6).
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, clears the
interrupt by:
a) Any read or write of PORTA. This will end the
mismatch condition, then,
b) Clear the flag bit RABIF.
A mismatch condition will continue to set flag bit RABIF.
Reading PORTA will end the mismatch condition and
allow flag bit RABIF to be cleared. The latch holding the
last read value is not affected by a MCLR
Reset. After these Resets, the RABIF flag will continue
to be set if a mismatch is present.
Note:If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RABIF
interrupt flag may not get set.
R = Readable bitW = Writable bitU = Unimplemented bit, read as ‘0’
-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown
bit 7-6Unimplemented: Read as ‘0’
bit 5-4WPUA<5:4>: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
bit 3Unimplemented: Read as ‘0’
bit 2-0WPUA<2:0>: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
Note 1: Global RABPU
2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISA = 0).
3: The RA3 pull-up is enabled when configured as MCLR and disabled as an I/O in the Configuration Word.
4: WPUA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.
bit of the OPTION register must be enabled for individual pull-ups to be enabled.
REGISTER 4-6:IOCA: INTERRUPT-ON-CHANGE PORTA REGISTER
U-0U-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
——IOCA5IOCA4IOCA3IOCA2IOCA1IOCA0
bit 7bit 0
Legend:
R = Readable bitW = Writable bitU = Unimplemented bit, read as ‘0’
-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown
bit 7-6Unimplemented: Read as ‘0’
bit 5-0IOCA<5:0>: Interrupt-on-change PORTA Control bit
The Ultra Low-Power Wake-up (ULPWU) on RA0 allows
a slow falling voltage to generate an interrupt-on-change
on RA0 without excess current consumption. The mode
is selected by setting the ULPWUE bit of the PCON
register. This enables a small current sink, which can be
used to discharge a capacitor on RA0.
Follow these steps to use this feature:
a) Charge the capacitor on RA0 by configuring the
RA0 pin to output (= 1).
b) Configure RA0 as an input.
c) Enable interrupt-on-change for RA0.
d) Set the ULPWUE bit of the PCON register to
begin the capacitor discharge.
e) Execute a SLEEP instruction.
When the voltage on RA0 drops below V
will be generated which will cause the device to
wake-up and execute the next instruction. If the GIE bit
of the INTCON register is set, the device will then call
the interrupt vector (0004h). See Section 4.4.2 “Inter-
rupt-on-change” and Section 14.3.3
“PORTA/PORTB Interrupt” for more information.
This feature provides a low-power technique for
periodically waking up the device from Sleep. The
time-out is dependent on the discharge time of the RC
circuit on RA0. See Example 4-2 for initializing the
Ultra Low-Power Wake-up module.
IL, an interrupt
A series resistor between RA0 and the external
capacitor provides overcurrent protection for the
RA0/AN0/C1IN+/ICSPDAT/ULPWU pin and can allow
for software calibration of the time-out (see Figure 4-1).
A timer can be used to measure the charge time and
discharge time of the capacitor. The charge time can
then be adjusted to provide the desired interrupt delay.
This technique will compensate for the affects of
temperature, voltage and component accuracy. The
Ultra Low-Power Wake-up peripheral can also be
configured as a simple Programmable Low-Voltage
Detect or temperature sensor.
Note:For more information, refer to Application
Note AN879, “Using the Microchip UltraLow-Power Wake-up Module” (DS00879).
EXAMPLE 4-2:ULTRA LOW-POWER
WAKE-UP INITIALIZATION
BCFSTATUS,RP0;Bank 0
BCFSTATUS,RP1;
BSFPORTA,0;Set RA0 data latch
BSFSTATUS,RP1;Bank 2
BCFANSEL,0;RA0 to digital I/O
BSFSTATUS,RP0;Bank 1
BCFSTATUS,RP1;
BCFTRISA,0;Output high to
CALLCapDelay;charge capacitor
BSFPCON,ULPWUE;Enable ULP Wake-up
BSFIOCA,0;Select RA0 IOC
BSFTRISA,0;RA0 to input
MOVLWB’10001000’;Enable interrupt
MOVWFINTCON;and clear flag
BCFSTATUS,RP0;Bank 0
SLEEP;Wait for IOC
NOP;
Each PORTA pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about individual functions
such as the comparator or the A/D Converter (ADC),
refer to the appropriate section in this data sheet.
FIGURE 4-1:BLOCK DIAGRAM OF RA0
Data Bus
WR
WPUA
WPUA
PORTA
RD
WR
D
Q
CK
Q
D
Q
CK
Q
4.2.5.1RA0/AN0/C1IN+/ICSPDAT/ULPWU
Figure 4-2 shows the diagram for this pin. The
RA0/AN0/C1IN+/ICSPDAT/ULPWU pin is configurable
to function as one of the following:
PORTB is a 4-bit wide, bidirectional port. The
corresponding data direction register is TRISB (Register
4-6). Setting a TRISB bit (= 1) will make the
corresponding PORTB pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISB bit (= 0) will make the corresponding
PORTB pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 4-3 shows how to initialize PORTB. Reading
the PORTB register (Register 4-5) reads the status of the
pins, whereas writing to it will write to the PORT latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, this value is modified and then written to the PORT
data latch.
The TRISB register controls the PORTB pin output
drivers, even when they are being used as analog inputs.
The user should ensure the bits in the TRISB register are
maintained set when using them as analog inputs. I/O
pins configured as analog input always read ‘0’.
to configure an analog channel as a digital
input. Pins configured as analog inputs will
read ‘0’.
4.4Additional PORTB Pin Functions
PORTB pins RB<7:4> on the device family device have
an interrupt-on-change option and a weak pull-up
option. The following three sections describe these
PORTB pin functions.
4.4.1WEAK PULL-UPS
Each of the PORTB pins has an individually configurable
internal weak pull-up. Control bits WPUB<7:4> enable or
disable each pull-up (see Register 4-9). Each weak
pull up is automatically turned off when the port pin is
configured as an output. All pull-ups are disabled on a
Power-on Reset by the RABPU
bit of the OPTION
register.
4.4.2INTERRUPT-ON-CHANGE
Four of the PORTB pins are individually configurable as
an interrupt-on-change pin. Control bits IOCB<7:4>
enable or disable the interrupt function for each pin.
Refer to Register 4-10. The interrupt-on-change feature
is disabled on a Power-on Reset.
For enabled interrupt-on-change pins, the present
value is compared with the old value latched on the last
read of PORTB to determine which bits have changed
or mismatch the old value. The ‘mismatch’ outputs are
OR’d together to set the PORTB Change Interrupt flag
bit (RABIF) in the INTCON register (Register 2-3).
This interrupt can wake the device from Sleep. The user,
in the Interrupt Service Routine, clears the interrupt by:
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear the flag bit RABIF.
A mismatch condition will continue to set flag bit RABIF.
Reading or writing PORTB will end the mismatch
condition and allow flag bit RABIF to be cleared. The latch
holding the last read value is not affected by a MCLR
Brown-out Reset. After these Resets, the RABIF flag will
continue to be set if a mismatch is present.
Note:If a change on the I/O pin should occur when
the read operation is being executed (start of
the Q2 cycle), then the RABIF interrupt flag
may not get set. Furthermore, since a read
or write on a port affects all bits of that port,
care must be taken when using multiple pins
in Interrupt-on-Change mode. Changes on
one pin may not be seen while servicing
changes on another pin.
nor
REGISTER 4-7:PORTB: PORTB REGISTER
R/W-xR/W-xR/W-xR/W-xU-0U-0U-0U-0
RB7RB6RB5RB4
bit 7bit 0
Legend:
R = Readable bitW = Writable bitU = Unimplemented bit, read as ‘0’
-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown
Each PORTB pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about individual functions
such as the SSP, I
appropriate section in this data sheet.
2
C™ or interrupts, refer to the
4.4.3.1RB4/AN10/SDI/SDA
Figure 4-7 shows the diagram for this pin. The
RB4/AN10/SDI/SDA
as one of the following:
• a general purpose I/O
• an analog input for the ADC (except PIC16F631)
• a SPI data I/O
2
C data I/O
•an I
Note 1: SDI and SDA are available on
PIC16F677
16F690 only.
(1)
pin is configurable to function
/PIC16F687/PIC16F689/PIC
FIGURE 4-7:BLOCK DIAGRAM OF RB4
(1)
Analog
Data Bus
WR
WPUB
RD
WPUB
WR
PORTB
WR
TRISB
RD
TRISB
D
CK
D
CK
D
CK
Q
Q
Q
Q
Q
Q
Input Mode
RABPU
SSPEN
SSPSR
From
SSP
0
1
1
0
0
1
1
0
Analog
Input Mode
VDD
Weak
VDD
I/O Pin
VSS
(1)
RD
PORTB
D
Q
D
WR
IOCB
RD
IOCB
Interrupt-on-
Note 1:ANSEL determines Analog Input mode.
CK
Q
Change
RD PORTB
To SSPSR
To A/D Converter
Available on PIC16F677/PIC16F687/PIC16F689/PIC16F690
only.
PORTC is a 8-bit wide, bidirectional port. The
corresponding data direction register is TRISC (Register
4-10). Setting a TRISC bit (= 1) will make the
corresponding PORTC pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISC bit (= 0) will make the corresponding
PORTC pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
The TRISC register controls the PORTC pin output
drivers, even when they are being used as analog inputs.
The user should ensure the bits in the TRISC register are
maintained set when using them as analog inputs. I/O
pins configured as analog input always read ‘0’.
Note:The ANSEL and ANSELH registers must
be initialized to configure an analog
channel as a digital input. Pins configured
as analog inputs will read ‘0’.
Example 4-4 shows how to initialize PORTC. Reading
the PORTC register (Register 4-9) reads the status of the
pins, whereas writing to it will write to the PORT latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, this value is modified and then written to the PORT
data latch.
EXAMPLE 4-4:INITIALIZING PORTC
BCFSTATUS,RP0;Bank 0
BCFSTATUS,RP1;
CLRFPORTC;Init PORTC
BSFSTATUS,RP1;Bank 2
CLRFANSEL;digital I/O
BSFSTATUS,RP0;Bank 1
BCFSTATUS,RP1;
MOVLW0Ch;Set RC<3:2> as inputs
MOVWFTRISC;and set RC<5:4,1:0>
;as outputs
BCFSTATUS,RP0;Bank 0
REGISTER 4-11:PORTC: PORTC REGISTER
R/W-0R/W-xR/W-xR/W-xR/W-xR/W-xR/W-xR/W-x
RC7RC6RC5RC4RC3RC2RC1RC0
bit 7bit 0
Legend:
R = Readable bitW = Writable bitU = Unimplemented bit, read as ‘0’
-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown
bit 7-0RC<7:0>: PORTC General Purpose I/O Pin bit
1 = Port pin is > V
0 = Port pin is < VIL
IH
REGISTER 4-12:TRISC: PORTC TRI-STATE REGISTER
R/W-1R/W-1R/W-1R/W-1R-1R/W-1R/W-1R/W-1
TRISC7TRISC6TRISC5TRISC4TRISC3TRISC2TRISC1TRISC0
bit 7bit 0
Legend:
R = Readable bitW = Writable bitU = Unimplemented bit, read as ‘0’
-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown
bit 7-0TRISC<7:0>: PORTC Tri-State Control bit
1 = PORTC pin configured as an input (tri-stated)
0 = PORTC pin configured as an output
a conflict on RC4 and create unpredictable
results. Therefore, if C2OUT is enabled,
the ECCP+ can not be used in Half-Bridge
or Full-Bridge mode and vise-versa.
Legend:x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.
Note 1:PIC16F687/PIC16F689/PIC16F690 only.
The Timer0 module is an 8-bit timer/counter with the
following features:
• 8-bit timer/counter register (TMR0)
• 8-bit prescaler (shared with Watchdog Timer)
• Programmable internal or external clock source
• Programmable external clock edge selection
• Interrupt on overflow
Figure 5-1 is a block diagram of the Timer0 module.
5.1Timer0 Operation
When used as a timer, the Timer0 module can be used
as either an 8-bit timer or an 8-bit counter.
5.1.18-BIT TIMER MODE
When used as a timer, the Timer0 module will
increment every instruction cycle (without prescaler).
Timer mode is selected by clearing the T0CS bit of the
OPTION register to ‘0’.
When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
Note:The value written to the TMR0 register can
be adjusted, in order to account for the two
instruction cycle delay when TMR0 is
written.
5.1.28-BIT COUNTER MODE
When used as a counter, the Timer0 module will
increment on every rising or falling edge of the T0CKI
pin. The incrementing edge is determined by the T0SE
bit of the OPTION register. Counter mode is selected by
setting the T0CS bit of the OPTION register to ‘1’.
FIGURE 5-1:BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
FOSC/4
0
1
T0CKI
pin
T0SE
WDTE
SWDTEN
31 kHz
INTOSC
Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register.
2: SWDTEN and WDTPS<3:0> are bits in the WDTCON register.
3: WDTE bit is in the Configuration Word register.
A single software programmable prescaler is available
for use with either Timer0 or the Watchdog Timer
(WDT), but not both simultaneously. The prescaler
assignment is controlled by the PSA bit of the OPTION
register. To assign the prescaler to Timer0, the PSA bit
must be cleared to a ‘0’.
There are 8 prescaler options for the Timer0 module
ranging from 1:2 to 1:256. The prescale values are
selectable via the PS<2:0> bits of the OPTION register.
In order to have a 1:1 prescaler value for the Timer0
module, the prescaler must be assigned to the WDT
module.
The prescaler is not readable or writable. When the
prescaler is assigned to the Timer0 module, all
instructions writing to the TMR0 register will clear the
prescaler.
When the prescaler is assigned to WDT, a CLRWDT
instruction will clear the prescaler along with the WDT.
5.1.3.1Switching Prescaler Between
Timer0 and WDT Modules
As a result of having the prescaler assigned to either
Timer0 or the WDT, it is possible to generate an
unintended device Reset when switching prescaler
values. When changing the prescaler assignment from
Timer0 to the WDT module, the instruction sequence
shown in Example 5-1, must be executed.
EXAMPLE 5-1:CHANGING PRESCALER
(TIMER0 → WDT)
BANKSEL TMR0;
CLRWDT;Clear WDT
CLRFTMR0;Clear TMR0 and
When changing the prescaler assignment from the
WDT to the Timer0 module, the following instruction
sequence must be executed (see Example 5-2).
EXAMPLE 5-2:CHANGING PRESCALER
(WDT → TIMER0)
CLRWDT;Clear WDT and
;prescaler
BANKSEL OPTION_REG;
MOVLWb’11110000’ ;Mask TMR0 select and
ANDWFOPTION_REG,W ; prescaler bits
IORLWb’00000011’ ;Set prescale to 1:16
MOVWFOPTION_REG;
5.1.4TIMER0 INTERRUPT
Timer0 will generate an interrupt when the TMR0
register overflows from FFh to 00h. The T0IF interrupt
flag bit of the INTCON register is set every time the
TMR0 register overflows, regardless of whether or not
the Timer0 interrupt is enabled. The T0IF bit must be
cleared in software. The Timer0 interrupt enable is the
T0IE bit of the INTCON register.
Note:The Timer0 interrupt cannot wake the
processor from Sleep since the timer is
frozen during Sleep.
5.1.5USING TIMER0 WITH AN
EXTERNAL CLOCK
When Timer0 is in Counter mode, the synchronization
of the T0CKI input and the Timer0 register is accomplished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, the
high and low periods of the external clock source must
meet the timing requirements as shown in
Section 17.0 “Electrical Specifications”.
Figure 6-1 is a block diagram of the Timer1 module.
FIGURE 6-1:TIMER1 BLOCK DIAGRAM
6.1Timer1 Operation
The Timer1 module is a 16-bit incrementing counter
which is accessed through the TMR1H:TMR1L register
pair. Writes to TMR1H or TMR1L directly update the
counter.
When used with an internal clock source, the module is
a timer. When used with an external clock source, the
module can be used as either a timer or counter.
6.2Clock Source Selection
The TMR1CS bit of the T1CON register is used to select
the clock source. When TMR1CS = 0, the clock source
OSC/4. When TMR1CS = 1, the clock source is
is F
supplied externally.
Clock
Source
OSC/4xxxx0
F
T1OSCEN
T1CKI pin0xxx1
T1LPOSC1LP or
FOSC
Mode
INTOSCIO
TMR1CS
1
Set flag bit
TMR1IF on
Overflow
OSC1/T1CKI
OSC2/T1G
INTOSC
Without CLKOUT
T1OSCEN
Note 1:ST Buffer is low power type when using LP oscillator, or high speed type when using T1CKI.
To C2 Comparator Module
(2)
TMR1
TMR1HTMR1L
Oscillator
2:Timer1 register increments on rising edge.
3:Synchronize does not operate while in Sleep.
4:SYNCC2OUT is synchronized when the C2SYNC bit of the
When the internal clock source is selected the
TMR1H:TMR1L register pair will increment on multiples
OSC as determined by the Timer1 prescaler.
of F
6.2.2EXTERNAL CLOCK SOURCE
When the external clock source is selected, the Timer1
module may work as a timer or a counter.
When counting, Timer1 is incremented on the rising
edge of the external clock input T1CKI. In addition, the
Counter mode clock can be synchronized to the
microcontroller system clock or run asynchronously.
If an external clock oscillator is needed (and the
microcontroller is using the INTOSC without CLKOUT),
Timer1 can use the LP oscillator as a clock source.
Note:In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge after any one or
more of the following conditions:
• Timer1 enabled after POR reset
• Write to TMR1H or TMR1L
• Timer1 is disabled
• Timer1 is disabled (TMR1ON 0) when
T1CKI is high then Timer1 is enabled
(TMR1ON=1) when T1CKI is low.
Note:See Figure 6-2
6.3Timer1 Prescaler
Timer1 has four prescaler options allowing 1, 2, 4 or 8
divisions of the clock input. The T1CKPS bits of the
T1CON register control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write to
TMR1H or TMR1L.
6.4Timer1 Oscillator
A low-power 32.768 kHz crystal oscillator is built-in
between pins OSC1 (input) and OSC2 (amplifier
output). The oscillator is enabled by setting the
T1OSCEN control bit of the T1CON register. The
oscillator will continue to run during Sleep.
The Timer1 oscillator is shared with the system LP
oscillator. Thus, Timer1 can use this mode only when
the primary system clock is derived from the internal
oscillator or when the oscillator is in the LP mode. The
user must provide a software time delay to ensure
proper oscillator start-up.
TRISA5 and TRISA4 bits are set when the Timer1
oscillator is enabled. RA5 and RA4 bits read as ‘0’ and
TRISA5 and TRISA4 bits read as ‘1’.
Note:The oscillator requires a start-up and
stabilization time before use. Thus,
T1OSCEN should be set and a suitable
delay observed prior to enabling Timer1.
6.5Timer1 Operation in
Asynchronous Counter Mode
If control bit T1SYNC of the T1CON register is set, the
external clock input is not synchronized. The timer
increments asynchronously to the internal phase
clocks. If external clock source is selected then the
timer will continue to run during Sleep and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in
software are needed to read/write the timer (see
Section 6.5.1 “Reading and Writing Timer1 in
Asynchronous Counter Mode”).
Note:When switching from synchronous to
asynchronous operation, it is possible to
skip an increment. When switching from
asynchronous to synchronous operation,
it is possible to produce an additional
increment.
6.5.1READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will ensure a valid
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers,
while the register is incrementing. This may produce an
unpredictable value in the TMR1H:TMR1L register pair.
6.6Timer1 Gate
The Timer1 gate (when enabled) allows Timer1 to count
when Timer1 gate is active. Timer1 gate source is
software configurable to be the T1G pin or the output of
Comparator C2. This allows the device to directly time
external events using T1G
Comparator C2. See the CM2CON1 register
(Register 8-3) for selecting the Timer1 gate source. This
feature can simplify the software for a Delta-Sigma A/D
converterand many other applications.
be set to use either T1G
Timer1 gate source. See the CM2CON1
register (Register 8-3) for more information on selecting the Timer1 gate source.
Timer1 gate can be inverted using the T1GINV bit of
the T1CON register, whether it originates from the T1G
pin or Comparator C2 output. This configures Timer1 to
measure either the active-high or active-low time
between events.
or C2OUT as the
6.7Timer1 Interrupt
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 interrupt flag bit of the PIR1 register is
set. To enable the interrupt on rollover, you must set
these bits:
• TMR1ON bit of the T1CON register
• TMR1IE bit of the PIE1 register
• PEIE bit of the INTCON register
• GIE bit of the INTCON register
The interrupt is cleared by clearing the TMR1IF bit in
the Interrupt Service Routine.
Note:The TMR1H:TTMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts.
6.8Timer1 Operation During Sleep
Timer1 can only operate during Sleep when setup in
Asynchronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To set up the timer to wake the device:
• TMR1ON bit of the T1CON register must be set
• TMR1IE bit of the PIE1 register must be set
• PEIE bit of the INTCON register must be set
• T1SYNC
• TMR1CS bit of the T1CON register must be set
• T1OSCEN bit of the T1CON register (can be set)
The device will wake-up on an overflow and execute
the next instructions. If the GIE bit of the INTCON
register is set, the device will call the Interrupt Service
Routine (0004h).
bit of the T1CON register must be set
In Compare mode, an event is triggered when the value
CCPR1H:CCPR1L register pair matches the value in
the TMR1H:TMR1L register pair. This event can be a
Special Event Trigger.
For more information, see Section 11.0 “Enhanced
Capture/Compare/PWM Module”.
6.10ECCP Special Event Trigger
When the ECCP is configured to trigger a special
event, the trigger will clear the TMR1H:TMR1L register
pair. This special event does not cause a Timer1 interrupt. The ECCP module may still be configured to
generate a ECCP interrupt.
In this mode of operation, the CCPR1H:CCPR1L
register pair becomes the period register for Timer1.
Timer1 should be synchronized to the F
the Special Event Trigger. Asynchronous operation of
Timer1 can cause a Special Event Trigger to be
missed.
In the event that a write to TMR1H or TMR1L coincides
with a Special Event Trigger from the ECCP, the write
will take precedence.
For more information, see Section 11.2.4 “SpecialEvent Trigger”.
OSC to utilize
6.11Comparator Synchronization
The same clock used to increment Timer1 can also be
used to synchronize the comparator output. This
feature is enabled in the Comparator module.
When using the comparator for Timer1 gate, the
comparator output should be synchronized to Timer1.
This ensures Timer1 does not miss an increment if the
comparator changes.
For more information, see Section 8.8.2
“Synchronizing Comparator C2 output to Timer1”.
6.9ECCP Capture/Compare Time Base
The ECCP module uses the TMR1H:TMR1L register
pair as the time base when operating in Capture or
Compare mode.
In Capture mode, the value in the TMR1H:TMR1L
register pair is copied into the CCPR1H:CCPR1L
register pair on a configured event.
The clock input to the Timer2 module is the system
instruction clock (F
Timer2 prescaler, which has prescale options of 1:1,
1:4 or 1:16. The output of the prescaler is then used to
increment the TMR2 register.
The values of TMR2 and PR2 are constantly compared
to determine when they match. TMR2 will increment
from 00h until it matches the value in PR2. When a
match occurs, two things happen:
• TMR2 is reset to 00h on the next increment cycle.
• The Timer2 postscaler is incremented
The match output of the Timer2/PR2 comparator is fed
into the Timer2 postscaler. The postscaler has
postscale options of 1:1 to 1:16 inclusive. The output of
the Timer2 postscaler is used to set the TMR2IF
interrupt flag bit in the PIR1 register.
OSC/4). The clock is fed into the
The TMR2 and PR2 registers are both fully readable
and writable. On any Reset, the TMR2 register is set to
00h and the PR2 register is set to FFh.
Timer2 is turned on by setting the TMR2ON bit in the
T2CON register to a ‘1’. Timer2 is turned off by clearing
the TMR2ON bit to a ‘0’.
The Timer2 prescaler is controlled by the T2CKPS bits
in the T2CON register. The Timer2 postscaler is
controlled by the TOUTPS bits in the T2CON register.
The prescaler and postscaler counters are cleared
when:
Comparators are used to interface analog circuits to a
digital circuit by comparing two analog voltages and
providing a digital indication of their relative magnitudes.
The comparators are very useful mixed signal building
blocks because they provide analog functionality
independent of program execution. The Analog
Comparator module includes the following features:
• Independent comparator control
• Programmable input selection
• Comparator output is available internally/externally
• Programmable output polarity
• Interrupt-on-change
• Wake-up from Sleep
•PWM shutdown
• Timer1 gate (count enable)
• Output synchronization to Timer1 clock input
•SR Latch
• Programmable and fixed voltage reference
Note:Only Comparator C2 can be linked to
Timer1.
8.1 Comparator Overview
FIGURE 8-1:SINGLE COMPARATOR
VIN+
IN-
V
VIN-
VIN+
Output
Note:The black areas of the output of the
comparator represents the uncertainty
due to input offsets and response time.
+
–
Output
A single comparator is shown in Figure 8-1 along with
the relationship between the analog input levels and
the digital output. When the analog voltage at VIN+ is
less than the analog voltage at V
comparator is a digital low level. When the analog
voltage at VIN+ is greater than the analog voltage at
IN-, the output of the comparator is a digital high level.
Each comparator has a separate control and
Configuration register: CM1CON0 for Comparator C1
and CM2CON0 for Comparator C2. In addition,
Comparator C2 has a second control register,
CM2CON1, for controlling the interaction with Timer1 and
simultaneous reading of both comparator outputs.
The CM1CON0 and CM2CON0 registers (see Registers
8-1 and 8-2, respectively) contain the control and Status
bits for the following:
• Enable
• Input selection
• Reference selection
•Output selection
• Output polarity
8.2.1COMPARATOR ENABLE
Setting the CxON bit of the CMxCON0 register enables
the comparator for operation. Clearing the CxON bit
disables the comparator resulting in minimum current
consumption.
8.2.2COMPARATOR INPUT SELECTION
The CxCH<1:0> bits of the CMxCON0 register direct
one of four analog input pins to the comparator
inverting input.
Note:To use CxIN+ and C12INx- pins as analog
inputs, the appropriate bits must be set in
the ANSEL register and the corresponding
TRIS bits must also be set to disable the
output drivers.
8.2.3COMPARATOR REFERENCE
SELECTION
Setting the CxR bit of the CMxCON0 register directs an
internal voltage reference or an analog input pin to the
non-inverting input of the comparator. See Section 8.9“Comparator SR Latch” for more information on the
Internal Voltage Reference module.
8.2.4COMPARATOR OUTPUT
SELECTION
The output of the comparator can be monitored by
reading either the CxOUT bit of the CMxCON0 register
or the MCxOUT bit of the CM2CON1 register. In order
to make the output available for an external connection,
the following conditions must be true:
• CxOE bit of the CMxCON0 register must be set
• Corresponding TRIS bit must be cleared
• CxON bit of the CMxCON0 register must be set
Note 1: The CxOE bit overrides the PORT data
latch. Setting the CxON has no impact on
the port override.
2: The internal output of the comparator is
latched with each instruction cycle.
Unless otherwise specified, external
outputs are not latched.
8.2.5COMPARATOR OUTPUT POLARITY
Inverting the output of the comparator is functionally
equivalent to swapping the comparator inputs. The
polarity of the comparator output can be inverted by
setting the CxPOL bit of the CMxCON0 register.
Clearing the CxPOL bit results in a non-inverted output.
Table 8-1 shows the output state versus input
conditions, including polarity control.
TABLE 8-1:COMPARATOR OUTPUT
STATE VS. INPUT CONDITIONS
Input ConditionCxPOLCxOUT
CxV
IN- > CxVIN+00
CxVIN- < CxVIN+01
IN- > CxVIN+11
CxV
CxVIN- < CxVIN+10
8.3Comparator Response Time
The comparator output is indeterminate for a period of
time after the change of an input source or the selection
of a new reference voltage. This period is referred to as
the response time. The response time of the
comparator differs from the settling time of the voltage
reference. Therefore, both of these times must be
considered when determining the total response time
to a comparator input change. See the Comparator and
Voltage Reference Specifications in Section 17.0“Electrical Specifications” for more details.
The comparator interrupt flag can be set whenever
there is a change in the output value of the comparator.
Changes are recognized by means of a mismatch
circuit which consists of two latches and an exclusiveor gate (see Figure 8-2 and Figure 8-3). One latch is
updated with the comparator output level when the
CMxCON0 register is read. This latch retains the value
until the next read of the CMxCON0 register or the
occurrence of a Reset. The other latch of the mismatch
circuit is updated on every Q1 system clock. A
mismatch condition will occur when a comparator
output change is clocked through the second latch on
the Q1 clock cycle. At this point the two mismatch
latches have opposite output levels which is detected
by the exclusive-or gate and fed to the interrupt
circuitry. The mismatch condition persists until either
the CMxCON0 register is read or the comparator
output returns to the previous state.
Note 1: A write operation to the CMxCON0
register will also clear the mismatch
condition because all writes include a read
operation at the beginning of the write
cycle.
2: Comparator interrupts will operate correctly
regardless of the state of CxOE.
The comparator interrupt is set by the mismatch edge
and not the mismatch level. This means that the interrupt flag can be reset without the additional step of
reading or writing the CMxCON0 register to clear the
mismatch registers. When the mismatch registers are
cleared, an interrupt will occur upon the comparator’s
return to the previous state, otherwise no interrupt will
be generated.
Software will need to maintain information about the
status of the comparator output, as read from the
CMxCON0 register, or CM2CON1 register, to determine
the actual change that has occurred.
The CxIF bit of the PIR1 register is the comparator
interrupt flag. This bit must be reset in software by
clearing it to ‘0’. Since it is also possible to write a '1' to
this register, an interrupt can be generated.
The CxIE bit of the PIE1 register and the PEIE and GIE
bits of the INTCON register must all be set to enable
comparator interrupts. If any of these bits are cleared,
the interrupt is not enabled, although the CxIF bit of the
PIR1 register will still be set if an interrupt condition
occurs.
FIGURE 8-4:COMPARATOR
INTERRUPT TIMING W/O
CMxCON0 READ
Q1
Q3
CxIN+
Cxout
Set CxIF (edge)
CxIF
TRT
reset by software
FIGURE 8-5:COMPARATOR
INTERRUPT TIMING WITH
CMxCON0 READ
Q1
Q3
CxIN+
Cxout
Set CxIF (edge)
CxIF
cleared by CMxCON0 read
Note 1: If a change in the CMxCON0 register
2: When either comparator is first enabled,
TRT
reset by software
(CxOUT) should occur when a read
operation is being executed (start of the
Q2 cycle), then the CxIF of the PIR1
register interrupt flag may not get set.
bias circuitry in the Comparator module
may cause an invalid output from the
comparator until the bias circuitry is
stable. Allow about 1 μs for bias settling
then clear the mismatch condition and
interrupt flags before enabling
comparator interrupts.
The comparator, if enabled before entering Sleep mode,
remains active during Sleep. The additional current
consumed by the comparator is shown separately in the
Section 17.0 “Electrical Specifications”. If the
comparator is not used to wake the device, power
consumption can be minimized while in Sleep mode by
turning off the comparator. Each comparator is turned off
by clearing the CxON bit of the CMxCON0 register.
A change to the comparator output can wake-up the
device from Sleep. To enable the comparator to wake
the device from Sleep, the CxIE bit of the PIE1 register
and the PEIE bit of the INTCON register must be set.
The instruction following the Sleep instruction always
executes following a wake from Sleep. If the GIE bit of
the INTCON register is also set, the device will then
execute the Interrupt Service Routine.
8.6Effects of a Reset
A device Reset forces the CMxCON0 and CM2CON1
registers to their Reset states. This forces both
comparators and the voltage references to their OFF
states.