Microchip Technology PIC16C62B/72A User Manual
PIC16C72A
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/V
REF
RA4/T0CKI
RA5/SS/AN4
V
SS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
V
DD
VSS
RC7
RC6
RC5/SDO
RC4/SDI/SDA
• 1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SDIP, SOIC, SSOP, Windowed CERDIP
PIC16C62B/72A
28-Pin 8-Bit CMOS Microcontrollers
Microcontroller Core Features:
• High-performance RISC CPU
• Only 35 single word instructions to learn
• All single cycle instructions except for program
branches, which are two cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• 2K x 14 words of Program Memory,
128 x 8 bytes of Data Memory (RAM)
• Interrupt capability
• Eight level deep hardware stack
• Direct, indirect, and relative addressing modes
• Power-on Reset (POR)
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Brown-out detection circuitry for
Brown-out Reset (BOR)
• Programmable code-protection
• Power saving SLEEP mode
• Selectable oscillator options
• Low-power, high-speed CMOS EPROM
technology
• Fully static design
• In-Circuit Serial Programming(ICSP)
• Wide operating voltage range: 2.5V to 5.5V
• High Sink/Source Current 25/25 mA
• Commercial, Industrial and Extended temperature
ranges
• Low-power consumption:
- < 2 mA @ 5V, 4 MHz
- 22.5 A typical @ 3V, 32 kHz
-< 1 A typical standby current
Pin Diagram
Peripheral Features:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be incremented during sleep via external
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Capture, Compare, PWM module
• Capture is 16-bit, max. resolution is 12.5 ns,
Compare is 16-bit, max. resolution is 200 ns,
PWM maximum resolution is 10-bit
• 8-bit multi-channel Analog-to-Digital converter
• Synchronous Serial Port (SSP) with Enhanced
SPI and I
2C
1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 1
PIC16C62B/72A
PIC16C62B
MCLR/VPP
RA0
RA1
RA2
RA3
RA4/T0CKI
RA5/SS
V
SS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
V
DD
VSS
RC7
RC6
RC5/SDO
RC4/SDI/SDA
• 1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SDIP, SOIC, SSOP, Windowed CERDIP
Pin Diagrams
Key Features
PIC® Mid-Range Reference Manual (DS33023)
PIC16C62B PIC16C72A
Operating Frequency DC - 20 MHz DC - 20 MHz
Resets (and Delays) POR, BOR (PWRT, OST) POR, BOR (PWRT, OST)
Program Memory (14-bit words) 2K 2K
Data Memory (bytes) 128 128
Interrupts 7 8
I/O Ports Ports A,B,C Ports A,B,C
Timers 3 3
Capture/Compare/PWM modules 1 1
Serial Communications SSP SSP
8-bit Analog-to-Digital Module — 5 input channels
DS35008C-page 2 Preliminary 1998-2013 Microchip Technology Inc.
PIC16C62B/72A
Table of Contents
1.0 Device Overview .................................................................................................................................................... 5
2.0 Memory Organization............................................................................................................................................. 7
3.0 I/O Ports ............................................................................................................................................................... 19
4.0 Timer0 Module ..................................................................................................................................................... 25
5.0 Timer1 Module ..................................................................................................................................................... 27
6.0 Timer2 Module ..................................................................................................................................................... 31
7.0 Capture/Compare/PWM (CCP) Module ............................................................................................................... 33
8.0 Synchronous Serial Port (SSP) Module ............................................................................................................... 39
9.0 Analog-to-Digital Converter (A/D) Module............................................................................................................ 49
10.0 Special Features of the CPU................................................................................................................................ 55
11.0 Instruction Set Summary ...................................................................................................................................... 67
12.0 Development Support........................................................................................................................................... 75
13.0 Electrical Characteristics...................................................................................................................................... 81
14.0 DC and AC Characteristics Graphs and Tables................................................................................................. 103
15.0 Packaging Information........................................................................................................................................ 105
Appendix A: Revision History ................................................................................................................................... 111
Appendix B: Conversion Considerations .................................................................................................................. 111
Appendix C: Migration from Base-line to Mid-Range Devices .................................................................................. 112
Index ...........................................................................................................................................................................113
On-Line Support.......................................................................................................................................................... 117
Reader Response....................................................................................................................................................... 118
PIC16C62B/72A Product Identification System .......................................................................................................... 119
To Our Valued Customers
Most Current Data Sheet
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An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended
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We appreciate your assistance in making this a better document.
1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 3
PIC16C62B/72A
NOTES:
DS35008C-page 4 Preliminary 1998-2013 Microchip Technology Inc.
PIC16C62B/72A
EPROM
Program
Memory
13
Data Bus
8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
RAM
File
Registers
Direct Addr
7
RAM Addr
(1)
9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
MCLR
VDD, VSS
PORTA
PORTB
PORTC
RB0/INT
RB7:RB1
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6
RC7
8
8
Brown-out
Reset
Note 1: Higher order bits are from the STATUS register.
2: The A/D module is not available on the PIC16C62B.
CCP1
Synchronous
A/D
(2)
Timer0 Timer1 Timer2
Serial Port
RA4/T0CKI
RA5/SS
/AN4
(2)
RA3/AN3/VREF
(2)
RA2/AN2
(2)
RA1/AN1
(2)
RA0/AN0
(2)
8
3
2K x 14
128 x 8
1.0 DEVICE OVERVIEW
This document contains device-specific information.
Additional information may be found in the PIC
Mid-Range Reference Manual, (DS33023), which may
be obtained from your local Microchip Sales Representative or downloaded from the Microchip website. The
Reference Manual should be considered a complementary document to this data sheet, and is highly rec-
FIGURE 1-1: PIC16C62B/PIC16C72A BLOCK DIAGRAM
®
MCU
ommended reading for a better understanding of the
device architecture and operation of the peripheral
modules.
There are two devices (PIC16C62B, PIC16C72A) covered by this datasheet. The PIC16C62B does not have
the A/D module implemented.
Figure 1-1 is the block diagram for both devices. The
pinouts are listed in Table 1-1.
1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 5
PIC16C62B/72A
TABLE 1-1 PIC16C62B/PIC16C72A PINOUT DESCRIPTION
Pin Name
DIP
Pin#
OSC1/CLKIN 9 9 I
SOIC
Pin#
I/O/P
Typ e
Buffer
Typ e
ST/CMOS
Description
(3)
Oscillator crystal input/external clock source input.
OSC2/CLKOUT 10 10 O — Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, the OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.
MCLR
/VPP
1 1 I/P ST Master clear (reset) input or programming voltage input. This
pin is an active low reset to the device.
PORTA is a bi-directional I/O port.
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/V
(4)
(4)
(4)
(4)
REF
2 2 I/O TTL RA0 can also be analog input 0
3 3 I/O TTL RA1 can also be analog input 1
4 4 I/O TTL RA2 can also be analog input 2
5 5 I/O TTL RA3 can also be analog input 3 or analog reference voltage
RA4/T0CKI 6 6 I/O ST RA4 can also be the clock input to the Timer0 module.
Output is open drain type.
RA5/SS/
AN4
(4)
7 7 I/O TTL RA5 can also be analog input 4 or the slave select for the
synchronous serial port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
RB0/INT 21 21 I/O TTL/ST
(1)
RB0 can also be the external interrupt pin.
RB1 22 22 I/O TTL
RB2 23 23 I/O TTL
RB3 24 24 I/O TTL
RB4 25 25 I/O TTL Interrupt on change pin.
RB5 26 26 I/O TTL Interrupt on change pin.
RB6 27 27 I/O TTL/ST
RB7 28 28 I/O TTL/ST
(2)
(2)
Interrupt on change pin. Serial programming clock.
Interrupt on change pin. Serial programming data.
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI 11 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1
clock input.
RC1/T1OSI 12 12 I/O ST RC1 can also be the Timer1 oscillator input.
RC2/CCP1 13 13 I/O ST RC2 can also be the Capture1 input/Compare1 output/
PWM1 output.
RC3/SCK/SCL 14 14 I/O ST RC3 can also be the synchronous serial clock input/output
for both SPI and I
RC4/SDI/SDA 15 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or
data I/O (I
2
C mode).
2
C modes.
RC5/SDO 16 16 I/O ST RC5 can also be the SPI Data Out (SPI mode).
RC6 17 17 I/O ST
RC7 18 18 I/O ST
SS 8, 19 8, 19 P — Ground reference for logic and I/O pins.
V
DD 20 20 P — Positive supply for logic and I/O pins.
V
Legend: I = input O = output I/O = input/output P = power or program
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
4: The A/D module is not available on the PIC16C62B.
DS35008C-page 6 Preliminary 1998-2013 Microchip Technology Inc.
PIC16C62B/72A
PC<12:0>
13
0000h
0004h
0005h
07FFh
0800h
1FFFh
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
On-chip Program
Memory
CALL, RETURN
RETFIE, RETLW
User Memory
Space
2.0 MEMORY ORGANIZATION
There are two memory blocks in each of these microcontrollers. Each block (Program Memory and Data
Memory) has its own bus, so that concurrent access
can occur.
Additional information on device memory may be found
in the PICmicro Mid-Range Reference Manual,
(DS33023).
2.1 Program Memory Organization
The PIC16C62B/72A devices have a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. Each device has 2K x 14 words of program memory. Accessing a location above 07FFh will
cause a wraparound.
The reset vector is at 0000h and the interrupt vector is
at 0004h.
FIGURE 2-1: PROGRAM MEMORY MAP
AND STACK
1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 7
PIC16C62B/72A
Unimplemented data memory locations,
read as '0'.
Note 1: Not a physical register.
2: These registers are not implemented on the
PIC16C62B, read as '0'.
File
Address
File
Address
00h INDF
(1)
INDF
(1)
80h
01h TMR0 OPTION_REG 81h
02h PCL PCL 82h
0 3 h S TATU S S TAT U S 8 3 h
04h FSR FSR 84h
05h PORTA TRISA 85h
06h PORTB TRISB 86h
07h PORTC TRISC 87h
08h
— — 88h
09h
— — 89h
0Ah PCLATH PCLATH 8Ah
0Bh INTCON INTCON 8Bh
0Ch PIR1 PIE1 8Ch
0Dh
— — 8Dh
0Eh TMR1L PCON 8Eh
0Fh TMR1H
— 8Fh
10h T1CON
— 90h
11h TMR2
— 91h
12h T2CON PR2 92h
13h SSPBUF SSPADD 93h
14h SSPCON SSPSTAT 94h
15h CCPR1L
— 95h
16h CCPR1H
— 96h
17h CCP1CON
— 97h
18h
— — 98h
19h
— — 99h
1Ah
— — 9Ah
1Bh
— — 9Bh
1Ch
— — 9Ch
1Dh
— — 9Dh
1Eh ADRES
(2)
— 9Eh
1Fh ADCON0
(2)
ADCON1
(2)
9Fh
20h
General
Purpose
Registers
General
Purpose
Registers
A0h
BFh
—
C0h
—
7Fh
—
FFh
Bank 0 Bank 1
2.2 Data Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 and RP0 are the
bank select bits.
(1)
RP1
= 00 Bank0
= 01 Bank1
= 10 Bank2 (not implemented)
= 11 Bank3 (not implemented)
Note 1: Maintain this bit clear to ensure upward compati-
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some “high use” Special Function
Registers from one bank may be mirrored in another
bank for code reduction and quicker access.
2.2.1 GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly, or indirectly through the File Select Register FSR
(Section 2.5).
DS35008C-page 8 Preliminary 1998-2013 Microchip Technology Inc.
RP0 (STATUS<6:5>)
bility with future products.
FIGURE 2-2: REGISTER FILE MAP
PIC16C62B/72A
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers can be classified into
two sets; core (CPU) and peripheral. Those registers
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
TABLE 2-1 SPECIAL FUNCTION REGISTER SUMMARY
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Val ue on:
POR,
BOR
Bank 0
00h INDF
01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu
02h PCL
03h STATUS
04h FSR
05h PORTA
06h PORTB
07h PORTC
08h-09h — Unimplemented — —
0Ah PCLATH
0Bh INTCON
0Ch PIR1
0Dh — Unimplemented — —
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
12h T2CON
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON
18h-1Dh — Unimplemented — —
1Eh ADRES
1Fh ADCON0
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0',
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents
3: A/D not implemented on the PIC16C62B, maintain as ’0’.
4: Other (non power-up) resets include: external reset through MCLR
5: The IRP and RP1 bits are reserved. Always maintain these bits clear.
6: On any device reset, these pins are configured as inputs.
7: This is the value that will be in the port output latch.
(1)
(1)
(1)
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
(1)
(6,7)
(6,7)
(6,7)
(1,2)
(1)
(3)
(3)
(5)
IRP
Indirect data memory address pointer xxxx xxxx uuuu uuuu
— — PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000
PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu
— — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
—ADIF
— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
— — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
A/D Result Register xxxx xxxx uuuu uuuu
ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON0000 00-0 0000 00-0
RP1
(5)
RP0 TO PD ZDCC0001 1xxx 000q quuu
(3)
— — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
Shaded locations are unimplemented, read as '0'.
are transferred to the upper byte of the program counter.
and the Watchdog Timer Reset.
Value on all
other resets
(4)
1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 9
PIC16C62B/72A
TABLE 2-1 SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 1
80h INDF
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h PCL
83h STATUS
84h FSR
85h TRISA
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
88h-89h — Unimplemented — —
8Ah PCLATH
8Bh INTCON
8Ch PIE1
8Dh — Unimplemented — —
8Eh PCON — — — — — —PORBOR ---- --qq ---- --uu
8Fh-91h — Unimplemented — —
92h PR2 Timer2 Period Register 1111 1111 1111 1111
93h SSPADD Synchronous Serial Port (I
94h SSPSTAT SMP CKE D/A
95h-9Eh — Unimplemented — —
9Fh ADCON1
(1)
(1)
(1)
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
(1)
(1,2)
(1)
(3)
(5)
IRP
Indirect data memory address pointer xxxx xxxx uuuu uuuu
— — PORTA Data Direction Register --11 1111 --11 1111
— — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
—ADIE
— — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
RP1
(5)
RP0 TO PD ZDCC0001 1xxx 000q quuu
(3)
— — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
2
C mode) Address Register 0000 0000 0000 0000
PSR/WUA B F 0000 0000 0000 0000
Val ue on:
POR,
BOR
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0',
Shaded locations are unimplemented, read as '0'.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents
are transferred to the upper byte of the program counter.
3: A/D not implemented on the PIC16C62B, maintain as ’0’.
4: Other (non power-up) resets include: external reset through MCLR
and the Watchdog Timer Reset.
5: The IRP and RP1 bits are reserved. Always maintain these bits clear.
6: On any device reset, these pins are configured as inputs.
7: This is the value that will be in the port output latch.
Value on all
other resets
(4)
DS35008C-page 10 Preliminary 1998-2013 Microchip Technology Inc.
PIC16C62B/72A
2.2.2.1 STATUS REGISTER
The STATUS register, shown in Register 2-1, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, the write to these three bits is disabled. These bits are set or cleared according to the
device logic. The TO
result of an instruction with the STATUS register as
destination may be different than intended.
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
and PD bits are not writable. The
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect the Z, C or DC bits from the STATUS register. For
other instructions, not affecting any status bits, see the
"Instruction Set Summary."
Note 1: The IRP and RP1 bits are reserved. Main-
tain these bits clear to ensure upward
compatibility with future products.
Note 2: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF
instructions.
REGISTER 2-1: STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD Z DC C R = Readable bit
bit7 bit0
bit 7: IRP: Register Bank Select bit (used for indirect addressing)
(reserved, maintain clear)
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes
Note: RP1 is reserved, maintain clear
bit 4: TO
bit 3: PD
bit 2: Z: Zero bit
bit 1: DC: Digit carry/borrow
bit 0: C: Carry/borrow
: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow, the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow, the polarity is reversed)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
Note: For borrow
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of
the source register.
1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 11
, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
PIC16C62B/72A
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value TMR0 Rate WDT Rate
2.2.2.2 OPTION_REG REGISTER
The OPTION_REG register is a readable and writable
register, which contains various control bits to configure
the TMR0 prescaler/WDT postscaler (single assignable register known as the prescaler), the External INT
Interrupt, TMR0 and the weak pull-ups on PORTB.
REGISTER 2-2: OPTION_REG REGISTER (ADDRESS 81h)
R/W-1 R/W-1 R /W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU
bit7 bit0
bit 7: RBPU: PORTB Pull-up Enable bit
bit 6: INTEDG: Interrupt Edge Select bit
bit 5: T0CS: TMR0 Clock Source Select bit
bit 4: T0SE: TMR0 Source Edge Select bit
bit 3: PSA: Prescaler Assignment bit
bit 2-0: PS2:PS0: Prescaler Rate Select bits
INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled for all PORTB inputs
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
Note: To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
W = Writable bit
- n = Value at POR reset
DS35008C-page 12 Preliminary 1998-2013 Microchip Technology Inc.
PIC16C62B/72A
2.2.2.3 INTCON REGISTER
The INTCON Register is a readable and writable register, which contains various interrupt enable and flag
bits for the TMR0 register overflow, RB Port change
and External RB0/INT pin interrupts.
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
REGISTER 2-3: INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0 R/W-0 R /W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF R = Readable bit
bit7 bit0
bit 7: GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6: PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5: T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4: IINTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3: RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2: T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (software must clear bit)
0 = TMR0 register did not overflow
bit 1: INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (software must clear bit)
0 = The RB0/INT external interrupt did not occur
bit 0: RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 input pins have changed state (clear by reading PORTB)
0 = None of the RB7:RB4 input pins have changed state
W = Writable bit
- n = Value at POR reset
1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 13
PIC16C62B/72A
2.2.2.4 PIE1 REGISTER
This register contains the individual enable bits for the
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
peripheral interrupts.
REGISTER 2-4: PIE1 REGISTER (ADDRESS 8Ch)
U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— ADIE
bit7 bit0
bit 7: Unimplemented: Read as ‘0’
bit 6: ADIE
bit 5-4: Unimplemented: Read as ‘0’
bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit
bit 2: CCP1IE: CCP1 Interrupt Enable bit
bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit
(1)
— — SSPIE CCP1IE TMR2IE TMR1IE R = Readable bit
(1)
: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
Note 1: The PIC16C62B does not have an A/D module. This bit location is reserved on these devices. Always maintain this
bit clear.
DS35008C-page 14 Preliminary 1998-2013 Microchip Technology Inc.
PIC16C62B/72A
2.2.2.5 PIR1 REGISTER
This register contains the individual flag bits for the
Peripheral interrupts.
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
REGISTER 2-5: PIR1 REGISTER (ADDRESS 0Ch)
U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— ADIF
bit7 bit0
bit 7: Unimplemented: Read as ‘0’
bit 6: ADIF
bit 5-4: Unimplemented: Read as ‘0’
bit 3: SSPIF: Synchronous Serial Port Interrupt Flag bit
bit 2: CCP1IF: CCP1 Interrupt Flag bit
bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit
(1)
(1)
— — SSPIF CCP1IF TMR2IF TMR1IF R = Readable bit
: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
Note 1: The PIC16C62B does not have an A/D module. This bit location is reserved on these devices. Always maintain this
1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 15
bit clear.
PIC16C62B/72A
2.2.2.6 PCON REGISTER
The Power Control register (PCON) contains flag bits to
allow differentiation between a Power-on Reset (POR),
Brown-Out Reset (BOR) and resets from other
sources. .
Note: On Power-on Reset, the state of the BOR
bit is unknown and is not predictable.
If the BODEN bit in the configuration word
is set, the user must first set the BOR bit on
a POR, and check it on subsequent resets.
If BOR is cleared while POR remains set,
a Brown-out reset has occurred.
If the BODEN bit is clear, the BOR bit may
be ignored.
REGISTER 2-6: PCON REGISTER (ADDRESS 8Eh)
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-q
— — — — — —PORBOR R = Readable bit
bit7 bit0
bit 7-2: Unimplemented: Read as '0'
bit 1: POR
bit 0: BOR
: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
W = Writable bit
U = Unimplemented bit,
- n = Value at POR reset
read as ‘0’
DS35008C-page 16 Preliminary 1998-2013 Microchip Technology Inc.
PIC16C62B/72A
2.3 PCL and PCLATH
The program counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 13 bits
wide. The low byte is called the PCL register and is
readable and writable. The high byte is called the PCH
register. This register contains the PC<12:8> bits and
is not directly accessible. All updates to the PCH register go through the PCLATH register.
2.3.1 STACK
The stack allows any combination of up to 8 program
calls and interrupts to occur. The stack contains the
return address from this branch in program execution.
Mid-range devices have an 8 level deep hardware
stack. The stack space is not part of either program or
data space and the stack pointer is not accessible. The
PC is PUSHed onto the stack when a CALL instruction
is executed or an interrupt causes a branch. The stack
is POPed in the event of a RETURN, RETLW or a RET-
FIE instruction execution. PCLATH is not modified
when the stack is PUSHed or POPed.
After the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
2.4 Program Memory Paging
The CALL and GOTO instructions provide 11 bits of
address to allow branching within any 2K program
memory page. When doing a CALL or GOTO instruction,
the upper bit of the address is provided by
PCLATH<3>. The user must ensure that the page
select bit is programmed to address the proper program memory page. If a return from a CALL instruction
(or interrupt) is executed, the entire 13-bit PC is popped
from the stack. Therefore, manipulation of the
PCLATH<3> bit is not required for the return instructions.
1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 17
PIC16C62B/72A
Note 1: Maintain clear for upward compatibility with future products.
2: Not implemented.
Data
Memory
Indirect AddressingDirect Addressing
bank select location select
RP1:RP0 6
0
from opcode
IRP FSR register
7
0
bank select
location select
00 01 10 11
Bank 0 Bank 1 Bank 2 Bank 3
not used
FFh
80h
7Fh
00h
17Fh
100h
1FFh
180h
(1)
(1)
(2) (2)
2.5 Indirect Addressing, INDF and FSR
Registers
The INDF register is not a physical register. Addressing INDF actually addresses the register whose
address is contained in the FSR register (FSR is a
pointer
).
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although STATUS bits may be affected).
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-1.
FIGURE 2-3: DIRECT/INDIRECT ADDRESSING
EXAMPLE 2-1: HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
movlw 0x20 ;initialize pointer
movwf FSR ; to RAM
NEXT clrf INDF ;clear INDF register
incf FSR ;inc pointer
btfss FSR,4 ;all done?
goto NEXT ;NO, clear next
CONTINUE
: ;YES, continue
An effective 9-bit address is obtained by concatenating
the 8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 2-3. However, IRP is not used in the
PIC16C62B/72A.
DS35008C-page 18 Preliminary 1998-2013 Microchip Technology Inc.
PIC16C62B/72A
Data
Bus
QD
Q
CK
QD
Q
CK
QD
EN
P
N
WR
Por t
WR
TRIS
Data Latch
TRIS Latch
RD TRIS
RD PORT
V
SS
VDD
I/O pin
(1)
Note 1: I/O pins have protection diodes to VDD and
V
SS.
Analog
input
mode
TTL
input
buffer
To A/D Converter (72A only)
(72A
only)
Data
Bus
WR
PORT
WR
TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Schmitt
Trigger
input
buffer
N
V
SS
I/O pin
(1)
TMR0 clock input
QD
Q
CK
QD
Q
CK
EN
QD
EN
Note 1: I/O pin has protection diodes to VSS only.
3.0 I/O PORTS
Some I/O port pins are multiplexed with an alternate
function for the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
Additional information on I/O ports may be found in the
®
MCU Mid-Range Reference Manual, (DS33023).
PIC
3.1 PORTA and the TRISA Register
PORTA is a 6-bit wide bi-directional port. The corresponding data direction register is TRISA. Setting a
TRISA bit (=1) will make the corresponding PORTA pin
an input, i.e., put the corresponding output driver in a
hi-impedance mode. Clearing a TRISA bit (=0) will
make the corresponding PORTA pin an output, (i.e., put
the contents of the output latch on the selected pin).
The PORTA register reads the state of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read,
this value is modified, and then written to the port data
latch.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain output.
All other RA port pins have TTL input levels and full
CMOS output drivers.
Pin RA5 is multiplexed with the SSP to become the
RA5/SS
On the PIC16C72A device, other PORTA pins are multiplexed with analog inputs and analog VREF input. The
operation of each pin is selected by clearing/setting the
control bits in the ADCON1 register (A/D Control
Register1).
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
pin.
Note: On a Power-on Reset, pins with analog
functions are configured as analog inputs
with digital input buffers disabled . A digital
read of these pins will return ’0’.
FIGURE 3-1: BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
FIGURE 3-2: BLOCK DIAGRAM OF
RA4/T0CKI PIN
1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 19
PIC16C62B/72A
TABLE 3-1 PORTA FUNCTIONS
Name Bit# Buffer Function
RA0/AN0 bit0 TTL Input/output or analog input
RA1/AN1 bit1 TTL Input/output or analog input
RA2/AN2 bit2 TTL Input/output or analog input
RA3/AN3/VREF bit3 TTL Input/output or analog input
Input/output or external clock input for Timer0
RA4/T0CKI bit4 ST
Output is open drain type
RA5/SS/AN4 bit5 TTL Input/output or slave select input for synchronous serial port or analog input
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: The PIC16C62B does not implement the A/D module.
TABLE 3-2 SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
(1)
(1)
(1)
(1)
or VREF
(1)
(1)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
05h PORTA
(for PIC16C72A only)
05h PORTA
(for PIC16C62B only)
85h TRISA
9Fh ADCON1
(1)
— — RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000
— — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu
— — PORTA Data Direction Register --11 1111 --11 1111
— — — — —PCFG2PCFG1PCFG0---- -000 ---- -000
Value on
POR,
BOR
Value on all
other resets
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
Note 1: The PIC16C62B does not implement the A/D module. Maintain this register clear.
DS35008C-page 20 Preliminary 1998-2013 Microchip Technology Inc.
PIC16C62B/72A
Data Latch
RBPU
(2)
P
V
DD
QD
CK
QD
CK
QD
EN
Data Bus
WR Port
WR TRIS
RD TRIS
RD Port
weak
pull-up
RD Port
RB0/INT
I/O
pin
(1)
TTL
Input
Buffer
Note 1: I/O pins have diode protection to V
DD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU
bit (OPTION_REG<7>).
Schmitt Trigger
Buffer
TRIS Latch
Data Latch
From other
RBPU
(2)
P
V
DD
I/O
QD
CK
QD
CK
QD
EN
QD
EN
Data Bus
WR Port
WR TRIS
Set RBIF
TRIS Latch
RD TRIS
RD Port
RB7:RB4 pins
weak
pull-up
RD Port
Latch
TTL
Input
Buffer
pin
(1)
Note 1: I/O pins have diode protection to VDD and VSS.
ST
Buffer
RB7:RB6 in serial programming mode
Q3
Q1
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU
bit (OPTION_REG<7>).
3.2 PORTB and the TRISB Register
PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a
TRISB bit (=1) will make the corresponding PORTB pin
an input, (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISB bit (=0) will
make the corresponding PORTB pin an output, (i.e.,
put the contents of the output latch on the selected pin).
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU
(OPTION_REG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are disabled on a Power-on Reset.
FIGURE 3-3: BLOCK DIAGRAM OF
RB3:RB0 PINS
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e. any RB7:RB4 pin configured as an output is excluded from the interrupt on
change comparison). The input pins (of RB7:RB4) are
compared with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the interrupt in the following manner:
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
RB0/INT is an external interupt pin and is configured
using the INTEDG bit (OPTION_REG<6>). RB0/INT is
discussed in detail in Section 10.10.1.
1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 21
FIGURE 3-4: BLOCK DIAGRAM OF
RB7:RB4 PINS
PIC16C62B/72A
TABLE 3-3 PORTB FUNCTIONS
Name Bit# Buffer Function
RB0/INT bit0 TTL/ST
RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up.
RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up.
RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up.
RB4 bit4 TTL Input/output pin (with interrupt on change).
RB5 bit5 TTL Input/output pin (with interrupt on change).
RB6 bit6 TTL/ST
RB7 bit7 TTL/ST
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
TABLE 3-4 SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
(1)
Input/output pin or external interrupt input.
Internal software programmable weak pull-up.
Internal software programmable weak pull-up.
Internal software programmable weak pull-up.
(2)
Input/output pin (with interrupt on change).
Internal software programmable weak pull-up. Serial programming clock.
(2)
Input/output pin (with interrupt on change).
Internal software programmable weak pull-up. Serial programming data.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
81h OPTION_REG RBPU
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Value on:
POR,
BOR
Value on all
other resets
DS35008C-page 22 Preliminary 1998-2013 Microchip Technology Inc.
3.3 PORTC and the TRISC Register
PORT/PERIPHERAL Select
(2)
Data Bus
WR
PORT
WR
TRIS
RD
Data Latch
TRIS Latch
RD TRIS
Schmitt
Trigger
QD
Q
CK
QD
EN
Peripheral Data Out
0
1
QD
Q
CK
P
N
V
DD
VSS
PORT
Peripheral
OE
(3)
Peripheral input
I/O
pin
(1)
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral select signal selects between port
data and peripheral output.
3: Peripheral OE (output enable) is only activated if
peripheral select is active.
PORTC is an 8-bit wide bi-directional port. The corresponding data direction register is TRISC. Setting a
TRISC bit (=1) will make the corresponding PORTC pin
an input, (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISC bit (=0) will
make the corresponding PORTC pin an output, (i.e.,
put the contents of the output latch on the selected pin).
PORTC is multiplexed with several peripheral functions
(Table 3-5). PORTC pins have Schmitt Trigger input
buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override maybe
in effect while the peripheral is enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISC as
destination should be avoided. The user should refer to
the corresponding peripheral section for the correct
TRIS bit settings.
PIC16C62B/72A
FIGURE 3-5: PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE)
1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 23
PIC16C62B/72A
TABLE 3-5 PORTC FUNCTIONS
bit0
Buffer
Function
Typ e
ST Input/output port pin or Timer1 oscillator output/Timer1 clock input Yes
output
RC3 can also be the synchronous serial clock for both SPI and I
modes.
2
RC4 can also be the SPI Data In (SPI mode) or data I/O (I
C mode).
Name Bit#
RC0/T1OSO/T1CKI
RC1/T1OSI bit1 ST Input/output port pin or Timer1 oscillator input Yes
RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/PWM1
RC3/SCK/SCL bit3 ST
RC4/SDI/SDA bit4 ST
RC5/SDO bit5 ST Input/output port pin or Synchronous Serial Port data output No
RC6 bit6 ST Input/output port pin No
RC7 bit7 ST Input/output port pin No
Legend: ST = Schmitt Trigger input
2
C
TRISC
Override
No
No
No
TABLE 3-6 SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Value on:
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged.
POR,
BOR
Value on all
other resets
DS35008C-page 24 Preliminary 1998-2013 Microchip Technology Inc.
PIC16C62B/72A
Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>).
2: The prescaler is shared with Watchdog Timer (refer to Figure 4-2 for detailed block diagram).
RA4/T0CKI
T0SE
0
1
1
0
pin
T0CS
FOSC/4
Programmable
Prescaler
Sync with
Internal
clocks
TMR0
PSout
(T
CY delay)
PSout
Data Bus
8
PSA
PS2, PS1, PS0
Set interrupt
flag bit T0IF
on overflow
3
4.0 TIMER0 MODULE
The Timer0 module timer/counter has the following features:
• 8-bit timer/counter
- Read and write
- INT on overflow
• 8-bit software programmable prescaler
• INT or EXT clock select
- EXT clock edge select
Figure 4-1 is a simplified block diagram of the Timer0
module.
Additional information on timer modules is available in
the PIC
(DS33023).
4.1 Timer0 Operation
Timer0 can operate as a timer or as a counter.
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In counter mode, Timer0 will
increment either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the Timer0 Source Edge Select bit T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are
discussed below.
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (T
incrementing of Timer0 after synchronization.
®
MCU Mid-Range Reference Manual,
OSC). Also, there is a delay in the actual
Additional information on external clock requirements
is available in the Electrical Specifications section of
this manual, and in the PIC
®
MCU Mid-Range Refer-
ence Manual, (DS33023).
4.2 Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer, respectively (Figure 4-2). For simplicity, this
counter is being referred to as “prescaler” throughout
this data sheet. There is only one prescaler available
which is shared between the Timer0 module and the
Watchdog Timer. A prescaler assignment for the
Timer0 module means that there is no prescaler for the
Watchdog Timer, and vice-versa.
The prescaler is not readable or writable.
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
determine the prescaler assignment and prescale ratio.
Clearing bit PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.
Setting bit PSA will assign the prescaler to the Watchdog Timer (WDT). When the prescaler is assigned to
the WDT, prescale values of 1:1, 1:2, ..., 1:128 are
selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,
BSF 1,x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the WDT.
Note: Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment or ratio.
FIGURE 4-1: TIMER0 BLOCK DIAGRAM
1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 25
PIC16C62B/72A
RA4/T0CKI
T0SE
pin
M
U
X
CLKOUT (= Fosc/4)
SYNC
2
T
CY
TMR0 reg
8-bit Prescaler
8 - to - 1MUX
M
U
X
M U X
Watchdog
Timer
PSA
0
1
0
1
WDT
Time-out
PS2:PS0
8
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
PSA
WDT Enable bit
M
U
X
0
1
0
1
Data Bus
Set flag bit T0IF
on Overflow
8
PSA
T0CS
Prescaler
4.2.1 SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software control, (i.e., it can be changed “on-the-fly” during program
execution).
Note: To avoid an unintended device RESET, a
specific instruction sequence (shown in the
®
MCU Mid-Range Reference Manual,
PIC
DS33023) must be executed when changing the prescaler assignment from Timer0
4.3 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP since the timer is shut off during SLEEP.
to the WDT. This sequence must be followed even if the WDT is disabled.
FIGURE 4-2: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
TABLE 4-1 REGISTERS ASSOCIATED WITH TIMER0
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu
0Bh,8Bh INTCON GIE
81h OPTION_REG
85h TRISA
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
DS35008C-page 26 Preliminary 1998-2013 Microchip Technology Inc.
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
— — PORTA Data Direction Register --11 1111 --11 1111
PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
Val ue o n:
POR,
BOR
Value on all
other resets
PIC16C62B/72A
5.0 TIMER1 MODULE
The Timer1 module timer/counter has the following features:
• 16-bit timer/counter
• Readable and writable
• Internal or external clock select
• Interrupt on overflow from FFFFh to 0000h
• Reset from CCP module trigger
Timer1 has a control register, shown in Register 5-1.
Timer1 can be enabled/disabled by setting/clearing
control bit TMR1ON (T1CON<0>).
Figure 5-1 is a simplified block diagram of the Timer1
module.
Additional information on timer modules is available in
the PIC
(DS33023).
®
MCU Mid-Range Reference Manual,
5.1 Timer1 Operation
Timer1 can operate in one of these modes:
•As a timer
• As a synchronous counter
• As an asynchronous counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
In timer mode, Timer1 increments every instruction
cycle. In counter mode, it increments on every rising
edge of the external clock input.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored.
Timer1 also has an internal “reset input”. This reset can
be generated by the CCP module as a special event
trigger (Section 7.0).
REGISTER 5-1:T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit7 bit0
bit 7-6: Unimplemented: Read as '0'
bit 5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3: T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled (TRISC<1:0> ignored)
0 = Oscillator is shut off
(The oscillator is turned off to reduce power drain
bit 2: T1SYNC
T
1 = Do not synchronize external clock input
0 = Synchronize external clock input
T
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1: TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0 = Internal clock (F
bit 0: TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
: Timer1 External Clock Input Synchronization Control bit
MR1CS = 1
MR1CS = 0
OSC/4)
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 27
PIC16C62B/72A
TMR1H
TMR1L
T1OSC
T1SYNC
TMR1CS
T1CKPS1:T1CKPS0
SLEEP input
T1OSCEN
Enable
Oscillator
(1)
FOSC/4
Internal
Clock
TMR1ON
on/off
Prescaler
1, 2, 4, 8
Synchronize
det
1
0
0
1
Synchronized
clock input
2
RC0/T1OSO/T1CKI
RC1/T1OSI
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
Set flag bit
TMR1IF on
Overflow
TMR1
FIGURE 5-1: TIMER1 BLOCK DIAGRAM
DS35008C-page 28 Preliminary 1998-2013 Microchip Technology Inc.
PIC16C62B/72A
5.2 Timer1 Oscillator
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). When the
Timer1 oscillator is enabled, RC0 and RC1 pins
become T1OSO and T1OSI inputs, overriding
TRISC<1:0>.
The oscillator is a low power oscillator rated up to 200
kHz. It will continue to run during SLEEP. It is primarily
intended for a 32 kHz crystal. Table 5-1 shows the
capacitor selection for the Timer1 oscillator.
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
TABLE 5-1 CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
Osc Type Freq C1 C2
LP 32 kHz 33 pF 33 pF
100 kHz 15 pF 15 pF
200 kHz 15 pF 15 pF
These values are for design guidance only.
Crystals Tested:
32.768 kHz Epson C-001R32.768K-A 20 PPM
100 kHz Epson C-2 100.00 KC-P 20 PPM
200 kHz STD XTL 200.000 kHz 20 PPM
Note 1: Higher capacitance increases the stability
of oscillator but also increases the start-up
time.
2: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appropriate values of external components.
5.3 Timer1 Interrupt
The TMR1 Register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 Interrupt, if enabled, is generated on overflow
and is latched in interrupt flag bit TMR1IF (PIR1<0>).
This interrupt can be enabled by setting TMR1 interrupt
enable bit TMR1IE (PIE1<0>).
5.4 Resetting Timer1 using a CCP Trigger
Output
If the CCP module is configured in compare mode to
generate a “special event trigger" (CCP1M3:CCP1M0
= 1011), this signal will reset Timer1 and start an A/D
conversion (if the A/D module is enabled).
Note: The special event trigger from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
Timer1 must be configured for either timer or synchronized counter mode to take advantage of this feature. If
Timer1 is running in asynchronous counter mode, this
reset operation may not work.
In the event that a write to Timer1 coincides with a special event trigger from CCP1, the write will take precedence.
In this mode of operation, the CCPR1H:CCPR1L registers pair effectively becomes the period register for
Timer1.
TABLE 5-2 REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0Bh,8Bh INTCON GIE PEIE
0Ch PIR1
8Ch PIE1
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register
10h T1CON
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 29
— ADIF — — SSPIF CCP1IF TMR2IF TMR1IF
— ADIE — — SSPIE CCP1IE TMR2IE TMR1IE
— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
T0IE INTE RBIE T0IF INTF RBIF
Value on
POR,
BOR
0000 000x 0000 000u
-0-- 0000 -0-- 0000
-0-- 0000 -0-- 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --uu uuuu
Value on
all other
resets
PIC16C62B/72A
NOTES:
DS35008C-page 30 Preliminary 1998-2013 Microchip Technology Inc.
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