Microchip Technology PIC10(L)F320, PIC10(L)F322 Data Sheet

PIC10(L)F320/322

Data Sheet

6/8-Pin, High-Performance,

Flash Microcontrollers

 2011 Microchip Technology Inc. Preliminary DS41585A

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC, K

EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

PIC

logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

ISBN: 978-1-61341-380-7

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

MCUs and dsPIC® DSCs, KEELOQ

code hopping

DS41585A-page 2 Preliminary  2011 Microchip Technology Inc.

PIC10(L)F320/322

6/8-Pin Flash-Based, 8-Bit Microcontrollers

High-Performance RISC CPU:

• Only 35 Instructions to Learn:

- All single-cycle instructions, except branches

• Operating Speed:

- DC – 16 MHz clock input

- DC – 250 ns instruction cycle

• Up to 512 Words of Flash Program Memory

• 64 Bytes Data Memory

• Eight-level Deep Hardware Stack

• Interrupt Capability

• Processor Self-Write/Read access to Program Memory

• Pinout Compatible to other 6-Pin PIC10FXXX Microcontrollers

Special Microcontroller Features:

• Low-Power 16 MHz Internal Oscillator:

- Software selectable frequency range from

16 MHz to 31 kHz

- Factory calibrated to  1%, typical

• Wide Operating Range:

- 1.8V to 3.6V (PIC10LF320/322)

- 2.3V to 5.5V (PIC10F320/322)

• Power-on Reset (POR)

• Power-up Timer (PWRT)

• Brown-out Reset (BOR)

• Ultra Low-Power Sleep Regulator

• Extended Watchdog Timer (WDT)

• Programmable Code Protection

• Power-Saving Sleep mode

• Selectable Oscillator options (EC mode or Internal Oscillator)

• In-Circuit Serial Programming™ (ICSP™) (via Two Pins)

• In-Circuit Debugger Support

• Fixed Voltage Reference (FVR) with 1.024V,

2.048V and 4.096V (‘F’ variant only) Output Levels

• Integrated Temperature Indicator

• 40-year Flash Data Retention

Low-Power Features (PIC10LF320/322):

• Standby Current:

- 20 nA @ 1.8V, typical

• Operating Current:

-25A @ 1 MHz, 1.8V, typical

• Watchdog Timer Current:

- 500 nA @ 1.8V, typical

Peripheral Features:

• 4 I/O Pins:

- 1 input-only pin

- High current sink/source for LED drivers

- Individually selectable weak pull-ups

- Interrupt-on-Change

• Timer0: 8-Bit Timer/Counter with 8-Bit Programmable Prescaler

• Timer2: 8-Bit Timer/Counter with 8-Bit Period Register, Prescaler and Postscaler

• Two PWM modules:

- 10-bit PWM, max. frequency 16 kHz

- Combined to single 2-phase output

• A/D Converter:

- 8-bit resolution with 3 channels

• Configurable Logic Cell (CLC):

- 8 selectable input source signals

- Two inputs per module

- Software selectable logic functions including:

AND/OR/XOR/D Flop/D Latch/SR/JK

- External or internal inputs/outputs

- Operation while in Sleep

• Numerically Controlled Oscillator (NCO):

- 20-bit accumulator

- 16-bit increment

- Linear frequency control

- High-speed clock input

- Selectable Output modes

- Fixed Duty Cycle (FDC)

- Pulse Frequency (PF) mode

• Complementary Waveform Generator (CWG):

- Selectable falling and rising edge dead-band

control

- Polarity control

- 2 auto-shutdown sources

- Multiple input sources: PWM, CLC, NCO

 2011 Microchip Technology Inc. Preliminary DS41585A-page 3

PIC10(L)F320/322

PIC10(L)F320 PIC10(L)F322

RA3/MCLR/V

VDD

RA2

ICSPCLK/RA1

ICSPDAT/RA0

SOT-23

PIC10(L)F320

PIC10(L)F322

RA3/MCLR/V

VSS

N/C

RA0/ICSPDAT

ICSPCLK/RA1

N/C

RA2

PDIP, DFN

TABLE 1: PIC10(L)F320/322 FEATURE SUMMARY

Program

Device

Memory

Flash

(words)

PIC10F320 256 64 4 3 1 2 2 1 1

PIC10LF320 256 64 4 3 1 2 2 1 1

PIC10F322 512 64 4 3 1 2 2 1 1

PIC10LF322 512 64 4 3 1 2 2 1 1

Note1: One pin is input-only.

FIGURE 1: 6-PIN DIAGRAM, PIC10(L)F320/322

SRAM (bytes)

I/O

(1)

8-bit A/D (ch) CLC

10-bit

PWM

Timers

8-bit

NCO CWG

FIGURE 2: 8-PIN DIAGRAM, PIC10(L)F320/322

TABLE 2: 6 AND 8-PIN ALLOCATION TABLE (PIC10(L)F320/322)

I/O 6-Pin 8-Pin Analog Timer PWM Interrupts Pull-ups CWG NCO CLC Basic ICSP

RA0 1 5 AN0 — PWM1 IOC0 Y CWG1A — CLC1IN1 — ICSPDAT

RA1 3 4 AN1 — PWM2 IOC1 Y CWG1B NCO1CLK CLC1 CLKIN ICSPCLK

RA2 4 3 AN2 T0CKI — INT/IOC2 Y CWG1FLT NCO1 CLC1IN2 CLKR

RA3 6 8 — — — IOC3 Y — — — MCLR VPP

N/C — 1 — — — — — — — — — —

N/C — 6 — — — — — — — — — —

VDD 5 2 — — — — — — — — VDD —

SS 27 — —— — — — — — VSS —

DS41585A-page 4 Preliminary  2011 Microchip Technology Inc.

PIC10(L)F320/322

1.0 Device Overview .......................................................................................................................................................................... 7

2.0 Memory Organization ................................................................................................................................................................. 11

3.0 Device Configuration.................................................................................................................................................................. 21

4.0 Oscillator Module........................................................................................................................................................................ 27

5.0 Resets ........................................................................................................................................................................................ 33

6.0 Interrupts .................................................................................................................................................................................... 41

7.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 51

8.0 Watchdog Timer (WDT) ............................................................................................................................................................. 53

9.0 Flash Program Memory Control ................................................................................................................................................. 57

10.0 I/O Port....................................................................................................................................................................................... 75

11.0 Interrupt-On-Change .................................................................................................................................................................. 81

12.0 Fixed Voltage Reference (FVR) ................................................................................................................................................. 85

13.0 Internal Voltage Regulator (IVR) ................................................................................................................................................ 87

14.0 Temperature Indicator Module ................................................................................................................................................... 89

15.0 Analog-to-Digital Converter (ADC) Module ................................................................................................................................ 91

16.0 Timer0 Module ......................................................................................................................................................................... 101

17.0 Timer2 Module ......................................................................................................................................................................... 105

18.0 Pulse Width Modulation (PWM) Module................................................................................................................................... 107

19.0 Configurable Cell Logic (CLC).................................................................................................................................................. 113

20.0 Numerically Controlled Oscillator (NCO) Module ..................................................................................................................... 129

21.0 Complementary Waveform Generator (CWG) Module ............................................................................................................ 139

22.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 155

23.0 Instruction Set Summary.......................................................................................................................................................... 159

24.0 Electrical Specifications............................................................................................................................................................ 169

25.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 187

26.0 Development Support............................................................................................................................................................... 189

27.0 Packaging Information.............................................................................................................................................................. 193

Appendix A: Data Sheet Revision History .......................................................................................................................................... 201

Index .................................................................................................................................................................................................. 203

The Microchip Web Site..................................................................................................................................................................... 207

Customer Change Notification Service .............................................................................................................................................. 207

Customer Support .............................................................................................................................................................................. 207

Reader Response .............................................................................................................................................................................. 208

Product Identification System ............................................................................................................................................................ 209

 2011 Microchip Technology Inc. Preliminary DS41585A-page 5

PIC10(L)F320/322

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.

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To determine if an errata sheet exists for a particular device, please check with one of the following:

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using.

Customer Notification System

DS41585A-page 6 Preliminary  2011 Microchip Technology Inc.

1.0 DEVICE OVERVIEW

The PIC10(L)F320/322 are described within this data sheet. They are available in 6/8-pin packages. Figure 1-1 shows a block diagram of the PIC10(L)F320/322 devices. Ta b le 1- 2 shows the pinout descriptions.

Reference Tab le 1- 1 for peripherals available per device.

TABLE 1-1: DEVICE PERIPHERAL

SUMMARY

Peripheral

PIC10(L)F322

PIC10(L)F320

Analog-to-Digital Converter (ADC) ●●

Configurable Logic Cell (CLC) ●●

Complementary Wave Generator (CWG) ●●

Fixed Voltage Reference (FVR) ●●

Numerically Controlled Oscillator (NCO) ●●

Temperature Indicator ●●

PWM Modules

PWM1 ●●

PWM2 ●●

Timers

Timer0 ●●

Timer2 ●●

PIC10(L)F320/322

 2011 Microchip Technology Inc. Preliminary DS41585A-page 7

PIC10(L)F320/322

PORTA

Note 1: See applicable chapters for more information on peripherals.

CPU

Program

Flash Memory

RAM

Timing

Generation

INTRC

Oscillator

MCLR

Figure 2-1

CLKIN

CLKR

ADC 8-Bit

FVR

Te mp .

Indicator

Timer2Timer0

PWM1

PWM2 NCO

CLC CWG

FIGURE 1-1: PIC10(L)F320/322 BLOCK DIAGRAM

DS41585A-page 8 Preliminary  2011 Microchip Technology Inc.

T ABLE 1-2: PIC10(L)F320/322 PINOUT DESCRIPTION

Input

Name Function

Type

Output

Type

PIC10(L)F320/322

Description

RA0/PWM1/CLC1IN1/CWG1A/ AN0/ICSPDAT

RA1/PWM2/CLC1/CWG1B/AN1/ CLKIN/ICSPCLK/NCO1CLK

RA2/INT/T0CKI/NCO1/CLC1IN2/ CLKR/AN2/CWG1FLT

RA3/MCLR

DD VDD Power — Positive supply.

SS VSS Power — Ground reference.

V Legend: AN = Analog input or output CMOS = CMOS compatible input or output

/VPP RA3 TTL — General purpose input.

TTL = CMOS input with TTL levels ST = CMOS input with Schmitt Trigger levels HV = High Voltage

RA0 TTL CMOS General purpose I/O with IOC and WPU.

PWM1 — CMOS PWM output.

CLC1IN1

CWG1A —

AN0 AN — A/D Channel input.

ICSPDAT ST CMOS ICSP™ Data I/O.

RA1 TTL CMOS General purpose I/O with IOC and WPU.

PWM2 — CMOS PWM output.

CLC1 — CMOS

CWG1B — CMOS

AN1 AN — A/D Channel input.

CLKIN ST — External Clock input (EC mode).

ICSPCLK ST — Serial Programming Clock.

NCO1CLK ST — Numerical Controlled Oscillator external clock input.

RA2 TTL CMOS General purpose I/O with IOC and WPU.

INT ST — External interrupt.

T0CKI ST — Timer0 clock input.

NCO1 — CMOS Numerically Controlled Oscillator output.

CLC1IN2 ST —

CLKR — CMOS Clock Reference output.

AN2 AN — A/D Channel input.

CWG1FLT

MCLR

PP HV — Programming voltage.

CMOS CWG primary output.

ST — Complementary Waveform Generator Fault 1 source input.

ST — Master Clear with internal pull-up.

CLC input.

—

CLC output.

CWG complementary output.

CLC input.

 2011 Microchip Technology Inc. Preliminary DS41585A-page 9

PIC10(L)F320/322

NOTES:

DS41585A-page 10 Preliminary  2011 Microchip Technology Inc.

PIC10(L)F320/322

2.0 MEMORY ORGANIZATION

These devices contain the following types of memory:

• Program Memory

- Configuration Words

- Device ID

-User ID

- Flash Program Memory

• Data Memory

- Core Registers

- Special Function Registers

- General Purpose RAM

- Common RAM

The following features are associated with access and control of program memory and data memory:

• PCL and PCLATH

•Stack

• Indirect Addressing

TABLE 2-1: DEVICE SIZES AND ADDRESSES

Device Program Memory Space (Words) Last Program Memory Address

PIC10(L)F320 256 00FFh

PIC10(L)F322 512 01FFh

2.1 Program Memory Organization

The mid-range core has a 13-bit program counter capable of addressing 8K x 14 program memory space. This device family only implements up to 512 words of the 8K program memory space. Table 2-1 shows the memory sizes implemented for the PIC10(L)F320/322 family. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figures 2-1, and 2-2).

 2011 Microchip Technology Inc. Preliminary DS41585A-page 11

PIC10(L)F320/322

PC<12:0>

0000h

0004h

Stack Level 0

Stack Level 8

Reset Vector

Interrupt Vector

Stack Level 1

0005h

On-chip

Program

Memory

Page 0

00FFh

Wraps to Page 0

0100h

CALL,

RETURN, RETLW

RETFIE

Rollover to Page 0

FFFh

PC<12:0>

0000h

0004h

Stack Level 0

Stack Level 8

Reset Vector

Interrupt Vector

Stack Level 1

0005h

On-chip

Program

Memory

Page 0

01FFh

Wraps to Page 0

0200h

CALL

RETURN, RETLW

RETFIE

Rollover to Page 0

FFFh

FIGURE 2-1: PROGRAM MEMORY MAP

AND STACK FOR PIC10(L)F320

FIGURE 2-2: PROGRAM MEMORY MAP

AND STACK FOR PIC10(L)F322

DS41585A-page 12 Preliminary  2011 Microchip Technology Inc.

PIC10(L)F320/322

2.2 Data Memory Organization

The data memory is in one bank, which contains the General Purpose Registers (GPR) and the Special Function Registers (SFR). The RP<1:0> bits of the STATUS register are the bank select bits.

RP0

RP1

00  Bank 0 is selected

The bank extends up to 7Fh (128 bytes). The lower locations of the bank are reserved for the Special Function Registers. Above the Special Function Registers are the General Purpose Registers, implemented as Stati c RAM.

2.2.1 GENERAL PURPOSE REGISTER

FILE

The register file is organized as 64 x 8 in the PIC10(L)F320/322. Each register is accessed, either directly or indirectly, through the File Select Register

(FSR) (see Section 2.4 “Indirect Addressing, INDF

and FSR Registers”).

2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Tab le 2- 3 ). These registers are static RAM.

The special registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the “core” are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature.

 2011 Microchip Technology Inc. Preliminary DS41585A-page 13

PIC10(L)F320/322

2.2.2.1 STATUS Register

The STATUS register, shown in Register 2-1, contains:

• the arithmetic status of the ALU

• the Reset status

• the bank select bits for data memory (SRAM)

The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.

For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘000u u1uu’ (where u = unchanged).

It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits (see Section 23.0 “Instruction Set

Summary”).

and PD bits are not

Note 1: Bits IRP and RP1 of the STATUS register

are not used by the PIC10(L)F320 and should be maintained as clear. Use of these bits is not recommended, since this may affect upward compatibility with future products.

2: The C and DC bits operate as a Borrow

and Digit Borrow out bit, respectively, in subtraction.

DS41585A-page 14 Preliminary  2011 Microchip Technology Inc.

PIC10(L)F320/322

REGISTER 2-1: STATUS: STATUS REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R-1/q R-1/q R/W-x/u R/W-x/u R/W-x/u

IRP RP1 RP0 TO PD ZDCC

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 IRP: Reserved bit 6-5 RP<1:0>: Reserved bit 4 TO: Time-out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred

bit 3 PD

bit 2 Z: Zero bit

bit 1 DC: Digit Carry/Borrow

bit 0 C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)

Note1: For Borrow

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register.

2: Maintain as ‘0’.

: Power-Down bit

1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result

1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred

, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

(2)

bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)

(1)

 2011 Microchip Technology Inc. Preliminary DS41585A-page 15

PIC10(L)F320/322

Legend: = Unimplemented data memory locations, read as ‘0’.

* = Not a physical register.

INDF

(*)

00h

PMADRL

20h

General

Purpose

Registers

32 Bytes

40h

5Fh

General

Purpose

Registers

32 Bytes

60h

7Fh

TMR0 01h PMADRH 21h

PCL 02h PMDATL 22h

STATUS 03h PMDATH 23h

FSR 04h PMCON1 24h

PORTA 05h PMCON2 25h

TRISA 06h CLKRCON 26h

LATA 07h NCO1ACCL 27h

ANSELA

08h

NCO1ACCH

28h

WPUA

09h

NCO1ACCU

29h

PCLATH 0Ah NCO1INCL 2Ah

INTCON 0Bh NCO1INCH 2Bh

PIR1 0Ch Reserved 2Ch

PIE1 0Dh NCO1CON 2Dh

OPTION_REG 0Eh NCO1CLK 2Eh

PCON 0Fh Reserved 2Fh

OSCCON 10h WDTCON 30h

TMR2 11h CLC1CON 31h

PR2 12h CLC1SEL1 32h

T2CON 13h CLC1SEL2 33h

PWM1DCL 14h CLC1POL 34h

PWM1DC 15h CLC1GATE1 35h

PWM1CON 16h CLC1GATE2 36h

PWM2DCL 17h CLC1GATE3 37h

PWM2DC 18h CLC1GATE4 38h

PWM2CON 19h CWG1CON0 39h

IOCAP 1Ah CWG1CON1 3Ah

IOCAN 1Bh CWG1ASD 3Bh

IOCAF 1Ch CWG1RC 3Ch

FVRCON 1Dh CWG1FC 3Dh

ADRES

1Eh

VREGCON

3Eh

ADCON 1Fh

BORCON

3Fh

2.2.3 DEVICE MEMORY MAPS

The memory maps for PIC10(L)F320/322 are as shown in Table 2-2.

TABLE 2-2: PIC10(L)F320/322 MEMORY MAP (BANK 0)

DS41585A-page 16 Preliminary  2011 Microchip Technology Inc.

PIC10(L)F320/322

TABLE 2-3: SPECIAL FUNCTION REGISTER SUMMARY (BANK 0)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0

00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx 01h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu 02h PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

03h STATUS IRP RP1 RP0 TO 04h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu

05h PORTA

06h TRISA

07h LATA

08h ANSELA

09h WPUA

0Ah PCLATH 0Bh INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 000u

0Ch PIR1

0Dh PIE1

0Eh OPTION_REG WPUEN

0Fh

10h OSCCON 11h TMR2 Timer2 Module Register 0000 0000 0000 0000 12h PR2 Timer2 Period Register 1111 1111 1111 1111

13h T2CON

14h PWM1DCL PWM1DCL<1:0> 15h PWM1DCH PWM1DCH<7:0> xxxx xxxx uuuu uuuu

16h PWM1CON

17h PWM2DCL PWM2DCL<1:0> 18h PWM2DCH PWM2DCH<7:0> xxxx xxxx uuuu uuuu

19h PWM2CON

1Ah IOCAP

1Bh IOCAN

1Ch IOCAF

1Dh FVRCON FVREN FVRRDY TSEN TSRNG 1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu

1Fh ADCON ADCS<2:0> CHS<2:0>

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: Unimplemented, read as ‘1’.

PCON — — — — — —PORBOR ---- --qq ---- --uu

Shaded locations are unimplemented, read as ‘0’.

— — — — RA3 RA2 RA1 RA0 ---- xxxx ---- uuuu

— — — — — — — — — — LATA2 LATA1 LATA0 ---- -xxx ---- -uuu — — — — — ANSA2 ANSA1 ANSA0 ---- -111 ---- -111 — — — — WPUA3 WPUA2 WPUA1 WPUA0 ---- 1111 ---- 1111 — — — — — — — PCLH0 ---- ---0 ---- ---0

—ADIF— NCO1IF CLC1IF —TMR2IF— -0-0 0-0- -0-0 0-0- —ADIE— NCO1IE CLC1IE —TMR2IE— -0-0 0-0- -0-0 0-0-

INTEDG T0CS T0SE PSA PS<2:0> 1111 1111 uuuu uuuu

— IRCF<2:0> HFIOFR — LFIOFR HFIOFS -110 0-00 -110 0-00

— TOUTPS<3:0> TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

— — — — — — xx-- ---- uu-- ----

PWM1EN PWM1OE PWM1OUT PWM1POL — — — —

— — — — — — xx-- ---- uu-- ----

PWM2EN PWM2OE PWM2OUT PWM2POL

— — — — IOCAP3 IOCAP2 IOCAP1 IOCAP0 ---- 0000 ---- 0000 — — — — IOCAN3 IOCAN2 IOCAN1 IOCAN0 ---- 0000 ---- 0000 — — — — IOCAF3 IOCAF2 IOCAF1 IOCAF0 ---- 0000 ---- 0000

PD ZDCC0001 1xxx 000q quuu

(1)

TRISA2 TRISA1 TRISA0 ---- 1111 ---- 1111

— — — — 0000 ---- 0000 ----

— —ADFVR<1:0>0x00 --00 0x00 --00

GO/

DONE

ADON 0000 0000 0000 0000

Value on

POR, BOR

0000 ---- 0000 ----

Value on all other resets

 2011 Microchip Technology Inc. Preliminary DS41585A-page 17

PIC10(L)F320/322

TABLE 2-3: SPECIAL FUNCTION REGISTER SUMMARY (BANK 0) (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0 (Continued)

20h PMADRL PMADR<7:0> 0000 0000 0000 0000

21h PMADRH 22h PMDATL PMDAT<7:0> xxxx xxxx uuuu uuuu

23h PMDATH

24h PMCON1 25h PMCON2 Program Memory Control Register 2 (not a physical register) 0000 0000 0000 0000

26h CLKRCON 27h NCO1ACCL NCO1 Accumulator <7:0> 0000 0000 0000 0000 28h NCO1ACCH NCO1 Accumulator <15:8> 0000 0000 0000 0000

29h NCO1ACCU 2Ah NCO1INCL NCO1 Increment <7:0> 0000 0001 0000 0001 2Bh NCO1INCH NCO1 Increment <15:8> 0000 0000 0000 0000

2Ch

2Dh NCO1CON N1EN N1OE N1OUT N1POL

2Eh NCO1CLK

2Fh

30h WDTCON

31h

32h

33h

34h

35h

36h

37h

38h

39h CWG1CON0

3Ah CWG1CON1

3Bh CWG1CON2 G1ASE G1ARSEN

3Ch CWG1DBR

3Dh CWG1DBF

3Eh

3Fh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Note 1: Unimplemented, read as ‘1’.

— Unimplemented — —

Reserved Reserved xxxx xxxx uuuu uuuu

CLC1CON

CLC1SEL0

CLC1SEL1

CLC1POL

CLC1GLS0

CLC1GLS1

CLC1GLS2

CLC1GLS3

VREGCON

BORCON

Shaded locations are unimplemented, read as ‘0’.

— — — — — — — PMADR8 ---- ---0 ---- ---0

— —PMDAT<13:8>--xx xxxx --uu uuuu — CFGS LWL O FR EE WRERR WREN WR RD 1000 0000 1000 q000

—CLKROE— — — — — — -0-- ---- -0-- ----

— NCO1 Accumulator <19..16> --- - 00 00 ---- 0000

— — —N1PFM0000 ---0 00x0 ---0

N1PWS<2:0> — — —N1CKS<1:0>

— —WDTPS<4:0>SWDTEN--01 0110 --01 0110

LC1EN LC1OE LC1OUT LC1INTP LC1INTN LC1MODE<2:0> 00x0 -000 00x0 -000

— LC1D2S<2:0> — LC1D1S<2:0> -xxx -xxx -uuu -uuu — LC1D4S<2:0> — LC1D3S<2:0> -xxx -xxx -uuu -uuu

LC1POL

LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D 2T LC1G 1D2N LC1G1D1 T LC1G 1D1N

LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D 2T LC1G 2D2N LC1G2D1 T LC1G 2D1N

LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D 2T LC1G 3D2N LC1G3D1 T LC1G 3D1N

LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D 2T LC1G 4D2N LC1G4D1 T LC1G 4D1N

G1EN G1OEB G1OEA G1POLB G1POLA

G1ASDLB<1:0> G1ASDLA<1:0>

— —CWG1DBR<5:0>--xx xxxx --uu uuuu — —CWG1DBF<5:0>--xx xxxx --uu uuuu

— — — — — —VREGPM1Reserved ---- --01 ---- --01

SBOREN BORFS — — — — — BORRDY 10-- ---q uu-- ---u

— — — LC1G4POL LC1G3POL LC1G2POL LC1G1POL 0--- xxxx 0--- uuuu

— —

— — — — G1ASDCLC1 G1ASDFLT xx-- --xx uu-- --uu

G1CS0

G1IS<1:0>

Value on

POR, BOR

000- --00 000- --00

xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 0000 0--0 0000 0--0 xxxx --xx uuuu --uu

Value on all other resets

DS41585A-page 18 Preliminary  2011 Microchip Technology Inc.

PIC10(L)F320/322

12 8 7 0

PCLATH<4:0>

PCLATH

Instruction with

ALU Result

GOTO, CALL

OPCODE <10:0>

12 11 10 0

PCLATH<4:3>

PCH PCL

PCLATH

PCH PCL

PCL as

Destination

MOVLW 0x40 ;initialize pointer MOVWF FSR ;to RAM

NEXT CLRF INDF ;clear INDF register

INCF FSR ;inc pointer BTFSS FSR,7 ;all done? GOTO NEXT ;no clear next

CONTINUE ;yes continue

2.3 PCL and PCLATH

The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-3 shows the two situations for the loading of the PC. The upper example in Figure 2-3 shows how the PC is loaded on a write to PCL (PCLATH<4:0>  PCH). The lower example in

Figure 2-3 shows how the PC is loaded during a CALL or

GOTO instruction (PCLATH<4:3>  PCH).

FIGURE 2-3: LOADING OF PC IN

DIFFERENT SITUATIONS

2.3.2 STACK

All devices have an 8-level x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation.

The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on).

Note 1: There are no Status bits to indicate Stack

Overflow or Stack Underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address.

2.4 Indirect Addressing, INDF and

FSR Registers

2.3.1 MODIFYING PCL

Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC<12:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper 5 bits to the PCLATH register. When the lower 8 bits are written to the PCL register, all 13 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register.

A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). Care should be exercised when jumping into a look-up table or program branch table (computed GOTO) by modifying the PCL register. Assuming that PCLATH is set to the table start address, if the table length is greater than 255 instructions or if the lower 8 bits of the memory address rolls over from 0xFF to 0x00 in the middle of the table, then PCLATH must be incremented for each address rollover that occurs between the table beginning and the target location within the table.

For more information refer to Application Note AN556,

“Implementing a Table Read” (DS00556).

The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the File Select Register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a no operation (although Status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR and the IRP bit of the STATUS register, as shown in Figure 2-4.

A simple program to clear RAM location 40h-7Fh using indirect addressing is shown in Example 2-1.

EXAMPLE 2-1: INDIRECT ADDRESSING

 2011 Microchip Technology Inc. Preliminary DS41585A-page 19

PIC10(L)F320/322

Data Memory

Indirect AddressingDirect Addressing

Location Select

From Opcode

File Select Register

Location Select

00h

7Fh

Bank 0

For memory map detail, see Figure 2-2.

FIGURE 2-4: DIRECT/INDIRECT ADDRESSING PIC10(L)F320/322

DS41585A-page 20 Preliminary  2011 Microchip Technology Inc.

3.0 DEVICE CONFIGURATION

Device Configuration consists of Configuration Word and Device ID.

3.1 Configuration Word

There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word at 2007h.

PIC10(L)F320/322

 2011 Microchip Technology Inc. Preliminary DS41585A-page 21

PIC10(L)F320/322

REGISTER 3-1: CONFIG: CONFIGURATION WORD

U-1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1

— WRT<1:0> BORV LPBOR

bit 13 bit 8

R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1

CP MCLRE PWRTE WDTE<1:0> BOREN<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared P = Programmable bit

bit 13 Unimplemented: Read as ‘1’ bit 12-11 WRT<1:0>: Flash Memory Self-Write Protection bits

256 W Flash memory: PIC10(L)F320:

11 =Write protection off 10 =000h to 03Fh write-protected, 040h to 0FFh may be modified by PMCON control 01 =000h to 07Fh write-protected, 080h to 0FFh may be modified by PMCON control 00 =000h to 0FFh write-protected, no addresses may be modified by PMCON control

512 W Flash memory: PIC10(L)F322:

11 =Write protection off 10 =000h to 07Fh write-protected, 080h to 1FFh may be modified by PMCON control 01 =000h to 0FFh write-protected, 100h to 1FFh may be modified by PMCON control 00 =000h to 1FFh write-protected, no addresses may be modified by PMCON control

bit 10 BORV: Brown-out Reset Voltage Selection bit

1 = Brown-out Reset Voltage (V 0 = Brown-out Reset Voltage (V

bit 9 LPBOR: Low-Power Brown-out Reset Enable bit

1 = Low-power Brown-out Reset is enabled 0 = Low-power Brown-out Reset is disabled

bit 8 LVP: Low-Voltage Programming Enable bit

1 = Low-Voltage Programming enabled. MCLR 0 = High Voltage on MCLR

bit 7 CP

bit 6 MCLRE: MCLR

bit 5 PWRTE

: Code Protection bit

1 = Program memory code protection is disabled 0 = Program memory code protection is enabled

If LVP bit =

This bit is ignored.

If LVP bit = 0:

1 =MCLR 0 =MCLR

1 = PWRT disabled 0 = PWRT enabled

/VPP pin function is MCLR; Weak pull-up enabled. /VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of

WPUA3 bit.

: Power-up Timer Enable bit

/VPP Pin Function Select bit

(2)

BOR) set to 1.9V (PIC10LF320/322) or 2.4V (PIC10F320/322) BOR) set to 2.7V

/VPP pin function is MCLR.

/VPP must be used for programming

(1)

R/P-1/1

LVP

R/P-1/1

FOSC

Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.

2: Once enabled, code-protect can only be disabled by bulk erasing the device.

DS41585A-page 22 Preliminary  2011 Microchip Technology Inc.

PIC10(L)F320/322

bit 4-3 WDTE<1:0>: Watchdog Timer Enable bit

11 = WDT enabled 10 = WDT enabled while running and disabled in Sleep 01 = WDT controlled by the SWDTEN bit in the WDTCON register 00 = WDT disabled

bit 2-1 BOREN<1:0>: Brown-out Reset Enable bits

11 = Brown-out Reset enabled; SBOREN bit is ignored 10 = Brown-out Reset enabled while running, disabled in Sleep; SBOREN bit is ignored 01 = Brown-out Reset controlled by the SBOREN bit in the BORCON register 00 = Brown-out Reset disabled; SBOREN bit is ignored

bit 0 FOSC: Oscillator Selection bit

1 = EC on CLKIN pin 0 = INTOSC oscillator I/O function available on CLKIN pin

Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.

2: Once enabled, code-protect can only be disabled by bulk erasing the device.

 2011 Microchip Technology Inc. Preliminary DS41585A-page 23

PIC10(L)F320/322

3.2 Code Protection

Code protection allows the device to be protected from unauthorized access. Program memory protection and data memory protection are controlled independently. Internal access to the program memory and data memory are unaffected by any code protection setting.

3.2.1 PROGRAM MEMORY PROTECTION

The entire program memory space is protected from external reads and writes by the CP Word. When CP program memory are inhibited and a read will return all ‘0’s. The CPU can continue to read program memory, regardless of the protection bit settings. Writing the program memory is dependent upon the write

protection setting. See Section 3.3 “Write

Protection” for more information.

= 0, external reads and writes of

3.3 Write Protecti on

Write protection allows the device to be protected from unintended self-writes. Applications, such as boot loader software, can be protected while allowing other regions of the program memory to be modified.

The WRT<1:0> bits in Configuration Word define the size of the program memory block that is protected.

bit in Configuration

3.4 User ID

Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are readable and writable during normal execution. See

Section 3.5 “Device ID and Revision ID” for more

information on accessing these memory locations. more information on checksum calculation, see the “PIC10(L)F320/322 Flash Memory Programming Specification” (DS41572).

For

DS41585A-page 24 Preliminary  2011 Microchip Technology Inc.

PIC10(L)F320/322

Device

DEVICEID<13:0> Values

DEV<8:0> REV<4:0>

PIC10F320 10 1001 101 x xxxx PIC10LF320 10 1001 111 x xxxx PIC10F322 10 1001 100 x xxxx PIC10LF322 10 1001 110 x xxxx

3.5 Device ID and Revision ID

The memory location 2006h is where the Device ID and Revision ID are stored. The upper nine bits hold the Device ID. The lower five bits hold the Revision ID. See

Section 9.4 “User ID, Device ID and Configuration Word Access” for more information on accessing

these memory locations.

Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID.

RRRRRR

DEV8 DEV7 DEV6 DEV5 DEV4 DEV3

bit 13 bit 8

RRRRRRRR

DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0

bit 7 bit 0

(1)

Legend: U = Unimplemented bit, read as ‘0’

R = Readable bit W = Writable bit ‘0’ = Bit is cleared

-n = Value at POR ‘1’ = Bit is set x = Bit is unknown

bit 13-5 DEV<8:0>: Device ID bits

bit 4-0 REV<4:0>: Revision ID bits

These bits are used to identify the revision.

Note 1: This location cannot be written.

 2011 Microchip Technology Inc. Preliminary DS41585A-page 25

PIC10(L)F320/322

NOTES:

DS41585A-page 26 Preliminary  2011 Microchip Technology Inc.

PIC10(L)F320/322

HFINTOSC

16 MHz

HFIOFR

(1)

HFIOFS

(1)

Divider

16 MHz

8 MHz 4 MHz 2 MHz 1 MHz

500 kHz

250 kHz

MUX

111 110

101 100 011 010 001

LFINTOSC

31 kHz

000

IRCF<2:0>

INTOSC

LFIOFR

(1)

CLKIN

MUX

FOSC

(Configuration

Word)

System Clock

(CPU and Peripherals)

CLKROE

CLKR

31 kHz

Note 1: HFIOFR, HFIOFS and LFIOFR are Status bits in the OSCCON register.

4.0 OSCILLATOR MODULE

4.1 Overview

The oscillator module has a variety of clock sources and selection features that allow it to be used in a range of applications while maximizing performance and minimizing power consumption. Figure 4-1 illustrates a block diagram of the oscillator module.

The system can be configured to use an internal calibrated high-frequency oscillator as clock source, with a choice of selectable speeds via software.

Clock source modes are configured by the FOSC bit in Configuration Word (CONFIG).

1. EC oscillator from CLKIN.

2. INTOSC oscillator, CLKIN not enabled.

FIGURE 4-1: PIC10(L)F320/322 CLOCK SOURCE BLOCK DIAGRAM

 2011 Microchip Technology Inc. Preliminary DS41585A-page 27

PIC10(L)F320/322

4.2 Clock Source Modes

Clock source modes can be classified as external or internal.

• Internal clock source (INTOSC) is contained within the oscillator module, which has eight selectable output frequencies, with a maximum internal frequency of 16 MHz.

• The External Clock mode (EC) relies on an external signal for the clock source.

The system clock can be selected between external or internal clock sources via the FOSC bit of the Configuration Word.

4.3 Internal Clock Modes

The internal clock sources are contained within the oscillator module. The internal oscillator block has two internal oscillators that are used to generate all internal system clock sources: the 16 MHz High-Frequency Internal Oscillator (HFINTOSC) and the 31 kHz (LFINTOSC).

The HFINTOSC consists of a primary and secondary clock. The secondary clock starts first with rapid startup time, but low accuracy. The secondary clock ready signal is indicated with the HFIOFR bit of the OSCCON register. The primary clock follows with slower start-up time and higher accuracy. The primary clock is stable when the HFIOFS bit of the OSCCON register bit goes high.

4.3.2 FREQUENCY SELECT BITS (IRCF)

The output of the 16 MHz HFINTOSC is connected to a divider and multiplexer (see Figure 4-1). The Internal Oscillator Frequency Select bits (IRCF) of the OSCCON register select the frequency output of the internal oscillator:

•HFINTOSC

-16 MHz

- 8 MHz (default after Reset)

-4 MHz

-2 MHz

-1 MHz

-500 kHz

-250 kHz

•LFINTOSC

-31 kHz

Note: Following any Reset, the IRCF<2:0> bits

of the OSCCON register are set to ‘110’ and the frequency selection is set to 8 MHz. The user can modify the IRCF bits to select a different frequency.

There is no delay when switching between HFINTOSC frequencies with the IRCF bits. This is because the switch involves only a change to the frequency output divider.

Start-up delay specifications are located in

Section 24.0 “Electrical Specifications”.

4.3.1 INTOSC MODE

When the FOSC bit of the Configuration Word is cleared, the INTOSC mode is selected. When INTOSC is selected, CLKIN pin is available for general purpose

I/O. See Section 3.0 “Device Configuration” for

more information.

DS41585A-page 28 Preliminary  2011 Microchip Technology Inc.

PIC10(L)F320/322

4.3.3 REFERENCE CLOCK OUTPUT CONTROL

FOSC/4 output is enabled via the CLKROE bit of CLKRCON register. The signal drives the pin regardless of the TRIS setting.

REGISTER 4-1: CLKRCON – REFERENCE CLOCK CONTROL REGISTER

U-0 R/W-0/0 U-0 U-0 U-0 U-0 U-0 U-0

—CLKROE— — — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

q = Value depends on condition

bit 7 Unimplemented: Read as ‘0’ bit 6 CLKROE: Reference Clock Output Enable bit

1 = Reference Clock output (CLKR), regardless of TRIS 0 = Reference Clock output disabled

bit 5-0 Unimplemented: Read as ‘0’

 2011 Microchip Technology Inc. Preliminary DS41585A-page 29

PIC10(L)F320/322

4.4 Oscillator Control Registers

4.4.1 OSCILLATOR CONTROL

The Oscillator Control (OSCCON) register (Register 4-2) displays the oscillator readiness, stability and allows frequency selection of the internal oscillator (INTOSC) system clock.

REGISTER 4-2: OSCCON: OSCILLATOR CONTROL REGISTER

U-0 R/W-1/1 R/W-1/1 R/W-0/0 R-0/0 U-0 R-0/0 R-0/0

— IRCF<2:0> HFIOFR —LFIOFRHFIOFS

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 Unimplemented: Read as ‘0’ bit 6-4 IRCF<2:0>: INTOSC (F

111 = 16 MHz 110 = 8 MHz (default value) 101 = 4 MHz 100 = 2 MHz 011 = 1 MHz 010 = 500 kHz 001 = 250 kHz 000 = 31 kHz (LFINTOSC)

bit 3 HFIOFR: High-Frequency Internal Oscillator Ready bit

1 = 16 MHz Internal Oscillator (HFINTOSC) is ready 0 = 16 MHz Internal Oscillator (HFINTOSC) is not ready

bit 2 Unimplemented: Read as ‘0’ bit 1 LFIOFR: Low-Frequency Internal Oscillator Ready bit

1 = 31 kHz Internal Oscillator (LFINTOSC) is ready 0 = 31 kHz Internal Oscillator (LFINTOSC) is not ready

bit 0 HFIOFS: High-Frequency Internal Oscillator Stable bit

1 = 16 MHz Internal Oscillator (HFINTOSC) is stable 0 = 16 MHz Internal Oscillator (HFINTOSC) is not stable

OSC) Frequency Select bits

DS41585A-page 30 Preliminary  2011 Microchip Technology Inc.

+ 180 hidden pages

Microchip Technology PIC10(L)F320, PIC10(L)F322 Data Sheet

Specifications and Main Features

Frequently Asked Questions

User Manual

High-Performance RISC CPU:

Special Microcontroller Features:

Low-Power Features (PIC10LF320/322):

Peripheral Features:

TABLE 1: PIC10(L)F320/322 FEATURE SUMMARY

TABLE 2: 6 AND 8-PIN ALLOCATION TABLE (PIC10(L)F320/322)

Table of Contents

Most Current Data Sheet

Errata

Customer Notification System

1.0 DEVICE OVERVIEW

FIGURE 1-1: PIC10(L)F320/322 BLOCK DIAGRAM

T ABLE 1-2: PIC10(L)F320/322 PINOUT DESCRIPTION

2.0 MEMORY ORGANIZATION

TABLE 2-1: DEVICE SIZES AND ADDRESSES

2.1 Program Memory Organization

2.2 Data Memory Organization

2.2.2 SPECIAL FUNCTION REGISTERS

REGISTER 2-1: STATUS: STATUS REGISTER

2.2.3 DEVICE MEMORY MAPS

TABLE 2-2: PIC10(L)F320/322 MEMORY MAP (BANK 0)

TABLE 2-3: SPECIAL FUNCTION REGISTER SUMMARY (BANK 0)

2.3 PCL and PCLATH

2.3.2 STACK

2.3.1 MODIFYING PCL

EXAMPLE 2-1: INDIRECT ADDRESSING

FIGURE 2-4: DIRECT/INDIRECT ADDRESSING PIC10(L)F320/322

3.0 DEVICE CONFIGURATION

3.1 Configuration Word

REGISTER 3-1: CONFIG: CONFIGURATION WORD

3.2 Code Protection

3.2.1 PROGRAM MEMORY PROTECTION

3.3 Write Protecti on

3.4 User ID

3.5 Device ID and Revision ID

4.0 OSCILLATOR MODULE

4.1 Overview

FIGURE 4-1: PIC10(L)F320/322 CLOCK SOURCE BLOCK DIAGRAM

4.2 Clock Source Modes

4.3 Internal Clock Modes

4.3.2 FREQUENCY SELECT BITS (IRCF)

4.3.1 INTOSC MODE

4.3.3 REFERENCE CLOCK OUTPUT CONTROL

REGISTER 4-1: CLKRCON – REFERENCE CLOCK CONTROL REGISTER

4.4 Oscillator Control Registers

4.4.1 OSCILLATOR CONTROL

REGISTER 4-2: OSCCON: OSCILLATOR CONTROL REGISTER