Microchip Technology PIC10F200, PIC10F202, PIC10F204, PIC10F206 Data Sheet
PIC10F200/202/204/206
Data Sheet
6-Pin, 8-Bit Flash Microcontrollers
2004 Microchip Technology Inc. Preliminary DS41239A
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Millennium Copyright Act. If suc h a c t s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K
EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL,
SmartSensor and The Embedded Control Solutions Company
are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Migra table Memory, MPASM,
MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,
PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, rfLAB, rfPICD EM, Select Mode, Smart Serial,
SmartTel and Total Endurance are trademarks of Micro chip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
®
8-bit MCUs, KEELOQ
®
code hopping
DS41239A-page ii Preliminary 2004 Microchip Technology Inc.
PIC10F200/202/204/206
6-Pin, 8-Bit Flash Microcontrollers
Devices Included In This Data Sheet:
•PIC10F200
•PIC10F202
•PIC10F204
•PIC10F206
High-Performance RISC CPU:
• Only 33 single-word instructions to learn
• All single- cycle instructions except for program
branches, which are two-cycle
• 12-bit wide instructions
• 2-level deep hardware stack
• Direct, Indirect and Relative Addressing modes
for data and instructions
• 8-bit wide data path
• 8 Special Function Hardware registers
• Operating speed:
- 4 MHz internal clock
-1µs instruction cycle
Special Microcontroller Features:
• 4 MHz precision internal oscillator:
- Factory calibrated to ±1%
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit Debugging (ICD) support
• Power-on Reset (PO R)
• Device Reset Tim er (DRT)
• Watchdog Timer (WDT) with dedicated on-chip
RC oscillator for reliable operation
• Programmable code protection
• Multiplexed MCLR
• Internal weak pull-ups on I/O pins
• Power-saving Sleep mode
• Wake-up from Sleep on pin change
input pin
Low-Power Features/CMOS Technology:
• Operating Current:
- < 350 µA @ 2V, 4 MHz
• Standby Current:
- 100 nA @ 2V, typical
• Low-power, high-speed Flash technology:
- 100,000 Flash endurance
- > 40 year retention
• Fully static design
• Wide operating voltage range: 2.0V to 5.5V
• Wide temperature range:
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
Peripheral Features (PIC10F200/202):
• 4 I/O pins:
- 3 I/O pins with individual direction control
- 1 input only pin
- High current sink/source for direct LED drive
- Wake-on-change
- Weak pull-ups
• 8-bit real-time cloc k/counter (TMR0) with 8-bit
programmable prescaler
Peripheral Features (PIC10F204/206):
• 4 I/O pins:
- 3 I/O pins with individual direction control
- 1 input only pin
- High current sink/source for direct LED drive
- Wake-on-change
- Weak pull-ups
• 8-bit real-time cloc k/counter (TMR0) with 8-bit
programmable prescaler
• 1 Comparator
- Internal absolute voltage refere nc e
- Both comparator inputs visible externally
- Comparator output visible externally
2004 Microchip Technology Inc. Preliminary DS41239A-page 1
PIC10F200/202/204/206
Pin Diagrams
SOT-23
GP0/ICSPDAT
SS
V
GP1/ICSPCLK
PDIP
N/C
VDD
GP2/T0CKI/FOSC4
GP1/ICSPCLK
PIC10F200/202
1
6
2
5
3
4
1
2
3
4
PIC10F200/202
8
7
6
5
GP3/MCLR
VDD
GP2/T0CKI/FOSC4
/VPP
GP3/MCLR/VPP
VSS
N/C
GP0/ICSPDAT
GP0/ICSPDAT/CIN+
GP1/ICSPCLK/CIN-
GP2/T0CKI/COUT/FOSC4
SOT-23
SS
V
PDIP
N/C
VDD
GP1/ICSPCLK/CIN-
PIC10F204/206
1
6
2
5
3
4
1
2
3
4
GP3/MCLR
VDD
GP2/T0CKI/COUT/FOSC4
PIC10F204/206
8
7
6
5
/VPP
GP3/MCLR/VPP
VSS
N/C
GP0/CIN+
TABLE 1-1: PIC10F2XX MEMORY AND FEATURES
Device
I/O
Flash (words) SRAM (bytes)
PIC10F200 256 16 4 1 0
PIC10F202 512 24 4 1 0
PIC10F204 256 16 4 1 1
PIC10F206 512 24 4 1 1
Program Memory Data Memory
Timers
8-bit
Comparator
DS41239A-page 2 Preliminary 2004 Microchip Technology Inc.
PIC10F200/202/204/206
Table of Contents
1.0 General Description............................................................................ ....... .... .. .... .. .... ................................................................... 5
2.0 PIC10F200/202/204/206 Device Varieties ............... .. .... ..... .... .. .. .... .. .. ....... .. .... .. .. .... ..... .... .. .. .... .. .. ..............................................7
3.0 Architectural Ov erview .................................................................................................................................................................9
4.0 Memory Organization................................................................................................................................................................. 15
5.0 I/O Port.......................................................................................................................................................................................25
6.0 Timer0 Module and TMR0 Register (PIC10F200/202)............................................................................................................... 29
7.0 Timer0 Module and TMR0 Register (PIC10F204/206)............................................................................................................... 33
8.0 Comparator Module................................................................................................... ....... .......................................................... 37
9.0 Special Feature s of th e CPU.......... ....................................................................... .....................................................................41
10.0 Instruction Set Summary............................................................................................................................................................ 51
11.0 Development Support............................................................................................. .................................................................... 59
12.0 Electrical Characteristics............................................................................................................................................................ 65
13.0 DC and AC Characteristics Graphs and Charts......................................................................................................................... 75
14.0 Packaging Information. ............................................................................................................................................................... 77
Index ................................................ . ................................................................................................................................................... 81
On-Line Support................................................................................................................................................................................... 83
2004 Microchip Technology Inc. Preliminary DS41239A-page 3
PIC10F200/202/204/206
NOTES:
DS41239A-page 4 Preliminary 2004 Microchip Technology Inc.
PIC10F200/202/204/206
1.0 GENERAL DESCRIPTION
The PIC10F200/202/204/206 devices from Microchip
T ec hnology are lo w-cost, hig h-performance , 8-bit, fullystatic, Flash-based CMOS microcontrollers. They
employ a RISC architecture with only 33 single-word/
single-cycle instructions. All instructions are single
cycle (1 µs) except for program branches, which take
two cycles. The PIC10F200/202/204/206 devices
deliver performance in an order of magnitude higher
than their competitors in the same price category. The
12-bit wide instructions are highly symmetrical, resulting in a typ ical 2:1 co de compre ssion over o ther 8-bi t
microcontrollers in its class. The easy to use and easy
to remember instruction set reduces development time
significantly.
The PIC10F200/202/204/206 products are equipped
with special features that reduce system cost and
power requirements. The Power-on Reset (POR) and
Device Reset Timer (DRT) eliminate the need for
external Reset circuitry. INTRC Internal Oscillator
mode is provided, thereby preserving the limited
number of I/O available. Power-saving Sleep mode,
Watchdog Timer and code protection features improve
system cost, power and reliabil ity.
The PIC10F200/202/204/206 devices are available in
cost-effective Flash, which is suitable for production in
any volume. The customer can take full advantage of
Microchip’s price leadership in Flash programmable
microcontrollers, while benefiting from the Flash
programmable flexibility.
The PIC10F200/202/204/206 products are supported
by a full-featured macro assembler, a software simulator, an in-circuit debugger, a ‘C’ compiler, a low-cost
development programmer and a full featured programmer. All the tools are supported on IBM
compatible machines.
®
PC and
1.1 Applications
The PIC10F200/202/204/20 6 devices fit in applicati ons
ranging from personal care appliances and security
systems to low-power remote transmitters/receivers.
The Flash technology makes customizing application
programs (transmitter codes, appliance settings,
receiver frequencies, etc.) extremely fast and convenient. The small footpri nt p ackag es, for t hrough h ole or
surface mounting, make these microcontrollers well
suited for application s with sp ac e limit atio ns. Low cos t,
low power, high performance, ease of use and I/O
flexibility make the PIC10F200/202/204/206 devices
very versatile even in areas where no microcontroller
use has been considered before (e.g., timer functions,
logic and PLDs in larger systems and coprocessor
applications).
T ABLE 1-1: PIC10F200/202/204/206 DEVICES
PIC10F200 PIC10F202 PIC10F204 PIC10F206
Clock Maximum Frequency of Operation (MHz) 4 4 4 4
Memory Flash Program Memory 256 512 256 512
Data Memory (bytes) 16 24 16 24
Peripherals Timer Module(s) TMR0 TMR0 TMR0 TMR0
Wake-up from Sleep on Pin Change Yes Yes Yes Yes
Comparators 0 0 1 1
Features I/O Pins 3 3 3 3
Input Only Pins 1 1 1 1
Internal Pull-ups Yes Yes Yes Yes
In-Circuit Serial Programming Yes Yes Yes Yes
Number of Instructions 33 33 33 33
Packages 6-pin SOT-23
8-pin PDIP
The PIC10F200/202/204/206 devices have Power-on Reset, selectable Watchdog Timer, selectable code-protect, high I/O current
capability and precision internal oscillator.
The PIC10F200/202/204/206 device uses serial programming with data pin GP0 and clock pin GP1.
2004 Microchip Technology Inc. Preliminary DS41239A-page 5
6-pin SOT-23
8-pin PDIP
6-pin SOT-23
8-pin PDIP
6-pin SOT-23
8-pin PDIP
PIC10F200/202/204/206
NOTES:
DS41239A-page 6 Preliminary 2004 Microchip Technology Inc.
PIC10F200/202/204/206
2.0 PIC10F200/202/204/206 DEVICE VARIETIES
A variety of packaging options are available. Depending on application and production requirements, the
proper device option can be selected using the
information in th is section. Wh en placing orde rs, please
use the PIC10F200/202 /204 /20 6 Prod uc t Ide ntif ic atio n
System at the back of this data sheet to specify the
correct part number.
2.1 Quick Turn Programming (QTP)
Devices
Microchip offers a QTP programming service for
factory production orders. This service is made
available for users who choose not to program
medium-to-high quantity units and whose code
patterns have stabilized. The devices are identical to
the Flash devices but with all Flash locations and fuse
options already programmed by the factory. Certain
code and prototype verification procedures do apply
before production shipments are available. Please
contact your loc al Microchi p Technology sales of fice for
more details.
2.2 Serialized Quick Turn
Programming
Microchip offers a unique programming service, where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
Serial programming allows each device to have a
unique number, which can serve as an entry code,
password or ID number.
SM
(SQTPSM) Devices
2004 Microchip Technology Inc. Preliminary DS41239A-page 7
PIC10F200/202/204/206
NOTES:
DS41239A-page 8 Preliminary 2004 Microchip Technology Inc.
PIC10F200/202/204/206
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC10F200/202/204/206
devices can be attributed to a number of architectural
features commonly found in RISC microprocessors. To
begin with, the PIC10F200/202/204/206 devices use a
Harvard architecture in which program and data are
accessed on separate buses. This improves bandwidth over traditional von Neumann architectures
where program and data are fetched on the same bus.
Separating program and data memory further allows
instructions to be sized differently than the 8-bit wide
data word. Instruction opcodes are 12 bits wide,
making it possible to have all single-word instructions.
A 12-bit wide program memory access bus fetches a
12-bit instruction in a single cycle. A two-stage pipeline
overlaps fetch and execution of instructions.
Consequently, all instructions (33) execute in a single
cycle (1 µs @ 4 MHz) except for program branches.
The table belo w lists p rogram me mory (Flash) and data
memory (RAM) for the PIC10F200/202/204/206
devices.
TABLE 3-1: PIC10F2XX MEMORY
Memory
Device
Program Data
PIC10F200 256 x 12 16 x 8
PIC10F202 512 x 12 24 x 8
PIC10F204 256 x 12 16 x 8
PIC10F206 512 x 12 24 x 8
The PIC10F200/202/204/206 devices contain an 8-bit
ALU and working register. The ALU is a general
purpose arithmetic unit. It performs arithmetic and
Boolean functions be tween dat a in the work ing regist er
and any register file.
The ALU is 8 bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise
mentioned, arithmetic operations are two’s complement in nature. In two-operand instructions, one operand is typically the W (working) register. The other
operand is either a file register or an immediate
constant. In sing le ope ran d inst ruction s, the operan d is
either the W register or a file register.
The W register is an 8-bit workin g register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC) and
Zero (Z) bits in the Status register. The C and DC bits
operate as a borrow
tively, in subtraction. See the SUBWF and ADDWF
instructions for examples.
A simplified block diagram is shown in Figure 3-1 and
Figure 3-2, with the corresponding device pins
described in Table 3-2.
and digit borrow out bit, respec-
The PIC10F200/202/204/206 devices can directly or
indirectly address its reg ister file s and dat a mem ory. All
Special Function Registers (SFR), including the PC,
are mapped in the data memory. The PIC10F200/202/
204/206 devices have a highly orthogonal
(symmetrica l) instruct ion set that m akes it possib le to
carry out any operation, on any register, using any
addressing mode. This symmetrical nature and lack of
“special optimal situ ations” make programm ing with the
PIC10F200/202/204/206 devices simple, yet efficient.
In addition, the learning curve is reduced significantly.
2004 Microchip Technology Inc. Preliminary DS41239A-page 9
PIC10F200/202/204/206
FIGURE 3-1: PIC10F200/202 BLOCK DIAGRAM
Program
Bus
Flash
512 x12 or
256 x12
Program
Memory
12
Instruction reg
Instruction
Decode &
Control
Timing
Generation
9-10
Program Counter
Direct Addr
8
Device Reset
Power-on
Watchdog
Internal RC
MCLR
Stack 1
Stack 2
Timer
Reset
Timer
Clock
VDD, VSS
RAM Addr
5
Data Bus
RAM
24 or 16
bytes
File
Registers
(1)
Addr MUX
3
ALU
8
W reg
9
Indirect
5-7
FSR reg
Status re g
MUX
Timer0
Addr
8
GPIO
GP0/ICSPDAT
GP1/ICSPCLK
GP2/T0CKI/FOSC4
GP3/MCLR/VPP
DS41239A-page 10 Preliminary 2004 Microchip Technology Inc.
PIC10F200/202/204/206
FIGURE 3-2: PIC10F204/206 BLOCK DIAGRAM
Program
Bus
Flash
512 x12 or
256 x12
Program
Memory
12
Instruction reg
Instruction
Decode &
Control
Timing
Generation
9-10
Program Counter
Direct Addr
8
Device Reset
Power-on
Watchdog
Internal RC
MCLR
Stack 1
Stack 2
Timer
Reset
Timer
Clock
VDD, VSS
RAM Addr
5
Data Bus
RAM
24 or 16
bytes
File
Registers
(1)
Addr MUX
3
ALU
8
W reg
9
Indirect
5-7
FSR reg
Status re g
MUX
Timer0
Addr
8
GPIO
Comparator
GP0/ICSPDAT
GP1/ICSPCLK
GP2/T0CKI/FOSC4
GP3/MCLR/VPP
CIN+
CINCOUT
2004 Microchip Technology Inc. Preliminary DS41239A-page 11
PIC10F200/202/204/206
TABLE 3-2: PIC10F200/202/204/206 PINOUT DESCRIPTION
Name Function
GP0/ICSPDA T/ CIN+ GP0 TTL CMOS Bidirectional I/O pin. Can be software programmed for i nternal
ICSPDAT ST CMOS In -Circu it Serial Programming
CIN+ AN — Comparator input (PIC10F204/206 only).
GP1/ICSPCLK/CIN- GP1 TTL CMOS Bidirectional I/O pin. Can be software programmed for i nternal
ICSPCLK ST CMOS In-Circuit Serial Programming clock pin.
CIN- AN — Comparator input (PIC10F204/206 only).
GP2/T0CKI/COUT/
FOSC4
GP3/MCLR
DD VDD P — Positive supply for logic and I/O pins.
V
VSS VSS P — Ground reference for logic and I/O pins.
Legend: I = Input, O = Output, I/O = Input/Output, P = Power, — = Not used, TTL = TTL input,
/VPP GP3 TTL — Input pin. Can be software programmed for internal weak
ST = Schmitt Trigger input, AN = Analog input
GP2 TTL CMOS Bidirectional I/O pin.
T0CKI ST — Clock input to TMR0.
COUT — CMOS Comparator output (PIC10F204/206 only).
FOSC4 — CMOS Oscillator/4 output.
MCLR
VPP HV — Programming voltage input.
Input
Type
Output
Type
weak pull-up and wake-up from Sleep on pin change.
weak pull-up and wake-up from Sleep on pin change.
pull-up and wake-up from Sleep on pin change.
ST — Master Clear (Reset). When configured as MCLR, this pin is
an active-low Rese t to the de vice. Voltage on GP3/M
must not exceed V
device will enter Programming mode. Weak pull-up alway s on
if configured as MCLR.
Description
™
data pin.
CLR/VPP
DD during normal device operation or the
DS41239A-page 12 Preliminary 2004 Microchip Technology Inc.
PIC10F200/202/204/206
3.1 Clocking Scheme/Instruction
Cycle
The clock is internally divided by four to generate four
non-overlapping quadrature clocks, namely Q1, Q2,
Q3 and Q4. Internal ly, the PC is incremented ev ery Q1
and the instruction is fetched from program memory
and latched into the instruction register in Q4. It is
decoded and execute d during the followin g Q1 throug h
Q4. The clocks and instruction execution flow is shown
in Figure 3-3 and Example 3-1.
FIGURE 3-3: CLOCK/INSTRUCTION CYCLE
Q2 Q3 Q4
OSC1
Q1
Q2
Q3
Q4
PC
Q1
PC PC+1 PC+2
Q1
3.2 Instruction Flow/Pipelining
An instruction cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute take another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the PC to change (e.g ., GOTO), t hen two c yc le s
are required to complete the ins tructi on (Exampl e 3-1).
A fetch cycle begins with the PC incrementing in Q1.
In the execution cy cle, the fetch ed instruction i s latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 c ycles. Dat a m emory is read during Q2
(operand read) and written during Q4 (destination
write).
Q2 Q3 Q4
Q1
Q2 Q3 Q4
Internal
phase
clock
Fetch INST (PC)
Execute INST (PC – 1)
Fetch INST (PC + 1)
Execute INST (PC)
Fetch INST (PC + 2)
Execute INST (PC + 1)
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
1. MOVLW 03H
2. MOVWF GPIO
3. CALL SUB_1
4. BSF GPIO, BIT1
All instructions are si ngle cycle, except for any program bra nches. These tak e two cycles, since th e fetch instruction
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
Fetch 1 Execute 1
Fetch 2 Execute 2
Fetch 3 Execute 3
Fetch 4 Flush
Fetch SUB_1 Execute SUB_1
2004 Microchip Technology Inc. Preliminary DS41239A-page 13
PIC10F200/202/204/206
NOTES:
DS41239A-page 14 Preliminary 2004 Microchip Technology Inc.
PIC10F200/202/204/206
4.0 MEMORY ORGANIZATION
The PIC10F200/202/204/206 memories are organized
into program memory and data memory. Data memory
banks are accessed using the File Select Register
(FSR).
4.1 Program Memory Organization for
the PIC10F200/204
The PIC10F200/204 devices have a 9-bit Program
Counter (PC) capable of addressing a 512 x 12
program memory space.
Only the first 256 x 12 (0000h-00FFh) for the
PIC10F200/204 are physically implemented (see
Figure 4-1). Accessing a location above these
boundaries will cause a wraparound within the first
256 x 12 space (PIC10F200/204). The effective
Reset vector is at 0000h (see Figure 4-1). Location
00FFh (PIC10F200/204) contains the interna l clock
oscillator calibration value. This value should never
be overwritten.
FIGURE 4-1: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC10F200/204
PC<7:0>
CALL, RETLW
Stack Level 1
Stack Level 2
Reset Vector
On-chip Program
Memory
Space
User Memory
256 Word
9
(1)
0000h
00FFh
0100h
Note 1: Address 0000h becomes the
effective Reset vector. Location
00FFh contains the MOVLW XX
internal oscillator calibration value.
01FFh
2004 Microchip Technology Inc. Preliminary DS41239A-page 15
PIC10F200/202/204/206
4.2 Program Memory Organization for
the PIC10F202/206
The PIC10F202/206 devices have a 10-bit Program
Counter (PC) capable of addressing a 1024 x 12
program memory space.
Only the first 512 x 12 (0000h-01FFh) for the
PIC10F202/206 are physically implemented (see
Figure 4-2). Accessing a location above these
boundaries will cause a wraparound within the first
512 x 12 space (PIC10F202/206). The effective
Reset vector is at 0000h (see Figure 4-2). Location
01FFh (PIC10F202/206) contains the interna l clock
oscillator calibration value. This value should never
be overwritten.
FIGURE 4-2: PROGRAM MEMORY MAP
AND STACK FOR TH E
PIC10F202/206
PC<8:0>
CALL, RETLW
Stack Level 1
Stack Level 2
Reset Vector
On-chip Program
Memory
10
(1)
0000h
4.3 Data Memory Organization
Data memory is composed of registers or bytes of
RAM. Therefore, da ta memory for a device is sp eci fie d
by its register file. The register file is divided into two
functional groups: Special Function Registers (SFR)
and General Purpose Registers (GPR).
The Special Function Regi st ers in cl ude the TMR0 register, the Program Counter (PCL), the Status register,
the I/O register (GPIO) and the File Select Register
(FSR). In addition, Special Func tion Registers are use d
to control the I/O port configuration and prescaler
options.
The General Purpose Registers are used for data and
control informatio n u nd er com ma nd of the instructions.
For the PIC10F200/204, the register file is composed of
7 Special Function Registers and 16 General Purpose
Registers (see Figure 4-3 and Figure 4-4).
For the PIC10F202/206, the register file is composed of
8 Special Function Registers and 24 General Purpose
Registers (see Figure 4-4).
4.3.1 GENERAL PURPOSE REGISTER
FILE
The General Purpose Register file is accessed, either
directly or indirectly, through the File Select Register
(FSR). See Section 4.9 “Indirect Data Addressing:
INDF and FSR Registers”.
Space
User Memory
512 Words
Note 1: Address 0000h becomes the
effective Reset vector. Location
01FFh contains the MOVLW XX
internal oscillator calibration value.
01FFh
0200h
02FFh
DS41239A-page 16 Preliminary 2004 Microchip Technology Inc.
PIC10F200/202/204/206
FIGURE 4-3: PIC10F200/204 REGISTER
FILE MAP
File Address
(1)
00h
01h
02h
03h
04h
05h
06h
07h
08h
0Fh
10h
1Fh
Note 1: Not a physical register. See Section 4.9
“Indirect Data Addressing: INDF and
FSR Registers”.
2: PIC10F204 only. Unimplemented on the
PIC10F200 and reads as 00h.
3: Unimplemented, read as 00h.
INDF
TMR0
PCL
STATUS
FSR
OSCCAL
GPIO
General
Purpose
Registers
(2)
CMCON0
Unimplemented
(3)
FIGURE 4-4: PIC10F202/206 REGISTER
FILE MAP
File Address
(1)
00h
01h
02h
03h
04h
05h
06h
07h
08h
18h
Note 1: Not a physical register. See Section 4.9
“Indirect Data Addressing: INDF and
FSR Registers”.
2: PIC10F206 only. Unimplemented on the
PIC10F202 and reads as 00h.
INDF
TMR0
PCL
STATUS
FSR
OSCCAL
GPIO
CMCON0
General
Purpose
Registers
(2)
2004 Microchip Technology Inc. Preliminary DS41239A-page 17
PIC10F200/202/204/206
4.3.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and per ipheral functio ns to con trol the
operation of the device (Table 4-1).
The Special Function Registers can be classified into
two sets. The Special Function Registers associated
with the “core” functions are described in this section.
Those related to the operation of the peripheral
features are described in the section for each
peripheral feature.
TABLE 4-1: SPECIAL FUNCTION REGISTER (SFR) SUMMARY (PIC10F200/202/204/206)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
00h INDF Uses Contents of FSR to Address Data Memory (not a physical register) xxxx xxxx 23
01h TMR0 8-bit Real-Time Clock/Counter xxxx xxxx 29, 33
(1)
02h
03h STATUS GPWUF CWUF
04h FSR Indirect Data Memory Address Pointer 111x xxxx 23
05h OSCCAL CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 FOSC4 1111 1110 21
06h GPIO
07h
N/A TRISGPIO
N/A OPTION GPWU
Legend: — = unimplemented, read as ‘0’, x = unknown, u = unchanged, q = value depends on condition.
Note 1: The upper byte of the Program Counter is not directly accessible. See S ection 4.7 “Program Counter” for an
PCL Low-order 8 bits of PC 1111 1111 22
(5)
—TOPD ZDCC00-1 1xxx
— — — — GP3 GP2 GP1 GP0 ---- xxxx 25
(4)
CMCON0 CMPOUT COUTEN POL CMPT0CS CMPON CNREF CPREF CWU 1111 1111 34
— — — — I/O Control Register ---- 1111 37
GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 20
explanation of how to access these bits.
2: Other (non Power-up) Resets include external Reset through MCLR
Reset.
3: See Table 9-1 for other Reset specific values.
4: PIC10F204/206 only.
5: PIC10F204/206 only. On all other devices, this bit is reserved and should not be used.
, Watchdog Timer and wake-up on pin change
Value on
Power-On
(2)
Reset
(3)
Page #
19
DS41239A-page 18 Preliminary 2004 Microchip Technology Inc.
PIC10F200/202/204/206
4.4 Status Register
This register contains the arithmetic status of the ALU,
the Reset status and the page preselect bit.
The Status register can be the destination for any
instruction, as with any other register. If the Status
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bit s are set or cleared ac cording to the
device logic. Furthermore, the TO
writable. Therefore, the result of an instruction with the
Status register as destination may be different than
intended.
and PD bits are not
For example, CLRF STATUS, will clear the upper three
bits and set the Z bit. Thi s leav es the Status register as
000u u1uu (where u = unchanged).
Therefore, it is recommended that only BCF, BSF and
MOVWF instructions be used to alter the Status register.
These instructions do no t affect the Z, DC or C bit s from
the Status register. For other instructions which do
affect Status bits, see Section 10.0 “Instruction Set
Summary”.
REGISTER 4-1: STATUS REGISTER (ADDRESS: 03h)
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
GPWUF CWUF
bit 7 bit 0
bit 7 GPWUF: GPIO Reset bit
1 = Reset due to wake-up from Sleep on pin change
0 = After power-up or other Reset
bit 6 CWUF: Comparator Wake-up on Change Flag Bit
1 = Reset due to wake-up from Sleep on comparator change
0 = After power-up or other Reset conditions.
bit 5 Reserved: Do not use. Use of this bit may affect upward compatibility with future products.
bit 4 TO
bit 3 PD
bit 2 Z: Zero bit
bit 1 DC: Digit carry/borrow
bit 0 C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions)
: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
ADDWF
:
1 = A carry from the 4th low-order bit of the result occurred
0 = A carry from the 4th low-order bit of the result did not occur
:
SUBWF
1 = A borrow from the 4th low-order bit of the result did not occur
0 = A borrow from the 4th low-order bit of the result occurred
ADDWF
: SUBWF: RRF or RLF:
1 = A carry occurred 1 = A borrow did not occur Load bit with LSb or MSb, respectively
0 = A carry did not occur 0 = A borrow occurred
(1)
—TO PD ZDCC
bit (for ADDWF and SUBWF instructions)
(1)
Note 1: This bit is used on the PIC10F204/206. For code compatibili ty do not use this bit on
the PIC10F200/202.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc. Preliminary DS41239A-page 19
PIC10F200/202/204/206
4.5 Option Register
The Option register is a 8-bit wide, write-only register,
which contains various control bits to configure the
Timer0/WDT prescaler and Timer0.
By executin g the OPTION instruction, the contents of
the W register will be transfe rred to the Option registe r.
A Reset sets the OPTION<7:0> bits.
REGISTER 4-2: OPTION REGISTER
W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1
GPWU
bit 7 bit 0
GPPU T0CS T0SE PSA PS2 PS1 PS0
Note: If TRIS bit is set to ‘0’, the wake-up on
change and pull-up functions are disabled
for that pin (i.e., note that TRIS overrides
Option control of GPPU
Note: If the T0CS bit is set to ‘1’, it will override
the TRIS function on the T0CKI pin.
and GPWU).
bit 7 GPWU
bit 6 GPPU
bit 5 T0CS: Timer0 Clock Source Select bit
bit 4 T0SE: Timer0 Source Edge Select bit
bit 3 PSA: Prescaler Assignment bit
bit 2-0 PS<2:0>: Prescaler Rate Select bits
: Enable Wake-up on Pin Change bit (GP0, GP1, GP3)
1 = Disabled
0 = Enabled
: Enable Weak Pull-ups bit (GP0, GP1, GP3)
1 = Disabled
0 = Enabled
1 = Transition on T0CKI pin (overrides TRIS on the T0CKI pin)
0 = Transition on internal instruction cycle clock, F
1 = Increment on high-to-low transition on the T0CKI pin
0 = Increment on low-to-high transition on the T0CKI pin
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to Timer0
Bit Value Timer0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
OSC/4
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
DS41239A-page 20 Preliminary 2004 Microchip Technology Inc.
PIC10F200/202/204/206
4.6 OSCCAL Register
The Oscillator Calibrati on (OSCCAL) register is used to
calibrate the internal precision 4 MHz oscillator. It
contains seven bit s for cal ibra tio n
Note: Erasing the device will also erase the pre-
programmed internal calibration value for
the internal oscillator. The calibration
value must be read prior to erasing the
part so it can be reprogrammed correctly
later.
After you move in the calibration constant, do not
change the value. See Section 9.2.2 “Internal 4 MHz
Oscillator”.
REGISTER 4-3: OSCCAL REGISTER (ADDRESS: 05h)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0
bit 7 bit 0
bit 7-1 CAL<6:0>: Oscillator Calibration bits
0111111 = Maximum frequency
•
•
•
0000001
0000000 = Center frequency
1111111
•
•
•
1000000 = Minimum frequency
bit 0 FOSC4: INTOSC/4 Output Enable bit
1 = INTOSC/4 output onto GP2
0 = GP2/T0CKI/COUT applied to GP2
.
CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 FOSC4
(1)
Note 1: Overrides GP2/T0CKI/COUT control registers when enabled.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc. Preliminary DS41239A-page 21
PIC10F200/202/204/206
4.7 Program Counter
As a program instruction is executed, the Program
Counter (PC) will contain the address of the next
program instruction to be executed. The PC value is
increased by one every instruction cycle, unless an
instruction changes the PC.
For a GOTO instruction, bits 8:0 of the PC are provided
by the GOTO instruction word. The Program Counter
(PCL) is mapped to PC<7:0>.
For a CALL instruction, or any instruction where the
PCL is the destinatio n, bits 7:0 of the PC ag ain are pr ovided by the instruction word. However, PC<8> does
not come from the instruction word, but is always
cleared (Figure 4-5).
Instructions wh ere the PCL is th e destinatio n, or modif y
PCL instructions, include MOVWF PC, ADDWF PC and
BSF PC,5.
Note: Because PC<8> is cleared in the CALL
instruction or any modify PCL instruction,
all subroutine calls or computed jumps are
limited to the first 256 locations of any
program memory page (512 words long).
FIGURE 4-5: LOADING OF PC
BRANCH INSTRUCTIONS
GOTO Instruction
87 0
PC
PCL
Instruction Wor d
4.7.1 EFFECTS OF RESET
The PC is set upon a Reset, which means that the PC
addresses the last location in program memory (i.e.,
the oscillator calibration instruction). After executing
MOVLW XX, the PC will roll over to location 0000h and
begin executing user code.
4.8 Stack
The PIC10F200/204 devi ce s have a 2-deep, 8-b it wid e
hardware PUSH/POP stack.
The PIC10F202/206 devi ce s have a 2-deep, 9-b it wid e
hardware PUSH/POP stack.
A CALL instruction will PUSH the current value of Stack 1
into Stack 2 and then PUSH the current PC value,
incremented by o ne , i nt o Stack Level 1. If m ore th an t w o
sequential CALLs are executed, o nly the mo st recen t two
return addresse s a r e s tor ed .
A RETLW instruction will POP the contents of Stack
Level 1 into the PC and then copy Stack Level 2
contents into level 1. If more than two sequential
RETLWs are execute d, the stack will be fi lled with the
address previously stored in Stack Level 2. Note that
the W register will be loaded with the literal value
specified in the i nstruction. Th is is particu larly useful for
the implementation of data look-up tables within the
program memory.
Note 1: There are no Status bits to indicate stack
overflows or stack underflow conditions.
2: There are no instruction mnemonics
called PUSH or POP. These are actions
that occur from the e xecution of the CALL
and RETLW instructions.
CALL or Modify PCL Instruction
87 0
PC
Reset to ‘0’
DS41239A-page 22 Preliminary 2004 Microchip Technology Inc.
PCL
Instruction Word
PIC10F200/202/204/206
4.9 Indirect Data Addressing: INDF
and FSR Registers
The INDF register is not a physical register.
Addressing INDF actually addresses the register
whose address is contain ed in the FS R reg ist er (FSR
is a pointer). This is indirect addr es sing.
4.10 Indirect Addressing
• Register file 09 contains the value 10h
• Register file 0A contains the value 0Ah
• Load the value 09 into the FSR register
• A read of the INDF register will return the value
of 10h
• Increment the value of the FSR register by one
(FSR = 0A)
• A read of the INDR register now will return the
value of 0Ah.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no operation (although Status bits may be affected).
A simple program to clear RAM locations 10h-1Fh
using indirect addressing is shown in Example 4-1.
EXAMPLE 4-1: HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
MOVLW 0x10 ;initiali ze pointer
MOVWF FSR ;to RAM
NEXT CLRF INDF ;cle a r I N D F
;register
INCF FSR,F ;inc pointer
BTFSC FSR,4 ;all done?
GOTO NEXT ;NO, clear next
CONTINUE
: ;YES, continue
:
The FSR is a 5-bit wide register. It is used in conjunction with the INDF regis ter to indirectly a ddress the dat a
memory area.
The FSR<4:0> bits are used to select data memory
addresses 00h to 1Fh.
Note: PIC10F200/202/204/206 – Do not use
banking. FSR <7:5> are unimplemented
and read as ‘1’s.
FIGURE 4-6: DIRECT/INDIRECT ADDRESSING (PIC10F200/202/204/206)
Direct Addressing
(opcode) 04
Location Select
00h
Data
Memory
Note 1: For register map detail, see Section 4.3 “D ata Memory Organization”.
0Fh
(1)
10h
1Fh
Bank 0
Indirect Addressing
(FSR)
4
Location Select
0
2004 Microchip Technology Inc. Preliminary DS41239A-page 23
PIC10F200/202/204/206
NOTES:
DS41239A-page 24 Preliminary 2004 Microchip Technology Inc.
PIC10F200/202/204/206
5.0 I/O PORT
As with any other register, the I/O register(s) can be
written and read under pro gram contro l. However, read
instructions (e.g., MOVF GPIO, W) always read the I/O
pins independent of the pin’s Input/Output modes. On
Reset, all I/O ports are defined as input (inputs are at
high-impedance) since the I/O control registers are all
set.
5.1 GPIO
GPIO is an 8-bit I/O register. Only the low-order 4 bits
are used (GP<3:0>). Bits 7 through 4 are unimplemented and read as ‘0’s. Please note that GP3 is an
input only pin. Pins GP0, GP1 and GP3 can be configured with weak pull-ups and also for wake-up on
change. The wake-up on change and weak pull-up
functions are not pin s electable. I f GP3/MCLR
ured as MCLR
, weak pull-up is always on and wake-up
on change for this pin is not enabled.
5.2 TRIS Registers
The Output Driver Control register is loaded with the
contents of the W register by executing the TRIS f
instruction. A ‘1’ from a TRIS register bi t puts the corresponding output driver in a High-impedance mode. A
‘0’ puts the contents of the output data latch on the
selected pins, enabling the output buffer. The exceptions are GP3, which is input only and the GP2/T0CKI/
COUT/FOSC4 pin, which may be contro lled by variou s
registers. See Table 5-1.
is config-
5.3 I/O Interfacing
The equivalent circuit for an I/O port pin is shown in
Figure 5-2. All port pins, except GP3 which is input
only , ma y be used for both in put and out put operati ons.
For input operations , the se ports are non-latching. Any
input must be present until read by an input instruction
(e.g., MOVF GPIO, W). The outputs are latched and
remain unchanged unt il t he outp ut latc h is rewri tten. To
use a port pin as output, the corresponding direction
control bit in TRIS must be cleared (= 0). For use as an
input, the corresponding TRIS bit must be set. Any I/O
pin (except GP3) can be programmed individually as
input or output.
FIGURE 5-1: PIC10F200/202/204/206
EQUIVALENT CIRCUIT
FOR A SINGLE I/O PIN
Data
Bus
WR
Port
W
Reg
TRIS ‘f’
D
D
Data
Latch
CK
TRIS
Latch
CK
Q
VDD
VDD
Q
Q
Q
P
N
SS
VSS
V
I/O
pin
Note: A read of the ports reads the pins, not the
output data latches. That is , if an output
driver on a pin is enab led and driv en high,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
The TRIS registers are “write-only” and are set (output
drivers disabled) upon Reset.
TABLE 5-1: ORDER OF PRECEDENCE
FOR PIN FUNCTIONS
Priority GP0 GP1 GP2 GP3
1 CIN+ CIN- FOSC4 I/M
2 TRIS GPIO TRIS GPIO COUT —
3
4
— —T0CKI—
— —TRIS GPIO—
CLR
Reset
Note 1: See Table 3-2 for buffer type.
(1)
RD Port
2004 Microchip Technology Inc. Preliminary DS41239A-page 25
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