Microchip Technology Microsemi SmartFusion2, Microsemi IGLOO2 User Manual

UG0446

User Guide

SmartFusion2 and IGLOO2 FPGA High Speed DDR

Interfaces

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50200446. 7.0 6/19

Contents

1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Revision 7.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Revision 6.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.3 Revision 5.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.4 Revision 4.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.5 Revision 3.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.6 Revision 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.7 Revision 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.8 Revision 0.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.2 Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3 MDDR Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.2 Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.3 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.4 I/O Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.5.1 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.5.2 Port List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.5.3 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.5.4 Details of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.5.5 MDDR Subsystem Features Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.6 How to Use MDDR in IGLOO2 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.6.1 Configuring MDDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.6.2 Accessing MDDR from FPGA Fabric through the AXI Interface . . . . . . . . . . . . . . . . . . . . . . . 43

3.6.3 Accessing MDDR from FPGA Fabric Through the AHB Interface . . . . . . . . . . . . . . . . . . . . . . 48

3.6.4 Accessing MDDR from the HPDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.7 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.8 Timing Optimization Technique for AXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.9 DDR Memory Device Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3.9.1 Example 1: Connecting 32-Bit DDR2 to MDDR_PADs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3.9.2 Example 2: Connecting 32-Bit DDR3 to MDDR_PADs with SECDED . . . . . . . . . . . . . . . . . . 59

3.9.3 Example 3: Connecting 16-Bit LPDDR to MDDR_PADs with SECDED . . . . . . . . . . . . . . . . . 60

3.10 Board Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.11 MDDR Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.11.1 SYSREG Configuration Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

3.11.2 DDR Controller Configuration Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

3.11.3 DDR Controller Configuration Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.11.4 PHY Configuration Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

3.11.5 PHY Configuration Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

3.11.6 DDR_FIC Configuration Registers Summary . . . . . . . .

3.11.7 DDR_FIC Configuration Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

3.12 Appendix A: How to Use the MDDR in SmartFusion2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

3.12.1 Design Flow Using System Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

3.12.2 Design Flow Using SmartDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

3.12.3 Use Model 1: Accessing MDDR from FPGA Fabric Through the AXI Interface . . . . . . . . . . 126

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Microsemi Proprietary UG0446 User Guide Revision 7.0 iii

3.12.4 Use Model 2: Accessing MDDR from FPGA Fabric Through the AHB Interface . . . . . . . . . . 128

3.12.5 Use Model 3: Accessing MDDR from Cortex-M3 Processor . . . . . . . . . . . . . . . . . . . . . . . . . 130

3.12.6 Use Model 4: Accessing MDDR from the HPDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

4 Fabric DDR Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

4.2 Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

4.3 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

4.4 I/O Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

4.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

4.5.1 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

4.5.2 Port List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

4.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

4.6.1 Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

4.6.2 ZQ Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

4.6.3 Details of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

4.6.4 FDDR Subsystem Features Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

4.6.5 Memory Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

4.6.6 Bus Width Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

4.6.7 Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

4.6.8 Configuring Dynamic DRAM Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

4.6.9 Dynamic DRAM Bank Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

4.6.10 Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

4.7 How to Use FDDR in IGLOO2 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

4.7.1 Configuring FDDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

4.7.2 Accessing FDDR from FPGA Fabric through the AXI Interface . . . . . . . . . . . . . . . . . . . . . . 166

4.7.3 Accessing FDDR from FPGA Fabric through the AHB Interface . . . . . . . . . . . . . . . . . . . . . . 171

4.8 DDR Memory Device Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

4.8.1 Example 1: Connecting 32-Bit DDR2 to FDDR_PADs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

4.8.2 Example 2: Connecting 32-Bit DDR3 to FDDR_PADs with SECDED . . . . . . . . . . . . . . . . . . 173

4.8.3 Example 3: Connecting 16-Bit LPDDR to FDDR_PADs with SECDED . . . . . . . . . . . . . . . . 174

4.9 FDDR Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

4.9.1 FDDR SYSREG Configuration Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

4.9.2 FDDR SYSREG Configuration Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

4.10 Appendix A: How to Use the FDDR in SmartFusion2 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

4.10.1 Design Flow Using System Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

4.10.2 Design Flow Using SmartDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

4.10.3 Use Model 1: Accessing FDDR from FPGA Fabric Through AXI Interface . . . . . . . . . . . . . . 196

4.10.4 Use Model 2: Accessing FDDR from FPGA Fabric Through AHB Interface . . . . . . . . . . . . . 199

4.11 Appendix B: Register Lock Bits Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

4.11.1 Lock Bit File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

4.11.2 Lock Bit File Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

4.11.3 Locking and Unlocking a Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

5 DDR Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

5.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

5.1.1 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

5.1.2 Details of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

5.2 How to Use DDR Bridge in IGLOO2 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

5.2.1 Configuring the DDR Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

5.2.2 High-Speed Data Transactions from HPDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

5.2.3 Selecting Non-Bufferable Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

5.3 SYSREG Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

5.4 DDR Bridge Control Registers in MDDR and FDDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

5.5 Appendix A: How to Use DDR Bridge in SmartFusion2 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

5.5.1 Use Model 1: High Speed Data Transactions from Cortex-M3 Processor . . . . . . . . . . . . . . 217

Microsemi Proprietary UG0446 User Guide Revision 7.0 iv

5.5.2 Use Model 2: Selecting Non-Bufferable Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

6 Soft Memory Controller Fabric Interface Controller . . . . . . . . . . . . . . . . . . . . . . . . 219

6.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

6.1.1 Port List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

6.2 How to Use SMC_FIC in IGLOO2 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

6.3 SYSREG Control Register for SMC_FIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

6.4 Appendix A: How to Use SMC_FIC in SmartFusion2 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

6.4.1 Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

6.4.2 Use Model 1: Accessing SDRAM from MSS Through CoreSDR_AXI . . . . . . . . . . . . . . . . . . 228

Microsemi Proprietary UG0446 User Guide Revision 7.0 v

Figures

Figure 1 System Level MDDR Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2 MDDR Subsystem Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3 Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 4 DDR_FIC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 5 AXI Transaction Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 6 DDR Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 7 DDR RMW Operation (32-Bit DDR Bus Width and Burst Length 8) . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 8 DDR RMW Operation (16-Bit DDR Bus Width and Burst Length 8) . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 9 DDR RMW Operation (8-Bit DDR Bus Width and Burst Length 8) . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 10 Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 11 System Builder—Device Features Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 12 MDR Initialization Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 13 I/O Drive Strength Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 14 Selecting I/O Standard as LVCMOS18 or LPDDRI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 15 Memory Initialization Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 16 Memory Timing Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 17 System Builder - Peripherals Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 18 MDDR_CLK Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 19 DDR_FIC_CLK Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 20 I/O Editor Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 21 MDDR with AXI Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 22 System Builder - Device Features Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 23 Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 24 Peripherals Tab with the Master Added and Configure Icon Highlighted . . . . . . . . . . . . . . . . . . . . 46

Figure 25 AMBA Master Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 26 System Clocks Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 27 SmartDesign Connections (Top Level View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 28 MDDR with Single AHB-Lite Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 29 MDDR with HPDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 30 System Builder - Device Features Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 31 Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 32 Clocks Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 33 AXI Single Write Transaction and Corresponding DDR Controller Commands . . . . . . . . . . . . . . . 52

Figure 34 DDR Controller Command Sequence for Single AXI Write Transaction . . . . . . . . . . . . . . . . . . . . . 52

Figure 35 AXI Single Read Transaction and Corresponding DDR Controller Commands . . . . . . . . . . . . . . . 53

Figure 36 AXI INCR16 Write Transaction and Corresponding DDR Controller Commands . . . . . . . . . . . . . . 53

Figure 37 AXI INCR16 Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 38 DDR Controller Command Sequence for AXI INCR16 Write Transaction . . . . . . . . . . . . . . . . . . . 54

Figure 39 AXI INCR-16 Read Transaction and Corresponding DDR Controller Commands . . . . . . . . . . . . . 54

Figure 40 DDR Controller Command Sequence for AXI INCR-16 Read Transaction . . . . . . . . . . . . . . . . . . 55

Figure 41 AXI Timing Optimization Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 42 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 43 x16 DDR2 SDRAM Connected to MDDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 44 ×8 DDR3 SDRAM Connection to MDDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 45 ×16 LPDDR1 SDRAM Connection to MDDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 46 System Builder - Device Features Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 47 MSS External DDR Memory Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 48 I/O Drive Strength Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 49 Selecting I/O Standard as LVCMOS18 or LPDDRI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 50 DDR Memory initialization Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 51 DDR Memory Timing Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 52 MSS DDR FIC Subsystem Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 53 MDDR Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 54 DDR_FIC Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

. . . . . . . . 46

. . . . . . 117

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Figure 55 Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 56 MDDR Configurator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 57 Memory Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Figure 58 MSS External DDR Memory Configurator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Figure 59 MDDR Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 60 MDDR Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 61 FIC_2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Figure 62 I/O Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Figure 63 MDDR with AXI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Figure 64 MSS External Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 65 Configuring FIC_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 66 MDDR Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 67 SmartDesign Canvas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 68 MDDR with Single AHB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Figure 69 MDDR with Dual AHB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Figure 70 Accessing MDDR from Cortex-M3 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Figure 71 MSS External Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Figure 72 Configuring MDDR_CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Figure 73 Accessing MDDR from HPDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Figure 74 System Level FDDR Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Figure 75 FDDR Subsystem Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Figure 76 Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Figure 77 DDR_FIC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Figure 78 AXI Transaction Controller Block Diagram . . . . . . .

Figure 79 DDR Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Figure 80 Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Figure 81 System Builder - Device Features Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Figure 82 System Builder - Device Features Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Figure 83 Fabric DDR Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Figure 84 Selecting I/O Standard as LVCMOS18 or LPDDRI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Figure 85 Memory Initialization Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Figure 86 Memory Timing Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Figure 87 System Builder - Peripherals Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Figure 88 FDDR Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Figure 89 I/O Editor Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Figure 90 FDDR Subsystem with AXI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Figure 91 System Builder - Device Features Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Figure 92 Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Figure 93 Fabric DDR Subsystem Configuration Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Figure 94 AMBA Master Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Figure 95 Clocks Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Figure 96 SmartDesign Connections (Top Level View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Figure 97 FDDR with AHB-Lite interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Figure 98 x16 DDR2 SDRAM Connected to FDDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Figure 99 x8 DDR3 SDRAM Connection to FDDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Figure 100 x16 LPDDR1 SDRAM Connection to FDDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Figure 101 System Builder - Device Features Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Figure 102 MSS External DDR Memory Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Figure 103 Fabric DDR Memory Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Figure 104 Selecting I/O Standard as LVCMOS18 or LPDDRI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Figure 105 DDR Memory initialization Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Figure 106 DDR Memory Timing Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Figure 107 MSS DDR FIC Subsystem Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Figure 108 FDDR Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Figure 109 Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Figure 110 Fabric External Memory DDR Controller Configurator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Figure 111 FIC Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Figure 112 I/O Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Figure 113 FDDR with AXI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

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Figure 114 FDDR Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Figure 115 Fabric CCC Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Figure 116 SmartDesign Canvas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Figure 117 Accessing FDDR Subsystem Through Dual AHB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Figure 118 FIC_2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Figure 119 MSS CCC Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Figure 120 FDDR Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Figure 121 Fabric CCC Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Figure 122 CoreConfigP IP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Figure 123 CoreConfigP IP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Figure 124 SmartDesign Canvas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Figure 125 Lock Bit Configuration File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Figure 126 Register Lock Bit Settings Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Figure 127 DDR Bridges in the SmartFusion2/IGLOO2 FPGA Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Figure 128 DDR Bridge Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Figure 129 WCB Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Figure 130 Flow Chart for Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Figure 131 System Builder - Device Features Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Figure 132 Configuring HPMS DDR Bridge for HPDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Figure 133 Configuring HPMS DDR Bridge For Non-Bufferable Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Figure 134 Configuring DDR Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Figure 135 Configuring MSS DDR Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Figure 136 Configuring MSS DDR Bridge for Use Model 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Figure 137 Configuring MSS DDR Bridge for Use Model 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Figure 138 System Level SMC_FIC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

Figure 139 SMC_FIC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 140 HPMS External Memory Configurator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Figure 141 HPMS SMC_FIC Subsystem Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

Figure 142 CoreSDR_AXI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

Figure 143 MSS External Memory Configurator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Figure 144 Core_AXI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Figure 145 Subsystem Connections in SmartDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

. . . . . . . . 220

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Tables

Table 1 Additional Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Table 2 Supported Memory (DDR2, DDR3 and LPDDR1) Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3 DDR Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 4 I/O Utilization for SmartFusion2 and IGLOO2 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 5 MDDR Subsystem Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 6 AXI Slave Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 7 AHB Slave Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 8 MDDR APB Slave Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 9 MDDR_CLK to FPGA Fabric Clock Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 10 Priority Level Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 11 SECDED DQ Lines at DDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 12 Supported Bus Widths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 13 Supported Burst Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 14 Dynamically Enforced Bank Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 15 Dynamically-Enforced Bank Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 16 Dynamic DRAM Global Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 17 DDR Memory Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 18 Accessed DDR Memory Regions (Based on Mode Settings for 4 GB Memory) . . . . . . . . . . . . . . 31

Table 19 Accessed DDR Memory Regions Based on Mode Settings for a 2 GB Memory . . . . . . . . . . . . . . 32

Table 20 Accessed DDR Memory Regions Based on Mode Settings for a 1 GB Memory . . . . . . . . . . . . . . 32

Table 21 Supported Address Width Range for Row, Bank and Column Addressing in DDR/LPDDR . . . . . . 35

Table 22 DDR I/O Standard is Configured Based on I/O Drive Strength Setting . . . . . . . . . . . . . . . . . . . . . 35

Table 23 MDDR Throughput (for AHB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 24 Number of Cycles for AXI/AHB Transactions to MDDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 25 I/O Standards and Calibration Resistance Requirements for MDDR/FDDR . . . . . . . . . . . . . . . . . 61

Table 26 Address Table for Register Interfaces . . . . . . . .

Table 27 SYSREG Configuration Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 28 DDR Controller Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 29 DDRC_DYN_SOFT_RESET_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 30 DDRC_DYN_REFRESH_1_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 31 DDRC_DYN_REFRESH_2_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 32 DDRC_DYN_POWERDOWN_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 33 DDRC_MODE_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 34 DDRC_ADDR_MAP_BANK_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 35 DDRC_ADDR_MAP_COL_1_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 36 DDRC_ADDR_MAP_COL_2_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 37 DDRC_ADDR_MAP_ROW_1_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 38 DDRC_ADDR_MAP_ROW_2_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 39 DDRC_INIT_1_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 40 DDRC_CKE_RSTN_CYCLES_1_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 41 DDRC_ CKE_RSTN_CYCLES_2_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 42 DDRC_INIT_MR_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 43 DDRC_INIT_EMR_CR . . . . . . . . . . . . . . . . . . .

Table 44 DDRC_INIT_EMR2_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 45 DDRC_INIT_EMR3_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 46 DDRC_DRAM_BANK_TIMING_PARAM_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 47 DDRC_DRAM_RD_WR_LATENCY_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 48 DDRC_DRAM_RD_WR_PRE_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 49 DDRC_DRAM_MR_TIMING_PARAM_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 50 DDRC_DRAM_RAS_TIMING_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 51 DDRC_DRAM_RD_WR_TRNARND_TIME_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 52 DDRC_DRAM_T_PD_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 53 DDRC_DRAM_BANK_ACT_TIMING_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 54 DDRC_ODT_PARAM_1_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

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Table 55 DDRC_ODT_PARAM_2_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 56 DDRC_ADDR_MAP_COL_3_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 57 DDRC_MODE_REG_RD_WR_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 58 DDRC_MODE_REG_DATA_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 59 DDRC_PWR_SAVE_1_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 60 DDRC_PWR_SAVE_2_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 61 DDRC_ZQ_LONG_TIME_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 62 DDRC_ZQ_SHORT_TIME_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 63 DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_1_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 64 DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_2_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 65 DDRC_PERF_PARAM_1_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 66 DDRC_HPR_QUEUE_PARAM_1_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 67 DDRC_HPR_QUEUE_PARAM_2_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 68 DDRC_LPR_QUEUE_PARAM_1_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 69 DDRC_LPR_QUEUE_PARAM_2_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 70 DDRC_WR_QUEUE_PARAM_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 71 DDRC_PERF_PARAM_2_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 72 DDRC_PERF_PARAM_3_CR . . . . . . . . . . . . . . . . .

Table 73 DDRC_DFI_RDDATA_EN_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 74 DDRC_DFI_MIN_CTRLUPD_TIMING_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 75 DDRC_DFI_MAX_CTRLUPD_TIMING_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 76 DDRC_DYN_SOFT_RESET_ALIAS_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 77 DDRC_AXI_FABRIC_PRI_ID_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 78 DDRC_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 79 DDRC_SINGLE_ERR_CNT_STATUS_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 80 DDRC_DOUBLE_ERR_CNT_STATUS_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 81 DDRC_LUE_SYNDROME_1_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 82 DDRC_LUE_SYNDROME_2_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 83 DDRC_LUE_SYNDROME_3_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 84 DDRC_LUE_SYNDROME_4_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 85 DDRC_LUE_SYNDROME_5_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 86 DDRC_LUE_ADDRESS_1_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 87 DDRC_LUE_ADDRESS_2_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 88 DDRC_LCE_SYNDROME_1_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 89 DDRC_LCE_SYNDROME_2_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 90 DDRC_LCE_SYNDROME_3_SR . . . . . . . . . . . . . . . .

Table 91 DDRC_LCE_SYNDROME_4_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 92 DDRC_LCE_SYNDROME_5_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 93 DDRC_LCE_ADDRESS_1_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 94 DDRC_LCE_ADDRESS_2_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 95 DDRC_LCB_NUMBER_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 96 DDRC_LCB_MASK_1_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 97 DDRC_LCB_MASK_2_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 98 DDRC_LCB_MASK_3_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 99 DDRC_LCB_MASK_4_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 100 DDRC_ECC_INT_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 101 DDRC_ECC_INT_CLR_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 102 PHY Configuration Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 103 PHY_DATA_SLICE_IN_USE_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 104 DDR_FIC Configuration Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 105 DDR_FIC_NB_ADDR_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 106 DDR_FIC_NBRWB_SIZE_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 107 DDR_FIC_BUF_TIMER_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 108 DDR_FIC_HPD_SW_RW_EN_CR . . . . . . . . . . . . . . .

Table 109 DDR_FIC_HPD_SW_RW_INVAL_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 110 DDR_FIC_SW_WR_ERCLR_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 111 DDR_FIC_ERR_INT_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 112 DDR_FIC_NUM_AHB_MASTERS_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 113 DDR_FIC_HPB_ERR_ADDR_1_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

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Table 114 DDR_FIC_HPB_ERR_ADDR_2_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 115 DDR_FIC_SW_ERR_ADDR_1_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 116 DDR_FIC_SW_ERR_ADDR_2_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 117 DDR_FIC_HPD_SW_WRB_EMPTY_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Table 118 DDR_FIC_SW_HPB_LOCKOUT_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Table 119 DDR_FIC_SW_HPD_WERR_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 120 DDR_FIC_LOCK_TIMEOUTVAL_1_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 121 DDR_FIC_LOCK_TIMEOUTVAL_2_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 122 DDR_FIC_LOCK_TIMEOUT_EN_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Table 123 DDR_FIC_RDWR_ERR_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Table 124 DDR I/O Standard Configured Based on I/O Drive Strength Setting . . . . . . . . . . . . . . . . . . . . . . 114

Table 125 Supported Memory (DDR2, DDR3, and LPDDR1) Configurations . . . . . . . . . . . . . . . . . . . . . . . . 135

Table 126 DDR Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Table 127 I/O Utilization for SmartFusion2 and IGLOO2 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Table 128 FDDR Subsystem Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Table 129 FDDR AXI Slave Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Table 130 FDDR AHB Slave Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Table 131 FDDR APB Slave Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Table 132 FDDR_CLK to FPGA Fabric Clock Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Table 133 SECDED DQ Lines at DDR . . . . . . . . . . . . . . .

Table 134 Supported Bus Widths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 135 Supported Burst Modes for M2S150 and M2GL150 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 136 Dynamically Enforced Bank Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 137 Dynamically Enforced Bank Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Table 138 Dynamic DRAM Global Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Table 139 Supported Address Width Range for Row, Bank and Column . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Table 140 DDR I/O Standard is Configured based on I/O Drive Strength Setting . . . . . . . . . . . . . . . . . . . . . 160

Table 141 FDDR Throughput (for AHB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Table 142 Address Table for Register Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Table 143 FDDR SYSREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Table 144 PLL_CONFIG_LOW_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Table 145 PLL_CONFIG_LOW_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Table 146 PLL_CONFIG_HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Table 147 FDDR_FACC_CLK_EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Table 148 FDDR_FACC_MUX_CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Table 149 FDDR_FACC_DIVISOR_RATIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Table 150 PLL_DELAY_LINE_SEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Table 151 FDDR_SOFT_RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Table 152 FDDR_IO_CALIB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Table 153 FDDR_INTERRUPT_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Table 154 F_AXI_AHB_MODE_SEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Table 155 PHY_SELF_REF_EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Table 156 FDDR_FAB_PLL_CLK_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Table 157 FDDR_FPLL_CLK_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Table 158 FDDR_INTERRUPT_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Table 159 FDDR_IO_CALIB_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Table 160 FDDR_FATC_RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Table 161 Supported Address Width Range for Row, Bank and Column Addressing in DDR/LPDDR . . . . . 186

Table 162 DDR I/O Standard is Configured Based on I/O Drive Stre

Table 163 SmartFusion2 and IGLOO2 FPGA DDR Bridge Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Table 164 SYSREG Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Table 165 DDR Bridge Control Registers in MDDR and FDDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Table 166 SMC_FIC 64-bit AXI Port List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Table 167 SMC_FIC 32-bit AHB-Lite Port List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Table 168 MDDR_CR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

ngth Setting . . . . . . . . . . . . . . . . . . . . 186

Microsemi ProprietaryUG0446 User Guide Revision 7.0 xi

Revision History

1 Revision History

The revision history describes the changes that were implemented in the document. The changes are
listed by revision, starting with the most current publication.

1.1 Revision 7.0

The following is a summary of the changes in this revision.

• Read and Write leveling is not supported. Removed information about all the Read and Write
leveling registers.

• Most of the PHY registers have been reserved.

1.2 Revision 6.0

The following is a summary of the changes in this revision.

• Updated I/O Utilization, page 7, I/O Utilization, page 136, DDRIO Calibration, page 16, and DDRIO

Calibration, page 145 (SAR 81073).

1.3 Revision 5.0

The following is a summary of the changes in this revision.

• Updated MDDR Subsystem, page 5 and Fabric DDR Subsystem, page 134 (SARs 62955 and

62858).

• Updated Table 2, page 7, Ta bl e 4 , page 7, Table 11, page 24 (SAR 78912).

• Updated Initialization, page 16 and Power Saving Modes, page 24 (SAR 52819).

• Updated Table 86, page 95, Table 87, page 95, Table 93, page 99, Table 94, page 99 (SAR 75057).

• Updated Architecture Overview, page 136 (SAR 79005).

• Added DDR Memory Initialization Time, page 18 (SAR 72725).

• Updated Appendix B: Register Lock Bits Configuration, page 204 (SAR 79864).

1.4 Revision 4.0

The following is a summary of the changes in this revision.

• Merged SmartFuion2 and IGLOO2 User Guides.

• Updated Additional Documentation, page 3 (SAR 68482).

• Updated MDDR Subsystem, page 5 and Fabric DDR Subsystem, page 134 (SARs 55467, 54300,
49186, 52819, 54053, 51933, 55041, 52727, 48832).

• Updated MDDR Subsystem, page 5 (SARs 62441, 66225, 60914, 69568, 66860, 69611, 69261,
68400, 64575, 65164, and 69655).

• Updated Fabric DDR Subsystem, page 134 (SARs 62441, 60914, 66860, 69144, and 54429).

• Updated DDR Bridge, page 207.

• Updated Soft Memory Controller Fabric Interface Controller, page 219.

1.5 Revision 3.0

The following is a summary of the changes in this revision.

• Updated the Part Numbers (M2S075 to M2S090, M2S080 to M2S100, and M2S120 to M2S150) as
required (SAR 47554).

• Updated MDDR Subsystem, page 5 (SARs 47919, 48832, 49947, 50561, 50732, 62858, and

62955).

• Updated Fabric DDR Subsystem, page 134 (SARs 62858 and 62955).

• Updated Soft Memory Controller Fabric Interface Controller, page 219 (SAR 48330).

1.6 Revision 2.0

The following is a summary of the changes in this revision.

Microsemi Proprietary UG0446 User Guide Revision 7.0 1

Revision History

• Restructured the user guide (SARs 47314, 45974, 45616, 43424, 46149, 46446).

• Updated MDDR Subsystem, page 5 (SARs 55041, 58032, 51465, 58034, 58035, 58037, 51933,
58038, 57034, and 57207).

• Updated Fabric DDR Subsystem, page 134 (SARs 58034, 58035, 58037, 51933, 58038, 57034,
57207, and 58038).

• Updated Soft Memory Controller Fabric Interface Controller, page 219 (SAR 54036).

• Updated MDDR Memory Map, page 30 (SAR 44198).

• Updated Address Mapping, page 155 (SAR 45761).

1.7 Revision 1.0

The following is a summary of the changes in this revision.

• Restructured the user guide.

• Updated the user guide (SAR 42443).

• Updated MDDR Subsystem, page 5, Fabric DDR Subsystem, page 134, and DDR Bridge, page 207
(SAR 50157).

• Updated MDDR Subsystem, page 5 and Fabric DDR Subsystem, page 134 (SAR 41901).

• Updated MDDR Subsystem, page 5 (SAR 42751).

• Updated Fabric DDR Subsystem, page 134 (SAR 41979).

1.8 Revision 0.0

The first publication of this document.

Microsemi Proprietary UG0446 User Guide Revision 7.0 2

Overview

2 Overview

This user guide describes the high speed memory interfaces in SmartFusion®2 System-on-Chip (SoC)
field programmable gate array (FPGA) and IGLOO
microcontroller/memory subsystem double-data rate (MDDR) subsystem and fabric DDR (FDDR)
subsystem provide access to DDR memories for high-speed data transfers. The DDR subsystems
functionality, configurations, and their use models are discussed in this user guide.

®

2 FPGA devices. The high speed interfaces

2.1 Contents

This user guide contains the following chapters:

• "MDDR Subsystem"

• "Fabric DDR Subsystem"

• "DDR Bridge"

• "Soft Memory Controller Fabric Interface Controller"

2.2 Additional Documentation

The following table describes additional documentation available for the SmartFusion2 and IGLOO2
devices. For more information, refer to the SmartFusion2 Documentation Page and IGLOO2

Documentation Page online. (continued)

Table 1 • Additional Documents

Document Description

PB0115: SmartFusion2 System-on-Chip FPGAs
Product Brief and PB0121: IGLOO2 FPGA Product
Brief

DS0128: IGLOO2 and SmartFusion2 Datasheet This datasheet contains SmartFusion2 and IGLOO2 DC and

DS0124: IGLOO2 Pin Descriptions Datasheet This document contains IGLOO2 pin descriptions, package

DS0115: SmartFusion2 Pin Descriptions Datasheet This document contains SmartFusion2 pin descriptions, package

UG0445: IGLOO2 FPGA and SmartFusion2 SoC
FPGA Fabric User Guide

UG0331: SmartFusion2 Microcontroller Subsystem
User Guide

UG0448: IGLOO2 High Performance Memory
Subsystem User Guide

This product brief provides an overview of SmartFusion2 and
IGLOO2 family, features, and development tools.

switching characteristics.

outline drawings, and links to pin tables in Excel format.

outline drawings, and links to pin tables in Excel format.
SmartFusion2 and IGLOO2 FPGAs integrate fourth generation

flash-based FPGA fabric. The FPGA fabric is comprised of Logic
Elements which consist of a 4 input look up table (LUT), includes
embedded memories and Mathblocks for DSP processing
capabilities. This document describes the SmartFusion2 and
IGLOO2SmartFusion2 and IGLOO2 FPGA fabric architecture,
embedded memories, Mathblocks, fabric routing, and I/Os.

SmartFusion2 devices integrate a hard microcontroller
subsystem (MSS). The MSS consists of a ARM Cortex-M3
processor with embedded trace macrocell (ETM), instruction
cache, embedded memories, DMA engines, communication
peripherals, timers, real-time counter (RTC), general purpose
I/Os, and FPGA fabric interfaces. This document describes the
SmartFusion2 MSS and its internal peripherals.

IGLOO2 devices integrate a hard high performance memory
subsystem (HPMS) consists of embedded memories, DMA
engines, and FPGA fabric interfaces. This document describes
the IGLOO2 HPMS and its internal peripherals.

Microsemi Proprietary UG0446 User Guide Revision 7.0 3

Overview

Table 1 • Additional Documents (continued)

Document Description

UG0447: IGLOO2 and SmartFusion2 High Speed
Serial Interfaces User Guide

SmartFusion2 and IGLOO2 devices integrate hard high-speed
serial interfaces (PCIe, XAUI/XGXS, SERDES). This document
describes the SmartFusion2 and IGLOO2SmartFusion2 and
IGLOO2 high-speed serial interfaces.

UG0449: SmartFusion2 and IGLOO2 Clocking
Resources User Guide

SmartFusion2 and IGLOO2 clocking resources include on-chip
oscillators, FPGA fabric global network, and clock conditioning
circuitry (CCCs) with dedicated phase-locked loops (PLLs).
These clocking resources provide flexible clocking schemes to
the on-chip hard IP blocks—HPMS, fabric DDR (FDDR)
subsystem, and high-speed serial interfaces (PCIe, XAUI/XGXS,
SERDES)—and logic implemented in the FPGA fabric.

UG0444: SmartFusion2 and IGLOO2 Low Power
Design User Guide

In addition to low static power consumption during normal
operation, the SmartFusion2 and IGLOO2 devices support an
ultra-low-power Static mode (Flash*Freeze mode) with power
consumption less than 1 mW. Flash*Freeze mode retains all the
SRAM and register data which enables fast recovery to Active
mode. This document describes the SmartFusion2 and IGLOO2
Flash*Freeze mode entry and exit mechanisms.

UG0443: SmartFusion2 and IGLOO2 FPGA
Security and Reliability User Guide

The SmartFusion2 and IGLOO2 devices incorporate essentially
all the security features that made third generation Microsemi
SoC devices the gold standard for security in the PLD industry.
Also included are unique design and data security features and
use models new to the PLD industry. SmartFusion2 and IGLOO2
flash-based FPGA fabric has zero FIT configuration rate due to
its single event upset (SEU) immunity, which is critical in reliability
applications. This document describes the SmartFusion2 and
IGLOO2 security features and error detection and correction
(EDAC) capabilities.

UG0450: SmartFusion2 SoC and IGLOO2 FPGA
System Controller User Guide

The system controller manages programming of the
SmartFusion2 and IGLOO2 devices and handles system service
requests. The subsystems, interfaces, and system services in the
system controller are discussed in this user guide.

UG0450: SmartFusion2 SoC and IGLOO2 FPGA
System Controller User Guide

Describes different programming modes supported in the
SmartFusion2 and IGLOO2 devices. High level schematics of
these programming methods are also provided as a reference.
Important board-level considerations are discussed.

®

Libero SoC User Guide Libero

System-on-Chip (SoC) is the most comprehensive and
powerful FPGA design and development software available,
providing start-to-finish design flow guidance and support for
novice and experienced users alike. Libero SoC combines
Microsemi SoC Products Group tools with such EDA
powerhouses as Synplify
discusses the usage of the software and design flow.

and ModelSim. This user guide

Microsemi Proprietary UG0446 User Guide Revision 7.0 4

MDDR Subsystem

3 MDDR Subsystem

The MDDR is a hardened ASIC block for interfacing the DDR2, DDR3, and LPDDR1 memories. The
MDDR subsystem is used to access DDR memories for high-speed data transfers and code execution.,
and includes a DDR memory controller, DDR PHY, and arbitration logic to support multiple masters. DDR
memory connected to the MDDR subsystem can be accessed by the MSS/HPMS masters and master
logic implemented in the FPGA fabric (FPGA fabric master).

The MSS/HPMS masters communicate with the MDDR subsystem through an MSS/HPMS DDR bridge
that provides an efficient access path. FPGA fabric masters communicate with the MDDR subsystem
through AXI or AHB interfaces.

3.1 Features

• Integrated on-chip DDR memory controller and PHY

• Capable of supporting LPDDR1, DDR2, and DDR3 memory devices

• Up to 667 Mbps (333.33 MHz DDR) performance

• Supports memory densities upto 4GB

• Supports 8/16/32-bit DDR standard dynamic random access memory (SDRAM) data bus width
modes

• Supports a maximum of 8 memory banks

• Supports single rank memory

• Single error correction and double error detection (SECDED) enable/disable feature

• Supports DRAM burst lengths of 4, 8, or 16, depending on the bus-width mode and DDR type
configuration

• Support for sequential and interleaved burst ordering

• Programs internal control for ZQ short calibration cycles for DDR3 configurations

• Supports dynamic scheduling to optimize bandwidth and latency

• Supports self refresh entry and exit on command

• Supports deep power-down entry and exit on command

• Flexible address mapper logic to allow application specific mapping of row, column, bank, and rank
bits

• Configurable support for 1T or 2T timing on the DDR SDRAM control signals

• Supports autonomous DRAM power-down entry and exit caused by lack of transaction arrival for
programmable time

The following illustration shows the system level block diagram of the MDDR subsystem.

Microsemi Proprietary UG0446 User Guide Revision 7.0 5

MDDR Subsystem

Cache

Controller

SD IC

Cortex-M3

Microcontroller

SD I

IDC

DS

FIC_0 FIC_1

AHB Bus Matrix

DDR

I/O

FPGA Fabric

AXI/AHB

Master

MSS/HPMS
DDR
Bridge

SmartFusion2/IGLOO2

Blocks in SmartFusion2

DDR

Controller

DDR
PHY

APB Config.

Register

MDDR

AXI

Transaction

Controller

DDR_FIC

64-Bit AXI

HPDMA

MSS/HPMS

DDR

SDRAM

APB

Master

64-Bit AXI /

Single 32-Bit AHBL /

Dual 32-Bit AHBL

16-Bit APB

APB_2

Figure 1 • System Level MDDR Block Diagram

The MDDR subsystem accepts data transfer requests from AXI or AHB interfaces. Any read/write
transactions to the DDR memories can occur from the following four paths:

• High performance DMA (HPDMA) controller can access DDR memories through the MSS/HPMS
DDR bridge for high speed data transactions.

• Other MSS/HPMS masters (for example, FIC_0, FIC_1, and PDMA) can access DDR memories
through the MSS/HPMS DDR bridge.

• AXI or AHBL masters in the FPGA fabric can access DDR memories through DDR_FIC interface.

Note: The Cortex-M3 processor can access DDR memories through the MSS DDR bridge for data and code

execution in SmartFusion2.

Note: The maximum DDR3 data rate supported by MDDR is 333MHz/667Mbps. Therefore, Write Leveling is

not mandatory and the interface works if the board layout includes length matching and follows AC393

SmartFusion2 and IGLOO2 Board Design Guidelines Application Note. For Read Leveling, Libero SOC

auto-generates pre-defined static delay ratios for MDDR initialization. These delay values are sufficient if
the board layout follows the SmartFusion2/IGLOO2 board-level guidelines.

3.2 Memory Configurations

The SmartFusion2 and IGLOO2 FPGA MDDR subsystem supports a wide range of common memory
types, configurations, and densities, as shown in the following table. If SECDED mode is enabled in the
MDDR controller, the external memory module must be connected to the following:

• Data lines MDDR_DQ_ECC[3:0] when data width is x32

• Data lines MDDR_DQ_ECC[1:0] when data width is x16

Microsemi Proprietary UG0446 User Guide Revision 7.0 6

MDDR Subsystem

• Data line MDDR_DQ_ECC[0] when data width is x8

Table 2 • Supported Memory (DDR2, DDR3 and LPDDR1) Configurations

SmartFusion2 and IGLOO2 Devices

Width

(in
Memory
Depth Width

128M or
Less

256M ×32 ×36 – – ✔✔

512M ×32 ×36 – – ✔✔

1G ×32 ×36 – – ✔✔

×32 ×36 – – ✔✔
×16 ×18 ✔✔✔✔
×8 ×9 ✔ ––✔

×16 ×18 ✔✔✔✔
×8 ×9 ✔ ––✔

×16 ×18 ✔✔✔✔
×8 ×9 ✔ ––✔

×16 ×18 ✔✔✔✔
x8 ×9 ✔ ––✔

SECDED

Mode)

M2S/M2GL
005/010/025/060/090
M2S/M2GL150­FCV484

M2S/M2GL 050
(FCS325,
VF400, FG484)

M2S/M2GL 050
(FG896) M2S/M2GL150(FC1152)

3.3 Performance

The following table shows the maximum data rates supported by MDDR subsystem for supported
memory types.

For more Information, refer to the "DDR Memory Interface Characteristics" section in DS0128: IGLOO2

FPGA and SmartFusion2 SoC FPGA Datasheet.

Table 3 • DDR Speeds

Memory Type Maximum Data Rate (Mbps)

LPDDR1 400 Mbps (200 MHz)
DDR2 667 Mbps (333.33 MHz)
DDR3 667 Mbps (333.33 MHz)

3.4 I/O Utilization

The following table lists the I/O utilization for the SmartFusion2 and IGLOO2 devices corresponding to
supported bus widths. The remaining I/Os in Bank 0 can be used for general purposes.

Table 4 • I/O Utilization for SmartFusion2 and IGLOO2 Devices

M2S/M2GL005/010/025/060/0
MDDR Bus
Width

36-bit – – Bank0 (85 pins) Bank2 (85 pins)
32-bit – – Bank0 (76 pins) Bank2 (76 pins)
18-bit Bank0 (59 pins) Bank0 (59 pins) Bank0 (59 pins) Bank2 (59 pins)

90

M2S/M2GL150-FCV484

M2S/M2GL 050
(FCS325, VF400,
FG484)

M2S/M2GL 050
(FG896)

M2S/M2GL 150
(FC1152)

Microsemi Proprietary UG0446 User Guide Revision 7.0 7

MDDR Subsystem

Table 4 • I/O Utilization for SmartFusion2 and IGLOO2 Devices

16-bit Bank0 (53 pins) Bank0 (53 pins) Bank0 (53 pins) Bank2 (53 pins)

9-bit Bank0 (47 pins) – – Bank2 (47 pins)
8-bit Bank0 (41 pins) – – Bank2 (41 pins)

Note: If MDDR is configured for LPDDR, one more IO also available for every 8-bit as the LPDDR does not

have DQS_N.

For general purpose use of the unused I/Os in the MDDR bank, select one of the I/O standards with the

same voltage level as the DDR I/Os.

Self refresh must be disabled if the MDDR banks contain a mixed of I/Os used for DDR and for general

purpose fabric I/Os.For more information, see "Self Refresh (DDR2, DDR3, LPDDR1)" on page 24.

3.5 Functional Description

This section provides the functional description of the MDDR subsystem.

3.5.1 Architecture Overview

The following illustration shows a functional block diagram of the MDDR subsystem. The main

components include the DDR fabric interface controller (DDR_FIC), AXI transaction handler, DDR

memory controller, and DDR PHY.

Figure 2 • MDDR Subsystem Functional Block Diagram

64-Bit AXI

Connected to

MSS/HPMS
DDR Bridge

64-Bit AXI /

Single 32-Bit

AHBL / Dual

32-Bit AHBL

Slave Interface

DDR_FIC

AXI

Transaction

Controller

DDR Controller

PHY

DDR

SDRAM

16-Bit APB
Configuration Bus

The DDR_FIC facilitates communication between the FPGA fabric masters and AXI transaction

controller. The DDR_FIC can be configured to provide either one 64-bit AXI slave interface or two

independent 32-bit AHB-Lite (AHBL) slave interfaces to the FPGA fabric masters.

The AXI transaction controller receives read and write requests from AXI masters (MSS/HPMS DDR

bridge and DDR_FIC) and schedules for the DDR controller by translating them into DDR controller

commands.

The DDR controller receives the commands from the AXI transaction controller. These commands are

queued internally and scheduled for access to the DDR SDRAM while satisfying DDR SDRAM

constraints, transaction priorities, and dependencies between the transactions. The DDR controller in

turn issues commands to the PHY module, which launches and captures data to and from the DDR

SDRAM.

DDR PHY receives commands from the DDR controller and generates DDR memory signals required to

access the external DDR memory.

The 16-bit APB configuration bus provides an interface to configure the MDDR subsystem registers. The

MDDR subsystem operates on MDDR_CLK. MSS/HPMS CCC generates the MDDR_CLK using MPLL.

For more details on MSS/HPMS CCC refer UG0449: SmartFusion2 and IGLOO2 Clocking Resources

User Guide.

Configuration Registers

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MDDR Subsystem

3.5.2 Port List

Table 5 • MDDR Subsystem Interface Signals

Signal Name Type Polarity Description

APB_S_PCLK In – APB clock. This clock drives all the registers of the

APB interface.

APB_S_PRESET_N In Low APB reset signal. This is an active low signal. This

drives the APB interface and is used to generate the
soft reset for the DDR controller as well.

MDDR_DDR_CORE_RESET_N In Low Global reset. This resets the

DDR_FIC/DDRC/PHY/DDRAXI logic.

MDDR_DDR_AXI_S_RMW In High AXI mode only Indicates whether all bytes of a

64-bit lane are valid for all beats of an AXI transfer.
0: Indicates that all bytes in all beats are valid in the
burst and the controller should default to write
commands.
1: Indicates that some bytes are invalid and the
controller should default to RMW commands. This
is classed as an AXI write address channel
sideband signal and is valid with the AWVALID
signal.

HPMS_DDR_FIC_SUBSYSTEM_CLK
or,
MSS_DDR_FIC_SUBSYSTEM_CLK

HPMS_DDR_FIC_SUBSYSTEM_LOCK
or,
MSS_DDR_FIC_SUBSYSTEM_LOCK

Bus Interfaces

AXI_SLAVE
AHB0_SLAVE
AHB1_SLAVE

1

2

3

APB_SLAVE Bus – APB slave interface 3.0 bus

DRAM Interface

MDDR_CAS_N Out Low DRAM CASN
MDDR_CKE Out High DRAM CKE
MDDR_CLK Out – DRAM single-ended clock – for differential pads
MDDR_CLK_N Out – DRAM single-ended clock – for differential pads
MDDR_CS_N Out Low DRAM CSN
MDDR_ODT Out High DRAM ODT.

MDDR_RAS_N Out Low DRAM RASN
MDDR_ RESET_N Out Low DRAM reset for DDR3
MDDR_WE_N Out Low DRAM WEN

Out – This output clock is derived from the MDDR_CLK

and is based on the DDR_FIC divider ratio. This is
the clock that should be used for the AXI or AHB
slave interfaces to move data in and out of the
MDDR.

Out – This indicates the lock from FCCC which generates

HPMS_DDR_FIC_SUBSYSTEM_CLK for IGLOO2
and MSS_DDR_FIC_SUBSYSTEM_LOCK in
SmartFusion2.

Bus – AXI slave interface 1.0 bus
Bus – AHB0 slave interface 3.0 bus
Bus – AHB1 slave interface 3.0 bus

0: Termination Off
1: Termination On

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MDDR Subsystem

Table 5 • MDDR Subsystem Interface Signals (continued)

Signal Name Type Polarity Description

MDDR_ADDR[15:0] Out – Dram address bits
MDDR_BA[2:0] Out – Dram bank address
MDDR_DM_RDQS[3:0] In/out – DRAM data mask – from bidirectional pads
MDDR_DQS[3:0] In/out – DRAM single-ended data strobe output – for

bidirectional pads

MDDR_DQS_N[3:0] In/out – DRAM single-ended data strobe output – for

bidirectional pads
MDDR_DQ[31:0] In/out – DRAM data input/output – for bidirectional pads
MDDR_DQ_ECC[3:0] In/out – DRAM data input/output for SECDED
MDDR_DM_RDQS_ECC In/out High DRAM single-ended data strobe output – for

bidirectional pads
MDDR_DQS_ECC In/out High DRAM single-ended data strobe output – for

bidirectional pads
MDDR_DQS_ECC_N In/out Low DRAM data input/output – for bidirectional pads
MDDR_DQS_TMATCH_0_IN In High DQS enables input for timing match between DQS

and system clock. For simulations, tie to

MDDR_DQS_TMATCH_0_OUT.
MDDR_DQS_TMATCH_1_IN In High DQS enables input for timing match between DQS

and system clock. For simulations, tie to

MDDR_DQS_TMATCH_1_OUT.
MDDR_DQS_TMATCH_0_OUT Out High DQS enables output for timing match between DQS

and system clock. For simulations, tie to

MDDR_DQS_TMATCH_0_IN.
MDDR_DQS_TMATCH_1_OUT Out High DQS enables output for timing match between DQS

and system clock. For simulations, tie to

MDDR_DQS_TMATCH_1_IN.
MDDR_DQS_TMATCH_ECC_IN In High DQS enables input for timing match between DQS

and system clock. For simulations, tie to

MDDR_DQS_TMATCH_ECC_OUT.
MDDR_DQS_TMATCH_ECC_OUT Out High DQS enables output for timing match between DQS

and system clock.

For simulations, tie to

MDDR_DQS_TMATCH_ECC_IN.

Note:1 AXI or AHB interface, depending on configuration.

2

MDDR_DQS_N[3:0] signals are not available for LPDDR.

3

TMATCH_IN and TMATCH_OUT pins are required to be connected together outside the device. They
are used for gate training as part of the read data capture operation. The two pins create an internal DQS
Enable signal that is used to calibrate the flight path. DQS needs to be gated to prevent false triggering of
the FIFO write clock. This DQS Enable signal is derived from the system clock and physically matches
the clock output buffer and DQS input buffer to compensate for I/O buffer uncertainty due to Process­Voltage-Temperature (PVT) changes. Without this connection, the circuit is not operable.

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MDDR Subsystem

3.5.2.1 AXI Slave Interface

The following table describes the MDDR AXI slave interface signals. These signals will be available only
if the MDDR interface is configured for AXI mode. For more AXI protocol details, refer to AMBA AXI v1.0
protocol specification.

Table 6 • AXI Slave Interface Signals

Signal Name Direction Polarity Description

MDDR_DDR_AXI_S_ARREADY Output High Indicates whether or not the slave is

ready to accept an address and
associated control signals.
1: Slave ready
0: Slave not ready

MDDR_DDR_AXI_S_AWREADY Output High Indicates that the slave is ready to

accept an address and associated
control signals.
1: Slave ready
0: Slave not ready

MDDR_DDR_AXI_S_BID[3:0] Output Indicates response ID. The

identification tag of the write response.

MDDR_DDR_AXI_S_BRESP[1:0] Output Indicates write response. This signal

indicates the status of the write
transaction.
00: Normal access okay
01: Exclusive access okay
10: Slave error
11: Decode error

MDDR_DDR_AXI_S_BVALID Output High Indicates whether a valid write

response is available.
1: Write response available

0: Write response not available
MDDR_DDR_AXI_S_RDATA[63:0] Output Indicates read data.
MDDR_DDR_AXI_S_RID[3:0] Output Read ID tag. This signal is the ID tag of

the read data group of signals.
MDDR_DDR_AXI_S_RLAST Output High Indicates the last transfer in a read

burst.
MDDR_DDR_AXI_S_RRESP[1:0] Output Indicates read response. This signal

indicates the status of the read transfer.

00: Normal access

01: Exclusive access

10: Slave error

11: Decode error
MDDR_DDR_AXI_S_RVALID Output Indicates whether the required read

data is available and the read transfer

can complete.

1: Read data available

0: Read data not available
MDDR_DDR_AXI_S_WREADY Output High Indicates whether the slave can accept

the write data.

1: Slave ready

0: Slave not ready

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MDDR Subsystem

Table 6 • AXI Slave Interface Signals (continued)

Signal Name Direction Polarity Description

MDDR_DDR_MDDR_DDR_AXI_S_ARADDR[31:0] Input Indicates initial address of a read burst

transaction.

Note: DDR_FIC AXI interface

supports only 64-bit
aligned addresses.

MDDR_DDR_AXI_S_ARBURST[1:0] Input Indicates burst type. The burst type,

coupled with the size information,

details how the address for each

transfer within the burst is calculated.

00: FIXED - Fixed-address burst FIFO

type (Not Supported)

01: INCR - Incrementing-address burst

normal sequential memory

10: WRAP - Incrementing-address

burst that wraps to a lower address at

the wrap boundary

11: Reserved
MDDR_DDR_AXI_S_ARID[3:0] Input Indicates identification tag for the read

address group of signals.
MDDR_DDR_AXI_S_ARLEN[3:0] Input Indicates burst length. The burst length

gives the exact number of transfers in a

burst.

0000: 1

0001: 2

0010: 3

0011: 4

0100: 5

0101: 6

0110: 7

0111: 8

1000: 9

1001: 10

1010: 11

1011: 12

1100: 13

1101: 14

1110: 15

1111: 16
MDDR_DDR_AXI_S_ARLOCK[1:0] Input Indicates lock type. This signal provides

additional information about the atomic

characteristics of the read transfer.

00: Normal access

01: Exclusive access

10: Locked access

11: Reserved
MDDR_DDR_AXI_S_ARSIZE[1:0] Input Indicates the maximum number of data

bytes to transfer in each data transfer,

within a burst.

00: 10 : Not Supported

11: 8

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MDDR Subsystem

Table 6 • AXI Slave Interface Signals (continued)

Signal Name Direction Polarity Description

MDDR_DDR_AXI_S_ARVALID Input High Indicates the validity of read address

and control information.

1: Address and control information valid

0: Address and control information not

valid
MDDR_DDR_AXI_S_AWADDR[31:0] Input Indicates write address. The write

address bus gives the address of the

first transfer in a write burst transaction.

Note: DDR_FIC AXI interface

supports only 64-bit
aligned addresses

MDDR_DDR_AXI_S_AWBURST[1:0] Input Indicates burst type. The burst type,

coupled with the size information,

details how the address for each

transfer within the burst is calculated.

00: FIXED - Fixed-address burst FIFO-

type (Not Supported)

01: INCR - Incrementing-address burst

normal sequential memory

10: WRAP - Incrementing-address

burst that wraps to a lower address at

the wrap boundary

11: Reserved
MDDR_DDR_AXI_S_AWID[3:0] Input Indicates identification tag for the write

address group of signals.
MDDR_DDR_AXI_S_AWLEN[3:0] Input Indicates burst length. The burst length

gives the exact number of transfers in a

burst. This information determines the

number of data transfers associated

with the address.

0000: 1

0001: 2

0010: 3

0011: 4

0100: 5

0101: 6

0110: 7

0111: 8

1000: 9

1001: 10

1010: 11

1011: 12

1100: 13

1101: 14

1110: 15

1111: 16
MDDR_DDR_AXI_S_AWLOCK[1:0] Input Indicates lock type. This signal provides

additional information about the atomic

characteristics of the write transfer.

00: Normal access

01: Exclusive access

10: Locked access

11: Reserved

.

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MDDR Subsystem

Table 6 • AXI Slave Interface Signals (continued)

Signal Name Direction Polarity Description

MDDR_DDR_AXI_S_AWSIZE[1:0] Input Indicates the maximum number of data

bytes to transfer in each data transfer,

within a burst.

00 to 10 : Not Supported

11: 8
MDDR_DDR_AXI_S_AWVALID Input High Indicates whether or not valid write

address and control information are

available.

1: Address and control information

available

0: Address and control information not

available
MDDR_DDR_AXI_S_BREADY Input High Indicates whether or not the master can

accept the response information.

1: Master ready

0: Master not ready
MDDR_DDR_AXI_S_RREADY Input High Indicates whether or not the master can

accept the read data and response

information.

1: Master ready

0: Master not ready
MDDR_DDR_AXI_S_WDATA[63:0] Input Indicates write data.
MDDR_DDR_AXI_S_WID[3:0] Input Indicates response ID. The

identification tag of the write response.
MDDR_DDR_AXI_S_WLAST Input High Indicates the last transfer in a write

burst.
MDDR_DDR_AXI_S_WSTRB[7:0] Input Indicates which byte lanes to update in

memory.
MDDR_DDR_AXI_S_WVALID Input High Indicates whether or not valid write data

and strobes are available.

1: Write data and strobes available

0: Write data and strobes not available

3.5.2.2 AHB Slave Interface

The following table describes the MDDR AHB slave interface signals. These signals are available only if
MDDR interface is configured for single or dual AHB mode. For more AHB protocol details, refer to
AMBA AHB v3.0 protocol specification.

Table 7 • AHB Slave Interface Signals

Signal Name Direction Polarity Description

MDDR_DDR_AHBx_S_HREADYOUT Output High Indicates that a transfer has finished on the

bus. The signal is asserted Low to extend a
transfer. Input to Fabric master.

MDDR_DDR_AHBx_S_HRESP Output High Indicates AHB transfer response to Fabric

master.
MDDR_DDR_AHBx_S_HRDATA[31:0] Output Indicates AHB read data to Fabric master.
MDDR_DDR_AHBx_S_HSEL Input High Indicates AHB slave select signal from Fabric

master.

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MDDR Subsystem

Table 7 • AHB Slave Interface Signals (continued)

Signal Name Direction Polarity Description

MDDR_DDR_AHBx_S_HADDR[31:0] Input Indicates AHB address initiated by Fabric

master.
MDDR_DDR_AHBx_S_HBURST[2:0] Input Indicates AHB burst type from Fabric master.

000: Single burst

001: Incrementing burst of undefined length

010: 4-beat wrapping burst

011: 4-beat incrementing burst

100: 8-beat wrapping burst

101: 8-beat incrementing burst

110: 16-beat wrapping burst

111: 16-beat incrementing burst
MDDR_DDR_AHBx_S_HSIZE[1:0] Input Indicates AHB transfer size from Fabric master.

00: 8 Byte

01: 16 Halfword

10: 32 Word
MDDR_DDR_AHBx_S_HTRANS[1:0] Input Indicates AHB transfer type from Fabric

master.

00: IDLE

01: BUSY

10: NONSEQUENTIAL

11: SEQUENTIAL.
MDDR_DDR_AHBx_S_HMASTLOCK Input High Indicates AHB master lock signal from Fabric

master.
MDDR_DDR_AHBx_S_HWRITE Input High Indicates AHB write control signal from Fabric

master.
MDDR_DDR_AHBx_S_HREADY Input High Indicates that a transfer has finished on the

bus. Fabric master can drive this signal Low to

extend a transfer.
MDDR_DDR_AHBx_S_HWDATA[31:0] Input Indicates AHB write data from Fabric master.

Note: AHBx indicates AHB0 or AHB1.

3.5.2.3 APB Slave Interface

The following table describes the MDDR APB slave interface signals. For more APB protocol details,
refer to AMBA APB v3.0 protocol specification.

Table 8 • MDDR APB Slave Interface Signals

Signal Name Direction Polarity Description

MDDR_APB_S_PREADY Output High Indicates APB Ready signal to Fabric master.
MDDR_APB_S_PSLVERR Output High Indicates error condition on an APB transfer to

Fabric master.
MDDR_APB_S_PRDATA[15:0] Output Indicates APB read data to Fabric master.
MDDR_APB_S_PENABLE Input High Indicates APB enable from Fabric master. The

enable signal is used to indicate the second cycle

of an APB transfer.
MDDR_APB_S_PSEL Input High Indicates APB slave select signal from Fabric

master

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MDDR Subsystem

Table 8 • MDDR APB Slave Interface Signals (continued)

Signal Name Direction Polarity Description

MDDR_APB_S_PWRITE Input High Indicates APB write control signal form Fabric

master
MDDR_APB_S_PADDR[10:2] Input Indicates APB address initiated by Fabric master.
MDDR_APB_S_PWDATA[15:0] Input Indicates APB write data from Fabric master.

3.5.3 Initialization

After power-up, the MDDR needs to have all of the configuration registers written to establish the
operating modes of the blocks. When using the System Builder design flow through Libero SoC, this is all
handled for the user through the use of the System Builder module. All of the configuration register
values are selected by the user and stored in a special portion of the embedded non-volatile memory
(eNVM). Before the MDDR subsystem is active, it goes through an initialization phase and this process
starts with a reset sequence. For DDR3 memories, the initialization phase also includes ZQ calibration
and DRAM training.

3.5.3.1 Reset Sequence

The following illustration shows the reset sequence for the MDDR subsystem from the power on reset
stage. The MDDR subsystem comes out of reset after MPLL Lock is asserted by the MSS/HPMS_CCC.
De-assertion of MDDR_AXI_RESET_N signifies the end of the reset sequence. The MDDR reset can be
generated by asserting MDDR_CTLR_SOFTRESET bit in SOFT_RESET_CR to 1. The DDR controller
performs external DRAM memory reset and initialization as per the JEDEC specification, including reset,
refresh, and mode registers.

3.5.3.2 DDRIO Calibration

Each DDRIO has an ODT feature, which is calibrated depending on the DDR I/O standard. DDR I/O
calibration occurs after the DDR I/Os are enabled. If the impedance feature is enabled, impedance can
be programmed to the desired value in three ways:

• Calibrate the ODT/driver impedance with a calibration block (recommended)

• Calibrate the ODT/driver impedance with fixed calibration codes

• Configure the ODT/driver impedance to the desired value directly
The system register, MDDR_IO_CALIB_CR, can be configured for changing the ODT value to the

desired value.

The I/O calibration is always enabled when the DDR subsystem is configured for DDR2 and DDR3
memories.

The I/O calibration can be disabled or enabled using the DDR configurator when the DDR subsystem is
configured for LPDDR memories.

Note: If I/O calibration is enabled, all I/Os in the DDR bank are calibrated even though the DDR controller is not

using all I/Os in the bank.

For more information on DDR I/O calibration, refer to the Configurable ODT and Driver Impedance
section of the I/Os chapter in the UG0445: IGLOO2 FPGA and SmartFusion2 SoC FPGA Fabric User

Guide.

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MDDR Subsystem

Figure 3 • Reset Sequence

PO_RESET_N

50 MHz Clock

Enable

Enable I/Os

DDRIO

Calibration

SC_HPMS_RESET_N

SC_MSS_RESET_N

or,

(for IGLOO2)

(for SmartFusion2)

MPLL Lock

MDDR_AXI_RESET_N

3.5.3.3 ZQ Calibration

This is applicable for DDR3 only. The ZQ calibration command is used to calibrate DRAM output drivers

) and on-die termination (ODT) values. The DDR3 SDRAM needs a longer time to calibrate RON

(R

ON

and ODT at initialization and a relatively smaller time to perform periodic calibrations.

The DDR controller performs ZQ calibration by issuing a ZQ calibration long (ZQCL) command and ZQ
calibration short (ZQCS) command.

ZQCL is used to perform initial calibration during the power-up initialization sequence. This command is
allowed for a period of t
through register bits REG_DDRC_T_ZQ_LONG_NOP.

The ZQCS command is used to perform periodic calibration to account for voltage and temperature
variations. A shorter timing window is provided to perform calibration and transfer of values as defined by
timing parameter tZQCS. The tZQCS parameter can be modified through register bits

REG_DDRC_T_ZQ_SHORT_NOP.

Other activities are not performed by the controller for the duration of t
are precharged and tRP is met before ZQCL or ZQCS commands are issued by the DDR controller.

3.5.3.4 DRAM Training

High Speed DDR3 memories typically requires the DDR controller to implement Write-Leveling, Read
DQS Gate Training, and Read Data Eye Training. However, MDDR only supports a maximum data rate
of 333 MHz/667 Mbps, which means the clock period and data window are relatively large compared to
high-speed DDR3 memory interfaces. Therefore dynamic write-leveling and read training are not
performed. The following sections describe how write-leveling and read training are addressed by the
MDDR.

, as specified by memory vendor. The value of t

ZQinit

can be modified

ZQinit

and tZQCS. All DRAM banks

ZQinit

3.5.3.4.1 Write Leveling

Dynamic write-leveling is not required for the MDDR controller. The board-layout needs to follow AC393

SmartFusion2 and IGLOO2 Board Design Guidelines Application Note to keep the skew between DQS

and CK within the JEDEC DDR3 tDQSS limit of +/- 750ps at each memory device. For board layouts
which do not meet the Board Design Guidelines, the MDDR controller allows static delay ratios which
delays DQS for each byte lane so that the skew between DQS and CK is kept within JEDEC limits.

333 MHz/667 Mbps is the maximum DDR3 rate MDDR supports. Leveling is not mandatory and the
interface will work if the board layout guidelines are followed and length matching is done.

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MDDR Subsystem

3.5.3.4.2 Read Leveling

MDDR does not perform dynamic Read DQS Gate Training and Data Eye Training. Instead, these
functions are achieved by using built-in static delay values automatically generated by Libero SoC for the
MDDR automatic register initialization.

3.5.3.4.3 Read Gate

The DQS gate is aligned by the Libero SoC auto-generated MDDR initialization code containing fixed
delay ratios to account for board round-trip time between FPGA and the DDR3 memory. The
TMATCH_OUT and TMATCH_IN signals are shorted close to the FPGA balls to remove the FPGA
output and input delays from the round trip delay time. Therefore, the fixed delay ratios represent only the
board delay.

The fixed delay ratios work in combination with board layouts which follow the SmartFusion2/IGLOO2
Board Design Guidelines (refer AC393: Board Design Guidelines for SmartFusion2/IGLOO2 FPGA

Application Note).

3.5.3.4.4 DQS Alignment within Data Eye

The incoming read DQS is internally centered within the read DQ data window using a static delay ratio.
This static delay is applied by the Libero SoC auto-generated MDDR initialization code. The fixed delay
ratios work in combination with board layouts which follow the SmartFusion2/IGLOO2 Board Design
Guidelines (refer AC393: Board Design Guidelines for SmartFusion2/IGLOO2 FPGA Application Note).

Note: The Libero SOC auto-generated delay ratio for read DQS data eye centering is written to the required

register.

3.5.3.5 DDR Memory Initialization Time

The time to initialize the DDR memory depends on the following factors:

• Power-up and register initialization by system controller. It depends on the power on reset delay
configuration in the Libero project (Project > Project Settings > Device settings).

• DDR controller and PHY configuration registers initialization. In SmartFusion2 devices, the Cortex­M3 initializes these registers. In IGLOO2 devices, the ConfigMaster in the FPGA fabric initializes
these registers.

• DDR memory initialization by the DDR Controller according to the JEDEC standard (mode register
configuration and training).

• DDR memory settling time configured in the System Builder memory configuration window.

3.5.4 Details of Operation

This section provides a functional description of each block in the MDDR subsystem.

3.5.4.1 DDR_FIC

The following illustration shows the DDR_FIC block diagram.

Figure 4 • DDR_FIC Block Diagram

AHB

64-Bit AXI / Single

32-Bit AHBL /

Dual 32-Bit AHBL

Slave Interface

16-Bit APB

Configuration Bus

MUX

Configuration

Registers

AHB

AXI

Synchronous

DDR Bridge

AXI-AXI

Bridge

AXI

AXI

MUX

AXI Transaction
Controller

Fabric masters can access the MDDR subsystem in the following ways:

• Single AXI-64 interface

• Single AHB-32 interface

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MDDR Subsystem

• Dual AHB-32 bit interfaces

If the AXI-64 interface is selected, the DDR_FIC acts as an AXI to AXI synchronous bridge. In this mode,
DDR_FIC provides FPGA fabric masters to access the MDDR subsystem through locked transactions.
For this purpose, a user configurable 20-bit down counter keeps track of the duration of the locked
transfer. If the transfer is not completed before the down counter reaches zero, a single clock cycle pulse
interrupt is generated to the fabric interface.

If single or dual AHB-32 interfaces are selected, DDR_FIC converts the single/dual 32-bit AHBL master
transactions from the FPGA fabric to 64-bit AXI transactions. In this mode the DDR bridge, embedded as
part of the DDR_FIC, is enabled. The DDR bridge has an arbiter, which arbitrates read and write
requests from the two AHB masters on a round robin priority scheme. Refer to the "DDR Bridge Control

Registers in MDDR and FDDR" chapter on page 216 for a detailed description.

The DDR_FIC input interface is clocked by the FPGA fabric clock and the MDDR is clocked by
MDDR_CLK from the MSS/HPMS CCC. Clock ratios between MDDR_CLK and DDR_FIC clock can
vary. The following table lists supported ratios. Clock ratios can be configured through Libero System-on­Chip (SoC) software or through system register MSSDDR_FACC1_CR. For more information, refer to
the "MDDR Configuration Registers" section on page 61.

Table 9 • MDDR_CLK to FPGA Fabric Clock Ratios

DIVISOR_A[1:0] FIC64_DIVISOR[2:0] MDDR_CLK: FPGA FABRIC Clock Ratio

00 000 1:1
00 001 2:1
00 010 4:1
00 100 8:1
00 101 16:1
01 000 2:1
01 001 4:1
01 010 8:1
01 100 16:1
11 000 3: 1
11 001 6: 1
11 010 12:1

3.5.4.2 AXI Transaction Controller

The AXI transaction controller receives 64-bit AXI transactions from various masters (MSS/HPMS DDR
bridge and DDR_FIC) and translates them into DDR controller transactions. The following illustration
shows the block diagram of the AXI transaction controller interfaced with the DDR controller.

The AXI transaction controller performs arbitration of the read/write requests initiated by AXI compliant
masters.

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