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INTRODUCTION
This chapter contains general information that will be useful to know before using the
MCP651 Input Offset Evaluation Board. Items discussed in this chapter include:
• Document Layout
• Conventions Used in this Guide
• Recommended Reading
• The Microchip Web Site
• Customer Support
• Document Revision History
DOCUMENT LAYOUT
This document describes how to use the MCP651 Input Offset Evaluation Board. The
manual layout is as follows:
• Chapter 1. “Product Overview” - Important information about the MCP651 Input
Offset Evaluation Board.
• Chapter 2. “Installation and Operation” – Covers the initial set-up of the
MCP651 Input Offset Evaluation Board. It lists the required tools, shows how to
set up the board and how to connect lab equipment. It then demonstrates how to
use this board.
• Chapter 3. “Possible Modifications” – Shows how to modify the board for other
single Microchip op amps in SOIC-8, PDIP-8 and other packages.
• Appendix A. “Schematics and Layouts” – Shows the schematic and board
layouts for the MCP651 Input Offset Evaluation Board.
• Appendix B. “Bill Of Materials (BOM)” – Lists the parts used to populate the
MCP651 Input Offset Evaluation Board. Also lists loose parts shipped with the
board in an ESD bag, alternate components and components not populated.
This user's guide describes how to use MCP651 Input Offset Evaluation Board. Other
useful documents are listed below. The following Microchip documents are available
and recommended as supplemental reference resources.
MCP6V01/2/3 Data Sheet, “300 µA, Auto-Zeroed Op Amps”, DS22058
Gives detailed information on the op amp family that is used for signal processing and
output voltage control on the MCP651 Input Offset Evaluation Board.
MCP651 Data Sheet, “5 mA Op Amps with mCal”,DS22146
Gives detailed information on the op amp family that is used as the DUT on the
MCP651 Input Offset Evaluation Board.
AN1177 Application Note, “Op Amp Precision Design: DC Errors”,DS01177
Discusses how to achieve high DC accuracy in op amp circuits. Also discusses the
relationship between an op amp’s input offset voltage (V
Open-Loop Gain and V
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for support. Local sales offices are also available to help customers. A listing of sales
offices and locations is included in the back of this document.
Technical support is available through the web site at: http://support.microchip.com
The MCP651 Input Offset Evaluation Board is intended to provide a simple means to
measure the MCP651 Input Offset Evaluation Board op amp’s input offset voltage
under a variety of operating conditions. The measured input offset voltage (V
includes the input offset voltage specified in the data sheet (V
power supply voltage (PSRR), common mode voltage (CMRR), output voltage (A
input offset voltage drift over temperature (ΔV
The MCP651 Input Offset Evaluation Board works most effectively at room temperature (near 25°C). Measurements at other temperatures should be done in an oven
where the air velocity is minimal.
1.4DESCRIPTION
This section starts with the conversion of DUT bias voltages described in the MCP651
data sheet to the voltages on this board. Then there is a discussion of the circuitry that
controls the DUT’s output voltage (V
(V
OST
details of this board are given in Appendix A. “Schematics and Layouts” and
Appendix B. “Bill Of Materials (BOM)”.
1.4.1Conversion of Bias Voltages
) plus changes due to:
OS
/ΔTA) and 1/f noise.
OS
) and amplifies its total input offset voltage
OUTX
). Finally, other portions of the circuit, and their purpose, are discussed. Complete
OST
)
),
OL
The MCP651 data sheet describes all of its bias voltages relative to VSS, which is
assumed to be at ground (0V). On the other hand, the MCP651 Input Offset Evaluation
Board sets the DUT’s input common mode voltage to 0V. The user needs to convert
from the first set of voltages to the second set (by subtracting V
Figure 1-2 is a simplified diagram of the circuitry that biases the DUT and produces an
amplified version of the DUT’s input offset voltage (V
a Proportional plus Integral (PI) controller loop, a high gain amplifier and a filter.
). It includes gain at the input,
OST
FIGURE 1-2:Simplified Circuit.
The elements of Figure 1-2 correspond to the components in the complete schematic
(A.3 “Board – Schematic”) as follows.
Analysis of this simplified circuit gives the following nominal circuit outputs:
EQUATION 1-2:
R
and R2 (R12) balance the circuit at the DUT’s input. These resistors are small, and
1
are oriented on the Printed Circuit Board (PCB) to cancel their thermoelectric voltages.
The parallel resistances R
DUT’s input bias currents to the measured V
affect V
V
OST
); the typical value of IOS at +125°C is ±100 pA, which produces a change in
M
of ±0.02 µV.
The unity gain buffer (+1 gain on the bottom right) isolates the V
the following attenuator and integrator. Although it’s not shown here, the resistor R14
at the input to the “+1 Buffer” ensures its output voltage is 0V when the V
is left open.
The attenuators (1/G
U2 and U3 (“+1 Buffer” and (“Integrator”). For instance, when V
V
=0.3V and V
SSI
DDI
1.80V.
The differential integrator accumulates the scaled difference between V
V
, which slowly forces this difference to zero (the I part of the PI controller).
OUTX
Resistor R
R
; it minimizes the error at V
3
injects the integrator’s output at the DUT’s input through resistors R4 and
56
A proportional term (the P part of the PI controller) is also injected at the DUT’s input
through resistor R
78
negligible above 16 Hz). It also sets a low frequency DUT noise gain of about 505 V/V.
This proportional term is rolled off by C
interact with the integrator term, and low enough to keep the DUT stable. Thus, C
minimizes noise gain at higher frequencies, which reduces the chance of unwanted
feedback effects.
With the overall gain G
V
values up to either ±12.4 mV or ±1.25 mV. A voltmeter with 1 mV resolution can
OST
distinguish steps of either 5 µV or 0.5 µV, respectively.
The DUT’s noise seen at the input to G
R
and C2 (0.28 kHz). This implies that this noise is dominated by the 1/f noise. The
78
Lowpass Filter (f
≈ 1.6 Hz) reduces this 1/f noise a little more before it is seen at VM.
BW
The measured noise, over a 140 second period of time with a typical part, was about
19 µV
V
OS
referred to input (RTI). This compares favorably with the MCP651’s calibrated
P-P
specification (±200 µV, maximum at +25°C).
||R2 and R3||R4 are equal to minimize the contribution of the
) scale V
INT
1
and V
COX
(contributions by R5 through R8 do not
OST
input filters from
COX
COX
so that they do not overdrive op amps
OUTX
= 5.6V (given
OUTX
connector
= 5.8V), the voltages at the outputs of the attenuators (1/G
and
COX
.
OUTX
; it stabilizes the control loop (the integrator term becomes
starting at 0.18 kHz; this is high enough to not
2
of either 201 V/V or 1998 V/V, this circuit can measure
The values chosen allow the POT to cover the specified V
Connecting a voltmeter to V
that it is also possible to drive V
be, but doesn’t have to be, at mid-range).
V
is set, as previously explained, to be equal to V
OUTX
control loop. If V
railed at the corresponding supply voltage.
The load resistor (R
usually set to mid-supply. The V
loading on V
and V
DDX
DDI
SSX
and V
and ISS can be calculated as (ISS is negative):
pin sets its internal common mode voltage (V
CAL
.
CALX
makes it possible to set the POT accurately. Notice
CALX
with an external voltage source (the wiper should
CALX
or V
SSI
connection can be left open, which minimizes the
LX
, then the loop forces V
DDI
is at or beyond V
COX
OUTX
or R10) is biased to the externally supplied voltage VLX. VLX is
L
(about 40 kΩ).
. The resistors R29, R30, R37 and
) are different by 30 mV to
SSI
of the MCP651)
CMX
) is small when V
OS
and R43, sets V
42
range, and a little more.
CALX
by the integrator in the PI
COX
CMX
OUTX
(0V on
CALX
to be
.
MCP651 Input Offset Evaluation Board User’s Guide
C
9
R
21
10 kΩ
R
37
R
29
4.49Ω
4.99Ω
V
DDX
1.0 µF
DUT
CAL/CS
U
1
V
SS
V
DD
R
38
R
30
4.49Ω
4.99Ω
V
SSX
S
1
R
41
10Ω
R
19
10 kΩ
R
20
100 kΩ
1.4.4CAL Input
The DUT’s CAL/CS input pin is normally held at V
keeps the MCP651 in its normal mode of operation. When S
pulls CAL/CS
its low power mode of operation. Releasing S
a time set by R
enough to de-glitch S
up to V
, R21 and C9); the time constant (R20+R21)C9 is 0.11s, which is slow
20
(after a time set by R20 and C9), so that the MCP651 enters
DDX
. Note that the supply voltages need to be constant while the
1
then brings CAL/CS back to V
1
by resistors R20 and R21; this
SSX
is closed by the user, R20
1
SSX
(after
DUT is being put into calibration mode, and during calibration mode (up to 4 ms of time
after CAL/CS
goes low).
FIGURE 1-4:CAL Switch and De-glitching Circuitry.
1.4.5Bias Inputs for Other Op Amps
The other op amps (U2, U3 and U4) are run on dual power supplies centered on ground.
The design assumes that these supplies are ±2.5V, for the best performance. These
supplies can be set as low as ±0.9V, which will keep the MCP6V01’s working, but will
reduce the range of possible V
and VM values.
COX
1.4.6Outputs
The connector V
used to measure the actual DUT supply voltages, and to estimate its supply currents
I
Lab equipment is connected to this board as shown in Figure 2-1. The (surface mount)
test points allow lab equipment to be connected to these boards.
FIGURE 2-1:Lab Equipment Connections and Configuration Switches for the MCP651 Input Offset
Evaluation Board.
The arrows and numbers in Figure 2-1 signify the following:
1. Gain Setting Switch – top position (# 1)
a) To the right (ON) for low gain (G
2. Voltmeter to measure VM
a) Gives amplified offset (G
b) To the left for high gain (G
3. Power Supply for VCOX
a) Can be left open (forces VOUTX = 0V).
M
AGMVOST
= 201 V/V).
M
=1998V/V).
).
b) Set between VSSI and VDDI.
4. ±2.5V Power Supplies with GND
a) Set at +2.5V and -2.5V (for best performance).
5. Power Supply for VLX (Load Resistor’s bias point)
a) Can be left open (fewer lab power supplies; R
b) Can be shorted to GND with a jumper wire (VLX = 0V and R
c) Can connect to an external lab power supply (R
a) Typically not used (mainly used for validating DUT and board).
7. POT (RCAL) Thumb-wheel (to adjust VCALX)
a) Rotate clockwise (CW) to increase VCALX.
b) Rotate counter-clockwise (CCW) to decrease VCALX.
c) Usually set at mid-turn.
d) Can override with an external power supply at VCALX or a jumper wire (see
# 9 below)
8. Power Supply for VSSX
a) Minimum of about VDDX – (DUT’s maximum operating supply
voltage) – (0.12V for the resistors in the supply line).
b) Maximum of +0.3V (for V
c) When VSSX = -2.5V and VDDX = +2.5V, you can connect to the -2.5V
supply with a jumper wire (fewer lab power supplies).
9. Power Supply for VCALX
a) Usually not connected (RCAL sets V
b) Can be shorted to GND with a jumper wire (fewer lab power supplies;
V
CALX=VCMX
=0V).
c) Can connect to an external lab power supply (it is best, but not necessary, to
set RCAL to mid-supply).
10. Power Supply for VDDX
a) Minimum of -0.3V (for V
b) Maximum of about VSSX + (DUT’s maximum operating supply
voltage) + (0.12V for the resistors in the supply line).
c) When VSSX = -2.5V and VDDX = +2.5V, you can connect to the +2.5V
supply with a jumper wire (fewer lab power supplies).
11. CAL Switch
a) Press to initiate calibration sequence (corrects DUT’s V
common mode voltage set to VCALX).
b) There is a delay of about 4 ms for the calibration to complete, plus several
tenths of a second for the circuit to settle.
12. Voltmeter at VDDI and VDDX (to measure I
a) Measure ΔV=V
b) Calculate I
DDX–VDDI
= ΔV/(10Ω)
DD
13. Voltmeter at VSSI and VSSX (to measure I
a) Measure ΔV=V
b) Calculate I
SSX–VSSI
= ΔV/(10Ω); (this is a negative value)
SS
at 0.3V below negative rail).
CMX
; fewer lab power supplies).
CALX
at 0.3V above positive rail).
CMX
)
DD
.
)
SS
.
, with internal
OST
Note:For the best accuracy and ease of use, short VCALX to GND, set the other
voltages for the desired bias during calibration, then initiate a calibration
event in the DUT (push S1). Change the bias point afterwards to see how
V
The MCP651 Input Offset Evaluation Board works most effectively at room
temperature (near 25°C). Measurements at other temperatures should be done in an
oven where the air velocity is minimal. Table 2-1 shows the various DUT voltages (as
described in the data sheet), their nominal values and ranges, and how to convert to
the voltages needed on the MCP651 Input Offset Evaluation Board.
TABLE 2-1:CONVERTING VOLTAGES FOR THE BOARD
Single Supply Voltages (V)
Data Sheet
Symbol
V
DD
V
SS
V
CM
NominalRange
2.5 or 5.52.5 to 5.5V
00V
VDD/3VSS– 0.3 to VDD–1.3
0← VCM–V
(Note 1)
V
(Note 2)VDD/2VSS+ 0.2 to VDD–0.2V
OUT
V
L
V
CAL
CAL/CSV
VDD/2VSS to V
DD
V
VDD/3 (Note 3)VSS+ 0.1 to VDD–1.4V
SS
VSS to V
DD
(Note 4)
Note 1: At TA= +25°C. See the data sheet for changes in VCM range vs. TA.
2: Set the desired V
voltage at the V
OUT
input; the integrator then forces V
COX
be the same voltage.
3: When the V
connected, so V
4: The circuit forces CAL/CS
pin left open. However, this board always has the POT (R43)
CAL
is never truly open.
CALX
to stay within its range (as long as the supply voltages
are constant when the CAL switch is activated). Normally, the part is on.
5: These numbers are for the MCP651 op amp.
Once the MCP651 Input Offset Evaluation Board is powered up, the switches can be
set for the desired operation. S1 (a normally off push-button switch) starts a calibration
event (CAL), internal to the DUT, when pushed. S2 (top position) sets the gain of the
amplifier (G
) either high or low. See Table 2-2 for details.
M
Conversion
Equations (V)
← VDD–V
DDX
← VSS–V
SSX
← V
OUTX
← VL–V
LX
← V
CALX
CM
CM
CM
OUT–VCM
CM
CAL–VCM
OUT
to
TABLE 2-2:SWITCH OPERATION
SwitchInputResult
S1No InputNormal Operation
PushedCalibration event started in DUT
S2Top Switch to the leftHigh Gain (1998 V/V)
Top Switch to the rightLow Gain (201 V/V)
(Bottom Switch)(Don’t Care)
The gain is usually set low. It can be set high just after a calibration event, before
changing the DUT’s bias point, to obtain more accurate results for the calibrated offset
voltage.
The POT (R
or R43) adjusts V
CAL
. This voltage is where the DUT’s common mode
CALX
input voltage set during a calibration event (initiated by pushing S1). Adjusting this POT
does not have an effect on the circuit’s behavior until the CAL switch (S1) is pushed.
Table 2-3 shows one possible measurement matrix that will allow the user to estimate
key parameters for the DUT. Obviously, other values of V
selected.
TABLE 2-3:MEASUREMENT MATRIX
Operating InputsMeasurement (Note 1)
T
V
DD
(V)
V
(V)
A
(°C)
+255.52.751.8340V
0.201.83V
5.30V
2.51.250.83V
0.200.83V
2.30V
-405.52.751.83V
+85V
+125V
V
OUT
CM
(V)
-0.304V
4.20V
-0.30V
1.20V
G
M
(V/V)
SymbolComments
VOS and PSRR
M1
CMRR
M2
CMRR
M3
A
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
OL
A
OL
VOS and PSRR
CMRR
CMRR
A
OL
A
OL
VOS at temperature and ΔVOS/ΔT
Note 1: Before making these measurements, set up the DUT to the bias point described for
. Short V
V
M1
, then alter the operating conditions for each succeeding measurement; do not
V
M1
to GND. Then start a calibration (CAL) event using S1. Measure
CALX
initiate another calibration event until all measurements are done.
Based on these measurements, we can make the following estimates, where the
V
values are calculated from the measured VMk values (see Equation 2-1):
OST_k
DD
and V
could be
CAL
A
TABLE 2-4:ESTIMATES
Operating InputsEstimates
V
DD
(V)
1.8 and 5.5+251/PSRR = (V
5.5-40V
1.8+25V
Obviously, other values of T
T
A
(°C)
OST_1–VOST_6
=V
OS
+25VOS=V
+85V
+125V
OS
OS
-40 to +125ΔVOS/ΔTA=(V
+251/CMRR = (V
1/AOL=(V
OS
1/CMRR = (V
1/A
OL
, VDD, … can be used instead, with the proper adjustments
input and VM, is set mainly by the lowpass filter at the VM test point (TP5); this
bandwidth is about 1.6 Hz. This bandwidth sets the settling time seen at VM (after the
DUT’s bias point has been changed) to about 0.6 seconds.
The noise seen in the measurements is a result of DUT’s input noise voltage passed
through the same 1.6 Hz lowpass filter. The MCP651’s 1/f noise dominates at such low
frequencies, so V
will appear to wander over time. The standard deviation of this
OST
1/f wander can be estimated to be roughly:
•5µV
•34µV
for a time period of 1 second
P-P
for a time period of 10 years
P-P
Averaging several measurements together will help reduce the noise over a short
period of time. It must be understood, however, that the 1/f noise will make V
OST
appear to change over long periods of time.
There is a practical limit on increasing the sample rate; the noise does not improve
significantly after a certain point. The analog lowpass pole at 1.6 Hz causes closely
spaced samples to be correlated. To avoid the overhead caused by sampling too fast,
keep the sampling period near or above the pole’s time constant (0.10s); this gives a
minimum sample rate of 10 samples per second.
Note:Sampling much faster than 10 SPS will not improve the averaged noise
This chapter shows how to modify the MCP651 Input Offset Evaluation Board to
measure other single op amps from Microchip Technology Inc. Items discussed in this
chapter include:
• Range of Parts Supported by the MCP651 Input Offset Evaluation Board
• Changes to Accommodate Other DUTs
3.2RANGE OF PARTS SUPPORTED BY MCP651 INPUT OFFSET EVALUATION
BOARD
Only op amps that fall within a certain performance range are supported by the
MCP651 Input Offset Evaluation Board.
3.2.1Input Offset Voltage
In order to keep op amps U3 and U4 operating normally, the DUT’s VOS must be:
EQUATION 3-1:
More accurate op amps need higher gain for good resolution. Table 3-1 shows what
V
specs can be supported for different voltmeter resolutions and amplifier gains.
OS
TABLE 3-1:LOWER LIMIT ON V
Voltmeter Resolution
(mV)
1 mV201 (low gain)500
0.1 mV201 (low gain)50
Note 1: These results assume a minimum measurement resolution of 1% of the V
2: The DUT needs to be soldered to the PCB when the maximum V
±50 µV, or so. Inserting a PDIP-8 part into a 8-pin socket creates a contact potential
(error) of the order of ±1 µV. Also, 1/f noise needs to be low.
This section focuses on methods to connect to other DUTs; the circuit’s design is not
changed. Parts information can be found in Appendix B. “Bill Of Materials (BOM)”.
3.3.1Pinout
Figure 3-1 shows the MCP651 op amp’s pinout. This is the standard 8-lead pinout,
except for pins 5 and 8 (V
Board is designed to take advantage of these input pins, but they are not necessary to
this board’s operation.
FIGURE 3-1:MCP651 Pinout.
Op Amps with No Connection (NC) at pins 1, 5 and 8 will operate properly on the
MCP651 Input Offset Evaluation Board. Other op amps may need to use an adaptor
board; see Section 3.3.5 “Other Single Op Amps”.
and CAL/CS). The MCP651 Input Offset Evaluation
CAL
3.3.2Removing the DUT
Since these boards come with the DUT (in SOIC-8) soldered on, it is necessary to
de-solder them. Figure 3-2 shows the location of the DUT for either a SOIC-8 or a
PDIP-8 package. A good de-soldering station makes this work much easier to do.
Solder onto the SOIC-8 pad shown in Figure 3-2. Pin 1 is on the top left (next to the U1
label). To avoid soldering and de-soldering many times, for slower parts, it may be
better to use the option discussed in Section 3.3.5 “Other Single Op Amps”.
3.3.4Single Op Amps in PDIP-8 Package
Remove the original SOIC-8 packaged part. Solder a DIP-8 IC Socket in the PDIP-8
location shown on Figure 3-2; this makes it easy to change PDIP-8 parts. It also is
helpful for parts for other package and pinout options; see Section 3.3.5 “Other Single Op Amps”. Figure 3-3 shows this board after the DIP-8 IC socket has been
installed.
FIGURE 3-3:PCB with SOIC-8 Part Removed and DIP-8 IC Socket Installed.
The socket may not work well in two cases (solder directly to the PCB instead):
• Very fast op amps (i.e., GBWP > 100 MHz)
• Very accurate op amps (i.e., V
<±50µV)
OST
3.3.5Other Single Op Amps
With a DIP-8 IC Socket on the evaluation board (see Section 3.3.4 “Single Op Amps
in PDIP-8 Package”), it is relatively easy to adapt the MCP651 Input Offset Evaluation
Board to many other op amps. An adaptor board is stacked on top using headers that
solder to the adaptor board, using PDIP-8 through holes, and are inserted into the
DIP-8 socket on the evaluation board. The adaptor board can accommodate:
• Different packages
• Different pinout options (can be dealt with on the adaptor board)
• Parts with multiple op amps
The adaptor boards approach may not work well in two cases:
• Fast op amps (i.e., GBWP > 10 MHz); adding bypass capacitors to the adaptor
board may help
Figure 3-4 shows a SOIC-8 op amp soldered onto the 8-Pin SOIC/MSOP/TSSOP/DIP
Evaluation Board available from Microchip Technology Inc. The two interconnect strips
on the bottom are soldered into the through holes for the DIP-8 socket. Figure 3-5
shows this board plugged into the MCP651 Input Offset Evaluation Board.
Note 1:Build the adaptor board in the following sequence. Insert the interconnect
headers into the DIP-8 socket on the MCP651 Input Offset Evaluation
Board. Place the SOIC8EV board on the top of the interconnect headers,
while maintaining the correct pin orientation. Solder the headers to the
top board. Clip the pins flush with the top surface of the SOIC8EV board,
then solder the (SOIC-8) op amp on the top.
2:See Table B-4 for part numbers of this board and its components.
FIGURE 3-4:Op Amp in SOIC-8 Package and Connector Headers Soldered to
Adaptor PCB.
FIGURE 3-5:Adaptor Board Connected to the MCP651 Input Offset Evaluation
Board.
This appendix contains the schematics and layouts for the MCP651 Input Offset
Evaluation Board.
A.2SCHEMATIC AND LAYOUTS
See A.3 “Board – Schematic” for the circuit diagram. U1 is the DUT (MCP651). U2
buffers the attenuated and filtered control voltage VCOX. U3 is the differential
integrator. U4 is the amplifier that gives the final gain to the DUT’s input offset voltage
(V
). Switch S1 gives the user a means of starting an auto-calibration cycle in the
OST
DUT. Switch S2 makes it so the amplifier (U4) can have two different gains, providing
a tradeoff between accuracy and range.
A.4 “Board – Combination of the Top Silk-Screen, Top Solder Mask and Top Metal
Layers” through A.7 “Board – Bottom Metal Layer” show the PCB layout plots. This
PCB has two metal layers: signal and power traces on top and ground plane on bottom.
Groups of critical resistors have been arranged so that their thermoelectric voltages
cancel (assuming constant temperature gradient); these groups are:
•R
through R
1
•R5 and R
•R7 and R
•R21 through R
•R24 and R
The Gerber files for this board are available on the Microchip website
(www.microchip.com) and are contained in the zip file “00258R2_Gerbers.zip”.
The BOM in Table B-1 shows all of the components assembled on the PCB. Table B-2
shows alternate components that can be placed on this PCB (after modification).
Table B-3 shows components that are not populated.
Note 1: The MCP6XXX represents any Microchip single op amp, with standard pinout, that fits the given design.
Reference
Designator
0.285" max. O.D.
1/4" long, Nylon
2: The components listed in this Bill of Materials are representative of the PCB assembly. The released BOM
used in manufacturing uses all RoHS-compliant components.
DescriptionManufacturerPart Number
MCP6XXX (Note 1)
Technology Inc.
2-641260-1
Electronics
Keystone
Electronics
Building
Fasteners
1902C
NY PMS 440 0025 PH
TABLE B-3:BILL OF MATERIALS FOR NOT POPULATED COMPONENTS
Qty
0C1Unknown Value, 0603 SMD, X7R, 16V, 10%Panasonic
Note 1: The components listed in this Bill of Materials are representative of the PCB assembly. The released BOM