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INTRODUCTION
This chapter contains general information that will be useful to know before using the
MCP651 Input Offset Evaluation Board. Items discussed in this chapter include:
• Document Layout
• Conventions Used in this Guide
• Recommended Reading
• The Microchip Web Site
• Customer Support
• Document Revision History
DOCUMENT LAYOUT
This document describes how to use the MCP651 Input Offset Evaluation Board. The
manual layout is as follows:
• Chapter 1. “Product Overview” - Important information about the MCP651 Input
Offset Evaluation Board.
• Chapter 2. “Installation and Operation” – Covers the initial set-up of the
MCP651 Input Offset Evaluation Board. It lists the required tools, shows how to
set up the board and how to connect lab equipment. It then demonstrates how to
use this board.
• Chapter 3. “Possible Modifications” – Shows how to modify the board for other
single Microchip op amps in SOIC-8, PDIP-8 and other packages.
• Appendix A. “Schematics and Layouts” – Shows the schematic and board
layouts for the MCP651 Input Offset Evaluation Board.
• Appendix B. “Bill Of Materials (BOM)” – Lists the parts used to populate the
MCP651 Input Offset Evaluation Board. Also lists loose parts shipped with the
board in an ESD bag, alternate components and components not populated.
This user's guide describes how to use MCP651 Input Offset Evaluation Board. Other
useful documents are listed below. The following Microchip documents are available
and recommended as supplemental reference resources.
MCP6V01/2/3 Data Sheet, “300 µA, Auto-Zeroed Op Amps”, DS22058
Gives detailed information on the op amp family that is used for signal processing and
output voltage control on the MCP651 Input Offset Evaluation Board.
MCP651 Data Sheet, “5 mA Op Amps with mCal”,DS22146
Gives detailed information on the op amp family that is used as the DUT on the
MCP651 Input Offset Evaluation Board.
AN1177 Application Note, “Op Amp Precision Design: DC Errors”,DS01177
Discusses how to achieve high DC accuracy in op amp circuits. Also discusses the
relationship between an op amp’s input offset voltage (V
Open-Loop Gain and V
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Customers should contact their distributor, representative or field application engineer
for support. Local sales offices are also available to help customers. A listing of sales
offices and locations is included in the back of this document.
Technical support is available through the web site at: http://support.microchip.com
The MCP651 Input Offset Evaluation Board is intended to provide a simple means to
measure the MCP651 Input Offset Evaluation Board op amp’s input offset voltage
under a variety of operating conditions. The measured input offset voltage (V
includes the input offset voltage specified in the data sheet (V
power supply voltage (PSRR), common mode voltage (CMRR), output voltage (A
input offset voltage drift over temperature (ΔV
The MCP651 Input Offset Evaluation Board works most effectively at room temperature (near 25°C). Measurements at other temperatures should be done in an oven
where the air velocity is minimal.
1.4DESCRIPTION
This section starts with the conversion of DUT bias voltages described in the MCP651
data sheet to the voltages on this board. Then there is a discussion of the circuitry that
controls the DUT’s output voltage (V
(V
OST
details of this board are given in Appendix A. “Schematics and Layouts” and
Appendix B. “Bill Of Materials (BOM)”.
1.4.1Conversion of Bias Voltages
) plus changes due to:
OS
/ΔTA) and 1/f noise.
OS
) and amplifies its total input offset voltage
OUTX
). Finally, other portions of the circuit, and their purpose, are discussed. Complete
OST
)
),
OL
The MCP651 data sheet describes all of its bias voltages relative to VSS, which is
assumed to be at ground (0V). On the other hand, the MCP651 Input Offset Evaluation
Board sets the DUT’s input common mode voltage to 0V. The user needs to convert
from the first set of voltages to the second set (by subtracting V
Figure 1-2 is a simplified diagram of the circuitry that biases the DUT and produces an
amplified version of the DUT’s input offset voltage (V
a Proportional plus Integral (PI) controller loop, a high gain amplifier and a filter.
). It includes gain at the input,
OST
FIGURE 1-2:Simplified Circuit.
The elements of Figure 1-2 correspond to the components in the complete schematic
(A.3 “Board – Schematic”) as follows.
Analysis of this simplified circuit gives the following nominal circuit outputs:
EQUATION 1-2:
R
and R2 (R12) balance the circuit at the DUT’s input. These resistors are small, and
1
are oriented on the Printed Circuit Board (PCB) to cancel their thermoelectric voltages.
The parallel resistances R
DUT’s input bias currents to the measured V
affect V
V
OST
); the typical value of IOS at +125°C is ±100 pA, which produces a change in
M
of ±0.02 µV.
The unity gain buffer (+1 gain on the bottom right) isolates the V
the following attenuator and integrator. Although it’s not shown here, the resistor R14
at the input to the “+1 Buffer” ensures its output voltage is 0V when the V
is left open.
The attenuators (1/G
U2 and U3 (“+1 Buffer” and (“Integrator”). For instance, when V
V
=0.3V and V
SSI
DDI
1.80V.
The differential integrator accumulates the scaled difference between V
V
, which slowly forces this difference to zero (the I part of the PI controller).
OUTX
Resistor R
R
; it minimizes the error at V
3
injects the integrator’s output at the DUT’s input through resistors R4 and
56
A proportional term (the P part of the PI controller) is also injected at the DUT’s input
through resistor R
78
negligible above 16 Hz). It also sets a low frequency DUT noise gain of about 505 V/V.
This proportional term is rolled off by C
interact with the integrator term, and low enough to keep the DUT stable. Thus, C
minimizes noise gain at higher frequencies, which reduces the chance of unwanted
feedback effects.
With the overall gain G
V
values up to either ±12.4 mV or ±1.25 mV. A voltmeter with 1 mV resolution can
OST
distinguish steps of either 5 µV or 0.5 µV, respectively.
The DUT’s noise seen at the input to G
R
and C2 (0.28 kHz). This implies that this noise is dominated by the 1/f noise. The
78
Lowpass Filter (f
≈ 1.6 Hz) reduces this 1/f noise a little more before it is seen at VM.
BW
The measured noise, over a 140 second period of time with a typical part, was about
19 µV
V
OS
referred to input (RTI). This compares favorably with the MCP651’s calibrated
P-P
specification (±200 µV, maximum at +25°C).
||R2 and R3||R4 are equal to minimize the contribution of the
) scale V
INT
1
and V
COX
(contributions by R5 through R8 do not
OST
input filters from
COX
COX
so that they do not overdrive op amps
OUTX
= 5.6V (given
OUTX
connector
= 5.8V), the voltages at the outputs of the attenuators (1/G
and
COX
.
OUTX
; it stabilizes the control loop (the integrator term becomes
starting at 0.18 kHz; this is high enough to not
2
of either 201 V/V or 1998 V/V, this circuit can measure