Microchip Technology EVB-LAN9252-HBI+ User Manual

EVB-LAN9252-HBI+

EtherCAT

®

Evaluation Board

User’s Guide

 2015-2016 Microchip Technology Inc. DS50002333C

Note the following details of the code protection feature on Microchip devices:

YSTEM 

CERTIFIEDBYDNV

== ISO/TS16949==

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be super­seded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REP­RESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR
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The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer,
LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST
Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

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Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial
Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless
DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.

GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.

All other trademarks mentioned herein are property of their respective companies.

© 2015-2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

ISBN: 9781522406839

QUALITYMANAGEMENTS

DS50002333C-page 2  2015-2016 Microchip Technology Inc.

Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

®

MCUs and dsPIC® DSCs, KEELOQ

®

code hopping

Object of Declaration: EVB-LAN9252-HBI+

 2015-2016 Microchip Technology Inc. DS50002333C-page 3

EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide

NOTES:

DS50002333C-page 4  2015-2016 Microchip Technology Inc.

EVB-LAN9252-HBI+

ETHERCAT® EVALUATION BOARD

USER’S GUIDE

Table of Contents

Preface ........................................................................................................................... 7

Introduction............................................................................................................ 7

Document Layout .................................................................................................. 7

Conventions Used in this Guide ............................................................................ 8

The Microchip Web Site ........................................................................................ 9

Development Systems Customer Change Notification Service ............................ 9

Customer Support ................................................................................................. 9

Document Revision History ................................................................................. 10

Chapter 1. Overview

1.1 Introduction ................................................................................................... 11

1.2 References ................................................................................................... 13

1.3 Terms and Abbreviations ............................................................................. 13

Chapter 2. Board Details & Configuration

2.1 Power ........................................................................................................... 14

2.1.1 +5V Power ................................................................................................. 14

2.2 Resets .......................................................................................................... 14

2.2.1 Power-on Reset ......................................................................................... 14

2.2.2 Reset Out .................................................................................................. 14

2.2.3 GPIO Reset ............................................................................................... 14

2.3 Clock ............................................................................................................ 15

2.4 Configuration ................................................................................................ 15

2.4.1 Strap Options ............................................................................................ 16

2.4.2 LED Indicators ........................................................................................... 18

2.4.3 EEPROM Switch ....................................................................................... 19

2.4.4 DIGIO/HBI/SPI+GPIO Selection ................................................................ 19

2.4.5 SoC ........................................................................................................... 23

2.5 DIGIO & SPI+16GPIO Signals on P1 and P2 Headers ................................ 25

2.5.1 DIGIO on P1 and P2 Headers (up to 16 bits supported) ........................... 25

2.5.2 SPI+GPIO on P1 and P2 Headers (up to 16 bits supported) .................... 26

2.6 Additional Features ...................................................................................... 27

2.6.1 Potentiometer ............................................................................................ 27

2.6.2 Temperature Sensor ................................................................................. 27

2.6.3 UART RS-232 ........................................................................................... 27

2.6.4 DAC ........................................................................................................... 27

2.7 Limitations .................................................................................................... 27

2.8 Mechanicals ................................................................................................. 28

Chapter 3. Software Development Kit

3.1 Prerequisites ................................................................................................ 29

 2015-2016 Microchip Technology Inc. DS50002333C-page 5

EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide

3.1.1 Hardware Requirements ............................................................................29

3.1.2 Software Requirements .............................................................................29

3.2 ESC SDK Sample Overview ........................................................................ 29

3.2.1 User Module ...............................................................................................30

3.2.2 EtherCAT® Slave Stack .............................................................................30

3.2.3 Hardware Abstraction Layer (HAL) ............................................................30

3.3 Using the Sample Project ............................................................................. 31

3.3.1 MPLAB IDE Project Settings & Firmware Download .................................31

3.3.2 Compiling and Programming SoC Firmware .............................................33

3.4 Programming the LAN9252 EEPROM ......................................................... 34

3.4.1 Programming LAN9252 EEPROM using the TwinCAT Master Tool .........34

Appendix A. Evaluation Board Photo

A.1 Introduction .................................................................................................. 37

Appendix B. Evaluation Board Schematics

B.1 Introduction .................................................................................................. 38

Appendix C. Bill of Materials (BOM)

C.1 Introduction .................................................................................................. 49

Worldwide Sales and Service .....................................................................................54

DS50002333C-page 6  2015-2016 Microchip Technology Inc.

EVB-LAN9252-HBI+

ETHERCAT® EVALUATION BOARD

USER’S GUIDE

Preface

NOTICE TO CUSTOMERS

All documentation becomes dated, and this manual is no exception. Microchip tools and
documentation are constantly evolving to meet customer needs, so some actual dialogs
and/or tool descriptions may differ from those in this document. Please refer to our web site
(www.microchip.com) to obtain the latest documentation available.

Documents are identified with a “DS” number. This number is located on the bottom of each
page, in front of the page number. The numbering convention for the DS number is
“DSXXXXXA”, where “XXXXX” is the document number and “A” is the revision level of the
document.

For the most up-to-date information on development tools, see the MPLAB
Select the Help menu, and then Topics to open a list of available online help files.

®

IDE online help.

INTRODUCTION

This chapter contains general information that will be useful to know before using the
EVB-LAN9252-HBI+. Items discussed in this chapter include:

• Document Layout

• Conventions Used in this Guide

• The Microchip Web Site

• Development Systems Customer Change Notification Service

• Customer Support

• Document Revision History

DOCUMENT LAYOUT

This document describes how to use the EVB-LAN9252-HBI+ as a development tool
for the Microchip LAN9252 EtherCAT® slave controller. The manual layout is as
follows:

• Chapter 1. “Overview” – Shows a brief description of the EVB-LAN9252-HBI+.

• Chapter 2. “Board Details & Configuration” – Includes details and instructions

for using the EVB-LAN9252-HBI+.

• Chapter 3. “Software Development Kit” – Includes details and instructions for

using the LAN9252 EtherCAT® slave stack firmware and SDK framework.

• Appendix A. “Evaluation Board Photo” – This appendix shows the

EVB-LAN9252-HBI+.

• Appendix B. “Evaluation Board Schematics” – This appendix shows the

EVB-LAN9252-HBI+ schematics.

• Appendix C. “Bill of Materials (BOM)” – This appendix includes the

EVB-LAN9252-HBI+ Bill of Materials (BOM).

 2015-2016 Microchip Technology Inc. DS50002333C-page 7

EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide

CONVENTIONS USED IN THIS GUIDE

This manual uses the following documentation conventions:

DOCUMENTATION CONVENTIONS

Description Represents Examples

Arial font:

Italic characters Referenced books MPLAB® IDE User’s Guide

Emphasized text ...is the only compiler...

Initial caps A window the Output window

A dialog the Settings dialog
A menu selection select Enable Programmer

Quotes A field name in a window or

dialog

Underlined, italic text with
right angle bracket

Bold characters A dialog button Click OK

N‘Rnnnn A number in verilog format,

Text in angle brackets < > A key on the keyboard Press <Enter>, <F1>

Courier New font:

Plain Courier New Sample source code #define START

Italic Courier New A variable argument file.o, where file can be

Square brackets [ ] Optional arguments mcc18 [options] file

Curly brackets and pipe
character: { | }

Ellipses... Replaces repeated text var_name [,

A menu path File>Save

A tab Click the Power tab

where N is the total number of
digits, R is the radix and n is a
digit.

Filenames autoexec.bat
File paths c:\mcc18\h
Keywords _asm, _endasm, static
Command-line options -Opa+, -Opa-
Bit values 0, 1
Constants 0xFF, ‘A’

Choice of mutually exclusive
arguments; an OR selection

Represents code supplied by
user

“Save project before build”

4‘b0010, 2‘hF1

any valid filename

[options]
errorlevel {0|1}

var_name...]

void main (void)
{ ...
}

DS50002333C-page 8  2015-2016 Microchip Technology Inc.

Preface

THE MICROCHIP WEB SITE

Microchip provides online support via our web site at www.microchip.com. This web
site is used as a means to make files and information easily available to customers.
Accessible by using your favorite Internet browser, the web site contains the following
information:

• Product Support – Data sheets and errata, application notes and sample

programs, design resources, user’s guides and hardware support documents,
latest software releases and archived software

• General Technical Support – Frequently Asked Questions (FAQs), technical

support requests, online discussion groups, Microchip consultant program
member listing

• Business of Microchip – Product selector and ordering guides, latest Microchip

press releases, listing of seminars and events, listings of Microchip sales offices,
distributors and factory representatives

DEVELOPMENT SYSTEMS CUSTOMER CHANGE NOTIFICATION SERVICE

Microchip’s customer notification service helps keep customers current on Microchip
products. Subscribers will receive e-mail notification whenever there are changes,
updates, revisions or errata related to a specified product family or development tool of
interest.

To register, access the Microchip web site at www.microchip.com, click on Customer
Change Notification and follow the registration instructions.

The Development Systems product group categories are:

• Compilers – The latest information on Microchip C compilers, assemblers, linkers

and other language tools. These include all MPLAB C compilers; all MPLAB
assemblers (including MPASM assembler); all MPLAB linkers (including MPLINK
object linker); and all MPLAB librarians (including MPLIB object librarian).

• Emulators – The latest information on Microchip in-circuit emulators.This

includes the MPLAB REAL ICE and MPLAB ICE 2000 in-circuit emulators.

• In-Circuit Debuggers – The latest information on the Microchip in-circuit

debuggers. This includes MPLAB ICD 3 in-circuit debuggers and PICkit 3 debug
express.

• MPLAB IDE – The latest information on Microchip MPLAB IDE, the Windows

Integrated Development Environment for development systems tools. This list is
focused on the MPLAB IDE, MPLAB IDE Project Manager, MPLAB Editor and
MPLAB SIM simulator, as well as general editing and debugging features.

• Programmers – The latest information on Microchip programmers. These include

production programmers such as MPLAB REAL ICE in-circuit emulator, MPLAB
ICD 3 in-circuit debugger and MPLAB PM3 device programmers. Also included
are nonproduction development programmers such as PICSTART Plus and
PIC-kit 2 and 3.

CUSTOMER SUPPORT

Users of Microchip products can receive assistance through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

 2015-2016 Microchip Technology Inc. DS50002333C-page 9

EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide

Customers should contact their distributor, representative or field application engineer
(FAE) for support. Local sales offices are also available to help customers. A listing of
sales offices and locations is included in the back of this document.

Technical support is available through the web site at:

http://www.microchip.com/support

DOCUMENT REVISION HISTORY

Revision Section/Figure/Entry Correction

DS50002333C (06-17-16)

All

Figure 1-1

Chapter 2. “Board
Details & Configuration”

2.1.1 “+5V Power”

2.6 “Additional Features”

Chapter 3. “Software
Development Kit”

Appendix A. “Evaluation
Board Photo”

Appendix B. “Evaluation
Board Schematics”

Appendix C. “Bill of
Materials (BOM)”

DS50002333B (05-12-15)

All

Section 1.2 “References”

Section 2.4.4 “DIGIO/HBI/
SPI+GPIO Selection”

Table 2-13, Table 2-14,
and Table 2-15

DS50002333A (02-27-15) Initial Release of Document

Updated board name to “EVB-LAN9252-HBI+”
throughout document.

Updated figure to include UART, Temp. Sensor,
DAC, and ADC.

Updated Figures 1, 5, 6, 7, and 10. Added new Fig­ure 2.

Updated Tables 13, 14, 15, 21.

Removed power supply manufacturer and part num­ber.

Added new section with new features.

Updated figures throughout chapter.

Updated appendix with new photos.

Updated appendix with new schematics.

Updated appendix with updated BOM.

Updated board name to “EVB-LAN9252-HBI”
throughout document, corrected misc. typos and
grammatical errors.

Updated list of application notes.

Added additional information on DIGIO mode.

Simplified table and added note under each table for
clarity.

DS50002333C-page 10  2015-2016 Microchip Technology Inc.

1.1 INTRODUCTION

The LAN9252 is a 2-port EtherCAT® Slave Controller (ESC) with dual integrated Ether­net PHYs which each contain a full-duplex 100BASE-TX transceiver and support
100Mbps (100BASE-TX) operation. 100BASE-FX is supported via an external fiber
transceiver.

Each port receives an EtherCAT® frame, performs frame checking and forwards it to
the next port. Time stamps of received frames are generated when they are received.
The Loop-back function of each port forwards the frames to the next logical port if there
is either no link at a port, if the port is not available, or if the loop is closed for that port.
The Loop-back function of port 0 forwards the frames to the EtherCAT® Processing
Unit. The loop settings can be controlled by the EtherCAT® master.

Packets are forwarded in the following order:

Port 0 -> EtherCAT® Processing Unit -> Port 1 -> Port 2.

The EtherCAT® Processing Unit (EPU) receives, analyzes and processes the Ether­CAT® data stream. The main purpose of the EtherCAT® Processing unit is to enable
and coordinate access to the internal registers and the memory space of the ESC,
which can be addressed both from the EtherCAT® master and from the local applica­tion. Data exchange between master and slave applications is comparable to a
dual-ported memory (process memory), enhanced by special functions for consistency
checking (SyncManager) and data mapping (FMMU). Each FMMU performs bitwise
mapping of logical EtherCAT® system addresses to physical device addresses.

The scope of this document is to describe the EVB-LAN9252-HBI+ setup, which sup­ports a HBI/SPI+GPIO Interface and corresponding jumper configurations. The
LAN9252 is connected to an RJ45 Ethernet jack with integrated magnetics for
100BASE-TX connectivity. A simplified block diagram of the EVB-LAN9252-HBI+ is
shown in Figure 1-1.

EVB-LAN9252-HBI+

ETHERCAT® EVALUATION BOARD

USER’S GUIDE

Chapter 1. Overview

 2015-2016 Microchip Technology Inc. DS50002333C-page 11

EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide

Microchip

LAN9252

EEPROM

EVB-LAN9252-HBI+

100BASE-TX

Ethernet

Magnetics &

RJ45

100BASE-TX

Ethernet

Magnetics &

RJ45

Straps

Port 0 Port 1

Crystal

Power

Supply

Module

Ethernet Ethernet

5V

HBI or SPI+GPIO

Selection

HBI Mode

Selection

Board to Board Connector

Board to Board Connector

Onboard Soc

PIC32MX795F512L

SPI/SQI/I2C

AARDVARK

Fiber-

SFP

Port 0

Fiber-

SFP

Port 1

UART

Temp

Sensor

DAC

ADC

FIGURE 1-1: EVB-LAN9252-HBI+ BLOCK DIAGRAM

DS50002333C-page 12  2015-2016 Microchip Technology Inc.

1.2 REFERENCES

Concepts and material available in the following documents may be helpful when read­ing this document. Visit www.microchip.com for the latest documentation.

• LAN9252 Data Sheet

• AN 8.13 Suggested Magnetics

• EVB-LAN9252-HBI+ Schematics

• The following application notes:

- AN1916 Integrating Microchip’s LAN9252 SDK with Beckhoff’s EtherCAT®
SSC

- AN1920 Microchip LAN9252 EEPROM Configuration and Programming

- AN1907 Microchip LAN9252 Migration from Beckhoff ET1100



1.3 TERMS AND ABBREVIATIONS

IDE - Integrated Development Environment

ESC - EtherCAT® Slave Controller

EVB - Engineering Validation Board

HAL - Hardware Abstraction Layer

HBI - Host Bus Interface

SPI - Serial Protocol Interface

SSC - Slave Stack Code

Overview

 2015-2016 Microchip Technology Inc. DS50002333C-page 13

Chapter 2. Board Details & Configuration

2.1 POWER

EVB-LAN9252-HBI+

ETHERCAT® EVALUATION BOARD

USER’S GUIDE

This chapter includes sub-sections on the following EVB-LAN9252-HBI+ details:

•Power

• Resets

• Clock

• Configuration

• Additional Features

• Limitations

• Mechanicals

2.1.1 +5V Power

Power is supplied to the LAN9252 by a +3.3V on-board regulator, which is powered by
a +5V external wall adapter. The LAN9252 includes an internal +1.2V regulator which
supplies power to the internal core logic. Assertion of the D1 Green LED indicates suc­cessful generation of +3.3V o/p. The SW1 switch must be in the ON position for the +5V
to power the +3.3V regulator.

2.2 RESETS

2.2.1 Power-on Reset

A power-on reset occurs whenever power is initially applied to the LAN9252 or if the
power is removed and reapplied to the LAN9252. This event resets all circuitry within
the LAN9252. After initial power-on, the LAN9252 can be reset by pressing the reset
switch SW2. The reset LED D2 will assert (red) when the LAN9252 is in reset condition.
For stability, a delay of approximately 180ms is added from the +3.3V o/p to reset
release.

2.2.2 Reset Out

The LAN9252 reset pin can be configured as an output to reset the SoC. The RST# pin
becomes an open-drain output and is asserted for the minimum required time of 80ms.

2.2.3 GPIO Reset

The EVB-LAN9252-HBI+ provides the option to reset the LAN9252 through a PIC
GPIO pin [95(RG14)]. The SW10 switch is used for this selection, as shown in
Ta bl e 2 -1 .

TABLE 2-1: RESET CONFIGURATION SWITCH

Switch Short Pins Knob Position Function

SW10 1-3 1-2 System Reset (SYS_RESETN) (Default)

SW10 1-2 1-3 GPIO Reset (RST_GPIO)

 2015-2016 Microchip Technology Inc. DS50002333C-page 14

2.3 CLOCK

The EVB-LAN9252-HBI+ utilizes an external 25MHz 25ppm crystal from Cardinal
Components Inc. (P/N: CSM1Z-A5B2C5-40-25.0D18-F).

2.4 CONFIGURATION

The following sub-sections describe the various board features and configuration set­tings. A top view of the EVB-LAN9252-HBI+ is shown in Figure 2-1. Figure 2-2 details
new features.

FIGURE 2-1: EVB-LAN9252-HBI+ TOP VIEW WITH CALLOUTS

Board Details & Configuration

 2015-2016 Microchip Technology Inc. DS50002333C-page 15

EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide

FIGURE 2-2: EVB-LAN9252-HBI+ TOP VIEW NEW FEATURE CALLOUTS

2.4.1 Strap Options

2.4.1.1 CHIP MODE SELECTION

Table 2-2 details the LAN9252 chip mode configuration straps.

TABLE 2-2: CHIP MODE CONFIGURATION STRAP

Header Description Pins Settings

J4,J6,J7,J9 Chip mode configuration strap

inputs. This strap determines
the number of active ports and
port types.

1-2

Short 1-2 for high (pull-up)
(Not supported in this EVB)

2-3

Short 2-3 for low (pull-down) (default)

Note: This EVB supports Chip mode 00 which is 2-port mode, where Port 0 = PHY

A and Port 1 = PHY B. This requires J4, J6, J7, and J9 to be pulled-down
(2-3) shorted. All other configurations are not supported with this EVB.

2.4.1.2 EEPROM SIZE CONFIGURATION

The EEPROM size configuration strap (J5 & J8) determines the supported EEPROM
size range. A low selects 1Kbits (128 x 8) through 16Kbits (2K x 8)_24C16. A high
selects 32Kbits (4K x 8) through 512Kbits (64K x 8) or 4Mbits (512K x 8)_24C512.

TABLE 2-3: EEPROM SIZE CONFIGURATION STRAP

Header Description Pins Settings

J5, J8 EEPROM size configuration

strap inputs. This strap deter­mines the supported
EEPROM size range.

1-2

Short 1-2 for high (pull-up) (default)

2-3

Short 2-3 for low (pull-down)

2.4.1.3 COPPER AND FIBER STRAPS

The LAN9252 supports 100BASE-TX (Copper) and 100BASE-FX (Fiber) modes. In
100BASE-FX operation, the presence of the receive signal is indicated by the external
transceiver as either an open-drain, CMOS level, Loss of Signal (SFP) or a LVPECL
Signal Detect (SFF).

DS50002333C-page 16  2015-2016 Microchip Technology Inc.

Board Details & Configuration

This EVB supports 100BASE-TX (Copper) and SFP 100BASE-FX (Fiber) modes. By
default Copper Mode is active. Fiber Mode is supported as an assembly option. To
select the Copper or Fiber Mode, the respective strap and signal routing resister
assembly options must to be configured.

Note: Vendor part number for SFP: Finisar/FTLF1217P2

2.4.1.3.1 Copper Mode

The EVB-LAN9252-HBI+ is set to Copper Mode by default. Table 2-4 details the
required strap resistor settings for Copper Mode operation.

TABLE 2-4: COPPER MODE STRAP RESISTORS

Resistors Description

R79 (10K) Configures Port 0 & 1 to Copper Mode

R76, R80 (10K) Configures Port 0 and Port 1 to Copper Mode, respectively

Note: R75, R77, and R78 must not be populated (DNP).

Additionally, the signal routing resistors detailed in Table 2-5 must be assembled for
Copper Mode operation.

TABLE 2-5: COPPER MODE SIGNAL ROUTING RESISTORS

Resistors Description

R17, R19, R21, R23 Port 0 Copper Mode enabled

R31, R33, R35, R37 Port 1 Copper mode enabled

Note: R16, R18, R20, R22, R30, R32, R34, and R36 (0402 package) must not be

populated (DNP).

2.4.1.3.2 Fiber Mode

The EVB-LAN9252-HBI+ support SFP type 100BASE-FX. To enable Fiber Mode, the
respective strap and signal routing resistors must be configured.

Note: Copper Mode related resistors must be DNP while Fiber Mode is active

(See Section 2.4.1.3.1 “Copper Mode”).

Table 2-6 details the required strap resistor settings for Fiber Mode operation.

TABLE 2-6: FIBER MODE STRAP RESISTORS

Resistors Description

R77 (10K) Configures Port 0 & 1 to FX-LOS Mode

R75, R78 (10K) Configures Port 0 and Port 1 to Fiber Mode, respectively

Note: R76, R79, and R80 must not be populated (DNP).

Additionally, the signal routing resistors detailed in Table 2-7 must be assembled for
Fiber Mode operation.

TABLE 2-7: FIBER MODE SIGNAL ROUTING RESISTORS

Resistors Description

R16, R18, R20, R22 Port 0 Fiber Mode enabled

R30, R32, R34, R36 Port 1 Fiber mode enabled

 2015-2016 Microchip Technology Inc. DS50002333C-page 17

EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide

Note: R17, R19, R21, R23, R31, R33, R35, and R37 (0402 package) must not be

populated (DNP).

2.4.1.3.3 FX-LOS Fiber Mode Strap

FX-LOS strap details are shown in Table 2-8. These strap settings determine if the
ports are to operate in FX-LOS Fiber Mode or FX-SD/Copper Mode.

TABLE 2-8: FX-LOS MODE STRAP SETTINGS

R77 (10K) R79 (10K)

Populate DNP 3.3 A level above 2V selects FX-LOS for Port 0 and

Populate Populate 1.5 A level greater than 1.5V and below 2V selects

DNP Populate 0 (Default) A level of 0V selects FX-SD / copper twisted pair

Note: The above strap details describe the LAN9252 function. This EVB does not

support SFF Fiber Mode. Therefore, FX-SD related straps are not applica­ble.

Reference

Volta g e ( V )

Function

Port 1

FX-LOS for Port 0 and FX-SD / copper twisted
pair for Port 1, further determined by FXSDB

for Ports 0 and 1, further determined by FXSDA
and FXSDB

2.4.2 LED Indicators

The D3 and D4 LEDs are used to indicate the Link/Activity status on the corresponding
EVB ports, as detailed in Table 2-9. The Link/Act LED should be ON at each port when
the cable is present. If the Link/Act LED is not ON, it indicates there is an issue with the
connection or cable.

TABLE 2-9: D3 AND D4 LINK/ACTIVITY LED STATUS INDICATORS

State Description

Off Link is down

Flashing Green Link is up with activity

Steady Green Link is up with no activity

Additionally, the D5 LED is used as a RUN indicator (green) to show the AL status of
the EtherCAT® State Machine (ESM), as detailed in Table 2-10.

TABLE 2-10: D5 RUN LED STATUS INDICATOR

State Description

Off The device is in the INITIALIZATION state

Blinking (on 200ms, off 200ms) The device is in the PRE-OPERATIONAL state

Single Flash (on 200ms, off 1000ms) The device is in the SAFE-OPERATIONAL state

On The device is in the OPERATIONAL state

Flickering (on 50ms, off 50ms) The device is booting and has not yet entered

the INITIALIZATION state, or the device is in the
BOOTSTRAP state and firmware download is in
progress. (Optional. Off when not implemented.)

DS50002333C-page 18  2015-2016 Microchip Technology Inc.

Board Details & Configuration

R/W AA1 A00 A20 11

Start Read/Write

Slave Address

2.4.3 EEPROM Switch

The EVB-LAN9252-HBI+ utilizes 0x50 (7-bit) I2C slave addressing. The SW3 switch
can be used to select the A0, A1, and A2 address bits, as shown in Figure 2-3 and
Table 2-11. The eighth bit of the slave address determines if the master device wants
to read or write to the EEPROM (24FC512).

FIGURE 2-3: SLAVE ADDRESS ALLOCATION

TABLE 2-11: EEPROM SWITCH

Switch Description Settings

SW3 I2C EEPROM address selection switch

(A0, A1, A2). See Figure 2-3.

ON for logic 0 (default)
OFF for logic 1

2.4.4 DIGIO/HBI/SPI+GPIO Selection

The EVB-LAN9252-HBI+ supports three LAN9252 configurations:

• DIGIO Mode

•HBI Mode

• SPI + 16 GPIO Mode

DIGIO and HBI modes use the same switch configuration. The DIGIO/HBI or
SPI+GPIO configuration is selected using the DPDT SW11 to SW21 switches. By
default, the EVB is set to DIGIO mode and no code is programmed to the on-board
PIC32MX. In DIGIO mode, headers P1 and P2 can be used to probe the input and out­put control signals. It is not possible to configure the input or see to output on the LED
on the EVB. Refer to Table 2-22 for a mapping of the DIGIO signals on the P1 and P2
headers.

Note: The PDI configuration which is selected in hardware must match with the

PDI configuration that is chosen in the EtherCAT SDK during the SSC inte­gration process. An appropriate PDI configuration must be set in the ESC
configuration area of the EEPROM.

TABLE 2-12: HBI/SPI+GPIO SWITCH CONFIGURATIONS

Switch Description Settings

SW11 to SW21 Up DIGIO/HBI Mode (Default)

SW11 to SW21 Down SPI+GPIO Mode

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EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide

DIGIO/HBI Mode

SPI+GPIO Mode

FIGURE 2-4: SW11-SW21 DIGIO/HBI/SPI+GPIO MODE SELECTION

2.4.4.1 HBI MODE SELECTION

The LAN9252 supports six HBI modes. These six HBI modes (Multiplexed Modes and
Indexed Modes) can be selected using the SPST switches (P/N: 450301014042-Wurth
Electronics) SW5 through SW9 and SW22 through SW25. Through the switches the
LAN9252 HBI signals are connected to the SoC.

Note: For switch P/N: 450301014042, pin 1 is at the middle of the switch. To short

1-2, knob position must be in the 1-3 position, and vice versa.

2.4.4.1.1 Multiplexed Modes

The following four HBI Multiplexed Modes are supported:

1. 8-bit Multiplexed single-phase mode

2. 16-bit Multiplexed single-phase mode

3. 8-bit Multiplexed dual-phase mode

4. 16-bit Multiplexed dual-phase mode

Each HBI Multiplexed Mode requires an updated ESI file, EEPROM and PDI driver with
configured SSC to be programmed to the PIC32MX. For additional software informa­tion, refer to Chapter 3. “Software Development Kit”.

Figure 2-5 details the switch selection for Multiplexed Mode. All four Multiplexed Modes
utilize the same switch positions.

FIGURE 2-5: MULTIPLEXED HBI MODE SELECTION

Table 2-13 details the switch selection for Multiplexed Mode.

TABLE 2-13: MULTIPLEXED HBI MODE SELECTION

Switch Switch Knob Position Start Destination

SW5 Down A0_AD15 A0_CONFIG3

SW6 Up RD_RDWR GPMC_DIR

SW7 Down ALELO_A1 A1_CONFIG3

SW8 Down WR_ENB GPMC_DE0N_CLE

SW9 Down ALEHI_A2 A2_CONFIG3

SW24 Up A0_CONFIG3 GPMC_A0_ALE

SW25 Up A1_CONFIG3 GPMC_A1_ALEHI

DS50002333C-page 20  2015-2016 Microchip Technology Inc.

Board Details & Configuration

Note: When the switch knob is in the down position, pins 1-2 are shorted and the

dot on the switch can be seen. When the switch knob is in the up position,
pins 1-3 are shorted and no dot can be seen.

2.4.4.1.2 Indexed Mode

There are 2 different Indexed modes, 8-bit and 16-bit. Each HBI Indexed Mode requires
an updated ESI file, EEPROM and PDI driver with configured SSC to be programmed
to the PIC32MX. For additional software information, refer to Chapter 3. “Software
Development Kit”.

8-Bit Indexed Mode

Figure 2-6 details the switch selection for 8-Bit Indexed Mode.

FIGURE 2-6: 8-BIT INDEXED HBI MODE SELECTION

Table 2-14 details the switch selection for 8-bit Indexed HBI Mode.

TABLE 2-14: 8-BIT INDEXED HBI MODE SELECTION

Switch Switch Knob Position Start Destination

SW5 Up A0_AD15 AD15_CONFIG3

SW6 Up RD_RDWR GPMC_DIR

SW7 Up ALELO_A1 ALELO_CONFIG3

SW8 Down WR_ENB GPMC_DE0N_CLE

SW9 Up ALEHI_A2 ALEHI_CONFIG3

SW24 Down ALELO_CONFIG3 GPMC_A0_ALE

SW25 Down ALEHI_CONFIG3 GPMC_A1_ALEHI

Note: When the switch knob is in the down position, pins 1-2 are shorted and the

dot on the switch can be seen. When the switch knob is in the up position,
pins 1-3 are shorted and no dot can be seen.

16-Bit Indexed Mode

Figure 2-7 details the switch selection for 16-Bit Indexed Mode.

FIGURE 2-7: 16-BIT INDEXED HBI MODE SELECTION

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EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide

Table 2-15 details the switch selection for 16-bit Indexed HBI Mode.

TABLE 2-15: 16-BIT INDEXED HBI MODE SELECTION

Switch Switch Knob Position Start Destination

SW5 Down A0_AD15 A0_CONFIG3

SW6 Up RD_RDWR GPMC_DIR

SW7 Up ALELO_A1 ALELO_CONFIG3

SW8 Down WR_ENB GPMC_DE0N_CLE

SW9 Up ALEHI_A2 ALEHI_CONFIG3

SW24 X (Don’t Care) X X

SW25 Down ALEHI_CONFIG3 GPMC_A1_ALEHI

Note: When the switch knob is in the down position, pins 1-2 are shorted and the

dot on the switch can be seen. When the switch knob is in the up position,
pins 1-3 are shorted and no dot can be seen.

Note: If any other SoC is used, the user must check what modes are supported

and configure the HBI mode selection switches accordingly.

2.4.4.2 SPI+GPIO SELECTION

The knob position of SW11 to SW21 must be down to select the SPI+GPIO mode.
SW19, SW20, and SW21 are used to route the SPI/SQI signals from the LAN9252 to
the SoC. SW11 to SW18 are used to route the 16 GPIO signals from the LAN9252 to
the GPIO circuit.

TABLE 2-16: SW19-SW21 SIGNAL DEFINITIONS

Switch Signals

SW19 (pin 2-3 & pin 5-6) SIO3 & SIO2

SW20 (pin 2-3 & pin 5-6) SIO0 & SIO1

SW21 (pin 2-3 & pin 5-6) SCK & SCS#

2.4.4.2.1 SPI/SQI/I

2

C Aardvark Header

J11 and J12 are used as Aardvark/SPI/SQI headers. The respective pin details are
shown in Table 2-17.

TABLE 2-17: J11 & J12 HEADER PINOUT

Signal Pin Number

SCL J11.1

SDA J11.3

SCK J11.7

SCS# J11.9

SI(SIO0) J11.8

SO(SIO1) J11.5

SIO2 J12.3

SIO3 J12.4

DS50002333C-page 22  2015-2016 Microchip Technology Inc.

Board Details & Configuration

2.4.4.3 GPIO INPUT/OUTPUT SELECTION

To enable the SPI+GPIO configuration, the SW11 to SW18 switches must be in the
down position. Additionally, the following switches must be configured to select the
input or output modes, as shown in Table 2-18.

TABLE 2-18: GPIO MODE SWITCH CONFIGURATIONS

Switches Switch Knob Position Mode

SW28 to SW33
SW35 to SW39
SW41 to SW45

SW28 to SW33
SW35 to SW39
SW41 to SW45

2.4.4.3.1 GPIO INPUT Mode

In INPUT Mode, Digital I/O values can be selected through dip switches SW34 and
SW40:

• Logic 1 : (Default) SW34 & SW40 Off position. GPI0 to GPI15 tied to pull-up (R90
to R105)

• Logic 0 : The respective knob of 2-way, 8-position dip switch (SW34 & SW40)
need to be moved to ON side. Signals can be selected individually.

Short Pins 1 and 2 INPUT Mode

Short Pins 1 and 3 OUTPUT Mode

2.4.4.3.2 GPIO OUTPUT Mode

In OUTPUT Mode, updated GPO values will be seen on the green LEDs (D7 to D22):

• Logic 1 : LED illuminated (green)

• Logic 0 : LED not illuminated.

Note: The LED (D7 to D22) anode is connected to ASIC.

2.4.5 SoC

The EVB-LAN9252-HBI+ supports both an on-board SoC and add-on SoC. By default,
the on-board SoC is enabled. However, an external add-on SoC can be connected via
the add-on SoC headers P1 and P2. The SoC selection is configured via the SW26
switch, as detailed in the following subsections.

2.4.5.1 SOC SELECTION

The SW26 switch selects the enabled SoC. The SW26 switch knob position must be
down (Text = “PIC”) to select the on-board PIC. If the switch knob position is up (Text =
“PIM”), then the add-on board/SoC is selected and the on-board PIC is always in the
reset state. Whenever an add-on board/SoC is used, the switch knob must be in the up
position.

TABLE 2-19: SOC SELECTION

Switch Position Settings

SW26 Down On-board PIC enabled

SW26 Up Add-on board/SoC enabled

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EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide

2.4.5.2 ON-BOARD PIC

By default, the on-board Microchip PIC32MX795F512L (U7) is used as the default
SoC. The LAN9252 can be connected to the PIC using either an HBI or SPI interface.
The selection switches must be configured accordingly to enable the desired interface.
Refer to Section 2.4.4 “DIGIO/HBI/SPI+GPIO Selection” and Section 2.4.4.1 “HBI
Mode Selection” for additional details.

2.4.5.2.1 Reset

SW27 is used to reset the on-board PIC. The LAN9252 can also reset the SoC if the
reset pin is configured to output mode. For stability, a delay of approximately 180ms is
added from the 3.3V o/p to reset release.

2.4.5.2.2 ICSP Header

The on-board PIC programing is performed using the ICSP header J13. Table 2-20
details the ICSP header pinout

TABLE 2-20: J13 ICSP HEADER PINOUT

J13 Pin Settings

1MLCR

23V3

3GND

4PGD2

5PGC2

6NC

2.4.5.2.3 SoC EEPROM

The EVB-LAN9252-HBI+ provides an optional SoC EEPROM. Some SoCs may
require an EEPROM. However, the PIC on-board SoC and PIC based add-on SoC
boards do not require this EEPROM.

2.4.5.3 ADD-ON SOC

An add-on board can be attached to the EVB-LAN9252-HBI+ to use an add-on SoC.
The add-on board must be mounted to the P1 and P2 connectors (2x23, 100mil normal
gold plated berg stick). The SW26 switch must be in the up position when using an
add-on SoC. Additionally, the J10 2-pin jumper must be shorted to route power to the
add-on board from the EVB-LAN9252-HBI+.

2.4.5.4 ESC ID SELECT

The signals shown in Table 2-21 are provided as EtherCAT® ID selection for complex
ESCs. Jumper J20 and respective pull-up resistors are used to configure the ID select
signals high or low. By default, there are no resistors populated and all signals are nei­ther high or low. When required, populating the respective jumper or resistor will
change the ID select signal to low.

TABLE 2-21: ID SELECT SIGNALS

ID Selection

Signal

ID0 ID0_SELECT_RB0 25 R123 32:31

ID1 ID_SELECT_RB1 24 R124 30:29

ID2 ID_SELECT_RB2 23 R125 28:27

ID3 ID_SELECT_RB3 22 R126 26:25

ID4 ID_SELECT_RB4 21 R127 24:23

Signal Name

PIC Pin

Number

10k to Pull

High

Pins to Short

for Pull Low

DS50002333C-page 24  2015-2016 Microchip Technology Inc.

Board Details & Configuration

TABLE 2-21: ID SELECT SIGNALS (CONTINUED)

ID Selection

Signal

ID5 ID_SELECT_RB5 20 R128 22:21

ID6 ID_SELECT_RB8 32 R129 20:19

ID7 ID_SELECT_RB9 33 R130 18:17

ID8 ID_SELECT_RB10 34 R131 16:15

ID9 ID_SELECT_RB11 35 R132 14:13

ID10 ID_SELECT_RB12 41 R133 12:11

ID11 ID_SELECT_RB13 42 R134 10:9

ID12 ID_SELECT_RC1 6 R135 8:7

ID13 ID_SELECT_RC2 7 R136 6:5

ID14 ID_SELECT_RC3 8 R137 4:3

ID15 ID_SELECT_RC4 9 R138 2:1

Signal Name

2.5 DIGIO & SPI+16GPIO SIGNALS ON P1 AND P2 HEADERS

2.5.1 DIGIO on P1 and P2 Headers (up to 16 bits supported)

PIC Pin

Number

10k to Pull

High

Pins to Short

for Pull Low

The LAN9252 supports a DIGIO mode, where these signals can be probed on the P1
and P2 headers. To enable DIGIO mode, from the default state of the board, the SW26
switch must be changed to the PIM position (upward). The respective DIGIO signal
mappings on the P1 and P2 headers are detailed in Table 2-22.

Note 1: In the default state, headers P1 and P2 are not assembled. These headers

can each be populated with a Molex 87758-4616.

2: The user must ensure that the EEPROM is configured in DIGIO mode.

TABLE 2-22: DIGIO MODE P1 & P2 HEADER SIGNALS

HBI Indexed HBI Multiplexed DIGIO P1/P2 Pin

RD/RD_WR RD/RD_WR DIGIO15 P1.8

WR/ENB WR/ENB DIGIO14 P1.10

CS CS DIGIO13 P1.26

A4 - DIGIO12 P1.41

A3 - DIGIO11 P1.44

A2 ALEHI DIGIO10 P2.21

A1 ALELO OE_EXT P1.7

A0/D15 AD15 DIGIO9 P1.15

D14 AD14 DIGIO8 P1.16

D13 AD13 DIGIO7 P1.11

D12 AD12 DIGIO6 P1.12

D11 AD11 DIGIO5 P1.17

D10 AD10 DIGIO4 P1.14

D9 AD9 LATCH_IN P1.13

D8 AD8 DIGIO2 P1.19

D7 AD7 DIGIO1 P1.4

D6 AD6 DIGIO0 P1.3

D5 AD5 OUTVALID P1.22

D4 AD4 DIGIO3 P1.23

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EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide

TABLE 2-22: DIGIO MODE P1 & P2 HEADER SIGNALS (CONTINUED)

HBI Indexed HBI Multiplexed DIGIO P1/P2 Pin

D3 AD3 WD_TRIG P1.6

D2 AD2 SOF P1.5

D1 AD1 EOF P1.24

D0 AD0 WD_STATE P1.25

2.5.2 SPI+GPIO on P1 and P2 Headers (up to 16 bits supported)

The LAN9252 supports an SPI+16GPIO mode, where these signals can be probed on
the P1 and P2 headers. To enable SPI+16GPIO mode, from the default state of the
board, the SW26 switch must be changed to the PIM position (upward) and SW19,
SW20, and SW21 must be changed to the downward side. The respective
SPI+16GPIO signal mappings on the P1 and P2 headers are detailed in Table 2-23.

Note 1: In the default state, headers P1 and P2 are not assembled. These headers

can each be populated with a Molex 87758-4616.

2: The user must ensure that the EEPROM is configured in DIGIO mode.

TABLE 2-23: SPI+16GPIO MODE P1 & P2 HEADER SIGNALS

HBI Indexed HBI Multiplexed SPI+16GPIO P1/P2 Pin

RD/RD_WR RD/RD_WR GPI15/GPO15 P1.8

WR/ENB WR/ENB GPI14/GPO14 P1.10

CS CS GPI13/GPO13 P1.26

A4 - GPI12/GPO12 P1.41

A3 - GPI11/GPO11 P1.44

A2 ALEHI GPI10/GPO10 P2.21

A0/D15 AD15 GPI9/GPO9 P1.15

D14 AD14 GPI8/GPO8 P1.16

D13 AD13 GPI7/GPO7 P1.11

D12 AD12 GPI6/GPO6 P1.12

D11 AD11 GPI5/GPO5 P1.17

D10 AD10 GPI4/GPO4 P1.14

D9 AD9 SCK P1.13

D8 AD8 GPI2/GPO2 P1.19

D7 AD7 GPI1/GPO1 P1.4

D6 AD6 GPI0/GPO0 P1.3

D5 AD5 SCS# P1.22

D4 AD4 GPI3/GPO3 P1.23

D3 AD3 SIO3 P1.6

D2 AD2 SIO2 P1.5

D1 AD1 SO/SIO1 P1.24

D0 AD0 SI/SIO0 P1.25

DS50002333C-page 26  2015-2016 Microchip Technology Inc.

2.6 ADDITIONAL FEATURES

The EVB-LAN9252-HBI+ includes additional features that were not available in the pre­vious revision of the board. This section details these additional features. To learn more
about how to use them refer to the Quick Start guide found at microchip.com.

2.6.1 Potentiometer

The EVB-LAN9252-HBI+ includes a potentiometer, as shown in Figure 2-8. The poten­tiometer is used as an input to the PIC32 and is labeled as “pot1” on the board.

FIGURE 2-8: POTENTIOMETER POT1

Board Details & Configuration

2.6.2 Temperature Sensor

The EVB-LAN9252-HBI+ includes a Microchip temperature sensor (TC104AVNBTR),
as shown in Figure 2-9. The temperature sensor is used as an input into the PIC32 and
is labeled “U9” on the board.

FIGURE 2-9: TEMPERATURE SENSOR U9

2.6.3 UART RS-232

A RS-232 connector is present on the board as J24. This allows serial communication
with the PIC32. With this connector UART communication is possible as both an input
and an output.

2.6.4 DAC

Through an on-board Microchip digital to analog converter (MCP4726) it is possible to
use the EtherCAT application to input a value to the DAC and get a calculated voltage
output on the DAC. It it labeled as U10 on the board and can be seen next to the poten­tiometer.

2.7 LIMITATIONS

The EVB-LAN9252-HBI+ has the following limitations:

1. While the LAN9252 supports both SFP and SFF Fiber Modes, the

EVB-LAN9252-HBI+ supports only the SFP Fiber Mode.

2. SQI is not supported when using the on-board PIC32MX.

 2015-2016 Microchip Technology Inc. DS50002333C-page 27

EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide

2.8 MECHANICALS

FIGURE 2-10: EVB-LAN9252-HBI+ MECHANICAL DIMENSIONS

DS50002333C-page 28  2015-2016 Microchip Technology Inc.

Chapter 3. Software Development Kit

This chapter explains the architecture of the LAN9252 EtherCAT® slave stack firmware
sample and introduces the SDK framework for use with PIC32MX microcontroller for
EVB-LAN9252-HBI+ development.

This chapter includes the following sub-sections:

• Prerequisites

• ESC SDK Sample Overview

• Using the Sample Project

• Programming the LAN9252 EEPROM

3.1 PREREQUISITES

3.1.1 Hardware Requirements

• EVB-LAN9252-HBI+-SPI-SQI-GPIO

• Windows Host Machine with minimum 2GB RAM

• Programmers – Aardvark I2C/SPI Host Adapter, Pickit3 Programmer

EVB-LAN9252-HBI+

ETHERCAT® EVALUATION BOARD

USER’S GUIDE

3.1.2 Software Requirements

• MPLAB IDE v2.20 or higher

• MPLAB XC Compiler v1.33 or higher

• Total Phase Flash Centre V1.31 or higher

3.2 ESC SDK SAMPLE OVERVIEW

The LAN9252 ESC supports interfacing to an external SoC using an SPI or HBI inter­face. This PIC32 based SDK sample contains separate projects for HBI and SPI inter­faces.

This software SDK is developed as a bare-metal firmware implementation (not specific
to any OS) designed to access the LAN9252 ESC features via an HBI or SPI interface.
The EtherCAT® slave stack portion of the source is obtained from EtherCAT Technol­ogy Group.

This software project has been tested with the EVB-LAN9252-HBI+ using the
PIC32MX SoC.

Figure 3-1 provides an architectural block diagram of the SDK’s various source mod­ules. The subsequent sections detail these blocks.

 2015-2016 Microchip Technology Inc. DS50002333C-page 29

EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide

FIGURE 3-1: PIC32 SOC FIRMWARE FRAMEWORK

3.2.1 User Module

3.2.1.1 SOC INITIALIZATION

This code block is part of the user application that boots the PIC microcontroller with
the desired RAM configuration, clock speed, clock source and other related features of
the controller, per the user’s configuration.

3.2.1.2 PERIPHERAL INITIALIZATION

This code block configures and initiates the core peripherals (UART, I
external peripherals (EEPROM, LAN9252).

3.2.1.3 MAIN APPLICATION

This code block contains the code that runs the LAN9252 EtherCAT® slave module
demo application.

2

C, SPI) and

3.2.2 EtherCAT® Slave Stack

This code block contains the EtherCAT slave stack.

3.2.3 Hardware Abstraction Layer (HAL)

This code block contains the low level layer that provides software hooks/APIs to the
application module and slave stack, allowing communication between these modules
and the hardware resources. For additional information, refer to the ReadMe.txt file
located in the project source folder.

DS50002333C-page 30  2015-2016 Microchip Technology Inc.

3.3 USING THE SAMPLE PROJECT

3.3.1 MPLAB IDE Project Settings & Firmware Download

1. OncetheEtherCATSSCisintegratedwithLAN9252SDKasdetailedin“Integrat‐

ingLAN9252‐PIC32MXSDKwithEtherCATSSCfromETG”applicationnote,
Copyittothedesireddirectory.(Forthepurposesofthisdocument,theDesk‐
topwillbethetargetfolder).

2. Open the MPLAB IDE and import the SSC project into the IDE.

FIGURE 3-2: MPLAB IDE OPEN PROJECT

Software Development Kit

FIGURE 3-3: MPLAB IDE PROJECT DIRECTORY

The target directory contains two project folders:

• PIC32-HBI Project Folder

• PIC32 Project Folder

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EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide

3.3.1.1 PIC32-HBI PROJECT FOLDER

The PIC32 project folder contains the sample code that enables the LAN9252's HBI
interface to communicate with the SoC. HBI demo code is provided for each of the
LAN9252’s six HBI configurations. These configurations can be selected respectively
from the configuration drop down box as shown in Figure 3-4.

TABLE 3-1: HBI CONFIGURATIONS

HBI Configuration (Project) Description

HBI_INDEXED_8BIT_XC32_PIC32MX79F512 8-bit Indexed mode

HBI_INDEXED_16BIT_XC32_PIC32MX79F512 16-bit Indexed mode

HBI_MDP_8BIT_XC32_PIC32MX79F512 8-bit Multiplexed dual phase mode

HBI_MDP_16BIT_XC32_PIC32MX79F512 16-bit Multiplexed dual phase mode

HBI_MSP_8BIT_XC32_PIC32MX79F512 8-bit Multiplexed single phase mode

HBI_MSP_16BIT_XC32_PIC32MX79F512 16-bit Multiplexed single phase mode

FIGURE 3-4: MPLAB IDE HBI CONFIGURATION SELECTION

3.3.1.2 PIC32 PROJECT FOLDER

The PIC32-SPI project folder contains the demo code that enables the LAN9252's SPI
interface to communicate with the SoC.

• Refer to the LAN9252 data sheet for more details on these HBI interface and its
modes.

• Refer to Section 2.4.4 “DIGIO/HBI/SPI+GPIO Selection” for SPI jumper configura­tions.

DS50002333C-page 32  2015-2016 Microchip Technology Inc.

Software Development Kit

3.3.2 Compiling and Programming SoC Firmware

1. Compile the source code (with corresponding configuration selected if HBI proj­ect is loaded).

FIGURE 3-5: MPLAB IDE COMPILE PROJECT SELECTION

2. If the compilation is successful, the output window will display “BUILD SUC­CESSFUL”, as shown in Figure 3-6.

FIGURE 3-6: MPLAB IDE BUILD SUCCESSFUL

3. Before initiating the firmware download, ensure the debugger/programmer is
connected to the EVB’s JTAG pins. (This demo project is debugged with the
PICkit-3 In-Circuit debugger/programmer).

4. To program the PIC32 SoC, click the “Make and Program Device Main Project”
button.

FIGURE 3-7: MPLAB IDE PROGRAM DEVICE

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EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide

5. To debug the PIC32 SoC, click “Debug Main Project” button.

FIGURE 3-8: MPLAB IDE DEBUG DEVICE

3.4 PROGRAMMING THE LAN9252 EEPROM

The LAN9252 configures itself to the desired mode (SPI, 6 HBI modes) by reading the
strap settings located in EEPROM. The LAN9252 EEPROM is programmed and vali­dated via the TwinCAT master tool. The EEPROM can also be programmed using an
external IIC Master, like AARDVARK.

3.4.1 Programming LAN9252 EEPROM using the TwinCAT Master Tool

The programming procedure using the TwinCAT master tool is as follows:

Note 1: This example utilizes the TwinCAT tool. Procedures may differ when using

other EtherCAT® master tools.

2: Ensure the system network properties are configured properly for the Eth-

erCAT® frames, Ethernet cable linking your system, and EtherCAT® slave
board.

1. Load the corresponding ESI file in the directory path "C:\TwinCAT\3.1\Con-

fig\Io\EtherCAT". For this demo, the ESI file for the 16-Bit Multiplexed Sin­gle-Phase Mode is used.

2. If TwinCAT installed successfully, a TwinCAT icon will be shown in the bot-

tom-right corner of the desktop. After clicking the icon, a pop-up list will display.
Select “TwinCAT XAE (VS 2013)”, as shown in Figure 3-9.

FIGURE 3-9: TWINCAT SYSTEM MANAGER

DS50002333C-page 34  2015-2016 Microchip Technology Inc.

Software Development Kit

3. Click on “New TwinCAT Project” as shown in Figure 3-10. Choose a name and
click “ok”.

FIGURE 3-10: TWINCAT DELETE DEVICE

4. Scan for EtherCAT® slave devices by expanding “I/O” and right clicking
“Devices” and then selecting “Scan”, as shown in Figure 3-11.

FIGURE 3-11: TWINCAT SCAN DEVICES

5. After scanning is complete, a window showing devices found will appear similar
to Figure 3-12.

 2015-2016 Microchip Technology Inc. DS50002333C-page 35

EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide

FIGURE 3-12: TWINCAT DEVICE LIST

6. Click “Yes” for Scan for Boxes and “Yes” for Activate Free Run.

7. After a successful scan, click the “Device 2 (EtherCAT)” drop down bar on the left
panel of the TwinCAT tool (as highlighted in Figure 3-11). Then click the “Online”
tab on the right-side panel of the TwinCAT tool, as shown in Figure 3-13. Right
click the LAN9252 listing and select “EEPROM Update” from the contextual
menu.

FIGURE 3-13: TWINCAT EEPROM UPDATE

8. Upon selecting “EEPROM Update”, the Write EEPROM window will open. Click
the “OK” button to initiate EEPROM programming (Figure 3-14).

FIGURE 3-14: TWINCAT WRITE EEPROM

DS50002333C-page 36  2015-2016 Microchip Technology Inc.

ETHERCAT® EVALUATION BOARD

Appendix A. Evaluation Board Photo

A.1 INTRODUCTION

This appendix shows the EVB-LAN9252-HBI+ Evaluation Board.

FIGURE A-1: EVB-LAN9252-HBI+ EVALUATION BOARD

EVB-LAN9252-HBI+

USER’S GUIDE

 2015-2016 Microchip Technology Inc. DS50002333C-page 37

EVB-LAN9252-HBI+

ETHERCAT® EVALUATION BOARD

Appendix B. Evaluation Board Schematics

B.1 INTRODUCTION

This appendix shows the EVB-LAN9252-HBI+ Evaluation Board Schematics.

USER’S GUIDE

 2015-2016 Microchip Technology Inc. DS50002333C-page 38

2015-2016 Microchip Technology Inc. DS50002333C-page 39

5 4 3 2

D

C

B

Reset Generator

POWER SUPPLY

(Rb)

(Ra)

OKR-T/3-W12-C

3 V REGULATOR, 3A
( 3V3 fixed when Rb=503e)

"3V3 Present"

Note:

1.POR -> Reset to ASIC & SOC (Def ault)

2.RESET O/P from ASIC -> R eset to EX-PHY (PORT2) & SOC :Only Ethercat sku

3.RESET from SOC (GPIO/RST-O/P) -> Reset to ASIC

4.RESET from Push Botton -> Res et to ASIC & SOC

"Reset"

RESET Options

5V_SW

EN12_1

5V_EXT

3V3

3V3

5V

3V3

3V3

3V3

3V3

RST#

TP1
RED

TP2
ORANGE

C3

0.1uF

C6

0.1uF

R8 1K

U1

3_Amp

GND

3

VIN

2

ENABLE1TRIM

5

VOUT

4

R7
100E

1/10W
1%

1 2

TP3

BLACK

R5

4.75K

1%

Q1

NDS355AN_NMOS

1

G

3

S

2

D

U2

TPS3125

SOT23_5
Threshold = 2.64V
Delay = 180ms

RESET#

1

GND

2

RESET

3

MR#4VDD

5

SW1

P/N:1101M2S3CQE2

Switch, SPDT, Sli de

2

3

1

C4

10uF

C2
10uF

25V

D1
GRN

1

A

2

C

R6
10K

1/10W
1%

12

C5

0.1uF

U3

74LVC1G14

2 4

53

1

SW2

sw_pb_2P

D2

Br_Red-RA

1

A2C

R4
470R

1%

TP4

BLACK

R3

3.30K

1%

C1

4.7uF

DNP

R1
0R

R9

2.2K

R4A
33R

1%

FB1

2A/0.05DCR

R2
1K

J1

1

2

3

FIGURE B-1: EVB-LAN9252-HBI+ SCHEMATIC POWER SUPPLY & RESET

Evaluation Board Schematics

DS50002333C-page 40  2015-2016 Microchip Technology Inc.

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Note:

OSCVSS need to connect to Chip gnd.

Power Supply Filtering

Low ESR

REG_EN

RBIAS

VDD12TX1

VDD12TX2

VDD12TX2

VDD12TX1

OSCO

OSCI

3V3

VDD33TXRX1

VDD33TXRX2

VDDCR

VDD33TXRX1

VDD33TXRX2

3V3

3V3

3V3 3V3

3V3

VDDCR

FXSDA/FXLOSA

IRQ

ATEST/FXLOSEN

RXPA

RXNA

TXNA
TXPA

TXNB
TXPB
RXNB
RXPB

FXSDB/FXLOSB

GPIO0
GPIO1
GPIO2

I2C2_SCL

I2C2_SDA

RST#

Size:

Part Number:

Rev

Date:

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of

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JUTLAND

LAN9252

EVB-LAN9252-HBI

Size:

Part Number:

Rev

Date:

Sheet

of

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LAN9252

EVB-LAN9252-HBI

Size:

Part Number:

Rev

Date:

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of

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LAN9252

EVB-LAN9252-HBI

C14

0.1uF

FB3 2A/0.05DCR

R10 12.1K

1%

C27 18pF

POWER

INT PORT0INT PORT1

OSC

I2C

OTHER

SIGNALS

GPIO

(Only for

Lan9252)

U4A

LAN9252

FXSDENA/FXSDA/FXLOSA

9

FXSDENB/FXSDB/FXLOSB

10

VDD33TXRX1

51

TXNA

52

TXPA

53

RXNA

54

RXPA

55

VDD12TX1

56

RBIAS

57

VDD33BIAS

58

VDD12TX2

59

RXPB

60

RXNB

61

TXPB

62

TXNB

63

VDD33TXRX2

64

OSCI

1

OSCO

2

OSCVDD12

3

OSCVSS

4

REG_EN

7

ATEST/FXLOSEN

8

RST#

11

IRQ

44

TESTMODE

41

I2CSCL/EESCL/TCK

43

I2CSDA/EESDA/TMS

42

LINKACTLED0/TDO/LEDPOL0/CHIP_MODE0

48

LINKACTLED1/TDI/LEDPOL1/CHIP_MODE1

46

RUNLED/LEDPOL2/E2PSIZE

45

VDD33

5

VDDIO114VDDIO220VDDIO332VDDIO437VDDIO5

47

VDDCR16VDDCR224VDDCR3

38

GND

65

C25

0.1uF

C17

0.1uF

C11

0.1uF

C210.1uF

FB2 2A/0.05DCR

C220.1uF

C15

0.1uF

FB5
2A/0.05DCR

C24

0.1uF

C23

1.0uF

DNP

C13

0.1uF

C8

0.1uF
C20470pF

C12

1.0uF DNP

C26 18pF

C16

0.1uF

C9

1.0uF

DNP

C10

0.1uF

C19

1uF

C7

1.0uF

DNP

Y1

25.000MHz

25ppm

1 2

FB4 2A/0.05DCR

BLM18EG221SN1D

C180.1uF

FIGURE B-2: EVB-LAN9252-HBI+ SCHEMATIC LAN9252

EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide

2015-2016 Microchip Technology Inc. DS50002333C-page 41

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Note:
Capacitors C10 through C13 are optional for EMI purposes

and are not populated on the LAN8740/41 evaluation board.

These capacitor s are required for op eration in an EMI
constrained environment.

LED1 (Green) = LINK/ACT

LED2 (Yellow) = SPEED

Note:
Capacitors C10 through C13 are optional for EMI purposes

and are not populated on the LAN8740/41 evaluation board.

These capacitor s are required for op eration in an EMI
constrained environment.

LED1 (Green) = LINK/ACT

LED2 (Yellow) = SPEED

COP-RXPA

COP-TXNA

COP-RXNA

COP-TXPA

COP-RXPB

COP-TXNB

COP-RXNB

COP-TXPB

VDD33TXRX2

VDD33TXRX1

FX_SFP-RXPA

FX_SFP-RXNA

TXPA

TXNA FX_SFP-TXNA

FX_SFP-TXPA

RXPA

RXNA

FX_SFP-RXPB

FX_SFP-RXNB

TXPB

TXNB FX_SFP-TXNB

FX_SFP-TXPB

RXPB

RXNB

Size:

Part Number:

Rev

Date:

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of

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Copper Mode Interface

EVB-LAN9252-HBI

Size:

Part Number:

Rev

Date:

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of

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Copper Mode Interface

EVB-LAN9252-HBI

Size:

Part Number:

Rev

Date:

Sheet

of

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JUTLAND

Copper Mode Interface

EVB-LAN9252-HBI

C34
10pF

50V
5%
DNP

XMIT

RCV

75

75 75

1000 pF

2 kV

RJ45

1

4 & 5

2

3

7 & 8

6

75

GRN

YEL

T1

Pulse J0011D01BNL

RD+

3

RXCT

5

RD-

6

TD+

1

TXCT

4

TD-

2

CHS GND

8

GND13GND114MTG15MTG1

16

NC

7

C

10

A

9

C1

11

A1

12

C28
10pF

50V
5%
DNP

C36
10pF

50V
5%
DNP

R34 0R

DNP

R15

0R

R13

49.9R

1/10W
1%

R38 0R

RES1210

R37 0R

R28

49.9R

1/10W
1%

R36 0R

DNP

R21 0R

R17 0R

R16 0R

DNP

C37

0.022uF

50V
10%

R33 0R

R32 0R

DNP

R18 0R

DNP

C31
10pF

50V
5%
DNP

R24 0R

RES1210

R31 0R

XMIT

RCV

75

75 75

1000 pF

2 kV

RJ45

1

4 & 5

2

3

7 & 8

6

75

GRN

YEL

T2

Pulse J0011D01BNL

RD+

3

RXCT

5

RD-

6

TD+

1

TXCT

4

TD-

2

CHS GND

8

GND13GND114MTG15MTG1

16

NC

7

C

10

A

9

C1

11

A1

12

C30
10pF

50V
5%
DNP

R14

49.9R

1/10W
1%

C35
10pF

50V
5%
DNP

R25

49.9R

1/10W
1%

R23 0R

C29
10pF

50V
5%
DNP

R20 0R

DNP

R22 0R

DNP

R12

49.9R

1/10W
1%

R35 0R

R26

49.9R

1/10W
1%

C33
10pF

50V
5%
DNP

R19 0R

C32

0.022uF

50V
10%

R29

0R

R11

49.9R

1/10W
1%

R27

49.9R

1/10W
1%

R30 0R

DNP

FIGURE B-3: EVB-LAN9252-HBI+ SCHEMATIC COPPER MODE INTERFACE

Evaluation Board Schematics

DS50002333C-page 42  2015-2016 Microchip Technology Inc.

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Fiber Port 0 :SFP Interface

Fiber Port 1 :SFP Interface

Note:Place
capacitors,

and resistors

close to FOT

Note:Place

resistors

close to

ASIC

Note:Place
capacitors,

and resistors

close to FOT

Note:Place

resistors

close to

ASIC

SFP_VCCT

SFP_VCCR

SFP_TD-

SFP_TD+

SFP_RD-

SFP_RD+

SFP_VCCT2

SFP_VCCR2

SFP_TD2-

SFP_TD2+

SFP_RD2-

SFP_RD2+

SFP_VCCT

SFP_VCCT2

3V3

3V3

3V3

3V3

FXSDA/FXLOSA

FXSDB/FXLOSB

FX_SFP-TXPA

FX_SFP-RXNA

FX_SFP-RXPA

FX_SFP-TXNA

FX_SFP-RXNB

FX_SFP-RXPB

FX_SFP-TXPB

FX_SFP-TXNB

Size:

Part Number:

Rev

Date:

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of

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SFP Interface

EVB-LAN9252-HBI

Size:

Part Number:

Rev

Date:

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of

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SFP Interface

EVB-LAN9252-HBI

Size:

Part Number:

Rev

Date:

Sheet

of

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SFP Interface

EVB-LAN9252-HBI

C53

0.1uF

C49

0.1uF

+

C48
10uF

16V

R40

82R

L2 1uH

C51

0.1uF

L1 1uH

C39 0.1uF

C42

0.1uF

C43 0.1uF

R51
130R

J3

FTLF1217P2

VeeT1TXFault2TX Disable3MOD-DEF(2)4MOD-DEF (1)5MOD-DEF (0)6Rate Select7LOS8VeeR9VeeR1

10

VeeR311VeeR2

14

RD-

12

RD+

13

VccR

15

VccT

16

VeeT2

17

TD+

18

TD-

19

VeeT1

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

31

R54

4.7K

R44
82R

R56

4.7K

R59

4.7K

R49
130R

R41

49.9R

R48

100E

R57

4.7K

J2

FTLF1217P2

VeeT1TXFault2TX Disable3MOD-DEF(2)4MOD-DEF (1)5MOD-DEF (0)6Rate Select7LOS8VeeR9VeeR1

10

VeeR311VeeR2

14

RD-

12

RD+

13

VccR

15

VccT

16

VeeT2

17

TD+

18

TD-

19

VeeT1

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

31

R45

49.9R

C47

0.1uF

R39
82R

R47

100E

+

C52
10uF

16V

C41 0.1uF

R60

4.7K

+

C50
10uF

16V
DNP

C55

0.1uF

+

C54
10uF

16V

R55

4.7K

C57

0.1uF

+

C56
10uF

16V

R43
82R

R53

4.7K

C45 0.1uF

R50

130R

+

C46
10uF

16V
DNP

R42

49.9R

R58

4.7K

C44

0.1uF

R52

130R

L4 1uH

L3 1uH

C38 0.1uF

R46

49.9R

C40 0.1uF

FIGURE B-4: EVB-LAN9252-HBI+ SCHEMATIC SFP INTERFACE

EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide

2015-2016 Microchip Technology Inc. DS50002333C-page 43

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

GPIO [0:2] & LED_POL_Strap

LINK/ACT

RUNLED

LINK/ACT

GPIO0 =LED0,LEDPOL0,MNGT0

GPIO1 = LED1,LEDPOL1,MNGT1

GPIO2 = LED2,LEDPOL2,E2PSIZE

Note:

--To use GPIOs as LED

* Short 2-3 of both jumpers (ex. for GPIO0 short 2-3 of J48 & J51)

1

The LED is set as active low,

MNGT0

The LED is set as active high.

MNGT1

0

Signal Name

Connector

J48,J51 (1&2)

LED Polarity Strap

Logic

E2ESIZE

J48,J51 (2&3)

J50,J53 (1&2)

J50,J53 (2&3)

1

0

J49,J52 (1&2)

J49,J52 (2&3)

The LED is set as active low,

The LED is set as active high.

The LED is set as active low,
EEPROM Size=32K bits (4K x 8) through 512K bits (64K x 8) or 4Mbits (512K x 8) (LAN9252 only)

The LED is set as active high.
EEPROM Size=1K bits (128 x 8) through 16K bits (2K x 8)

1

0

Management/LED Polarity Strap

I2C EEPROM

TH IC.

Different sizes can be mounted

I2C EEPROM Lower size
Below 16K(2K X 8)

I2C EEPROM Higher size

Above 16K(2K X 8)

'HIDXOW
&RSSRUPRGH

5 '135 $VVHPEOH
6HOHFWV);6'FRSSHUWZLVWHGSDLUIRUSRUWV$DQG%IXUWKHUGHWHUPLQHG

E\);6'(1$DQG);6'(1%

5 .5 .

/HYHORI9VHOHFWV);/26IRUSRUW$DQG

);6'&RSSHUWZLVWHGSDLUIRUSRUW%IXUWKHUGHWHUPLQHGE\);6'(1%

5 $VVHPEOH5 '13

$ERYH9VHOHFWV);/26IRUSRUWV$DQG%

FX_Los_Strap_1 & 2 FX_Mode_Strap_1 & 2

'HIDXOW
&RSSRUPRGH
55$VVHPEOH

55 '13

)LEHU0RGH

55'13
55 $VVHPEOH

LED1_CATHODE

GPIO1

GPIO1

LED1_ANODE

LED2_ANODE

LED0_CATHODE
LED2_CATHODE

GPIO0

GPIO0 GPIO2

GPIO2

LED0_ANODE

LED0_ANODE

LED0_CATHODE

LED1_ANODE

LED1_CATHODE

LED2_ANODE

LED2_CATHODE

I2C2_2

I2C2_3

I2C2_7

I2C2_1

3V33V3 3V3

3V3

3V3

3V3

3V3

3V3

3V3

GPIO0

GPIO1

GPIO2

I2C2_SDA

I2C2_SCL

ATEST/FXLOSEN

FXSDA/FXLOSA

FXSDB/FXLOSB

Size:

Part Number:

Rev

Date:

Sheet

of

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JUTLAND

STRAP,GPIO,I2C & FXLOS

EVB-LAN9252-HBI

Size:

Part Number:

Rev

Date:

Sheet

of

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Name:

Board

UNG_8043

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JUTLAND

STRAP,GPIO,I2C & FXLOS

EVB-LAN9252-HBI

Size:

Part Number:

Rev

Date:

Sheet

of

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JUTLAND

STRAP,GPIO,I2C & FXLOS

EVB-LAN9252-HBI

R72
1K

D4
GRN

1

A2C

J7

123

R73
1K

R71
10K

12

R78 10KDNP

R76 10K

R634.7K

R77
10K

DNP

R644.7K

J6

123

R664.7K

R67

2K

C58

0.1uF

J9

123

D3
GRN

1

A2C

R75 10KDNP

SW3

SW DIP-4/SM

1
2
3
4

8
7
6
5

U5

24FC04

GND

4

VCC

8

SDA

5

SCL

6

A0

1

A1

2

A2

3

WP

7

J4

123

R70
10K

12

R80 10K

J5

123

R74
1K

R69
10K

12

R654.7K

R68

2K

D5
GRN

1

A2C

R79
10K

J8

123

FIGURE B-5: EVB-LAN9252-HBI+ SCHEMATIC STRAP, GPIO, I2C & FXLOS

Evaluation Board Schematics

DS50002333C-page 44  2015-2016 Microchip Technology Inc.

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Board to Board Connectors for SoC

Short 1 -2 = To Reset ASIC from SoC-GPIO
Short 2-3 = To Reset SoC from ASIC

5V power to
HOST SOC board
from EVB Board

Host SOC EEPROM

I2C EEPROM

Only for Host SOC

HBI or SPI+GPIO Config selection
Short 1-2 & 4-5 for HBI Config (2-3 & 5-6 open)

Short 2-3 & 5-6 for SPI+GPIO Config (1-2 & 4-5 open)

SW22,SW23 & SW 24 = HBI or SPI selection

*(1-2)

*(1-2)

*(1-2)

*(2-3)

*(1-2)

*(2-3)

RD_RDWR
WR_ENB

CS

AD6

AD7

AD8

AD9_SCK

AD10

AD11

AD12

AD13

AD14

A0_AD15

AD5_SCS#

AD4
AD3_SIO3
AD2_SIO2
AD1_SIO1
AD0_SIO0

A3

A4

ALEHI_A2
ALELO_A1

AD7_CONFIG3
AD3_CONFIG3

GPMC_OEN_REN

GPMC_WEN
AD12_CONFIG3
AD10_CONFIG3
AD14_CONFIG3

AD5_CONFIG3
AD1_CONFIG3

CS_CONFIG3

FIFOSEL_LATCH0
A3_CONFIG3
A1_CONFIG3

AD6_CONFIG3
AD2_CONFIG3

GPMC_BE0N_CLE
AD13_CONFIG3
AD9_CONFIG3
AD15_CONFIG3
AD11_CONFIG3
AD8_CONFIG3

AD4_CONFIG3
AD0_CONFIG3

A4_CONFIG3
A2_CONFIG3
A0_CONFIG3

VDD3V3EXP

VDD_5V

SYS_RESETN

GPMC_DIR

SIO3_CONFIG5
SCS#_CONFIG5
SIO1_CONFIG5

VDD3V3EXP

SIO2_CONFIG5

RST_GPIO

ALEHI_CONFIG3

SIO0_CONFIG5
SCK_CONFIG5

AD5_SCS#

CS A4

A3

AD4 AD8

AD7 AD6

A0_AD15_CONFIG3

ALEHI_A2_CONFIG3

ALELO_A1

RD_RDWR_CONFIG3

GPMC_DIR

GPMC_OEN_REN

WR_ENB_CONFIG3

GPMC_WEN

GPMC_BE0N_CLE

PME_LATCH1

VDD_5V

I2C1_SCL

I2C1_SDA

I2C3_2

I2C3_3

I2C3_7

I2C3_1

AD2_SIO2

WR_ENB

ALEHI_A2_CONFIG3
ALEHI_A2

AD10

AD13 AD14

A0_AD15_CONFIG3

A0_AD15 RD_RDWR

AD12AD11

AD3_SIO3

AD9_SCK

AD0_SIO0 AD1_SIO1

ALELO_CONFIG3

5V

3V3

3V3

SCS#_CONFIG5

AD5_CONFIG3

CS_CONFIG3

GPIO13_CONFIG5 GPIO12_CONFIG5

A4_CONFIG3

A3_CONFIG3

GPIO11_CONFIG5

AD4_CONFIG3

GPIO3_CONFIG5 GPIO2_CONFIG5

AD8_CONFIG3

AD7_CONFIG3

GPIO1_CONFIG5 GPIO0_CONFIG5

AD6_CONFIG3

PME_LATCH1

FIFOSEL_LATCH0

A1_CONFIG3

ALELO_CONFIG3

ALEHI_CONFIG3

A2_CONFIG3

A0_CONFIG3

IRQ

RST#

RST_GPIO

SYS_RESETN

AD15_CONFIG3

AD2_CONFIG3

SIO2_CONFIG5

GPIO14_CONFIG5 GPIO10_CONFIG5

GPIO4_CONFIG5

AD10_CONFIG3

AD13_CONFIG3

GPIO7_CONFIG5 GPIO8_CONFIG5

AD14_CONFIG3

GPIO9_CONFIG5 GPIO 15_CONFIG5

GPIO6_CONFIG5

AD12_CONFIG3AD11_CONFIG3

GPIO5_CONFIG5

SIO3_CONFIG5

AD3_CONFIG3

AD9_CONFIG3

SCK_CONFIG5

AD0_CONFIG3

SIO0_CONFIG5 SIO1_CONFIG5

AD1_CONFIG3

I2C1_SDA I2C1_SCL

WR_ENB_CONFIG3

RD_RDWR_CONFIG3

Size:

Part Number:

Rev

Date:

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JUTLAND

LAN9252(Part2)

EVB-LAN9252-HBI

Size:

Part Number:

Rev

Date:

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LAN9252(Part2)

EVB-LAN9252-HBI

Size:

Part Number:

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Date:

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JUTLAND

LAN9252(Part2)

EVB-LAN9252-HBI

R854.7K DNP

SW8

JS102011CQN

1

2

3

SW12

1
2
3

4
5
6

R844.7K DNP

SW13

1
2
3

4
5
6

SW6

JS102011CQN

1

2

3

SW7

JS102011CQN

1

2

3

R862K DNP

U4B

LAN9252

SYNC/LATCH1

18

SYNC/LATCH0

34

A4/DIGIO12/GPI12/GPO12/MII_RXD0

27

A3/DIGIO11/GPI11/GPO11/MII_RXDV

26

A2/ALEHI/DIGIO10/GPI10/GPO10/LINKACTLED2/MII_LINKPOL/LEDPOL6

29

A1/ALELO/OE_EXT/MII_CLK25

25

A0/D15/AD15/DIGIO9/GPI9/GPO9/MII_RXER

33

D14/AD14/DIGIO8/GPI8/GPO8/MII_TXD3/TX_SHIFT1

15

D13/AD13/DIGIO7/GPI7/GPO7/MII_TXD2/TX_SHIFT0

16

D12/AD12/DIGIO6/GPI6/GPO6/MII_TXD1

21

D11/AD11/DIGIO5/GPI5/GPO5/MII_TXD0

22

D10/AD10/DIGIO4/GPI4/GPO4/MII_TXEN

23

D9/AD9/LATCH_IN/SCK

19

D8/AD8/DIGIO2/GPI2/GPO2/MII_MDIO

40

D7/AD7/DIGIO1/GPI1/GPO1/MII_MDC

39

D6/AD6/DIGIO0/GPI0/GPO0/MII_RXCLK

36

D5/AD5/OUTVALID/SCS#

50

D3/AD3/WD_TRIG/SIO3

35

D2/AD2/SOF/SIO2

12

D1/AD1/EOF/SO/SIO1

13

D0/AD0/WD_STATE/SI/SIO0

17

RD/RD_WR/DIGIO15/GPI15/GPO15/MII_RXD3

31

WR/ENB/DIGIO14/GPI14/GPO14/MII_RXD2

30

CS/DIGIO13/GPI13/GPO13/MII_RXD1

28

D4/AD4/DIGIO3/GPI3/GPO3/MII_LINK

49

R832K DNP

P2

HEADER 23x2

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45

2
4
6

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46

C59

0.1uF

DNP

P1

HEADER 23x2

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45

2

4

6

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46

SW10

JS102011CQN

1

2

3

SW21

1
2
3

4
5
6

SW18

1
2
3

4
5
6

SW19

1
2
3

4
5
6

J10

1 2

D6

DIODE

1 2

C60 0.1uF

DNP

R814.7K DNP

SW15

1
2
3

4
5
6

SW9

JS102011CQN

1

2

3

SW17

1
2
3

4
5
6

R824.7K DNP

TP5
ORANGE

SW5

JS102011CQN

1

2

3

SW20

1
2
3

4
5
6

SW11

1
2
3

4
5
6

SW4

SW DIP-4/SM

DNP

1
2
3
4

8
7
6
5

SW16

1
2
3

4
5
6

SW14

1
2
3

4
5
6

U6

24FC512

DNP

GND

4

VCC

8

SDA

5

SCL

6

A0

1

A1

2

A2

3

WP

7

FIGURE B-6: EVB-LAN9252-HBI+ SCHEMATIC BOARD TO BOARD INTERFACE

EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide

2015-2016 Microchip Technology Inc. DS50002333C-page 45

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DNP

Decap for U3

DNP

DNP

RESET

SW Position 1-2 & 4-5 = PIM ON
SW Position 2-3 & 5-6 = PIC ON

J73 - SPI AARDVAR HEADER

J73+J74 - SPI STROM HEADER

Aardvark / SPI Storm- Connector

*(2-3)

*(2-3)

Error LED

*(1-2)

*(1-2)

PIC32MX Unused GPIOs with GND probing option

PWM1 & PWM2 Signal for Motor Control

External
Power
Option

1-2* = External PWR
2-3 = 5V (Default)

J20 - Default OPEN; Used as probing header.

Short when EtherCAT ID need to be used.

Also respective 10K pullup resister

need to be assembled

SMA for SYNC0 & SYNC1

Assemble R143,R144 & R152
if EtherCAT ID select is required.
Temp.Sener, ADC & DAC functions
will not work when
EtherCAT ID select is used

MCLR

VDDCORE

PMRD

ID_SELECT_RB5

RG13

RG12

GPMC_A0_ALE

PMRD

PMWR

GPMC_A0_ALE

GPMC_A1_ALEHI

ID_SELECT_RC1
ID_SELECT_RC2
ID_SELECT_RC3
ID_SELECT_RC4

RG6

RA0

ID_SELECT_RB4
ID_SELECT_RB3

RA1

PIC_MCLR

MCLR

PIC_MCLR

GPMC_A1_ALEHI

SCS#_CONFIG5

SIO0_CONFIG5

SIO1_CONFIG5
SCK_CONFIG5

ID_SELECT_RB8

ID_SELECT_RB9

ID_SELECT_RB10

ID_SELECT_RB11

ID_SELECT_RB12

ID_SELECT_RB13

RD11

RG2
RG3

RA4

RA5

RD9
RD8

RA9

RA10

ID_SELECT_RB1
ID_SELECT_RB0

PGC2

PGD2

RA7

RA6

RG15

PWM2

PWM1

RD14

RD15

RF3

FIFOSEL_LATCH0 PME_L ATCH1

RG3
RA4
RD8
RA9
RA1
RG6
RG12
RA7

RD15
RG2 RD14

RA5
RD9
RF3
RA10
RA0
RG15
RG13
RA6

RD11

PMWR

PWM2

ID_SELECT_RB0
ID_SELECT_RB1
ID_SELECT_RB2

ID_SELECT_RB8

ID_SELECT_RB3
ID_SELECT_RB4
ID_SELECT_RB5

ID_SELECT_RB9
ID_SELECT_RB10

ID_SELECT_RC4

ID_SELECT_RC3

ID_SELECT_RC2

ID_SELECT_RB11

ID_SELECT_RC1

ID_SELECT_RB12
ID_SELECT_RB13

ID_SELECT_RB2

3V3

3V3

3V3

3V3

5V

3V3

SYS_RESETN

CS_CONFIG3

AD7_CONFIG3

AD6_CONFIG3

SIO0_CONFIG5

SIO1_CONFIG5

SCK_CONFIG5

SCS#_CONFIG5

AD5_CONFIG3

A3_CONFIG3

A4_CONFIG3

A2_CONFIG3

ALEHI_CONFIG3

A1_CONFIG3

A0_CONFIG3

ALELO_CONFIG3

I2C1_SDA
I2C1_SCL

IRQ

AD4_CONFIG3

AD3_CONFIG3

AD2_CONFIG3

RST_GPIO

AD1_CONFIG3

AD0_CONFIG3

AD8_CONFIG3

AD9_CONFIG3

AD10_CONFIG3

AD11_CONFIG3

AD15_CONFIG3

AD14_CONFIG3

AD13_CONFIG3

AD12_CONFIG3

I2C2_SCL

I2C2_SDA

FIFOSEL_LATCH0

PME_LATCH1

RxD

TxD

SoC_OSC2

SoC_OSC1

SoC_SOSCO

SoC_SOSCI

ADC1 IN
TEMP IN

PIM_MCLR

PGC2
PGD2

LED_OUT

Switch _IN

RD2

RD3

SIO2_CONFIG5
SIO3_CONFIG5

WR_ENB_CONFIG3

RD_RDWR_CONFIG3

DAC_OUT_ADC2

I2C_SDA_DAC_CTL
I2C_SCL_DAC_CTL

GPMC_A1_ALEHI

GPMC_A0_ALE

Size:

Part Number:

Rev

Date:

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Wednesday, February 17, 2016

JUTLAND

ON-Board-PIC32MX

EVB-LAN9252-HBI

Size:

Part Number:

Rev

Date:

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ON-Board-PIC32MX

EVB-LAN9252-HBI

Size:

Part Number:

Rev

Date:

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JUTLAND

ON-Board-PIC32MX

EVB-LAN9252-HBI

J21

DNP

SIG

1

GND1

2

GND2

3

GND3

4

GND4

5

R87 0R

Y2

32Khz

R13710K DNP

C64 11pF

R152 0RDNP

R12610K DNP

J13

DBG ICSP Header

1
2
3
4
5
6

C65 20pF

J15D

HEADER 10x4

4
8
12
16
20
24
28
32
36
40

C670.1uF

SW24

JS102011CQN

1

2

3

R12810K DNP

C750.1uF

J18

HEADER 3X2

2
4
6

1
3
5

J22

DNP

SIG

1

GND1

2

GND2

3

GND3

4

GND4

5

R13110K DNP

R12710K DNP

R13210K DNP

Y3
8 Mhz

J15A

HEADER 10x4

1
5
9
13
17
21
25
29
33
37

TP9

J15C

HEADER 10x4

3
7
11
15
19
23
27
31
35
39

C730.1uF

R88

4.7K

R12510K DNP

R139
0R

R12910K DNP

TP8

C710.1uF

R12410K DNP

R140 1K

C62 10uF

C690.1uF

R143 0RDNP

J12

341

2

R13610K DNP

C61 0.1uF

SW25

JS102011CQN

1

2

3

SW27

sw_pb_2P

C63 11pF

R1220R

R13010K DNP

R12310K DNP

J20

HEADER 16X2

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

C66 20pF

J19

1

2

3

R144 0RDNP

D23

GRN

1

A2C

R13810K DNP

R620R

J15B

HEADER 10x4

2
6
10
14
18
22
26
30
34
38

R61 0R

U7

PIC32MX775F256L

AERXERR

1

VDD

2

PMD5

3

PMD6

4

PMD7

5

RC1

6

RC2

7

RC3

8

RC4

9

PMA5

10

PMA4

11

AERXDV

12

MCLR

13

AERXCLK/AEREFCLK

14

VSS

15

VDD1

16

TMS/RA0

17

AERXD0

18

AERXD1

19

AN5/C1IN+/VBUSON/CN7/RB5

20

RB4

21

RB3

22

RB2

23

RB1

24

RB0

25

PGEC2/AN6/RB626PGED2/AN7/RB727AERXD228AERXD329AVDD30AVSS31RB832RB933RB1034AETXERR35VSS136VDD237TCK/RA138SCK439SS440AECRS41MII2_COL42PMA1/AETXD3/PMALH43PMALL/PMA0/AETXD244VSS245VDD346AETXD047AETXD148SDI449SDO4

50

USBID/RF3

51

SDA3/SDI3/U1RX/RF2

52

SCL3/SDO3/U1TX/RF8

53

VBUS

54

VUSB

55

D-/RG3

56

D+/RG2

57

SCL2

58

SDA2

59

TDI/RA4

60

TDO/RA5

61

VDD4

62

OSC1/CLKI/RC12

63

OSC2/CLKO/RC15

64

VSS3

65

AETXCLK

66

AETXEN

67

EMDIO

68

SS1/IC2/RD9

69

PMCS2

70

EMDC

71

INT0

72

SOSCI/CN1/RC13

73

SOSCO/T1CK/CN0/RC14

74

VSS4

75

OC2/RD176OC3/RD277OC4/RD3

78

PMD1279PMD13

80

PMWR

81

PMRD

82

PMD1483PMD15

84

VCAP/VDDCORE

85

VDD5

86

PMD1187PMD10

88

PMD989PMD8

90

RA691RA7

92

PMD093PMD1

94

TRD2/RG14

95

RG1296RG13

97

PMD298PMD399PMD4

100

TP11

WHITE

R13410K DNP

SW26

JS202011CQN

1
2
3

4
5
6

J16

1

2

3

C680.1uF

C740.1uF

R13310K DNP

R13510K DNP

C720.1uF

TP6
WHITE

J17

1

2

3

TP10

WHITE

TP7
WHITE

R89 1K

C700.1uF

J11

2
4
6
8
10

1
3
5
7
9

FIGURE B-7: EVB-LAN9252-HBI+ SCHEMATIC PIC32MX

Evaluation Board Schematics

DS50002333C-page 46  2015-2016 Microchip Technology Inc.

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Input = one (Default);

Input = Zero (change the Switch position)

Digital INPUTS

Digital OUTUTS

GPI0
GPI1
GPI2

GPI6

GPI3
GPI4
GPI5

GPI7

GPI8
GPI9
GPI10

GPI14

GPI12
GPI13

GPI15

GPO0

GPO1

GPO2

GPO3

GPO4

GPO5

GPO6

GPO7

GPO8

GPO9

GPO10

GPO11

GPO12

GPO13

GPO14

GPO15

GPI11

GPO0

GPI0

GPO1

GPI1

GPO2

GPI2

GPO3

GPI3

GPO4

GPI4

GPO5

GPI5

GPO6

GPI6

GPO7

GPI7

GPO8

GPI8

GPO9

GPI9

GPO10

GPI10

GPO11

GPI11

GPO12

GPI12

GPO13

GPI13

GPO14

GPI14

GPO15

GPI15

3V3

3V3

GPIO0_CONFIG5

GPIO7_CONFIG5

GPIO5_CONFIG5

GPIO4_CONFIG5

GPIO3_CONFIG5

GPIO2_CONFIG5

GPIO1_CONFIG5

GPIO6_CONFIG5

GPIO15_CONFIG5

GPIO14_CONFIG5

GPIO13_CONFIG5

GPIO12_CONFIG5

GPIO11_CONFIG5

GPIO10_CONFIG5

GPIO9_CONFIG5

GPIO8_CONFIG5

Size:

Part Number:

Rev

Date:

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GPIOs

EVB-LAN9252-HBI

Size:

Part Number:

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Date:

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GPIOs

EVB-LAN9252-HBI

Size:

Part Number:

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Date:

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GPIOs

EVB-LAN9252-HBI

R9810K

D11

A1C

2

D21

A1C

2

D14

A1C

2

R117 1K

SW32

JS102011CQN

1

2

3

SW39

JS102011CQN

1

2

3

SW30

JS102011CQN

1

2

3

D20

A1C

2

R115 1K

R9710K

R107 1K

R9310K

R106 1K

D10

A1C

2

R10410K

R9010K

SW37

JS102011CQN

1

2

3

R10110K

R10210K

R108 1K

R10510K

R112 1K

R9910K

D8

A1C

2

R110 1K

R9610K

SW45

JS102011CQN

1

2

3

SW28

JS102011CQN

1

2

3

R120 1K

SW31

JS102011CQN

1

2

3

D15

A1C

2

SW34

SW DIP-8

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10
9

R118 1K

SW40

SW DIP-8

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10
9

R9510K

R9410K

R10010K

R116 1K

D16

A1C

2

R9210K

R114 1K

SW43

JS102011CQN

1

2

3

D9

A1C

2

D13

A1C

2

SW35

JS102011CQN

1

2

3

R109 1K

SW33

JS102011CQN

1

2

3

R113 1K

R9110K

D19

A1C

2

SW29

JS102011CQN

1

2

3

SW42

JS102011CQN

1

2

3

D18

A1C

2

D7

A1C

2

R111 1K

R10310K

SW38

JS102011CQN

1

2

3

R121 1K

SW36

JS102011CQN

1

2

3

SW41

JS102011CQN

1

2

3

D22

A1C

2

SW44

JS102011CQN

1

2

3

D17

A1C

2

R119 1K

D12

A1C

2

FIGURE B-8: EVB-LAN9252-HBI+ SCHEMATIC GPIOS

EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide

DS50002333C-page 47  2015-2016 Microchip Technology Inc.

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Temp sensor

POT (Analog Input)

RS-232 I/F

6.7

PICkit™ SERIALANALYZER

DAC (Analog output)

SW for Output

LED for Input

Default Open

Default Open

J26 Pin 2 = External Vref

Short J26 1-2 for Vfer = 3V3

C87 & C88 = Default DNP

Assemble only when Vref is used

Default Short

Short only when DAC need to be connect to onboard MX.

TxD_232
RxD_232

TxD_232

RxD_232

TxD

RxD

DAC_OUT

DAC_OUT

VREF

3V3

3V3

3V3

3V3

3V3

3V3

3V3

3V3

RxD

TxD

Switch _INADC1 IN

TEMP IN

LED_OUT

DAC_OUT_ADC2

I2C_SDA_DAC_CTL
I2C_SCL_DAC_CTL

Size:

Part Number:

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Date:

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JUTLAND

UART, ADC & DAC

EVB-LAN9252-HBI

Size:

Part Number:

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Date:

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of

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JUTLAND

UART, ADC & DAC

EVB-LAN9252-HBI

Size:

Part Number:

Rev

Date:

Sheet

of

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India

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Name:

Board

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JUTLAND

UART, ADC & DAC

EVB-LAN9252-HBI

C880.1uF

DNP

C80

0.1uF

+

C82

10uF

16V

C790.1uF

R1451K

R141 470R 1%

J27

1 2

C76

0.1uF

C830.1uF

J14

HRD 6pin

1
2
3
4
5
6

POT1
3352T-1-103LF

1

CCW

2

WIPER

3

CW

J24

CONNECTOR DB9-M

5

9

4

8

3

7

2

6

1

10

11

C840.1uF

DNP

TIA/EIA-232

RS-232

U8 <Device>

C1+

1

C1-

3

C2+

4

C2-

5

VS+

2

VS-

6

DIN1

11

RIN1

13

DOUT1

14

ROUT1

12

GND

15

VCC

16

DIN210DOUT2

7

ROUT29RIN2

8

C81

0.1uF

+

C87

10uF

16V

DNP

U10

MCP4726

VOUT

1

VSS

2

VDD

3

VREFF

6

SCL

5

SDA

4

U9

TC1047A

sot23-3-center3

VSS

3

VOUT

2

VDD

1

D24

GRN

1

A2C

R154
10K

1/10W
1%

12

J25

1 2

J26

DNP

12

C78

0.1uF

C77

0.1uF

R142
100E

1/10W
1%

1 2

SW50

sw_pb_2P

R146
10K

1/10W
1%

12

R153

10K

1/10W

1%

12

FIGURE B-9: EVB-LAN9252-HBI+ SCHEMATIC UART, ADC, &DAC

EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide

DS50002333C-page 48  2015-2016 Microchip Technology Inc.

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

63,
64,

+%,

PIM unused GPIOs with GND porbing option

PIM TXD & RXD can't be used in HBI mode.
In other modes, TXD & RXD can be
extrnally connected to UART

RN1 RN2 RN3 RN4

HBI

SPI

SQI

YES DNP DNP DNP

DNP

DNP

YES YESDNP

DNP DNPYES

PIM

U6TX=RPD1

U6RX=RPF2

SQI_D1

IRQ_PIM24

IRQ_PIM32MZ

AN0_RB0

AN1_RB1

AN3_RB3

AN4_RB4

AN5_RB5

AN8_RB8

AN9_RB9

PIM_DIG_RC2

PIM_DIG_RC1

PIM_DIG_RC4

PIM_DIG_RC3

IRQ_PIM32MZ

IRQ_PIM24

SQI_SCK

SQI_CS

SQI_D0

AN2_RB11

PIM_DIG_RC1

PIM_DIG_RC3

AN5_RB5

AN3_RB3

AN0_RB0

AN9_RB9

VDDCORE_PIM

AN8_RB8

AN2_RB11

AN1_RB1

PIM_DIG_RC2

PIM_DIG_RC4

AN4_RB4

PIM_PIN11
PIM_PIN12

PIM_PIN14

PIM_PIN10

PIM_PIN10
PIM_PIN11
PIM_PIN12
PIM_PIN14

SQI_SCK
SQI_D1
SQI_D0
SQI_CS

PIM_SPI2_SCK SPI_SCK
PIM_SPI2_SDI SPI_SO
PIM_SPI2_SDO SPI_SI
PIM_SPI2_CS SPI_CS

PIM_RX
PIM_TX

PIM_RX
PIM_TX

3V3

SoC_OSC1

SoC_OSC2

SoC_SOSCI

SoC_SOSCO

AD7_CONFIG3

AD6_CONFIG3

AD5_CONFIG3

AD4_CONFIG3

AD3_CONFIG3

AD2_CONFIG3

AD1_CONFIG3

AD0_CONFIG3

FIFOSEL_LATCH0

PME_LATCH1

PIM_MCLR

PGC2

PGD2

IRQ

SIO2_CONFIG5

SIO3_CONFIG5

RST_GPIO

RD2

RD3

WR_ENB_CONFIG3

RD_RDWR_CONFIG3

CS_CONFIG3

GPMC_A1_ALEHI

GPMC_A0_ALE

A4_CONFIG3

A3_CONFIG3

A2_CONFIG3

SCK_CONFIG5

SCS#_CONFIG5

SIO1_CONFIG5
SIO0_CONFIG5

Size:

Part Number:

Rev

Date:

Sheet

of

Chennai
India

Project
Name:

Page:

Name:

Board

UNG_8043

D

B

12 12

Wednesday, February 17, 2016

JUTLAND

PIM

EVB-LAN9252-HBI

Size:

Part Number:

Rev

Date:

Sheet

of

Chennai
India

Project
Name:

Page:

Name:

Board

UNG_8043

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Wednesday, February 17, 2016

JUTLAND

PIM

EVB-LAN9252-HBI

Size:

Part Number:

Rev

Date:

Sheet

of

Chennai
India

Project
Name:

Page:

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Board

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Wednesday, February 17, 2016

JUTLAND

PIM

EVB-LAN9252-HBI

RN2 0E

1
2
3
4 5

6

7

8

PIM1

PIM CONN

DNP

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

26272829303132333435363738394041424344454647484950

9998979695949392919089888786858483828180797877

76

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52

100

51

RN3 0E

1
2
3
4 5

6

7

8

C8610uF

DNP

R1490R

DNP

2

1

3

RN1 0E

1

2

3

4 5

6
7
8

J23
HEADER 14X2

DNP

2
4
6

8
10
12
14
16
18
20
22
24
26
28

1
3
5
7
9
11
13
15
17
19
21
23
25
27

C850.1uF DNP

RN4 0E

1

2

3

4 5

6
7
8

FIGURE B-10: EVB-LAN9252-HBI+ SCHEMATIC PIM

EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide

EVB-LAN9252-HBI+

ETHERCAT® EVALUATION BOARD

USER’S GUIDE

Appendix C. Bill of Materials (BOM)

C.1 INTRODUCTION

This appendix includes the EVB-LAN9252-HBI+ Evaluation Board Bill of Materials (BOM).

 2015-2016 Microchip Technology Inc. DS50002333C-page 49

DS50002333C-page 50  2015-2016 Microchip Technology Inc.

Item Qty Reference Part PCBFootprint DNP Vender VenderP/N

2 2 C2,C4 10uF CAP0805 No Murata GRM21BR61E106KA73L

C3,C5,C6,C8,C10,C11,C13,C14,C15,C16,C17,C18,C21,

334

5 1 C19 1uF CAP0603 No Murata GRM188R61C105KA93D

6 1 C20 470pF CAP0603 No Murata GRM188R71H471KA01D

7 2 C26,C27 18pF CAP0603 No Murata GRM1885C1H180JA01D

9 2 C32,C37 0.022uF CAP0603 No Kemet C0603C223K5RACTU

12 1 C62 10uF CAP0603 No TDK C1608X5R0J106K080AB

13 2 C63,C64 11pF CAP0603 No Murata GRM1885C1H110JA01D

14 2 C65,C66 20pF CAP0603 No Murata GRM1885C1H200JA01D

15 1 C82 10uF CAP_B_3528 No AVX TPSB106K016R0500

17 22

18 1 D2 Br_Red‐RA LED0603 No Wurthelectronics 150060RS75000

19 1 D6 DIODE SOD123 No MicroCommercialCo 1N4148W‐TP

20 5 FB1,FB2,FB3,FB4,FB5 2A/0.05DCR RES0603 No Murata BLM18EG221SN1D

21 1 J1 SKT_PWR_2R0mm_4A_THRU_RA th_conn_pwrjack_dc‐210_rt No CuiStack PJ‐002AH

23 9 J4,J5,J6,J7,J8,J9,J16,J17,J19 HDR_1x3 TH_CONN_1X3P No FCI 68000‐103HLF

24 3 J10,J25,J27 CONN_2P th_conn_1x2p No FCI 68000‐102HLF

25 1 J11 HEADER5X2 TH_CONN_2X5P No FCI 67997‐210HLF

26 1 J12 HEADER2X2 TH_CONN_2X2P No FCI 67997‐202HLF

27 1 J13 DBGICSPHeader TH_CONN_1x6P No FCI 68000‐106HLF

28 1 J14 HRD6pin TH_CONN_1x6P No FCI 68000‐106HLF

30 1 J18 HEADER3X2 TH_CONN_2X3P No FCI 67997‐206HLF

31 1 J20 HEADER16X2 TH_CONN_2X16P No FCI 67997‐232HLF

32 2 J21,J22 CONN_5P TH_CONN_SMA‐J‐

34 1 J24 CONNECTORDB9‐M th_conn_db9_m_rt No TE/AMP 5747840‐4

38 1 POT1 3352T‐1‐103LF TH_POT_3352T No BournsInc. 3352T‐1‐103LF

40 1 Q1 NDS355AN_NMOS sot23‐NDS No Fairchild NDS355AN

C22,C24,C25,C58,C61,C67,C68,C69,C70,C71,C72,C73,

C74,C75,C76,C77,C78,C79,C80,C81,C83

D1,D3,D4,D5,D7,D8,D9,D10,D11,D12,D13,D14,D15,

D16,D17,D18,D19,D20,D21,D22,D23,D24

0.1uF CAP0603 No Murata GRM188R71E104KA01D

GRN LED0603 No Wurthelectronics 150060GS75000

P‐H‐ST‐TH1 No TE 5‐1814832‐1

EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide

2015-2016 Microchip Technology Inc. DS50002333C-page 51

41 7 R1,R15,R29,R61,R62,R87,R122 0R RES0603 No Panasonic ERJ‐3GEY0R00V

R2,R8,R72,R73,R74,R89,R106,R107,R108,R109,R110,

42 24

43 1 R3 3.30K RES0603 No YageoAmerica 9C06031A3301FKHFT

44 2 R4,R141 470R RES0603 No BOURNS CR0603‐FX‐4700ELF

45 1 R4A 33R RES0603 No BOURNS CR0603‐FX‐33R0ELF

46 1 R5 4.75K RES0603 No Panasonic ERJ‐3EKF4751V

47 26

48 2 R7,R142 100E RES0603 No Panasonic ERJ‐3EKF1000V

49 1 R9 2.2K RES0603 No Panasonic ERJ‐3GEYJ222V

50 1 R10 12.1K RES0603 No Rohm CR03ERTF1212

51 8 R11,R12,R13,R14,R25,R26,R27,R28 49.9R RES0603 No YageoAmerica 9C06031A49R9FKHFT

53 8 R17,R19,R21,R23,R31,R33,R35,R37 0R RES0402 No Panasonic ERJ‐2GE0R00X

54 2 R24,R38 0R RES1210 Vishay CRCW12100000Z0EA

60 5 R63,R64,R65,R66,R88 4.7K RES0603 No Panasonic ERJ‐3EKF4701V

61 2 R67,R68 2K RES0603 No Panasonic ERJ‐3GEYJ202V

68 1 SW1 SW‐SPDT‐SLIDE sw_ck_1101m2s3cqe2 No C&K 1101M2S3CQE2

69 3 SW2,SW27,SW50 sw_pb_2P sw_pb_2P No Panasonic EVQ‐PJU04KorEVQ‐5PN04K

70 1 SW3 SWDIP‐4/SM TH_SW_DIP4 No Wurthelectronics 418117270904

72 8 SW5,SW6,SW7,SW8,SW9,SW10,SW24,SW25 JS102011CQN TH_SW_SPST_3P_10x2p5 No

72A 16

73 12

74 2 SW34,SW40 SWDIP

75 1 TP1 RED TH_TP_60D40 No Keystone 5000

76 1 TP2 ORANGE TH_TP_60D40 No Keystone 5003

77 3 TP3,TP4,TP9 BLACK TH_TP_60D40 No Keystone 5001

80 2 T1,T2 Pulse‐J0011D01BNL th_conn_pulse_rj45_j0026 No PulseElectronics J0011D01BNL

R111,R112,R113,R114,R115,R116,R117,R118,R119,

R120,R121,R140,R145

R6,R69,R70,R71,R146,R153,R154,R76,R79,R80,R90,
R91,R92,R93,R94,R95,R96,R97,R98,R99,R100,R101,

R102,R103,R104,R105

SW5,SW6,SW7,SW8,SW9,SW10,SW24,SW25,SW28,
SW29,SW30,SW31,SW32,SW33,SW35,SW36,SW37,

SW38,SW39,SW41,SW42,SW43,SW44,SW45

SW11,SW12,SW13,SW14,SW15,SW16,SW17,SW18,

SW19,SW20,SW21,SW26

1K RES0603 No Panasonic ERJ‐3GEYJ102V

10.0K RES0603 No Panasonic ERJ‐3EKF1002V

Wurthelectronics 450301014042

HDR_1x3 TH_SW_SPST_3P_10x2p5 No FCI 68000‐103HLF

JS202011CQN TH_SW_DPDT_6P No C&K JS202011CQN

‐8SW_DIP_SMT_8P‐ADE08S04 No TE 1‐1825058‐9

Bill of Materials (BOM)

DS50002333C-page 52  2015-2016 Microchip Technology Inc.

81 1 U1 3_Amp TH_DC‐DC_VERT_5PIN_P67 No Murata OKR‐T/3‐W12‐C

82 1 U2 TPS3125 SOT23_5 No TI TPS3125L30DBVR

83 1 U3 74LVC1G14 SOT23_5 No TI SN74LVC1G14DBVR

84 1 U4 LAN9252 IC_QFN64 No Microchip LAN9252

85 1 U5 24FC512 IC_DIP8_300 No Microchip 24FC512‐I/P

87 1 U7 PIC32MX775F256L IC_TQFP100_12x12x1‐0p4mm No Microchip PIC32MX795F512L‐80I/PT

88 1 U8 TRS3232_SO16 IC_SO16 No TI TRS3232IDR

89 1 U9 TC1047A sot23‐3 No Microchip TC1047AVNBTR

90 1 U10 MCP4726 SOT23_6 No Microchip MCP4726A0T‐E/CH

91 1 Y1 25.000MHz XTAL_HCM49 No

92 1 Y2 32Khz th_xtal_ecs‐31x‐13‐32khz No ECSINC ECS‐.320‐12.5‐13X

93 1 Y3 8Mhz th_hc49us_2p No CitizenFinetech HC‐49/U‐S8000000ABJB

DNPComponents

1 1 C1 4.7uF CAP0603 DNP

4 4 C7,C9,C12,C23 1.0uF CAP0603 DNP

8 8 C28,C29,C30,C31,C33,C34,C35,C36 10pF CAP0402 DNP

10 19

11 7 C46,C48,C50,C52,C54,C56,C87 10uF CAP_B_3528 DNP

16 1 C86 10uF CAP0603 DNP

22 2 J2,J3 FTLF1217P2 CONN_FX_SFP_FTLF1217P2 DNP

29 1 J15 HEADER10x4 TH_CONN_4X10P DNP

33 1 J23 HEADER14X2 TH_CONN_2x14P DNP

35 1 J26 CONN_2P th_conn_1x2p DNP

36 4 L1,L2,L3,L4 1uH L0805 DNP

37 1 PIM1 PIMCONN TH_CONN_PIM100 DNP

39 2 P1,P2 HEADER23x2 TH_CONN_2X23P DNP

52 8 R16,R18,R20,R22,R30,R32,R34,R36 0R RES0402 DNP

55 4 R39,R40,R43,R44 82R RES0603 DNP

56 4 R41,R42,R45,R46 49.9R RES0603 DNP

57 2 R47,R48 100E RES0603 DNP

C38,C39,C40,C41,C42,C43,C44,C45,C47,C49,C51,

C53,C55,C57,C59,C60,C84,C85,C88

0.1uF CAP0603 DNP

CardinalComponentsInc. CSM1Z‐A5B2C5‐40‐25.0D18‐F

EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide

2015-2016 Microchip Technology Inc. DS50002333C-page 53

58 4 R49,R50,R51,R52 130R RES0603 DNP

59 12 R53,R54,R55,R56,R57,R58,R59,R60,R81,R82,R84,R85 4.7K RES0603 DNP

62 19

64 2 R83,R86 2K RES0603 DNP

65 4 R139,R143,R144,R152 0R RES0603 DNP

67 1 R149 0R RES0603‐3DNP

71 1 SW4 SWDIP‐4/SM TH_SW_DIP4 DNP

78 1 TP5 ORANGE TH_TP_60D40 DNP

79 5 TP6,TP7,TP8,TP10,TP11 WHITE TH_TP_60D40 DNP

86 1 U6 24FC512 IC_DIP8_300 DNP

R75,R77,R78,R123,R124,R125,R126,R127,R128,R129,R130,

R131,R132,R133,R134,R135,R136,R137,R138

10K RES0603 DNP

Bill of Materials (BOM)

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07/14/15

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