Note the following details of the code protection feature on Microchip devices:
YSTEM
CERTIFIEDBYDNV
== ISO/TS16949==
•Microchip products meet the specification contained in their particular Microchip Data Sheet.
•Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•Microchip is willing to work with the customer who is concerned about the integrity of their code.
•Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold
harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or
otherwise, under any Microchip intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer,
LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST
Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch,
Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial
Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless
DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their respective companies.
DS50002333C-page 2 2015-2016 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
Worldwide Sales and Service .....................................................................................54
DS50002333C-page 6 2015-2016 Microchip Technology Inc.
EVB-LAN9252-HBI+
ETHERCAT® EVALUATION BOARD
USER’S GUIDE
Preface
NOTICE TO CUSTOMERS
All documentation becomes dated, and this manual is no exception. Microchip tools and
documentation are constantly evolving to meet customer needs, so some actual dialogs
and/or tool descriptions may differ from those in this document. Please refer to our web site
(www.microchip.com) to obtain the latest documentation available.
Documents are identified with a “DS” number. This number is located on the bottom of each
page, in front of the page number. The numbering convention for the DS number is
“DSXXXXXA”, where “XXXXX” is the document number and “A” is the revision level of the
document.
For the most up-to-date information on development tools, see the MPLAB
Select the Help menu, and then Topics to open a list of available online help files.
®
IDE online help.
INTRODUCTION
This chapter contains general information that will be useful to know before using the
EVB-LAN9252-HBI+. Items discussed in this chapter include:
• Document Layout
• Conventions Used in this Guide
• The Microchip Web Site
• Development Systems Customer Change Notification Service
• Customer Support
• Document Revision History
DOCUMENT LAYOUT
This document describes how to use the EVB-LAN9252-HBI+ as a development tool
for the Microchip LAN9252 EtherCAT® slave controller. The manual layout is as
follows:
• Chapter 1. “Overview” – Shows a brief description of the EVB-LAN9252-HBI+.
• Chapter 2. “Board Details & Configuration” – Includes details and instructions
for using the EVB-LAN9252-HBI+.
• Chapter 3. “Software Development Kit” – Includes details and instructions for
using the LAN9252 EtherCAT® slave stack firmware and SDK framework.
• Appendix A. “Evaluation Board Photo” – This appendix shows the
EVB-LAN9252-HBI+.
• Appendix B. “Evaluation Board Schematics” – This appendix shows the
EVB-LAN9252-HBI+ schematics.
• Appendix C. “Bill of Materials (BOM)” – This appendix includes the
Choice of mutually exclusive
arguments; an OR selection
Represents code supplied by
user
“Save project before build”
4‘b0010, 2‘hF1
any valid filename
[options]
errorlevel {0|1}
var_name...]
void main (void)
{ ...
}
DS50002333C-page 8 2015-2016 Microchip Technology Inc.
Preface
THE MICROCHIP WEB SITE
Microchip provides online support via our web site at www.microchip.com. This web
site is used as a means to make files and information easily available to customers.
Accessible by using your favorite Internet browser, the web site contains the following
information:
• Product Support – Data sheets and errata, application notes and sample
programs, design resources, user’s guides and hardware support documents,
latest software releases and archived software
• General Technical Support – Frequently Asked Questions (FAQs), technical
support requests, online discussion groups, Microchip consultant program
member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip
press releases, listing of seminars and events, listings of Microchip sales offices,
distributors and factory representatives
DEVELOPMENT SYSTEMS CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip’s customer notification service helps keep customers current on Microchip
products. Subscribers will receive e-mail notification whenever there are changes,
updates, revisions or errata related to a specified product family or development tool of
interest.
To register, access the Microchip web site at www.microchip.com, click on Customer
Change Notification and follow the registration instructions.
The Development Systems product group categories are:
• Compilers – The latest information on Microchip C compilers, assemblers, linkers
and other language tools. These include all MPLAB C compilers; all MPLAB
assemblers (including MPASM assembler); all MPLAB linkers (including MPLINK
object linker); and all MPLAB librarians (including MPLIB object librarian).
• Emulators – The latest information on Microchip in-circuit emulators.This
includes the MPLAB REAL ICE and MPLAB ICE 2000 in-circuit emulators.
• In-Circuit Debuggers – The latest information on the Microchip in-circuit
debuggers. This includes MPLAB ICD 3 in-circuit debuggers and PICkit 3 debug
express.
• MPLAB IDE – The latest information on Microchip MPLAB IDE, the Windows
Integrated Development Environment for development systems tools. This list is
focused on the MPLAB IDE, MPLAB IDE Project Manager, MPLAB Editor and
MPLAB SIM simulator, as well as general editing and debugging features.
• Programmers – The latest information on Microchip programmers. These include
production programmers such as MPLAB REAL ICE in-circuit emulator, MPLAB
ICD 3 in-circuit debugger and MPLAB PM3 device programmers. Also included
are nonproduction development programmers such as PICSTART Plus and
PIC-kit 2 and 3.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
Customers should contact their distributor, representative or field application engineer
(FAE) for support. Local sales offices are also available to help customers. A listing of
sales offices and locations is included in the back of this document.
Technical support is available through the web site at:
http://www.microchip.com/support
DOCUMENT REVISION HISTORY
RevisionSection/Figure/EntryCorrection
DS50002333C (06-17-16)
All
Figure 1-1
Chapter 2. “Board
Details & Configuration”
2.1.1 “+5V Power”
2.6 “Additional Features”
Chapter 3. “Software
Development Kit”
Appendix A. “Evaluation
Board Photo”
Appendix B. “Evaluation
Board Schematics”
Appendix C. “Bill of
Materials (BOM)”
DS50002333B (05-12-15)
All
Section 1.2 “References”
Section 2.4.4 “DIGIO/HBI/
SPI+GPIO Selection”
Table 2-13, Table 2-14,
and Table 2-15
DS50002333A (02-27-15)Initial Release of Document
Updated board name to “EVB-LAN9252-HBI+”
throughout document.
Updated figure to include UART, Temp. Sensor,
DAC, and ADC.
Updated Figures 1, 5, 6, 7, and 10. Added new Figure 2.
Updated Tables 13, 14, 15, 21.
Removed power supply manufacturer and part number.
Added new section with new features.
Updated figures throughout chapter.
Updated appendix with new photos.
Updated appendix with new schematics.
Updated appendix with updated BOM.
Updated board name to “EVB-LAN9252-HBI”
throughout document, corrected misc. typos and
grammatical errors.
Updated list of application notes.
Added additional information on DIGIO mode.
Simplified table and added note under each table for
clarity.
DS50002333C-page 10 2015-2016 Microchip Technology Inc.
1.1INTRODUCTION
The LAN9252 is a 2-port EtherCAT® Slave Controller (ESC) with dual integrated Ethernet PHYs which each contain a full-duplex 100BASE-TX transceiver and support
100Mbps (100BASE-TX) operation. 100BASE-FX is supported via an external fiber
transceiver.
Each port receives an EtherCAT® frame, performs frame checking and forwards it to
the next port. Time stamps of received frames are generated when they are received.
The Loop-back function of each port forwards the frames to the next logical port if there
is either no link at a port, if the port is not available, or if the loop is closed for that port.
The Loop-back function of port 0 forwards the frames to the EtherCAT® Processing
Unit. The loop settings can be controlled by the EtherCAT® master.
Packets are forwarded in the following order:
Port 0 -> EtherCAT® Processing Unit -> Port 1 -> Port 2.
The EtherCAT® Processing Unit (EPU) receives, analyzes and processes the EtherCAT® data stream. The main purpose of the EtherCAT® Processing unit is to enable
and coordinate access to the internal registers and the memory space of the ESC,
which can be addressed both from the EtherCAT® master and from the local application. Data exchange between master and slave applications is comparable to a
dual-ported memory (process memory), enhanced by special functions for consistency
checking (SyncManager) and data mapping (FMMU). Each FMMU performs bitwise
mapping of logical EtherCAT® system addresses to physical device addresses.
The scope of this document is to describe the EVB-LAN9252-HBI+ setup, which supports a HBI/SPI+GPIO Interface and corresponding jumper configurations. The
LAN9252 is connected to an RJ45 Ethernet jack with integrated magnetics for
100BASE-TX connectivity. A simplified block diagram of the EVB-LAN9252-HBI+ is
shown in Figure 1-1.
DS50002333C-page 12 2015-2016 Microchip Technology Inc.
1.2REFERENCES
Concepts and material available in the following documents may be helpful when reading this document. Visit www.microchip.com for the latest documentation.
• LAN9252 Data Sheet
• AN 8.13 Suggested Magnetics
• EVB-LAN9252-HBI+ Schematics
• The following application notes:
- AN1916 Integrating Microchip’s LAN9252 SDK with Beckhoff’s EtherCAT®
SSC
- AN1920 Microchip LAN9252 EEPROM Configuration and Programming
- AN1907 Microchip LAN9252 Migration from Beckhoff ET1100
This chapter includes sub-sections on the following EVB-LAN9252-HBI+ details:
•Power
• Resets
• Clock
• Configuration
• Additional Features
• Limitations
• Mechanicals
2.1.1+5V Power
Power is supplied to the LAN9252 by a +3.3V on-board regulator, which is powered by
a +5V external wall adapter. The LAN9252 includes an internal +1.2V regulator which
supplies power to the internal core logic. Assertion of the D1 Green LED indicates successful generation of +3.3V o/p. The SW1 switch must be in the ON position for the +5V
to power the +3.3V regulator.
2.2RESETS
2.2.1Power-on Reset
A power-on reset occurs whenever power is initially applied to the LAN9252 or if the
power is removed and reapplied to the LAN9252. This event resets all circuitry within
the LAN9252. After initial power-on, the LAN9252 can be reset by pressing the reset
switch SW2. The reset LED D2 will assert (red) when the LAN9252 is in reset condition.
For stability, a delay of approximately 180ms is added from the +3.3V o/p to reset
release.
2.2.2Reset Out
The LAN9252 reset pin can be configured as an output to reset the SoC. The RST# pin
becomes an open-drain output and is asserted for the minimum required time of 80ms.
2.2.3GPIO Reset
The EVB-LAN9252-HBI+ provides the option to reset the LAN9252 through a PIC
GPIO pin [95(RG14)]. The SW10 switch is used for this selection, as shown in
Ta bl e 2 -1 .
The EVB-LAN9252-HBI+ utilizes an external 25MHz 25ppm crystal from Cardinal
Components Inc. (P/N: CSM1Z-A5B2C5-40-25.0D18-F).
2.4CONFIGURATION
The following sub-sections describe the various board features and configuration settings. A top view of the EVB-LAN9252-HBI+ is shown in Figure 2-1. Figure 2-2 details
new features.
FIGURE 2-1:EVB-LAN9252-HBI+ TOP VIEW WITH CALLOUTS
FIGURE 2-2:EVB-LAN9252-HBI+ TOP VIEW NEW FEATURE CALLOUTS
2.4.1Strap Options
2.4.1.1CHIP MODE SELECTION
Table 2-2 details the LAN9252 chip mode configuration straps.
TABLE 2-2:CHIP MODE CONFIGURATION STRAP
HeaderDescriptionPinsSettings
J4,J6,J7,J9 Chip mode configuration strap
inputs. This strap determines
the number of active ports and
port types.
1-2
Short 1-2 for high (pull-up)
(Not supported in this EVB)
2-3
Short 2-3 for low (pull-down) (default)
Note:This EVB supports Chip mode 00 which is 2-port mode, where Port 0 = PHY
A and Port 1 = PHY B. This requires J4, J6, J7, and J9 to be pulled-down
(2-3) shorted. All other configurations are not supported with this EVB.
2.4.1.2EEPROM SIZE CONFIGURATION
The EEPROM size configuration strap (J5 & J8) determines the supported EEPROM
size range. A low selects 1Kbits (128 x 8) through 16Kbits (2K x 8)_24C16. A high
selects 32Kbits (4K x 8) through 512Kbits (64K x 8) or 4Mbits (512K x 8)_24C512.
TABLE 2-3:EEPROM SIZE CONFIGURATION STRAP
HeaderDescriptionPinsSettings
J5, J8EEPROM size configuration
strap inputs. This strap determines the supported
EEPROM size range.
1-2
Short 1-2 for high (pull-up) (default)
2-3
Short 2-3 for low (pull-down)
2.4.1.3COPPER AND FIBER STRAPS
The LAN9252 supports 100BASE-TX (Copper) and 100BASE-FX (Fiber) modes. In
100BASE-FX operation, the presence of the receive signal is indicated by the external
transceiver as either an open-drain, CMOS level, Loss of Signal (SFP) or a LVPECL
Signal Detect (SFF).
DS50002333C-page 16 2015-2016 Microchip Technology Inc.
Board Details & Configuration
This EVB supports 100BASE-TX (Copper) and SFP 100BASE-FX (Fiber) modes. By
default Copper Mode is active. Fiber Mode is supported as an assembly option. To
select the Copper or Fiber Mode, the respective strap and signal routing resister
assembly options must to be configured.
Note:Vendor part number for SFP: Finisar/FTLF1217P2
2.4.1.3.1Copper Mode
The EVB-LAN9252-HBI+ is set to Copper Mode by default. Table 2-4 details the
required strap resistor settings for Copper Mode operation.
TABLE 2-4:COPPER MODE STRAP RESISTORS
ResistorsDescription
R79 (10K)Configures Port 0 & 1 to Copper Mode
R76, R80 (10K)Configures Port 0 and Port 1 to Copper Mode, respectively
Note:R75, R77, and R78 must not be populated (DNP).
Additionally, the signal routing resistors detailed in Table 2-5 must be assembled for
Copper Mode operation.
TABLE 2-5:COPPER MODE SIGNAL ROUTING RESISTORS
ResistorsDescription
R17, R19, R21, R23Port 0 Copper Mode enabled
R31, R33, R35, R37Port 1 Copper mode enabled
Note:R16, R18, R20, R22, R30, R32, R34, and R36 (0402 package) must not be
populated (DNP).
2.4.1.3.2Fiber Mode
The EVB-LAN9252-HBI+ support SFP type 100BASE-FX. To enable Fiber Mode, the
respective strap and signal routing resistors must be configured.
Note:Copper Mode related resistors must be DNP while Fiber Mode is active
(See Section 2.4.1.3.1 “Copper Mode”).
Table 2-6 details the required strap resistor settings for Fiber Mode operation.
TABLE 2-6:FIBER MODE STRAP RESISTORS
ResistorsDescription
R77 (10K)Configures Port 0 & 1 to FX-LOS Mode
R75, R78 (10K)Configures Port 0 and Port 1 to Fiber Mode, respectively
Note:R76, R79, and R80 must not be populated (DNP).
Additionally, the signal routing resistors detailed in Table 2-7 must be assembled for
Fiber Mode operation.