Microchip Technology dsPIC33F Family Reference Manual

ADC

Section 16. Analog-to-Digital Converter (ADC)

HIGHLIGHTS

This section of the manual contains the following major topics:

16.1 Introduction..................................................................................................................16-2

16.2 Control Registers.........................................................................................................16-4

16.3 A/D Terminology and Conversion Sequence.............................................................16-14

16.4 ADC Module Configuration........................................................................................16-16

16.5 Selecting the Voltage Reference Source...................................................................16-16

16.6 Selecting the A/D Conversion Clock..........................................................................16-17

16.7 Selecting Analog Inputs for Sampling........................................................................16-18

16.8 Enabling the Module..................................................................................................16-20

16.9 Specifying Sample/Conversion Control .....................................................................16-20

16.10 How to Start Sampling...............................................................................................16-21

16.11 How to Stop Sampling and Start Conversions...........................................................16-22

16.12 Controlling Sample/Conversion Operation.................................................................16-32

16.13 Specifying Conversion Results Buffering...................................................................16-33

16.14 Conversion Sequence Exampl es....................................... ...... ................................. .16-3 7

16.15 A/D Sampling Requirements.................. ...... ..... ...... ...................................................16-49

16.16 Reading the ADC Result Buffer.................................... ..... .................................. ..... .16-50

16.17 Transfer Function (10-bit Mode).................................................................................16-52

16.18 Transfer Function (12-bit Mode).................................................................................16-53

16.19 ADC Accuracy/Error...................................................................................................16-54

16.20 Connection Considerati ons............................... ...... ...... ..... .................................. ..... .16-54

16.21 Code Examples..........................................................................................................16-54

16.22 Operation During Sleep and Idle Modes....................................................................16-61

16.23 Effects of a Reset.......................................................................................................16-62

16.24 Special Function Registers Associated with the ADC................................................16-62

16.25 Design Tips................................................................................................................16-64

16.26 Related Application Notes..........................................................................................16-65

16.27 Revision History.........................................................................................................16-66

dsPIC33F Family Reference Manual

16.1 INTRODUCTION

The dsPIC33F family devices hav e up to 32 A/D input ch ann els . Thes e dev ic es also hav e up to two ADC modules (ADC x, whe r e x = 1 or 2), ea ch with its own set of Special Func tio n Registers (SFRs).

The 10-bit or 12-bit Operation Mode (AD12B) bit in the ADCx Control 1(ADxCON1) register allows each of the ADC modules to be configured by the user application as either a 10-bit, 4 Sample/Hold (S/H) ADC (default configuration) or a 12-bit, 1 Sample/Hold ADC.

Note: The ADC module needs to be disabled before the AD12B bit is modified.

The 10-bit ADC configuration (AD12B = 0) has the following key features:

• Successive Approximation (SAR) conversion

• Conversion speeds of up to 1.1 Msps

• Up to 32 analog input pins

• External voltage reference input pins

• Simultaneous sampling of up to four analog input pins

• Automatic Channel Scan mode

• Selectable conversion trigger source

• Selectable Buffer Fill modes

• DMA support, including Peripheral Indirect Addressing

• Four result alignment options (signed/unsigned, fractional/integer)

• Operation during CPU Sleep and Idle mode s Depending on the partic ul ar dev ic e pin out, the ADC can have up to 32 analog input pin s, desi g-

nated AN0 through AN31. In addition, there are two analog input pins for external voltage reference connections. These voltage reference inputs can be shared with other analog input pins. The actual number of analog input pins and external voltage reference input configuration will depend on the specific device. Refer to the device data sheet for further details.

The analog inputs are multiplexed to four Sample/Hold amplifiers, designated CH0-CH3. One, two, or four of the Sample/Hold amplifiers can be enabled for acquiring input data. The analog input multiplexers can be switched between two sets of analog inputs during conversions. Unipolar differential conversions are possible on all channels using certain input pins (see Figure 16-1).

An Analog Input Scan mode can be enabled for the CH0 Sample/Hold Amplifier. A Control register specifies which analog input channels are included in the scanning sequence.

The ADC is c onnec ted to a sing le-w ord re sult buffer. Howev er, multiple c onver sion resul ts can be stored in a DMA RAM buffer with no CPU overhead. Each conversion result is converted to one of four 16-bit output formats when it is read from the buffer.

The 12-bit ADC configuration (AD12B = 1) supports all the above features, except:

• In the 12-bit configuration, conversion speeds of up to 500 ksps are supported

• There is only one Sample/Hold amplifier in the 12-bit configuration, so simultaneous sampling of multiple channels is not supported.

Section 16. Analog-to-Digital Converter (ADC)

ADC

Figure 16-1: ADC Block Diagram

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VREF+

(1)

VREF-

AVDD

AVSS

AN0

AN1

AN2

(3)

AN3

AN4

AN5

Analog Input Pins

AN6

AN7

AN8

AN9

AN10

AN11

AN0 AN3

AN6 AN9

VREF-

AN1 AN4

AN7 AN10 VREF-

AN2

AN5

AN8 AN11 VREF-

00000 00001 00010 00011

00100

00101

00110

00111

01000

01001

01010

01011

S/H

CH1

CH2

CH3

Sample

(2)

CH0,CH1, CH2,CH3

Conversion

Input

Switches

ADC

Result

Conversion Logic

16-bit

ADC Result

Buffer

Sample/Sequence

Control

Input MUX

Control

Data Format

Bus Interface

AN30

AN31

11110

11111

VREF-

AN1

CH0

S/H

Note1: VREF+, VREF- inputs can be multiplexed with other analog inputs. See device data sheet for details.

2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation. 3: The ADC1 module can use all 32 analog input pins (AN0-AN31), whereas ADC2 can use only 16

analog input pins (AN0-AN15).

dsPIC33F Family Reference Manual

16.2 CONTROL REGISTERS

The ADC module has ten Control and Status registers. These registers are:

• ADxCON1: ADCx Control Register 1(1)

• ADxCON2: ADCx Control Register 2(1)

• ADxCON3: ADCx Control Register 3(1)

• ADxCON4: ADCx Control Register 4(1)

• ADxCHS123: ADCx Input Channel 1, 2, 3 Select Register(1)

• ADxCHS0: ADCx Input Channel 0 Select Register

• AD1CSSH: ADC1 Input Scan Select Register High

• ADxCSSL: ADCx Input Scan Select Register Low

• AD1PCFGH: ADC1 Port Configuration Register High

• ADxPCFGL: ADCx Port Configuration Register Low The ADxCON1, ADxCON2 and ADxCON3 registers control the operation of the ADC module.

The ADxCON4 register s ets u p the numb er of conv ersion resul ts sto red in a D MA buf fer for each analog input in the Scatter/Gather mode. The ADxCHS123 and ADxCHS0 registers select the input pins to be connected to the Sampl e/Hold am plifi ers. The ADx PCFGH/ L regist ers conf igure the analog input pins as ana log inpu ts or as digit al I/O . The ADCSSH/L register s selec t input s to be sequentially scanned.

Section 16. Analog-to-Digital Converter (ADC)

ADC

R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 ADON — ADSIDL ADDMABM —AD12B FORM<1:0>

bit 15 bit 8

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R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0

HC,HS

SSRC<2:0>

— SIMSAM ASAM SAMP DONE

R/C-0

HC, HS

bit 7 bit 0

Legend: HC = Cleared by hardware HS = Set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 ADON: ADC Operating Mode bit

1 = ADC module is operating 0 =ADC is off

bit 14 Unimplemented: Read as ‘0’ bit 13 ADSIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode

bit 12 ADDMABM: DMA Buffer Build Mode bit

1 = DMA buffers are written in the ord er of co nversi on. The mo dule p rovide s an ad dress to th e DM A

channel that is the same as the address used for the non-DMA stand-alone buffer.

0 = DMA buffers are written in Scatter/Gathe r mode. The mo dule provi des a Scatter/ Gather addre ss

to the DMA channel, based on the index of the analog input and the size of the DMA buffer. bit 11 Unimplemented: Read as ‘0’ bit 10 AD12B: 10-bit or 12-bit Operation Mode bit

1 = 12-bit, 1-channel ADC operation 0 = 10-bit, 4-channel ADC operation

bit 9-8 FORM<1:0>: Data Output Format bits

For 10-bit operation:

11 = Signed fractional (DOUT = sddd dddd dd00 0000, where s = .NOT.d<9>) 10 = Fractional (D 01 = Signed integer (D 00 = Integer (D

OUT = dddd dddd dd00 0000)

OUT = ssss sssd dddd dddd, where s = .NOT.d<9>)

OUT = 0000 00dd dddd dddd)

For 12-bit operation:

11 = Signed fractional (DOUT = sddd dddd dddd 0000, where s = .NOT.d<11>) 10 = Fractional (D 01 = Signed Integer (D 00 = Integer (D

OUT = dddd dddd dddd 0000)

OUT = ssss sddd dddd dddd, where s = .NOT.d<11>)

OUT = 0000 dddd dddd dddd)

bit 7-5 SSRC<2:0>: Sample Clock Source Select bits

111 = Internal counter ends sampling and starts conversion (auto-convert) 110 = Reserved 101 = Reserved 100 = Reserved 011 = MPWM interval ends sampling and starts conversion 010 = GP timer (Timer3 for ADC1, Timer5 for ADC2) compare ends sampling and starts conversion 001 = Active transition on INTx pin ends sampling and starts conversion 000 = Clearing sample bit ends sampling and starts conversion

bit 4 Unimplemented: Read as ‘0’

Note 1: The ‘x’ in ADxCON1 and ADCx refers to ADC 1 or ADC 2.

dsPIC33F Family Reference Manual

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bit 3 SIMSAM: Simultaneous Sample Select bit (only applicable when CHPS<1:0> = 01 or 1x)

When AD12B = 1, SIMSAM is: U-0, Unimplemented, Read as ‘0’

1 = Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or

Samples CH0 and CH1 simultaneously (when CHPS<1:0> = 01)

0 = Samples multiple channels individually in sequence

bit 2 ASAM: ADC Sample Auto-Start bit

1 = Sampling begins immediately after last conversion. SAMP bit is auto-set. 0 = Sampling begins when SAMP bit is set

bit 1 SAMP: ADC Sample Enable bit

1 = ADC Sample/Hold amplifiers are sampling 0 = ADC Sample/Hold amplifiers are holding

If ASAM = 0, software can write ‘1’ to begin sampling. Automatically set by hardware if ASAM = 1. If SSRC = 000, software can write ‘0’ to end sampling and start conversion. If SSRC ≠ 000,

automatically cleared by hardware to end sampling and start conversion.

bit 0 DONE: ADC Conversion Status bit

1 = ADC conversion cycle is completed. 0 = ADC conversion not started or in progress

Automatically set b y hardwar e when A/D co nversion is complete . Software can write ‘0’ to clear DONE

status (software not allowed to write ‘1’). Clearing this bit does NOT affect any operation in progress. Automatically cleared by hardware at start of a new conversion.

Note 1: The ‘x’ in ADxCON1 and ADCx refers to ADC 1 or ADC 2.

(Continued)

Section 16. Analog-to-Digital Converter (ADC)

ADC

R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0

VCFG<2:0> — — CSCNA CHPS<1:0>

bit 15 bit 8

R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

BUFS — SMPI<3:0> BUFM ALTS

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 VCFG<2:0>: Converter Voltage Reference Configuration bits

VREFH VREFL

000 AVDD Avss 001 External VREF+Avss 010 A 011 External VREF+ External VREF- 1xx AVDD Avss

VDD External VREF-

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bit 12-11 Unimplemented: Read as ‘0’ bit 10 CSCNA: Input Scan Select bit

1 = Scan inputs for CH0+ during Sample A bit 0 = Do not scan inputs

bit 9-8 CHPS<1:0>: Channel Select bits

When AD12B = 1, CHPS<1:0> is: U-0, Unimplemented, Read as ‘0’

1x = Converts CH0, CH1, CH2 and CH3 01 = Converts CH0 and CH1 00 = Converts CH0

bit 7 BUFS: Buffer Fill Status bit (only valid when BUFM = 1)

1 = AD C is currently filling the second half of the buffer. The user application should access data in

the first half of the buffer

0 = ADC is currently filling the first half of the buffer. The user application should access data in the

second half of the buffer. bit 6 Unimplemented: Read as ‘0’ bit 5-2 SMPI<3:0>: Increment Rate for DMA Addresses bits

1111 = Increments the DMA address or generates interrupt after completion of every 16th

sample/conversi on ope ration

1110 = Increments the DMA address or generates interrupt after completion of every 15th

sample/conversi on ope ration

• • • 0001 = Increments the DMA address or generates interrupt after completion of every 2nd

sample/conversi on ope ration

0000 = Increments the DMA address or generates interrupt after completion of every

sample/conversi on ope ration

bit 1 BUFM: Buffer Fill Mode Select bit

1 = Starts buf fer fi lling th e first ha lf of the bu ffe r on th e first in terrupt an d the se cond ha lf of the bu ffe r

on next interrupt

0 = Always starts filling the buffer from the start address.

bit 0 ALTS: Alternate Input Sample Mode Select bit

1 = Uses channel input selects for Sample A on first sample and Sample B on next sample 0 = Always uses channel input selects for Sample A

Note 1: The ‘x’ in ADxCON2 and ADCx refers to ADC 1 or ADC 2.

dsPIC33F Family Reference Manual

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R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADRC — — SAMC<4:0>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADCS<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 ADRC: ADC Conversion Clock Source bit

1 = ADC Internal RC Clock 0 = Clock Derived From System Clock

bit 14-13 Unimplemented: Read as ‘0’ bit 12-8 SAMC<4:0>: Auto Sample Time bits

11111 = 31 T

• • • 00001 = 1 T

00000 = 0 TAD

bit 7-0 ADCS<7:0>: ADC Conversion Clock Select bits

11111111 = TCY · (ADCS<7:0> + 1) = 256 · TCY = TAD

• • •

00000010 = T 00000001 = T

CY · (ADCS<7:0> + 1) = 3 · TCY = TAD CY · (ADCS<7:0> + 1) = 2 · TCY = TAD

00000000 = TCY · (ADCS<7:0> + 1) = 1 · TCY = TAD

Note 1: The ‘x’ in ADxCON3 and ADCx refers to ADC 1 or ADC 2.

Section 16. Analog-to-Digital Converter (ADC)

ADC

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — DMABL<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 DMABL<2:0>: Selects Number of DMA Buffer Locations per Analog Input bits

111 =Allocates 128 words of buffer to each analog input 110 =Allocates 64 words of buffer to each analog input 101 =Allocates 32 words of buffer to each analog input 100 =Allocates 16 words of buffer to each analog input 011 =Allocates 8 words of buffer to each analog input 010 =Allocates 4 words of buffer to each analog input 001 =Allocates 2 words of buffer to each analog input 000 =Allocates 1 word of buffer to each analog input

Note 1: The ‘x’ in ADxCON4 and ADCx refers to ADC 1 or ADC 2.

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dsPIC33F Family Reference Manual

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U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — CH123NB<1:0> CH123SB

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — CH123NA<1:0> CH123SA

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-11 Unimplemented: Read as ‘0’ bit 10-9 CH123NB<1:0>: Channel 1, 2, 3 Negative Input Select for Sample B bits

When AD12B = 1, CHxNB is: U-0, Unimplemented, Read as ‘0’

11 = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11 10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8 0x = CH1, CH2, CH3 negative input is V

REFL

bit 8 CH123SB: Channel 1, 2, 3 Positive Input Select for Sample B bit

When AD12B = 1, CHxSA is: U-0, Unimplemented, Read as ‘0’

1 = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5 0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2

bit 7-3 Unimplemented: Read as ‘0’ bit 2-1 CH123NA<1:0>: Channel 1, 2, 3 Negative Input Select for Sample A bits

When AD12B = 1, CHxNA is: U-0, Unimplemented, Read as ‘0’

bit 0 CH123SA: Channel 1, 2, 3 Positive Input Select for Sample A bit

When AD12B = 1, CHxSA is: U-0, Unimplemented, Read as ‘0’

1 = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5 0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2

Note 1: The ‘x’ in ADxCHS123 and ADCx refers to ADC 1 or ADC 2.

Section 16. Analog-to-Digital Converter (ADC)

ADC

Register 16-6: ADxCHS0: ADCx Input Channel 0 Select Register

R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CH0NB

bit 15 bit 8

R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CH0NA — — CH0SA<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 CH0NB: Channel 0 Negative Input Select for Sample B bit

bit 14-13 Unimplemented: Read as ‘0’ bit 12-8 CH0SB<4:0>: Channel 0 Positive Input Select for Sample B bits

bit 7 CH0NA: Channel 0 Negative Input Select for Sample A bit

bit 6-5 Unimplemented: Read as ‘0’ bit 4-0 CH0SA<4:0>: Channel 0 Positive Input Select for Sample A bits

Note1: The AN16 – AN31 pins are not available for ADC 2.

2: The ‘x’ in ADxCHS0 and ADCx refers to ADC 1 or ADC 2

— — CH0SB<4:0>

Same definition as bit 7.

Same definition as bit<4:0>.

1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is V

11111 = Channel 0 positive input is AN31 11110 = Channel 0 positive input is AN30

• • •

00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0

REFL

(1, 2)

dsPIC33F Family Reference Manual

Register 16-7: AD1CSSH: ADC1 Input Scan Select Register High

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CSS31 CSS30 CSS29 CSS28 CSS27 CSS26 CSS25 CSS24

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CSS23 CSS22 CSS21 CSS20 CSS19 CSS18 CSS17 CSS16

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 CSS<31:16>: ADC Input Scan Selection bits

(1, 2)

1 = Select ANx for input scan 0 = Skip ANx for input scan

Note1: On devices with less than 32 analog inputs, all ADxCSSL bits can be selected by user. However, inputs

selected for scan without a corresponding input on device convert V

REF-.

2: ADC 2 only supports analog inputs AN0-AN15; therefore, no ADC 2 Input Scan Select register exists.

Register 16-8: ADxCSSL: ADCx Input Scan Select Register Low

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CSS15 CSS14 CSS13 CSS12 CSS11 CSS10 CSS9 CSS8

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 CSS<15:0>: ADC Input Scan Selection bits

(1, 2)

1 = Select ANx for input scan 0 = Skip ANx for input scan

Note1: On devices with less than 16 analog inputs, all ADxCSSL bits can be selected by the user. However, inputs

selected for scan without a corresponding input on device convert V

REF-.

2: The ‘x’ in ADxCSSL and ADCx refers to ADC 1 or ADC 2.

Section 16. Analog-to-Digital Converter (ADC)

ADC

Register 16-9: AD1PCFGH: ADC1 Port Configuration Register High

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PCFG31 PCFG30 PCFG29 PCFG28 PCFG27 PCFG26 PCFG25 PCFG24

bit 15

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PCFG23 PCFG22 PCFG21 PCFG20 PCFG19 PCFG18 PCFG17 PCFG16

bit 7

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 8

bit 0

bit 15-0 PCFG<31:16>: ADC Port Configuration Control bits

(1, 2)

1 = Port pin in Digital mode, port read input enabled, ADC input multiplexor connected to AVSS 0 = Port pin in Analog mode, port read input disabled, ADC samples pin voltage

Note1: On devices wi th less than 3 2 ana log i nput s, al l PC FG bit s are R/W by u ser. However, PCFG bit s are igno red

on ports without a corresponding input on device.

2: ADC2 only supports analog inputs AN0-AN15; therefore, no ADC2 Port Configuration register exists.

Register 16-10: ADxPCFGL: ADCx Port Configuration Register Low

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8

bit 15

bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0

bit 7

bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 PCFG<15:0>: ADC Port Configuration Control bits

(1, 2, 3)

1 = Port pin in Digital mode, port read input enabled, ADC input multiplexor connected to AVSS 0 = Port pin in Analog mode, port read input disabled, ADC samples pin voltage

Note1: On devices wi th less than 1 6 ana log i nput s, al l PC FG bit s are R/W by u ser. However, PCFG bit s are igno red

on ports without a corresponding input on device.

2: On devices with two analog-to-di gi t al modules, both AD1PCF GL and AD2PCFGL a f f ect the configuration of

port pins multiplexed with AN0-AN15.

3: The ‘x’ in ADxPCFGL and ADx refers to ADC 1 or ADC 2

dsPIC33F Family Reference Manual

16.3 A/D TERMINOLOGY AND CONVERSION SEQUENCE

Figure 16-2 shows a ba sic co nv ers ion seq uen ce and the terms that are used. A sa mp ling of the analog input pin volt age is pe rformed by Sampl e/Hold a mpli fiers (a lso c alled Sam ple/H old cha nnels). The 10-bit ADC configuration can use up to four Sample/Hold channels, designated CH0-CH3, whereas the 12-bit ADC configuration can use only one Sample/Hold channel, CH0. The Sample/Hold channels are connected to the analog input pins via the analog input multiplexer. The analog input multiplexer is controlled by the ADxCHS123 and ADxCHS0 registers. There are two set s of mult ipl ex er co ntro l bits in the ADC channel select registers that function identically. These two sets of control bits allow two different analog input multiplexer configurations to be programmed (called MUX A and MUX B). The ADC can optionally switch between the MUX A and M UX B co nfigura tions bet ween c onvers ions. The ADC can al so optio nally scan through a series of analog inputs.

Sample time is the time th at the ADC module ’s Sample/Hold Am plifier is co nnected to the an alog input pin. The sample time can be started manually by setting the ADC Sample Enable (SAMP) bit in ADCx Control Register 1 (ADxCON1<1>) or started automatically by the ADC hardware. The sample time is ended manua lly by clearin g the SAMP cont rol bit in the user softwar e or automatically by a conversion trigger source.

Conversion time i s the tim e requ ired fo r the AD C to c onvert the vo lta ge hel d by the Sam ple/Hol d Amplifier . Th e ADC is disc onnec ted from th e analo g input pi n at the end of the sam ple time. Th e ADC requires one A/D clock cycle (T cycles. A total of 12 T A total of 14 T

AD cycles are required to perform the complete conversion in 10-bit mode.

AD cycles are required to perform the complete conversion in 12-bit mode. When

the conversion time is complete, the result is loaded into the ADCxBUF0 register, the Sample/Hold Amplifier can be reconnected to the input pin and a CPU interrupt can be generated.

The sum of the sample time and the A/D conversion time provides the total conversion time. There is a minimum sample time to ensure that the Sample/Hold Amplifier provides the desired accuracy for the A/D conversion (see 16.15 “A/D Sampling Requirements”). Furthermore, there are multiple input clock options for the ADC. You must select an input clock option that does not violate the minimum T

AD specification.

AD) to convert each bit of the result plus two ad ditional cloc k

Figure 16-2: ADC Sample/Conversion Sequence

ADC Total Conversion Time

Sample Time

Sample/Hold Amplifier is connected to the analog input pin for sampling.

ADC Conversion Time

A/D conversion complete, result is loaded into result buffer. Optionally generate interrupt.

Sample/Hold Amplifier is disconnected from input and holds signal level . A/D conversion is started by the conversion trigger source.

The ADC allows many options for spe cifyi ng the sam ple/co nvert se quenc e. The samp le/co nvert sequence can be very simple, using only one Sample/Hold amplifier. A more elaborate sample/convert sequ ence performs mul tiple conversi ons using mo re than one Samp le/Hold amplif ier . The 10-bit ADC conf igurati on ca n use t wo Sampl e/Ho ld am plifie rs to pe rform two conv ersion s in a sample/convert sequence or four Sample/Hold amplifiers with four conversions.

Section 16. Analog-to-Digital Converter (ADC)

ADC

The number of Sample/Hold amplifiers, or channels per sample, used in the sample/convert sequence is determined by the Channel Select (CHPS<1:0>) control bits in ADCx Control Register 2 (ADxCON2<9:8>).

Note: The 12-bit ADC configuration can only perform one conversion in a single sam-

ple/convert sequence. The CHPS bits are irrelevant in this case.

A sample/convert sequence that uses multiple Sample/Hold channels can be simultaneously sampled or sequentially sampled, as controlled by the Simultaneous Sample Select (SIMSAM) bit (ADxCON1<3>). Simultaneously sampling multiple signals ensures that the snapshot of the analog inputs oc curs at precis ely the same tim e for all input s. Sequenti al sampling t akes a sna pshot of each analog input just before conversion starts on that input. The sampling of multiple inputs is not correlated.

Figure 16-3: Simultaneous and Sequential Sampling

AN0 AN1

AN2 AN3

Simultaneous

Sampling

The start time for sampling can be controlled in software by setting the ADC Sample Enable (SAMP) control bit (ADxCON1<1>). The start of the sampling time can also be controlled automatically by the hardware . Wh en the ADC mod ule op erates in the Auto-Sa mple mode, the Sam ple/Hold amplifier(s) is reconnected to the analog input pin at the end of the conversion in the sample/convert sequen ce. The auto-s ample function i s controlled by the ADC Sample Auto -St art (ASAM) control bit (ADxCON1<2>).

The conversion trigger source ends the sampling time and begins an A/D conversion or a sample/convert sequence. The conversion trigger source is selected by the Sample Clock Source Select (SSRC<2:0>) control bits (ADxCON1<7:5>. The conversion trigger can be taken from a variety of hardware sources, or can be controlled manually in software by clearing the SAMP control bit. One of th e conversion trigge r sources is an auto -conversion. The tim e between auto-conversions is s et by a coun ter and the AD C clo ck . The Auto -Sam pl e mo de an d auto -co nversion trigger can be used together to provide endles s automatic conversions w ith out s oftwa r e intervention.

An interrupt can be generated at the end of each sample/convert sequence or after multiple sample/convert sequences, as determined by the value of the Samples Per Interrupt (SMPI<3:0>) control bit s (ADxCON2 <5:2>). The number of sam ple/co nvert seque nces between interrupts can vary between 1 an d 16. T he tot al num ber of conv ersion resul ts between inter rupt s is the product of the channels per sample and the SMPI<3:0> value. However, since only one conversion result is stored in ADCxBUF0, each execution of the interrupt servi ce routi ne c an be used to read only one conversion result.

If multiple convers ion re sult s ne ed t o be b uff ered, a DMA buffer should be used to store the co nversion results. In this case, the SMPI<3:0> bits are used to select how often the DMA RAM buffer pointer i s incremented . The freque ncy of incr ementing the D MA RAM buf fer pointer should not exceed the DMA RAM buffer length.

Sequential

Sampling

dsPIC33F Family Reference Manual

16.4 ADC MODULE CONFIGURATION

The following steps should be followed for performing an A/D conversion:

1. Select 10-bit or 12-bit mode (ADxCON1<10>)

2. Select voltage reference source to match expected range on analog inputs (ADxCON2<15:13>)

3. Select the analog conversion clock to match desired data rate with processor clock (ADxCON3<7:0>)

4. Select port pins as analog inputs (ADxPCFGH<15:0> and ADxPCFGL<15:0>)

5. Determine how inputs will be allocated to Sample/Hold channels (ADxCHS0<15:0> and ADxCHS123<15:0>)

6. Determine how many Sample/Hold channels will be used (ADxCON2<9:8>, ADxPCFGH<15:0> and ADxPCFGL<15:0>)

7. Determine how sampling will occur (ADxCON1<3>, ADxCSSH<15:0> and ADxCSSL<15:0>)

8. Select Manual or Auto Sampling

9. Select conversion trigger and sampling time.

10. Select how conversion results are st ored in the buffer (ADxCON1<9:8>)

11. Select interrupt rate or DMA buffer pointer increment rate (ADxCON2<9:5>)

12. Select the number of samples in DMA buffer for each ADC module input (ADxCON4<2:0>)

13. Select the data format

14. Configure ADC interrupt (if required)

• Clear ADxIF bit

• Select interrupt priority (ADxIP<2:0)

• Set ADxIE bit

15. Configure DMA channel (if needed)

16. Turn on ADC module (ADxCON1<15>)

The options for these configuration steps are described in the subsequent sections.

16.5 SELECTING THE VOLTAGE REFERENCE SOURCE

The voltage references for A/D conversions are selected using the VCFG<2:0> control bits (ADxCON2<15:13>). The upper voltage reference (V

REFL) can be the internal AVDD and AVSS voltage rails or the VREF+ and VREF- input pins.

(V The external vo ltage reference pins can be sha red wit h the AN0 and A N1 input s on l ow pin count

devices. The ADC modu le can still perfo rm conversion s on these pins when they are shared wi th the Vref+ and Vref- input pins.

The voltages app lied to the external ref erence pins mu st meet certain s pecificatio ns. Refer to the “Electrical Specifications” section of the device data sheet for details

REFH) and the lower voltage reference

Section 16. Analog-to-Digital Converter (ADC)

ADC

16.6 SELECTING THE A/D CONVERSION CLOCK

The ADC module has a maximum rate at which conversions can be completed. An analog module clock, T

AD) in the 10-bit mode an d 14 clock period s (14 TAD) in the 12-bit mode. The A/D conv ersion

(12 T clock is derived from either the device instruction clock or an internal RC clock source.

The period of the A/D conversi on cloc k is softwa re selec ted using a 6-bit co unter. There are 256 possible options for T (ADxCON3<7:0>). Equation 16-1 gives the T the device instruction cycle clock period, T

Equation 16-1: A/D Conversion Clock Period

AD, controls the conversi on timing. T he A/D conv ersion require s 12 clock peri ods

AD, specified by the ADC Conversion Clock Select (ADCS<7:0>) bits

AD value as a function of the ADCS contro l bit s and

CY.

AD = TCY(ADCS + 1)

ADCS =

TCY

– 1

For correct A/D conversions, the A/D conversion clock (T minimum T

AD time of 75 nsec.

AD) must be selected to ensure a

The ADC module has a dedicated internal RC clock source that can be used to perform conversions. The in ternal RC clock s ource should be used when A/D co nversion s are perfo rmed while the device is in Sle ep mode. The inte rnal RC osci llator is se lected by setti ng the ADC Conversion Clock Source (ADRC) bit (ADxCON3<15>). When the ADRC bit is set, the ADCS<7:0> bits have no effect on the A/D operation.

Figure 16-4: A/D Conversion Clock Period Block Diagram

ADxCON3<15>

ADC Internal RC Clock

TCY

ADxCON3<7:0>

A/D Conversion Clock Multiplier

1, 2, 3, 4, 5,..., 256

TAD

dsPIC33F Family Reference Manual

16.7 SELECTING ANALOG INPUTS FOR SAMPLING

All Sample/Hold Amplifiers have analog multiplexers (see Figure 16-1) on both their non-inverting and inverting inputs to select which analog input(s) are sampled. Once the sample/convert sequence is specified, the ADxCHS0 and ADxCHS123 registers determine which analog inputs are selected for each sample.

Additionally, the selected inputs can vary on an alternating sample basis or on a repeated sequence of samples.

The same analog in put can be conn ected to two or more Sa mp le/Hold chann els to impro ve co nversion rates.

Note: Different devices will have different numbers of analog inputs. Verify the analog

input availability against the device data sheet.

16.7.1 Configuring Analog Port Pins

The ADPCFGH and ADPCFGL regi sters s pe ci fy th e in put con dit ion of de vic e p ins us ed a s an alog inputs. Along with the Data Direction (TRISx) register in the Parallel I/O Port module, these registers control the operation of the ADC pins.

A pin is configured as analog input when the corresponding PCFGn bit (ADPCFGH<n> or ADPCFGL<n>) is clear. The ADPCFGH and ADPCFGL registers are clear at Reset, cau sing the ADC input pins to be configured for analog input by default at Reset.

When configured for an alog input, the associ ated port I/O digit al input buff er is disabled so it doe s not consume current.

The port pins that are desire d as analog inp uts must h ave their correspo nding TRIS bit s et, specifying port input. If the I/O pin associated with an A/D input is configured as an output, the TRIS bit is cleared and the port’s digital output level (V all TRIS bits are set.

A pin is configured as digital I/O when the corresponding PCFGn bit is set. In this configuration, the input to the analog multiplexer is connected to AVss.

OH or VOL) is converted. After a device Reset,

Note 1: When the ADC Port register is read, any pin configured as an analog input reads

as a ‘0’.

2: Analog levels on any pin that is defined as a digital input (including the AN15:AN0

pins) may cause the input buffer to consume current that is out of the device’s specification.

16.7.2 Channel 0 Input Selection

Channel 0 is the most flexible of the four Sample/Hold channels in terms of selecting analog inputs. It allows you to select any of the up to 16 analog inputs as the input to the positive input of the channel. The Channel 0 Positive Input Select for Sample A (CH0SA<4:0>) bits (ADxCHS0<4:0>) normally select the analog input for the positive input of channel 0.

You can select either V (ADxCHS0<7>) normally selects the analog input for the negative input of channel 0.

16.7.2.1 SPECIFYING ALTERNATING CHANNEL 0 INPUT SELECTIONS

The Alternate Input Samp le M od e Se lect (ALTS) bit (ADxCON2<0>) causes the AD C m odu le to alternate between two sets of inputs that are selected during successive samples.

The inputs specified by CH0SA<4:0> (ADxCHS0<4:0>), CH0NA (ADxCHS0<7>), CH123SA (ADxCHS123<0>) and CH123NA<1:0> (ADxCHS123<2:1>) are collectively called the MUX A inputs. The inputs specified by CH0SB<4:0> (ADxCHS0<12:8>), CH0NB (ADxCHS0<15>), CH123SB (ADxCHS0<8>) and CH123NB<1:0> (ADxCHS0<10:9>) are collectively called the MUX B inputs. When the ALTS bit is ‘1’, the ADC module alternates between the MUX A inputs on one group of samples and the MUX B inputs on the subsequent group of samples.

REF- or AN1 as the negative input of the channel. The CH0NA bit

Section 16. Analog-to-Digital Converter (ADC)

ADC

For channel 0, if the ALTS bit is ‘0’, only the inputs specified by CH0SA<4:0> and CH0NA are selected for sampling.

If the ALTS bit is ‘1’, on the first sample/convert sequence for channel 0, the inputs specified by CH0SA<4:0> and CH0NA are selected for sampling. On the next sample convert sequence for channel 0, the inputs specified by CH0SB<4:0> and CH0NB are selected for sampling. This pattern repeats for subsequent sample conversion sequences.

Note that if multiple channels (CHPS = 01 or 1x) and simultane ous s am pli ng (SIM SAM = 1) a re specified, alternating inputs change every sample because all channels are sampled on every sample time. If multi ple chann els (CHPS = 01 or 1x) and sequ ential sa mpling (SIM SAM = 0) are specified, alternating inputs change only on each sample of a particular channel.

16.7.2.2 SCANNING THROUGH SEVERAL INPUTS WITH CHANNEL 0

Channel 0 can scan through a selected vector of inputs. The CSCNA bit (ADxCON2<10>) enables the CH0 chann el inputs to be sca nned across a selected number of analog input s. When CSCNA is set, the CH0SA<4:0> bits are ignored.

The ADCx Input Scan Select Register High (ADxCSSH) and ADCx Input Scan Select Register Low (ADxCSSL) registers specify the inputs to be scanned. Each bit in these registers corresponds to an analog input. Bit 0 corresponds to AN0, bit 1 corresponds to AN1 and so on. If a particular bit is ‘1’, the corre sponding inpu t is part of the scan sequence. The inputs are always scanned from low er to higher numbe red input s, starti ng at the first select ed chann el after each interrupt occurs.

Note: If the number of scanned inputs selected is greater than the number of samples

taken per interrupt, the higher numbered inputs will not be sampled.

The ADxCSSH and ADxCSSL bit s only specify the input of the pos itive input of the channel. The CH0NA bit still selects the input of the negative input of the channel during scanning.

If the ALTS bit is ‘1’, t he sc anni ng onl y appl ies to the MU X A inp ut se lect ion. Th e MUX B in put selection, as s pecified by the CH0SB<4:0>, still select s the alternatin g channel 0 input. When the input selections ar e program med in this manner, the channel 0 input alternates between a se t of scanning inputs specified by the ADxCSSL register and a fixed input specified by the CH0SB bits.

16.7.3 Channel 1, 2 and 3 Input Selection

Channel 1, 2 and 3 c an s ample a subset of the ana log in put pins. Channel 1, 2 and 3 c an se lec t one of two groups of three inputs.

The CH123SA bit (ADxCHS123< 0>) selects the sourc e for the positive input s of channel 1, 2 and

3. Clearing CH123SA selects AN0, AN1 and AN2 as the analog source to the positive inputs of channel 1, 2 and 3, respectively. Setting CH123SA selects AN3, AN4 and AN5 as the analog source.

The CH123NA<1:0> bit s (ADx CHS<2:1 >) selec t the sou rce for the negativ e input s of c hannel 1, 2 and 3. Programming CH12 3NA = 0x selects V of channels 1, 2 and 3. Programming CH123NA = 10 selects AN6, AN7 and AN8 as the analog source to the negative inputs of channels 1, 2 and 3 respectively. Programming CH123NA = 11 selects AN9, AN10 and AN11 as the analog source.

REF- as the analog source fo r the negative in puts

dsPIC33F Family Reference Manual

16.7.3.1 SELECTING MULTIPLE CHANNELS FOR A SINGLE ANALOG INPUT

The analog input multip lexer ca n be conf igu red so that th e sam e inpu t pin i s con necte d to tw o or more Sample/Hold channels. The ADC converts the value held on one Sample/Hold channel, while the second Sample/Hold channel acquires a new input sample.

16.7.3.2 SPECIFYING ALTERNATING CHANNEL 1, 2 AND 3 INPUT

SELECTIONS

As with the channel 0 inputs, the ALTS bit (ADxCON2<0>) causes the ADC module to alternate between two sets of inputs that are selected during successive samples for channel 1,2 and 3.

The MUX A inputs specified by CH123SA and CH123NA<1:0> always select the input when ALTS = 0.

The MUX A inputs alternate with the MUX B inputs specified by CH123SB and CH123NB<1:0> when ALTS = 1.

16.8 ENABLING THE MODULE

When the ADC Operating Mode (ADON) bit (ADxCON1<15>) is ‘1’, the ADC modul e is i n Active mode and is fully powered and functional.

When ADON is ‘0’, the ADC module is disab led. The digi tal and an alog portion s of the circuit ar e turned off for maximum current savings.

In order to return to the Activ e mode f rom th e Of f m ode, th e user must wai t for th e anal og st age s to stabilize. For the stabilization time, refer to the Electrical Characteristics section of the device data sheet.

Note: The SSRC<2:0>, SIMSAM, ASAM, CHPS<1:0>, SMPI<3:0>, BUFM and AL TS bits ,

as well as the ADxCON3, ADxCSSH and ADxCSSL registers, should not be written to while ADON = 1. This would lead to indeterminate results.

16.9 SPECIFYING SAMPLE/CONVERSION CONTROL

The ADC modul e use s fo ur Sa mple /Hol d am plif ie rs an d one A /D C onv erte r in the 10 -b it mode . The module can perform 1, 2 or 4 input samples and A/D conversions per sample/convert sequence.

16.9.1 Number of Sample/Hold Channels

The CHPS<1:0> control bit s (ADxCON2<9:8> ) are used to select how many Sample/Ho ld amplifiers are used by the ADC module during sample/conversion sequences. The following three options can be selected:

• CH0 only

• CH0 and CH1

• CH0, CH1, CH2, CH3

The CHPS control bits work in conjunction with the SIMSAM (simultaneous sample) control bit (ADxCON1<3>). The CHPS and SIMSAM bits are not relevant in 12-bit mode as there is only one Sample/Hold amplifier.

16.9.2 Simultaneous Sampling Enable

Some applications can require that multiple signals be sampled simultaneously. The SIMSAM control bit (ADxCON1<3>) works in conjunction with the CHPS control bits and controls the sample/convert sequen ce fo r mul tiple chann els a s sh own in Table 16-1. Th e SIMSA M contro l bit has no effect on the ADC module operat ion if CHPS<1:0> = 00. If more than on e Sample/Hold ampl ifier is enabled by the C HPS con trol bit s and the SI MSAM b it is ‘0’, the two or four selected channels are sampled and converted sequentially with two or four sampling periods. If the SIMSAM bit is ‘1’, two or four selected channels are sampled simultaneously with one sampling period. The channels are the n converte d seque ntiall y. The SIMSAM bit is not relevant in 12-bi t mo de as there is only one S/H.

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Microchip Technology dsPIC33F Family Reference Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Section 16. Analog-to-Digital Converter (ADC)

16.1 INTRODUCTION

Figure 16-1: ADC Block Diagram

16.2 CONTROL REGISTERS

Register 16-6: ADxCHS0: ADCx Input Channel 0 Select Register

Register 16-7: AD1CSSH: ADC1 Input Scan Select Register High

Register 16-8: ADxCSSL: ADCx Input Scan Select Register Low

Register 16-9: AD1PCFGH: ADC1 Port Configuration Register High

Register 16-10: ADxPCFGL: ADCx Port Configuration Register Low

16.3 A/D TERMINOLOGY AND CONVERSION SEQUENCE

Figure 16-2: ADC Sample/Conversion Sequence

Figure 16-3: Simultaneous and Sequential Sampling

16.4 ADC MODULE CONFIGURATION

16.5 SELECTING THE VOLTAGE REFERENCE SOURCE

16.6 SELECTING THE A/D CONVERSION CLOCK

Equation 16-1: A/D Conversion Clock Period

Figure 16-4: A/D Conversion Clock Period Block Diagram

16.7 SELECTING ANALOG INPUTS FOR SAMPLING

16.7.1 Configuring Analog Port Pins

16.7.2 Channel 0 Input Selection

16.7.3 Channel 1, 2 and 3 Input Selection

16.8 ENABLING THE MODULE

16.9 SPECIFYING SAMPLE/CONVERSION CONTROL

16.9.1 Number of Sample/Hold Channels

16.9.2 Simultaneous Sampling Enable