Microchip Technology dsPIC33, dsPIC24 Reference Manual
HIGHLIGHTS
Programmable Gain Amplifier (PGA)
This section of the manual contains the following major topics:
1.0 Introduction ....................................................................................................................... 2
2.0 Control Registers .............................................................................................................. 3
3.0 Module Application............................................................................................................ 6
4.0 Register Maps................................................................................................................... 9
5.0 Related Application Notes............................................................................................... 10
6.0 Revision History.............................................................................................................. 11
2014-2015 Microchip Technology Inc. DS70005146B-page 1
dsPIC33/PIC24 Family Reference Manual
GAIN<2:0> = 6
Gain of 64x
GAIN<2:0> = 5
GAIN<2:0> = 4
GAIN<2:0> = 3
GAIN<2:0> = 2
PGAx
(1)
–
+
PGAx Calibration<5:0>
(1)
PGAx Negative Input
(1)
PGAx Positive Input
(1)
Gain of 32x
Gain of 16x
Gain of 8x
Gain of 4x
PGAxOUT
(1)
Note 1: x = 1 and 2.
RIN
Note: This family reference manual section is meant to serve as a complement to device
data sheets. Depending on the device variant, this manual section may not apply to
all dsPIC33/PIC24 devices.
Please consult the note at the beginning of the “Programmable Gain Amplifier
(PGA)” chapter in the current device data sheet to check whether this document
supports the device you are using.
Device data sheets and family reference manual sections are available for
download from the Microchip Worldwide Web site at: http://www.microchip.com
1.0 INTRODUCTION
The Programmable Gain Amplifier (PGA) is essentially a non-inverting amplifier with userprogrammable gains. The output of the PGA can be connected to a number of dedicated
Sample-and-Hold (S&H) inputs of the Analog-to-Digital Converter (ADC) and/or to the high-speed
analog comparator module. The PGA has five selectable gains and may be used as a ground
referenced amplifier (single-ended) or as an amplifier with an independent ground reference.
The major features of the PGA are as follows:
• Selectable operation: single-ended with internal ground or operation with independent
ground reference
• Selectable gains: 4x, 8x, 16x, 32x and 64x
• High gain bandwidth product (40 MHz)
• Rail-to-rail output voltage
• Wide input voltage range (AV
A simplified block diagram of the PGA module is shown in Figure 1-1.
SS – 0.3, AVDD + 0.3)
Figure 1-1: PGAx Module Block Diagram
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Programmable Gain Amplifier (PGA)
2.0 CONTROL REGISTERS
Note: Each dsPIC33/PIC24 family device variant may have one or more PGA modules.
An ‘x’ used in the names of pins, control/status bits and registers denotes the
particular PGA module number. Refer to the “Programmable Gain Amplifier
(PGA)” chapter of the specific device data sheet for more details.
This section outlines the specific functions of each register that controls the operation of the PGA
module. The registers are as follows:
• PGAxCON: PGAx Control Register
- Enables or disables the PGA module
- Positive input selection
- Negative input selection
- Gain selection
• PGAxCAL: PGAx Calibration Register
- Stores the calibration value
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dsPIC33/PIC24 Family Reference Manual
Register 2-1: PGAxCON: PGAx Control Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PGAEN PGAOEN SELPI2 SELPI1 SELPI0 SELNI2 SELNI1 SELNI0
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — GAIN2 GAIN1 GAIN0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PGAEN: PGAx Enable bit
1 = PGAx module is enabled
0 = PGAx module is disabled (reduces power consumption)
bit 14 PGAOEN: PGAx Output Enable bit
1 = PGAx output is connected to the DACOUTx pin
0 = PGAx output is not connected to the DACOUTx pin
bit 13-11 SELPI<2:0>: PGAx Positive Input Selection bits
111 = Reserved
110 = Reserved
101 = Reserved
100 = Reserved
011 = PGAxP4
010 = PGAxP3
001 = PGAxP2
000 = PGAxP1
bit 10-8 SELNI<2:0>: PGAx Negative Input Selection bits
111 = Reserved
110 = Reserved
101 = Reserved
100 = Reserved
011 = Ground (Single-Ended mode)
010 = PGAxN3
001 = PGAxN2
000 = Ground (Single-Ended mode)
bit 7-3 Unimplemented: Read as ‘0’
bit 2-0 GAIN<2:0>: PGAx Gain Selection bits
111 = Reserved
110 = Gain of 64x
101 = Gain of 32x
100 = Gain of 16x
011 = Gain of 8x
010 = Gain of 4x
001 = Reserved
000 = Reserved
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Programmable Gain Amplifier (PGA)
Register 2-2: PGAxCAL: PGAx Calibration Register
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — PGACAL<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-6 Unimplemented: Read as ‘0’
bit 5-0 PGACAL<5:0>: PGAx Offset Calibration bits
The calibration values for the PGA1 and PGA2 bits have to be copied from Flash addresses, 0x800E48
and 0x800E4C, respectively, before the module is enabled. For more information, refer to the Calibration
Data Address table in the “Special Features” chapter in the specific device data sheet.
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