Microchip Technology dsPIC30F6010 Datasheet

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dsPIC30F6010

Data Sheet

High Performance

Digital Signal Controllers

 2004 Microchip Technology Inc. Advance Information DS70119B

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart and rfPIC are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartShunt and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, Select Mode, SmartSensor, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October

2003. The Company’s quality system processes and procedures are for its PICmicro EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

8-bit MCUs, KEELOQ

code hopping devices, Serial

DS70119B-page ii Advance Information  2004 Microchip Technology Inc.

dsPIC30F6010

dsPIC30F6010 Enhanced Flash

16-bit Digital Signal Controller

High Performance Modified RISC CPU:

• Modified Harvard architecture

• C compiler optimized instruction set architecture with flexible addressing modes

• 84 base instructions

• 24-bit wide instructions, 16-bit wide data path

• 144 Kbytes on-chip Flash program space (Instruction words)

• 8 Kbytes of on-chip data RAM

• 4 Kbytes of non-volatile data EEPROM

• Up to 30 MIPs operation:

- DC to 40 MHz external clock input

- 4 MHz-10 MHz oscillator input with

PLL active (4x, 8x, 16x)

• 44 interrupt sources

- 5 external interrupt sources

- 8 user selectable priority levels for each

interrupt source

- 4 processor trap sources

• 16 x 16-bit working register array

DSP Engine Features:

• Dual data fetch

• Accumulator write back for DSP operations

• Modulo and Bit-Reversed Addressing modes

• Two, 40-bit wide accumulators with optional saturation logic

• 17-bit x 17-bit single cycle hardware fractional/ integer multiplier

• All DSP instructions single cycle

• ± 16-bit single cycle shift

Peripheral Features:

• High current sink/source I/O pins: 25 mA/25 mA

•Timer module with programmable prescaler:

- Five 16-bit timers/counters; optionally pair 16-bit timers into 32-bit timer modules

• 16-bit Capture input functions

• 16-bit Compare/PWM output functions

•3-wire SPI

CTM module supports Multi-Master/Slave mode

•I and 7-bit/10-bit addressing

• 2 UART modules with FIFO Buffers

• 2 CAN modules, 2.0B compliant

modules (supports 4 Frame modes)

Motor Control PWM Module Features:

• 8 PWM output channels

- Complementary or Independent Output

modes

- Edge and Center Aligned modes

• 4 duty cycle generators

• Dedicated time base

• Programmable output polarity

• Dead-time control for Complementary mode

• Manual output control

• Trigger for A/D conversions

Quadrature Encoder Interface Module Features:

• Phase A, Phase B and Index Pulse input

• 16-bit up/down position counter

• Count direction status

• Position Measurement (x2 and x4) mode

• Programmable digital noise filters on inputs

• Alternate 16-bit Timer/Counter mode

• Interrupt on position counter rollover/underflow

 2004 Microchip Technology Inc. Advance Information DS70119B-page 1

dsPIC30F6010

Analog Features:

• 10-bit Analog-to-Digital Converter (A/D) with 4 S/H Inputs:

- 500 Ksps conversion rate

- 16 input channels

- Conversion available during Sleep and Idle

• Programmable Low Voltage Detection (PLVD)

• Programmable Brown-out Detection and Reset generation

Special Microcontroller Features:

• Self-reprogrammable under software control

• Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

• Flexible Watchdog Timer (WDT) with on-chip low power RC oscillator for reliable operation

• Fail-Safe clock monitor operation detects clock failure and switches to on-chip low power RC oscillator

• Programmable code protection

• In-Circuit Serial Programming™ (ICSP™)

• Selectable Power Management modes

- Sleep, Idle and Alternate Clock modes

• Enhanced Flash program memory:

- 10,000 erase/write cycle (min.) for industrial temperature range, 100K (typical)

• Data EEPROM memory:

- 100,000 erase/write cycle (min.) for industrial temperature range, 1M (typical)

CMOS Technology:

• Low power, high speed Flash technology

• Wide operating voltage range (2.5V to 5.5V)

• Industrial and Extended temperature ranges

• Low power consumption

dsPIC30F Motor Control and Power Conversion Family*

Device Pins

Program Mem. Bytes/ Instructions

SRAM

Bytes

EEPROM

Bytes

Timer 16-bit

Input

Cap

Output

Comp/Std

PWM

Moto

Control

PWM

A/D 10-bit

500 Ksps

Quad

Enc

UART

SPI

CAN

dsPIC30F2010 28 12K/4K 512 1024 3 4 2 6 ch 6 ch Ye s 1 1 1 -

dsPIC30F3010 28 24K/8K 1024 1024 5 4 2 6 ch 6 ch Ye s 1 1 1 -

dsPIC30F4012 28 48K/16K 2048 1024 5 4 2 6 ch 6 ch Ye s 1 1 1 1

dsPIC30F3011 40/44 24K/8K 1024 1024 5 4 4 6 ch 9 ch Ye s 2 1 1 -

dsPIC30F4011 40/44 48K/16K 2048 1024 5 4 4 6 ch 9 ch Ye s 2 1 1 1

dsPIC30F5015 64 66K/22K 2048 1024 5 4 4 8 ch 16 ch Ye s 1 2 1 1

dsPIC30F6010 80 144K/48K 8192 4096 5 8 8 8 ch 16 ch Yes 2 2 1 2

* This table provides a summary of the dsPIC30F6010 peripheral features. Other available devices in the dsPIC30F

Motor Control and Power Conversion Family are shown for feature comparison.

DS70119B-page 2 Advance Information  2004 Microchip Technology Inc.

Pin Diagram

80-Pin TQFP

PWM2L/RE2

PWM1H/RE1

PWM2H/RE3

PWM3L/RE4

PWM1L/RE0

C2RX/RG0

C2TX/RG1

C1TX/RF1

C1RX/RF0

OC8/CN16/UPDN/RD7

OC6/CN14/RD5

VSS

OC7/CN15/RD6

dsPIC30F6010

IC5/RD12

OC4/RD3

OC5/CN13/RD4

IC6/CN19/RD13

OC3/RD2

EMUD2/OC2/RD1

PWM3H/RE5

PWM4L/RE6

PWM4H/RE7

T2CK/RC1 T4CK/RC3

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

SS2/CN11/RG9

VDD

FLTA/INT1/RE8

FLTB/INT2/RE9

AN5/QEB/CN7/RB5

AN4/QEA/CN6/RB4

AN3/INDX/CN5/RB3

/LVDIN/CN4/RB2

AN2/SS1

PGC/EMUC/AN1/CN3/RB1

PGD/EMUD/AN0/CN2/RB0

2324252627282930313233

AN7/RB7

VREF-/RA9

VREF+/RA10

AN6/OCFA/RB6

767877

AVSS

727473

7170696867666564636261

dsPIC30F6010

VSS

AN8/RB8

AN9/RB9

AN11/RB11

AN10/RB10

AN12/RB12

AN13/RB13

AN14/RB14

IC7/CN20/RD14

IC8/CN21/RD15

U2TX/CN18/RF5

U2RX/CN17/RF4

EMUC1/SOSCO/T1CK/CN0/RC14

EMUD1/SOSCI/CN1/RC13

EMUC2/OC1/RD0

IC4/RD11

IC3/RD10

IC2/RD9

IC1/RD8

INT4/RA15

INT3/RA14

OSC2/CLKO/RC15 OSC1/CLKI

SCL/RG2

SDA/RG3

EMUC3/SCK1/INT0/RF6

SDI1/RF7

EMUD3/SDO1/RF8

U1RX/RF2

U1TX/RF3

AN15/OCFB/CN12/RB15

Note: Pinout subject to change.

 2004 Microchip Technology Inc. Advance Information DS70119B-page 3

dsPIC30F6010

Table of Contents

1.0 Device Overview ...................................................................................................................................................................... 5

2.0 CPU Architecture Overview.................................................................................................................................................... 11

3.0 Memory Organization ............................................................................................................................................................. 19

4.0 Address Generator Units........................................................................................................................................................ 31

5.0 Interrupts ................................................................................................................................................................................ 37

6.0 Flash Program Memory.......................................................................................................................................................... 43

7.0 Data EEPROM Memory ......................................................................................................................................................... 49

8.0 I/O Ports ................................................................................................................................................................................. 53

9.0 Timer1 Module ....................................................................................................................................................................... 57

10.0 Timer2/3 Module .................................................................................................................................................................... 61

11.0 Timer4/5 Module .................................................................................................................................................................... 67

12.0 Input Capture Module............................................................................................................................................................. 71

13.0 Output Compare Module ........................................................................................................................................................ 75

14.0 Quadrature Encoder Interface (QEI) Module ......................................................................................................................... 79

15.0 Motor Control PWM Module ................................................................................................................................................... 85

16.0 SPI™ Module ......................................................................................................................................................................... 95

17.0 I2C Module ............................................................................................................................................................................. 99

18.0 Universal Asynchronous Receiver Transmitter (UART) Module .......................................................................................... 107

19.0 CAN Module ......................................................................................................................................................................... 115

20.0 10-bit High Speed Analog-to-Digital Converter (A/D) Module .............................................................................................. 127

21.0 System Integration ............................................................................................................................................................... 135

22.0 Instruction Set Summary ...................................................................................................................................................... 149

23.0 Development Support........................................................................................................................................................... 157

24.0 Electrical Characteristics ...................................................................................................................................................... 163

25.0 Packaging Information.......................................................................................................................................................... 207

On-Line Support................................................................................................................................................................................. 217

Systems Information and Upgrade Hot Line ...................................................................................................................................... 217

Reader Response .............................................................................................................................................................................. 218

Product Identification System............................................................................................................................................................. 219

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

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• Your local Microchip sales office (see last page)

• The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include

literature number) you are using.

Customer Notification System

DS70119B-page 4 Advance Information  2004 Microchip Technology Inc.

1.0 DEVICE OVERVIEW

This document contains device specific information for the dsPIC30F6010 device. The dsPIC30F devices contain extensive Digital Signal Processor (DSP) functionality within a high performance 16-bit microcontroller (MCU) architecture. Figure 1-1 shows a device block diagram for the dsPIC30F6010 device.

dsPIC30F6010

 2004 Microchip Technology Inc. Advance Information DS70119B-page 5

dsPIC30F6010

FIGURE 1-1: dsPIC30F6010 BLOCK DIAGRAM

Interrupt

Controller

Address Latch

Program Memory

(144 Kbytes)

Data EEPROM

(4 Kbytes)

Data Latch

Control Signals to Various Blocks

OSC1/CLKI

Generation

CAN1,

CAN2

SPI1, SPI2

Instruction

Decode &

Control

Timing

MCLR

VDD, VSS

AVDD, AVSS

PSV & Table Data Access

Control Block

Stack

Control

Start-up Timer

10-bit ADC

Timers

Y Data Bus

PCH PCL

PCU

Program Counter

Logic

Power-up

Oscillator

POR/BOR

Watchdog

Low Voltage

ROM Latch

Timer

Reset

Timer

Detect

Input

Capture

Module

Loop

Control

Logic

Decode

QEI

Y Data

(4 Kbytes)

Address

Y AGU

DSP

Engine

Output

Compare

Module

Motor Control

PWM

X Data Bus

Data LatchData Latch

X RAGU X WAGU

16 x 16

ALU<16>

X Data

(4 Kbytes)

Address

Latch

Divide

Unit

UART1,

UART2

RAM

Latch

Effective Address

W Reg Array

RAM

I2C

PORTA

PORTB

PORTC

PORTD

PORTE

VREF-/RA9 VREF+/RA10 INT3/RA14 INT4/RA15

AN0/CN2/RB0

AN1/CN3/RB1

AN2/SS1/LVDIN/CN4/RB2

AN3/INDX/CN5/RB3

AN4/QEA/CN6/RB4 AN5/QEB/CN7/RB5 PGC/EMUC/AN6/OCFA/RB6 PGD/EMUD/AN7/RB7 AN8/RB8

AN9/RB9

AN10/RB10 AN11/RB11 AN12/RB12 AN13/RB13 AN14/RB14 AN15/OCFB/CN12/RB15

T2CK/RC1 T4CK/RC3 EMUD1/SOSCI/CN1/RC13 EMUC1/SOSCO/T1CK/CN0/RC14 OSC2/CLKO/RC15

EMUC2/OC1/RD0 EMUD2/OC2/RD1 OC3/RD2 OC4/RD3 OC5/CN13/RD4 OC6/CN14/RD5 OC7/CN15/RD6 OC8/CN16/UPDN/RD7 IC1/RD8 IC2/RD9 IC3/RD10 IC4/RD11 IC5/RD12 IC6/CN19/RD13 IC7/CN20/RD14 IC8/CN21/RD15

PWM1L/RE0 PWM1H/RE1 PWM2L/RE2 PWM2H/RE3 PWM3L/RE4 PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 FLTA/INT1/RE8 FLTB/INT2/RE9

C2RX/RG0

C2TX/RG1

SCL/RG2

SDA/RG3

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

SS2

/CN11/RG9

PORTG PORTF

C1RX/RF0 C1TX/RF1 U1RX/RF2 U1TX/RF3 U2RX/CN17/RF4 U2TX/CN18/RF5 EMUC3/SCK1/INT0/RF6 SDI1/RF7 EMUD3/SDO1/RF8

DS70119B-page 6 Advance Information  2004 Microchip Technology Inc.

dsPIC30F6010

Table 1-1 provides a brief description of the device I/O pinout and the functions that are multiplexed to a port pin. Multiple functions may exist on one port pin. When

multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin.

TABLE 1-1: dsPIC30F6010 I/O PIN DESCRIPTIONS

Pin Name

AN0-AN15 I Analog Analog input channels.

DD P P Positive supply for analog module.

SS P P Ground reference for analog module.

CLKI CLKO

CN0-CN23 I ST Input change notification inputs.

COFS CSCK CSDI CSDO

C1RX C1TX C2RX C2TX

EMUD EMUC EMUD1 EMUC1 EMUD2 EMUC2 EMUD3 EMUC3

IC1-IC8 I ST Capture inputs 1 through 8.

INDX QEA

QEB

UPDN

INT0 INT1 INT2 INT3 INT4

LVDIN I Analog Low Voltage Detect Reference Voltage input pin.

Legend: CMOS = CMOS compatible input or output Analog = Analog input

Type

I/O I/O

I/O I/O I/O I/O I/O I/O I/O I/O

I I

I I I I I

ST = Schmitt Trigger input with CMOS levels O = Output I = Input P = Power

Buffer

Type

AN0 and AN1 are also used for device programming data and clock inputs, respectively.

ST/CMOS—External clock source input. Always associated with OSC1 pin function.

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function.

Can be software programmed for internal weak pull-ups on all inputs.

ST ST ST

—

ST ST ST ST ST ST ST ST

ST ST

CMOS

ST ST ST ST ST

Data Converter Interface frame synchronization pin. Data Converter Interface serial clock input/output pin. Data Converter Interface serial data input pin. Data Converter Interface serial data output pin.

CAN1 bus receive pin. CAN1 bus transmit pin. CAN2 bus receive pin. CAN2 bus transmit pin.

ICD Primary Communication Channel data input/output pin. ICD Primary Communication Channel clock input/output pin. ICD Secondary Communication Channel data input/output pin. ICD Secondary Communication Channel clock input/output pin. ICD Tertiary Communication Channel data input/output pin. ICD Tertiary Communication Channel clock input/output pin. ICD Quaternary Communication Channel data input/output pin. ICD Quaternary Communication Channel clock input/output pin.

Quadrature Encoder Index Pulse input. Quadrature Encoder Phase A input in QEI mode. Auxiliary Timer External Clock/Gate input in Timer mode. Quadrature Encoder Phase A input in QEI mode. Auxiliary Timer External Clock/Gate input in Timer mode. Position Up/Down Counter Direction State.

External interrupt 0. External interrupt 1. External interrupt 2. External interrupt 3. External interrupt 4.

Description

 2004 Microchip Technology Inc. Advance Information DS70119B-page 7

dsPIC30F6010

TABLE 1-1: dsPIC30F6010 I/O PIN DESCRIPTIONS (CONTINUED)

Pin Name

FLTA FLTB PWM1L PWM1H PWM2L PWM2H PWM3L PWM3H PWM4L PWM4H

MCLR

OCFA OCFB OC1-OC8

OSC1 OSC2

PGD PGC

RA9-RA10 RA14-RA15

RB0-RB15 I/O ST PORTB is a bi-directional I/O port.

RC1 RC3 RC13-RC15

RD0-RD15 I/O ST PORTD is a bi-directional I/O port.

RE0-RE9 I/O ST PORTE is a bi-directional I/O port.

RF0-RF8 I/O ST PORTF is a bi-directional I/O port.

RG0-RG3 RG6-RG9

SCK1 SDI1 SDO1 SS1 SCK2 SDI2 SDO2 SS2

SCL SDA

SOSCO SOSCI

Legend: CMOS = CMOS compatible input or output Analog = Analog input

Typ e

I O O O O O O O O

I/P ST Master Clear (Reset) input or programming voltage input. This pin is an active

I O

I/O

I/O I/O

I/O I/O I/O

I/O I/O

I/O

I O

I/O

I O

I/O I/O

ST = Schmitt Trigger input with CMOS levels O = Output I = Input P = Power

Buffer

Typ e

ST ST

— — — — — — — —

ST ST

—

ST/CMOS—Oscillator crystal input. ST buffer when configured in RC mode; CMOS

ST ST

ST ST ST

ST ST

— ST ST ST

— ST

ST ST

—

ST/CMOS

PWM Fault A input. PWM Fault B input. PWM 1 Low output. PWM 1 High output. PWM 2 Low output. PWM 2 High output. PWM 3 Low output. PWM 3 High output. PWM 4 Low output. PWM 4 High output.

low Reset to the device.

Compare Fault A input (for Compare channels 1, 2, 3 and 4). Compare Fault B input (for Compare channels 5, 6, 7 and 8). Compare outputs 1 through 8.

otherwise. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes.

In-Circuit Serial Programming data input/output pin. In-Circuit Serial Programming clock input pin.

PORTA is a bi-directional I/O port.

PORTC is a bi-directional I/O port.

PORTG is a bi-directional I/O port.

Synchronous serial clock input/output for SPI1. SPI1 Data In. SPI1 Data Out. SPI1 Slave Synchronization. Synchronous serial clock input/output for SPI2. SPI2 Data In. SPI2 Data Out. SPI2 Slave Synchronization.

Synchronous serial clock input/output for I Synchronous serial data input/output for I

32 kHz low power oscillator crystal output. 32 kHz low power oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise.

Description

DS70119B-page 8 Advance Information  2004 Microchip Technology Inc.

dsPIC30F6010

TABLE 1-1: dsPIC30F6010 I/O PIN DESCRIPTIONS (CONTINUED)

Pin Name

T1CK T2CK T3CK T4CK T5CK

U1RX U1TX U1ARX U1ATX U2RX U2TX

DD P — Positive supply for logic and I/O pins.

SS P — Ground reference for logic and I/O pins.

REF+ I Analog Analog Voltage Reference (High) input.

REF- I Analog Analog Voltage Reference (Low) input.

Legend: CMOS = CMOS compatible input or output Analog = Analog input

Type

I I I I I

ST = Schmitt Trigger input with CMOS levels O = Output I = Input P = Power

Buffer

Type

ST ST ST ST ST

—

Description

Timer1 external clock input. Timer2 external clock input. Timer3 external clock input. Timer4 external clock input. Timer5 external clock input.

UART1 Receive. UART1 Transmit. UART1 Alternate Receive. UART1 Alternate Transmit. UART2 Receive. UART2 Transmit.

 2004 Microchip Technology Inc. Advance Information DS70119B-page 9

dsPIC30F6010

NOTES:

DS70119B-page 10 Advance Information  2004 Microchip Technology Inc.

dsPIC30F6010

2.0 CPU ARCHITECTURE OVERVIEW

This document provides a summary of the dsPIC30F6010 CPU and peripheral function. For a complete description of this functionality, please refer to the dsPIC30F Family Reference Manual (DS70046).

2.1 Core Overview

The core has a 24-bit instruction word. The Program Counter (PC) is 23 bits wide with the Least Significant (LS) bit always clear (see Section 3.1), and the Most Significant (MS) bit is ignored during normal program execution, except for certain specialized instructions. Thus, the PC can address up to 4M instruction words of user program space. An instruction pre-fetch mechanism is used to help maintain throughput. Program loop constructs, free from loop count management overhead, are supported using the DO and REPEAT instructions, both of which are interruptible at any point.

The working register array consists of 16x16-bit registers, each of which can act as data, address or offset registers. One working register (W15) operates as a software stack pointer for interrupts and calls.

The data space is 64 Kbytes (32K words) and is split into two blocks, referred to as X and Y data memory. Each block has its own independent Address Generation Unit (AGU). Most instructions operate solely through the X memory AGU, which provides the appearance of a single unified data space. The Multiply-Accumulate (MAC) class of dual source DSP instructions operate through both the X and Y AGUs, splitting the data address space into two parts (see Section 3.2). The X and Y data space boundary is device specific and cannot be altered by the user. Each data word consists of 2 bytes, and most instructions can address data either as words or bytes.

There are two methods of accessing data stored in program memory:

• The upper 32 Kbytes of data space memory can

be mapped into the lower half (user space) of program space at any 16K program word boundary, defined by the 8-bit Program Space Visibility Page (PSVPAG) register. This lets any instruction access program space as if it were data space, with a limitation that the access requires an additional cycle. Moreover, only the lower 16 bits of each instruction word can be accessed using this method.

• Linear indirect access of 32K word pages within

program space is also possible using any working register, via table read and write instructions. Table read and write instructions can be used to access all 24 bits of an instruction word.

Overhead-free circular buffers (modulo addressing) are supported in both X and Y address spaces. This is primarily intended to remove the loop overhead for DSP algorithms.

The X AGU also supports bit-reversed addressing on destination effective addresses, to greatly simplify input or output data reordering for radix-2 FFT algorithms. Refer to Section 4.0 for details on modulo and bit-reversed addressing.

The core supports Inherent (no operand), Relative, Literal, Memory Direct, Register Direct, Register Indirect, Register Offset and Literal Offset Addressing modes. Instructions are associated with predefined Addressing modes, depending upon their functional requirements.

For most instructions, the core is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, 3-operand instructions are supported, allowing C = A+B operations to be executed in a single cycle.

A DSP engine has been included to significantly enhance the core arithmetic capability and throughput. It features a high speed 17-bit by 17-bit multiplier, a 40-bit ALU, two 40-bit saturating accumulators and a 40-bit bi-directional barrel shifter. Data in the accumulator or any working register can be shifted up to 16 bits right or 16 bits left in a single cycle. The DSP instructions operate seamlessly with all other instructions and have been designed for optimal real-time performance. The MAC class of instructions can concurrently fetch two data operands from memory, while multiplying two W registers. To enable this concurrent fetching of data operands, the data space has been split for these instructions and linear for all others. This has been achieved in a transparent and flexible manner, by dedicating certain working registers to each address space for the MAC class of instructions.

The core does not support a multi-stage instruction pipeline. However, a single stage instruction pre-fetch mechanism is used, which accesses and partially decodes instructions a cycle ahead of execution, in order to maximize available execution time. Most instructions execute in a single cycle, with certain exceptions.

The core features a vectored exception processing structure for traps and interrupts, with 62 independent vectors. The exceptions consist of up to 8 traps (of which 4 are reserved) and 54 interrupts. Each interrupt is prioritized based on a user assigned priority between 1 and 7 (1 being the lowest priority and 7 being the highest) in conjunction with a predetermined ‘natural order’. Traps have fixed priorities, ranging from 8 to 15.

 2004 Microchip Technology Inc. Advance Information DS70119B-page 11

dsPIC30F6010

2.2 Programmer’s Model

The programmer’s model is shown in Figure 2-1 and consists of 16x16-bit working registers (W0 through W15), 2x40-bit accumulators (AccA and AccB), STATUS register (SR), Data Table Page register (TBLPAG), Program Space Visibility Page register (PSVPAG), DO and REPEAT registers (DOSTART, DOEND, DCOUNT and RCOUNT), and Program Counter (PC). The working registers can act as data, address or offset registers. All registers are memory mapped. W0 acts as the W register for file register addressing.

Some of these registers have a shadow register associated with each of them, as shown in Figure 2-1. The shadow register is used as a temporary holding register and can transfer its contents to or from its host register upon the occurrence of an event. None of the shadow registers are accessible directly. The following rules apply for transfer of registers into and out of shadows.

• PUSH.S and POP.S

W0, W1, W2, W3, SR (DC, N, OV, Z and C bits only) are transferred.

• DO instruction

DOSTART, DOEND, DCOUNT shadows are pushed on loop start, and popped on loop end.

When a byte operation is performed on a working register, only the Least Significant Byte of the target register is affected. However, a benefit of memory mapped working registers is that both the Least and Most Significant Bytes can be manipulated through byte wide data memory space accesses.

2.2.1 SOFTWARE STACK POINTER/ FRAME POINTER

The dsPIC® devices contain a software stack. W15 is the dedicated software stack pointer (SP), and will be automatically modified by exception processing and subroutine calls and returns. However, W15 can be referenced by any instruction in the same manner as all other W registers. This simplifies the reading, writing and manipulation of the stack pointer (e.g., creating stack frames).

Note: In order to protect against misaligned

stack accesses, W15<0> is always clear.

W15 is initialized to 0x0800 during a Reset. The user may reprogram the SP during initialization to any location within data space.

W14 has been dedicated as a stack frame pointer as defined by the LNK and ULNK instructions. However, W14 can be referenced by any instruction in the same manner as all other W registers.

2.2.2 STATUS REGISTER

The dsPIC core has a 16-bit Status Register (SR), the LS Byte of which is referred to as the SR Low Byte (SRL) and the MS Byte as the SR High Byte (SRH). See Figure 2-1 for SR layout.

SRL contains all the MCU ALU operation status flags (including the Z bit), as well as the CPU Interrupt Priority Level status bits, IPL<2:0>, and the REPEAT active status bit, RA. During exception processing, SRL is concatenated with the MS Byte of the PC to form a complete word value which is then stacked.

The upper byte of the SR register contains the DSP Adder/Subtractor status bits, the DO Loop Active bit (DA) and the Digit Carry (DC) status bit.

2.2.3 PROGRAM COUNTER

The Program Counter is 23 bits wide. Bit 0 is always clear. Therefore, the PC can address up to 4M instruction words.

DS70119B-page 12 Advance Information  2004 Microchip Technology Inc.

FIGURE 2-1: dsPIC30F6010 PROGRAMMER’S MODEL

W0/WREG

DSP Operand Registers

DSP Address Registers

W13/DSP Write Back

W10

W11

W12/DSP Offset

W14/Frame Pointer

W15/Stack Pointer

dsPIC30F6010

D0D15

PUSH.S Shadow

DO Shadow

Legend

Working Registers

DSP Accumulators

PC22

TABPAG

TBLPAG

PSVPAG

AD39 AD0AD31

AccA

AccB

Data Table Page Address

DOSTART

SPLIM

PC0

Program Space Visibility Page Address

RCOUNT

DCOUNT

DOEND

Stack Pointer Limit Register

AD15

Program Counter

REPEAT Loop Counter

DO Loop Counter

DO Loop Start Address

DO Loop End Address

CORCON

OA OB SA SB

 2004 Microchip Technology Inc. Advance Information DS70119B-page 13

OAB SAB

SRH

DA DC

IPL2 IPL1

IPL0 OV

SRL

Core Configuration Register

Status Register

dsPIC30F6010

2.3 Divide Support

The dsPIC devices feature a 16/16-bit signed fractional divide operation, as well as 32/16-bit and 16/16-bit signed and unsigned integer divide operations, in the form of single instruction iterative divides. The following instructions and data sizes are supported:

1. DIVF – 16/16 signed fractional divide

2. DIV.sd – 32/16 signed divide

3. DIV.ud – 32/16 unsigned divide

4. DIV.sw – 16/16 signed divide

5. DIV.uw – 16/16 unsigned divide

The divide instructions must be executed within a REPEAT loop. Any other form of execution (e.g. a series of discrete divide instructions) will not function correctly because the instruction flow depends on RCOUNT. The divide instruction does not automatically set up the RCOUNT value, and it must, therefore, be explicitly and correctly specified in the REPEAT instruction, as shown in Table 2-1 (REPEAT will execute the target instruction {operand value+1} times). The REPEAT loop count must be set up for 18 iterations of the DIV/DIVF instruction. Thus, a complete divide operation requires 19 cycles.

Note: The Divide flow is interruptible. However,

the user needs to save the context as appropriate.

TABLE 2-1: DIVIDE INSTRUCTIONS

Instruction Function

DIVF Signed fractional divide: Wm/Wn → W0; Rem → W1

DIV.sd Signed divide: (Wm+1:Wm)/Wn → W0; Rem → W1

DIV.sw (or DIV.s) Signed divide: Wm/Wn → W0; Rem → W1

DIV.ud Unsigned divide: (Wm+1:Wm)/Wn → W0; Rem → W1

DIV.uw (or DIV.u) Unsigned divide: Wm/Wn → W0; Rem → W1

2.4 DSP Engine

The DSP engine consists of a high speed 17-bit x 17-bit multiplier, a barrel shifter, and a 40-bit adder/ Subtractor (with two target accumulators, round and saturation logic).

The dsPIC30F devices have a single instruction flow which can execute either DSP or MCU instructions. Many of the hardware resources are shared between the DSP and MCU instructions. For example, the instruction set has both DSP and MCU Multiply instructions which use the same hardware multiplier.

The DSP engine also has the capability to perform inherent accumulator-to-accumulator operations, which require no additional data. These instructions are ADD, SUB and NEG.

The DSP engine has various options selected through various bits in the CPU Core Configuration Register (CORCON), as listed below:

1. Fractional or integer DSP multiply (IF).

2. Signed or unsigned DSP multiply (US).

3. Conventional or convergent rounding (RND).

4. Automatic saturation on/off for AccA (SATA).

5. Automatic saturation on/off for AccB (SATB).

6. Automatic saturation on/off for writes to data memory (SATDW).

7. Accumulator Saturation mode selection (ACCSAT).

Note: For CORCON layout, see Table 4-2.

A block diagram of the DSP engine is shown in Figure 2-2.

TABLE 2-2: DSP INSTRUCTION

SUMMARY

Instruction Algebraic Operation

CLR A = 0

ED A = (x – y)

EDAC A = A + (x – y)

MAC A = A + (x * y)

MOVSAC No change in A

MPY A = x * y

MPY.N A = – x * y

MSC A = A – x * y

DS70119B-page 14 Advance Information  2004 Microchip Technology Inc.

FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM

Carry/Borrow Out

Carry/Borrow In

40-bit Accumulator A 40-bit Accumulator B

Saturate

Adder

Negate

dsPIC30F6010

S a

Round

Logic

Y Data Bus

Sign-Extend

17-bit

Multiplier/Scaler

Barrel Shifter

X Data Bus

Zero Backfill

To/From W Array

 2004 Microchip Technology Inc. Advance Information DS70119B-page 15

dsPIC30F6010

2.4.1 MULTIPLIER

The 17x17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value. The output of the 17x17-bit multiplier/ scaler is a 33-bit value, which is sign-extended to 40 bits. Integer data is inherently represented as a signed two’s complement value, where the MSB is defined as a sign bit. Generally speaking, the range of an N-bit two’s complement integer is -2 16-bit integer, the data range is -32768 (0x8000) to 32767 (0x7FFF), including 0. For a 32-bit integer, the data range is -2,147,483,648 (0x8000 0000) to 2,147,483,645 (0x7FFF FFFF).

When the multiplier is configured for fractional multiplication, the data is represented as a two’s complement fraction, where the MSB is defined as a sign bit and the radix point is implied to lie just after the sign bit (QX format). The range of an N-bit two’s complement fraction with this implied radix point is -1.0 to (1-2 For a 16-bit fraction, the Q15 data range is -1.0 (0x8000) to 0.999969482 (0x7FFF), including 0 and has a precision of 3.01518x10 16x16 multiply operation generates a 1.31 product, which has a precision of 4.65661x10

The same multiplier is used to support the MCU multiply instructions, which include integer 16-bit signed, unsigned and mixed sign multiplies.

The MUL instruction may be directed to use byte or word sized operands. Byte operands will direct a 16-bit result, and word operands will direct a 32-bit result to the specified register(s) in the W array.

N-1

-5

N-1

to 2

. In fractional mode, a

-10

– 1. For a

1-N

2.4.2 DATA ACCUMULATORS AND

ADDER/SUBTRACTOR

The data accumulator consists of a 40-bit adder/ subtractor with automatic sign extension logic. It can select one of two accumulators (A or B) as its preaccumulation source and post-accumulation destination. For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled via the barrel shifter, prior to accumulation.

2.4.2.1 Adder/Subtractor, Overflow and Saturation

The adder/subtractor is a 40-bit adder with an optional zero input into one side and either true or complement data into the other input. In the case of addition, the carry/borrow true data (not complemented), whereas in the case of subtraction, the carry/borrow other input is complemented. The adder/subtractor generates overflow status bits SA/SB and OA/OB, which are latched and reflected in the status register.

• Overflow from bit 39: this is a catastrophic

overflow in which the sign of the accumulator is destroyed.

• Overflow into guard bits 32 through 39: this is a

recoverable overflow. This bit is set whenever all the guard bits are not identical to each other.

The adder has an additional saturation block which controls accumulator data saturation, if selected. It uses the result of the adder, the overflow status bits described above, and the SATA/B (CORCON<7:6>)

and ACCSAT (CORCON<4>) mode control bits to determine when and to what value to saturate.

Six status register bits have been provided to support saturation and overflow; they are:

1. OA:

AccA overflowed into guard bits

2. OB:

AccB overflowed into guard bits

3. SA:

AccA saturated (bit 31 overflow and saturation)

AccA overflowed into guard bits and saturated (bit 39 overflow and saturation)

4. SB:

AccB saturated (bit 31 overflow and saturation)

AccB overflowed into guard bits and saturated (bit 39 overflow and saturation)

5. OAB:

Logical OR of OA and OB

6. SAB:

Logical OR of SA and SB

The OA and OB bits are modified each time data passes through the adder/Subtractor. When set, they indicate that the most recent operation has overflowed into the accumulator guard bits (bits 32 through 39). The OA and OB bits can also optionally generate an arithmetic warning trap when set and the corresponding overflow trap flag enable bit (OVATEN, OVBTEN) in the INTCON1 register (refer to Section 5.0) is set. This allows the user to take immediate action, for example, to correct system gain.

input is active high and the other input is

input is active low and the

DS70119B-page 16 Advance Information  2004 Microchip Technology Inc.

dsPIC30F6010

The SA and SB bits are modified each time data passes through the adder/subtractor, but can only be cleared by the user. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation, or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled). When saturation is not enabled, SA and SB default to bit 39 overflow and thus indicate that a catastrophic overflow has occurred. If the COVTE bit in the INTCON1 register is set, SA and SB bits will generate an arithmetic warning trap when saturation is disabled.

The overflow and saturation status bits can optionally be viewed in the Status Register (SR) as the logical OR of OA and OB (in bit OAB) and the logical OR of SA and SB (in bit SAB). This allows programmers to check one bit in the Status Register to determine if either accumulator has overflowed, or one bit to determine if either accumulator has saturated. This would be useful for complex number arithmetic which typically uses both the accumulators.

The device supports three Saturation and Overflow modes.

1. Bit 39 Overflow and Saturation: When bit 39 overflow and saturation occurs, the saturation logic loads the maximally positive 9.31 (0x7FFFFFFFFF) or maximally negative 9.31 value (0x8000000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user. This is referred to as ‘super saturation’ and provides protection against erroneous data or unexpected algorithm problems (e.g., gain calculations).

2. Bit 31 Overflow and Saturation: When bit 31 overflow and saturation occurs, the saturation logic then loads the maximally positive 1.31 value (0x007FFFFFFF) or maximally negative 1.31 value (0x0080000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user. When this Saturation mode is in effect, the guard bits are not used (so the OA, OB or OAB bits are never set).

3. Bit 39 Catastrophic Overflow The bit 39 overflow status bit from the adder is used to set the SA or SB bit, which remain set until cleared by the user. No saturation operation is performed and the accumulator is allowed to overflow (destroying its sign). If the COVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap exception.

2.4.2.2 Accumulator ‘Write Back’

The MAC class of instructions (with the exception of MPY, MPY.N, ED and EDAC) can optionally write a

rounded version of the high word (bits 31 through 16) of the accumulator that is not targeted by the instruction into data space memory. The write is performed across the X bus into combined X and Y address space. The following addressing modes are supported:

1. W13, Register Direct: The rounded contents of the non-target accumulator are written into W13 as a 1.15 fraction.

2. [W13]+=2, Register Indirect with Post-Increment: The rounded contents of the non-target accumulator are written into the address pointed to by W13 as a 1.15 fraction. W13 is then incremented by 2 (for a word write).

2.4.2.3 Round Logic

The round logic is a combinational block, which performs a conventional (biased) or convergent (unbiased) round function during an accumulator write (store). The Round mode is determined by the state of the RND bit in the CORCON register. It generates a 16-bit, 1.15 data value which is passed to the data space write saturation logic. If rounding is not indicated by the instruction, a truncated 1.15 data value is stored and the LS Word is simply discarded.

Conventional rounding takes bit 15 of the accumulator, zero-extends it and adds it to the ACCxH word (bits 16 through 31 of the accumulator). If the ACCxL word (bits 0 through 15 of the accumulator) is between 0x8000 and 0xFFFF (0x8000 included), ACCxH is incremented. If ACCxL is between 0x0000 and 0x7FFF, ACCxH is left unchanged. A consequence of this algorithm is that over a succession of random rounding operations, the value will tend to be biased slightly positive.

Convergent (or unbiased) rounding operates in the same manner as conventional rounding, except when ACCxL equals 0x8000. If this is the case, the LS bit (bit 16 of the accumulator) of ACCxH is examined. If it is ‘1’, ACCxH is incremented. If it is ‘0’, ACCxH is not modified. Assuming that bit 16 is effectively random in nature, this scheme will remove any rounding bias that may accumulate.

The SAC and SAC.R instructions store either a truncated (SAC) or rounded (SAC.R) version of the contents of the target accumulator to data memory, via the X bus (subject to data saturation, see Section 2.4.2.4). Note that for the MAC class of instructions, the accumulator write back operation will function in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding.

 2004 Microchip Technology Inc. Advance Information DS70119B-page 17

dsPIC30F6010

2.4.2.4 Data Space Write Saturation

In addition to adder/subtractor saturation, writes to data space may also be saturated, but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder. These are combined and used to select the appropriate 1.15 fractional value as output to write to data space memory.

If the SATDW bit in the CORCON register is set, data (after rounding or truncation) is tested for overflow and adjusted accordingly. For input data greater than 0x007FFF, data written to memory is forced to the maximum positive 1.15 value, 0x7FFF. For input data less than 0xFF8000, data written to memory is forced to the maximum negative 1.15 value, 0x8000. The MS bit of the source (bit 39) is used to determine the sign of the operand being tested.

If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions.

2.4.3 BARREL SHIFTER

The barrel shifter is capable of performing up to 16-bit arithmetic or logic right shifts, or up to 16-bit left shifts in a single cycle. The source can be either of the two DSP accumulators or the X bus (to support multi-bit shifts of register or memory data).

The shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. A positive value will shift the operand right. A negative value will shift the operand left. A value of 0 will not modify the operand.

The barrel shifter is 40 bits wide, thereby obtaining a 40-bit result for DSP shift operations and a 16-bit result for MCU shift operations. Data from the X bus is presented to the barrel shifter between bit positions 16 to 31 for right shifts, and bit positions 0 to 15 for left shifts.

DS70119B-page 18 Advance Information  2004 Microchip Technology Inc.

dsPIC30F6010

3.0 MEMORY ORGANIZATION

3.1 Program Address Space

The program address space is 4M instruction words. It is addressable by the 23-bit PC, table instruction Effective Address (EA), or data space EA, when program space is mapped into data space, as defined by Table 3-1. Note that the program space address is incremented by two between successive program words, in order to provide compatibility with data space addressing.

User program space access is restricted to the lower 4M instruction word address range (0x000000 to 0x7FFFFE), for all accesses other than TBLRD/TBLWT, which use TBLPAG<7> to determine user or configuration space access. In Table 3-1, Read/Write instructions, bit 23 allows access to the Device ID, the User ID and the configuration bits. Otherwise, bit 23 is always clear.

FIGURE 3-1:

Space

User Memory

PROGRAM SPACE MEMORY MAP FOR dsPIC30F6010

Reset - GOTO Instruction

Reset - Target Address

Interrupt Vector Table

Reserved

Alternate Vector Table

User Flash Program Memory (48K instructions)

Reserved

(Read 0’s)

Data EEPROM

(4 Kbytes)

000000 000002 000004

Vector Tables

00007E 000080 000084 0000FE 000100

017FFE 018000

7FEFFE 7FF000

7FFFFE 800000

Space

Configuration Memory

UNITID (32 instr.)

Device Configuration

Reserved

Registers

Reserved

DEVID (2)

8005BE 8005C0

8005FE 800600

F7FFFE F80000

F8000E F80010

FEFFFE FF0000 FFFFFE

 2004 Microchip Technology Inc. Advance Information DS70119B-page 19

dsPIC30F6010

TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION

Access Type

Access

Space

<23> <22:16> <15> <14:1> <0>

Instruction Access User 0 PC<22:1> 0 TBLRD/TBLWT User

TBLPAG<7:0> Data EA <15:0>

(TBLPAG<7> = 0)

TBLRD/TBLWT Configuration

TBLPAG<7:0> Data EA <15:0>

(TBLPAG<7> = 1)

Program Space Visibility User 0 PSVPAG<7:0> Data EA <14:0>

FIGURE 3-2: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

23 bits

Using Program Counter

Program Space Address

0Program Counter

Select

Using Program Space Visibility

Using Table Instruction

Note: Program Space Visibility cannot be used to access bits <23:16> of a word in program memory.

1/0

User/ Configuration

Spac e Select

PSVPAG Reg

8 bits

TBLPAG Reg

8 bits

24-bit EA

15 bits

16 bits

Byte

Select

DS70119B-page 20 Advance Information  2004 Microchip Technology Inc.

dsPIC30F6010

3.1.1 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS

This architecture fetches 24-bit wide program memory. Consequently, instructions are always aligned. However, as the architecture is modified Harvard, data can also be present in program space.

There are two methods by which program space can be accessed; via special table instructions, or through the remapping of a 16K word program space page into the upper half of data space (see Section 3.1.2). The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the LS Word of any address within program space, without going through data space. The TBLRDH and TBLWTH instructions are the only method whereby the upper 8 bits of a program space word can be accessed as data.

The PC is incremented by two for each successive 24-bit program word. This allows program memory addresses to directly map to data space addresses. Program memory can thus be regarded as two 16-bit word wide address spaces, residing side by side, each with the same address range. TBLRDL and TBLWTL access the space which contains the LS Data Word, and TBLRDH and TBLWTH access the space which contains the MS Data Byte.

Figure 3-2 shows how the EA is created for table operations and data space accesses (PSV = 1). Here, P<23:0> refers to a program space word, whereas D<15:0> refers to a data space word.

A set of Table Instructions are provided to move byte or word sized data to and from program space.

1. TBLRDL: Table Read Low Word: Read the LS Word of the program address; P<15:0> maps to D<15:0>. Byte: Read one of the LS Bytes of the program address; P<7:0> maps to the destination byte when byte select = 0; P<15:8> maps to the destination byte when byte select = 1.

2. TBLWTL: Table Write Low (refer to Section 6.0 for details on Flash Programming).

3. TBLRDH: Table Read High Word: Read the MS Word of the program address; P<23:16> maps to D<7:0>; D<15:8> always be = 0. Byte: Read one of the MS Bytes of the program address; P<23:16> maps to the destination byte when byte select = 0; The destination byte will always be = 0 when byte select = 1.

4. TBLWTH: Table Write High (refer to Section 6.0 for details on Flash Programming).

FIGURE 3-3: PROGRAM DATA TABLE ACCESS (LS WORD)

PC Address

0x000000 0x000002

0x000004 0x000006

Program Memory ‘Phantom’ Byte (Read as ‘0’).

00000000

TBLRDL.W

TBLRDL.B (Wn<0> = 1)

TBLRDL.B (Wn<0> = 0)

 2004 Microchip Technology Inc. Advance Information DS70119B-page 21

dsPIC30F6010

FIGURE 3-4: PROGRAM DATA TABLE ACCESS (MS BYTE)

TBLRDH.W

PC Address

0x000000 0x000002

0x000004 0x000006

Program Memory ‘Phantom’ Byte (Read as ‘0’)

00000000

TBLRDH.B (Wn<0> = 1)

3.1.2 DATA ACCESS FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY

The upper 32 Kbytes of data space may optionally be mapped into any 16K word program space page. This provides transparent access of stored constant data from X data space, without the need to use special instructions (i.e., TBLRDL/H, TBLWTL/H instructions).

Program space access through the data space occurs if the MS bit of the data space EA is set and program space visibility is enabled, by setting the PSV bit in the Core Control register (CORCON). The functions of CORCON are discussed in Section 2.4, DSP Engine.

Data accesses to this area add an additional cycle to the instruction being executed, since two program memory fetches are required.

Note that the upper half of addressable data space is always part of the X data space. Therefore, when a DSP operation uses program space mapping to access this memory region, Y data space should typically contain state (variable) data for DSP operations, whereas X data space should typically contain coefficient (constant) data.

Although each data space address, 0x8000 and higher, maps directly into a corresponding program memory address (see Figure 3-5), only the lower 16-bits of the 24-bit program word are used to contain the data. The upper 8 bits should be programmed to force an illegal instruction to maintain machine robustness. Refer to the dsPIC30F Programmer’s Reference Manual (DS70030) for details on instruction encoding.

TBLRDH.B (Wn<0> = 0)

Note that by incrementing the PC by 2 for each program memory word, the LS 15 bits of data space addresses directly map to the LS 15 bits in the corresponding program space addresses. The remaining bits are provided by the Program Space Visibility Page register, PSVPAG<7:0>, as shown in Figure 3-5.

Note: PSV access is temporarily disabled during

Table Reads/Writes.

For instructions that use PSV which are executed outside a REPEAT loop:

• The following instructions will require one instruction cycle in addition to the specified execution time:

- MAC class of instructions with data operand

pre-fetch

- MOV instructions

- MOV.D instructions

• All other instructions will require two instruction cycles in addition to the specified execution time of the instruction.

For instructions that use PSV which are executed inside a REPEAT loop:

• The following instances will require two instruction cycles in addition to the specified execution time of the instruction:

- Execution in the first iteration

- Execution in the last iteration

- Execution prior to exiting the loop due to an

interrupt

- Execution upon re-entering the loop after an

interrupt is serviced

• Any other iteration of the REPEAT loop will allow the instruction, accessing data using PSV, to execute in a single cycle.

DS70119B-page 22 Advance Information  2004 Microchip Technology Inc.

dsPIC30F6010

FIGURE 3-5: DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION

Program Space

Data Space

0x0000

EA<15> =

Data

Space

BSET CORCON,#2 ; PSV bit set MOV #0x21, W0 ; Set PSVPAG register MOV W0, PSVPAG MOV 0x8200, W0 ; Access program memory location

Note: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address

EA<15> = 1

Upper half of Data Space is mapped into Program Space

(i.e., it defines the page in program space to which the upper half of data space is being mapped).

; using a data space access

0x8000

0xFFFF

PSVPAG

Address Concatenation

(1)

0x21

23 15 0

Data Read

0x108000

0x108200

0x10FFFF

3.2 Data Address Space

The core has two data spaces. The data spaces can be considered either separate (for some DSP instructions), or as one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths.

3.2.1 DATA SPACE MEMORY MAP

The data space memory is split into two blocks, X and Y data space. A key element of this architecture is that Y space is a subset of X space, and is fully contained within X space. In order to provide an apparent linear addressing space, X and Y spaces have contiguous addresses.

 2004 Microchip Technology Inc. Advance Information DS70119B-page 23

When executing any instruction other than one of the MAC class of instructions, the X block consists of the 64 Kbyte data address space (including all Y addresses). When executing one of the MAC class of instructions, the X block consists of the 64 Kbyte data address space excluding the Y address block (for data reads only). In other words, all other instructions regard the entire data memory as one composite address space. The MAC class instructions extract the Y address space from data space and address it using EAs sourced from W10 and W11. The remaining X data space is addressed using W8 and W9. Both address spaces are concurrently accessed only with the MAC class instructions.

A data space memory map is shown in Figure 3-6.

Figure 3-7 shows a graphical summary of how X and Y data spaces are accessed for MCU and DSP instructions.

dsPIC30F6010

FIGURE 3-6: dsPIC30F6010 DATA SPACE MEMORY MAP

2 Kbyte SFR Space

8 Kbyte

SRAM Space

MS Byte

Address

0x0001

0x07FF

0x0801

0x17FF

0x1801

0x27FF 0x27FE

0x8001

16 bits

LSBMSB

SFR Space

X Data RAM (X)

Y Data RAM (Y)

0x0000

0x07FE 0x0800

0x17FE 0x1800

0x1FFE0x1FFF

0x28000x2801

0x8000

LS Byte Address

8 Kbyte Near

Data Space

Optionally Mapped into Program Memory

0xFFFF

X Data

Unimplemented (X)

0xFFFE

DS70119B-page 24 Advance Information  2004 Microchip Technology Inc.

dsPIC30F6010

FIGURE 3-7: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE

SFR SPACE

UNUSED

(Y SPACE)

X SPACE

Non-MAC Class Ops (Read/Write) MAC Class Ops Read Only

MAC Class Ops (Write)

Indirect EA using any W Indirect EA using W8, W9 Indirect EA using W10, W11

Y SPACE

UNUSED

SFR SPACE

UNUSED

X SPACE

 2004 Microchip Technology Inc. Advance Information DS70119B-page 25

dsPIC30F6010

3.2.2 DATA SPACES

The X data space is used by all instructions and supports all addressing modes. There are separate read and write data buses. The X read data bus is the return data path for all instructions that view data space as combined X and Y address space. It is also the X address space data path for the dual operand read instructions (MAC class). The X write data bus is the only write path to data space for all instructions.

The X data space also supports Modulo Addressing for all instructions, subject to Addressing mode restrictions. Bit-Reversed Addressing is only supported for writes to X data space.

The Y data space is used in concert with the X data space by the MAC class of instructions (CLR, ED, EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide two concurrent data read paths. No writes occur across the Y bus. This class of instructions dedicates two W register pointers, W10 and W11, to always address Y data space, independent of X data space, whereas W8 and W9 always address X data space. Note that during accumulator write back, the data address space is considered a combination of X and Y data spaces, so the write occurs across the X bus. Consequently, the write can be to any address in the entire data space.

The Y data space can only be used for the data prefetch operation associated with the MAC class of instructions. It also supports Modulo Addressing for automated circular buffers. Of course, all other instructions can access the Y data address space through the X data path, as part of the composite linear space.

The boundary between the X and Y data spaces is defined as shown in Figure 3-6 and is not user programmable. Should an EA point to data outside its own assigned address space, or to a location outside physical memory, an all-zero word/byte will be returned. For example, although Y address space is visible by all non-MAC instructions using any Addressing mode, an attempt by a MAC instruction to fetch data from that space, using W8 or W9 (X space pointers), will return 0x0000.

3.2.3 DATA SPACE WIDTH

The core data width is 16-bits. All internal registers are organized as 16-bit wide words. Data space memory is organized in byte addressable, 16-bit wide blocks.

3.2.4 DATA ALIGNMENT

To help maintain backward compatibility with PICmicro usage efficiency, the dsPIC30F instruction set supports both word and byte operations. Data is aligned in data memory and registers as words, but all data space EAs resolve to bytes. Data byte reads will read the complete word, which contains the byte, using the LS bit of any EA to determine which byte to select. The selected byte is placed onto the LS Byte of the X data path (no byte accesses are possible from the Y data path as the MAC class of instruction can only fetch words). That is, data memory and registers are organized as two parallel byte wide entities with shared (word) address decode, but separate write lines. Data byte writes only write to the corresponding side of the array or register which matches the byte address.

As a consequence of this byte accessibility, all effective address calculations (including those generated by the DSP operations, which are restricted to word sized data) are internally scaled to step through word aligned memory. For example, the core would recognize that Post-Modified Register Indirect Addressing mode, [Ws++], will result in a value of Ws+1 for byte operations and Ws+2 for word operations.

All word accesses must be aligned to an even address. Mis-aligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. Should a misaligned read or write be attempted, an Address Error trap will be generated. If the error occurred on a read, the instruction underway is completed, whereas if it occurred on a write, the instruction will be executed but the write will not occur. In either case, a trap will then be executed, allowing the system and/or user to examine the machine state prior to execution of the address fault.

devices and improve data space memory

TABLE 3-2: EFFECT OF INVALID

MEMORY ACCESSES

Attempted Operation Data Returned

EA = an unimplemented address 0x0000

W8 or W9 used to access Y data space in a MAC instruction

W10 or W11 used to access X data space in a MAC instruction

All effective addresses are 16 bits wide and point to bytes within the data space. Therefore, the data space address range is 64 Kbytes or 32K words.

DS70119B-page 26 Advance Information  2004 Microchip Technology Inc.

0x0000

FIGURE 3-8: DATA ALIGNMENT

15 8 7 0

0001

0003

0005

Byte 1 Byte 0

Byte 3 Byte 2

Byte 5 Byte 4

LS ByteMS Byte

0000

0002

0004

dsPIC30F6010

All byte loads into any W register are loaded into the LS Byte. The MSB is not modified.

A sign-extend (SE) instruction is provided to allow users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, users can clear the MSB of any W register by executing a zero-extend (ZE) instruction on the appropriate address.

Although most instructions are capable of operating on word or byte data sizes, it should be noted that some instructions, including the DSP instructions, operate only on words.

3.2.5 NEAR DATA SPACE

An 8 Kbyte ‘near’ data space is reserved in X address memory space between 0x0000 and 0x1FFF, which is directly addressable via a 13-bit absolute address field within all memory direct instructions. The remaining X address space and all of the Y address space is addressable indirectly. Additionally, the whole of X data space is addressable using MOV instructions, which support memory direct addressing with a 16-bit address field.

3.2.6 SOFTWARE STACK

The dsPIC device contains a software stack. W15 is used as the Stack Pointer.

The stack pointer always points to the first available free word and grows from lower addresses towards higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as shown in Figure 3-9. Note that for a PC push during any CALL instruction, the MSB of the PC is zero-extended before the push, ensuring that the MSB is always clear.

Note: A PC push during exception processing

will concatenate the SRL register to the MSB of the PC prior to the push.

There is a Stack Pointer Limit register (SPLIM) associated with the stack pointer. SPLIM is uninitialized at Reset. As is the case for the stack pointer, SPLIM<0> is forced to ‘0’, because all stack operations must be word aligned. Whenever an effective address (EA) is generated using W15 as a source or destination pointer, the address thus generated is compared with the value in SPLIM. If the contents of the Stack Pointer (W15) and the SPLIM register are equal and a push operation is performed, a Stack Error Trap will not occur. The Stack Error Trap will occur on a subsequent push operation. Thus, for example, if it is desirable to cause a Stack Error Trap when the stack grows beyond address 0x2000 in RAM, initialize the SPLIM with the value, 0x1FFE.

Similarly, a Stack Pointer Underflow (Stack Error) trap is generated when the stack pointer address is found to be less than 0x0800, thus preventing the stack from interfering with the Special Function Register (SFR) space.

A write to the SPLIM register should not be immediately followed by an indirect read operation using W15.

FIGURE 3-9: CALL STACK FRAME

0x0000

Higher Address

Stack Grows Towards

PC<15:0>

000000000

PC<22:16>

015

W15 (before CALL)

W15 (after CALL)

POP: [--W15] PUSH: [W15++]

 2004 Microchip Technology Inc. Advance Information DS70119B-page 27

dsPIC30F6010

0000 0000 0000 0000

0000 1000 0000 0000

0000 0000 0000 0000

uuuu uuuu uuuu uuuu

0000 0000 0uuu uuuu

uuuu uuuu uuuu uuuu

uuuu uuuu uuuu uuu0

0000 0000 0010 0000

0000 0000 0uuu uuuu

uuuu uuuu uuuu uuu0

0000 0000 0000 0000

— — BWM<3:0> YWM<3:0> XWM<3:0>

— — — — — — — — —PCH

— — — — — — — — TBLPAG

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

(Home)

Address

SFR Name

W0 0000 W0 / WREG

W1 0002 W1

W2 0004 W2

W3 0006 W3

W4 0008 W4

TABLE 3-3: CORE REGISTER MAP

W5 000A W5

W6 000C W6

W7 000E W7

W8 0010 W8

W9 0012 W9

W10 0014 W10

— — — — — — — —PSVPAG

W11 0016 W11

W12 0018 W12

W13 001A W13

W14 001C W14

W15 001E W15

SPLIM 0020 SPLIM

ACCAL 0022 ACCAL

ACCAH 0024 ACCAH

ACCAU 0026 Sign-Extension (ACCA<39>) ACCAU

ACCBL 0028 ACCBL

ACCBH 002A ACCBH

ACCBU 002C Sign-Extension (ACCB<39>) ACCBU

PCL 002E PCL

PCH 0030

TBLPAG 0032

PSVPAG 0034

RCOUNT 0036 RCOUNT

DCOUNT 0038 DCOUNT

DOSTARTL 003A DOSTARTL 0

— — — — — — — — — DOSTARTH

DOSTARTH 003C

DOENDL 003E DOENDL 0

SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C

DOENDH 0040 — — — — — — — — — DOENDH

— — — US EDT DL2 DL1 DL0 SATA SATB SATDW ACCSAT IPL3 PSV RND IF

CORCON 0044

MODCON 0046 XMODEN YMODEN

DS70119B-page 28 Advance Information  2004 Microchip Technology Inc.

Legend: u = uninitialized bit

uuuu uuuu uuuu uuu0

uuuu uuuu uuuu uuu1

uuuu uuuu uuuu uuu0

uuuu uuuu uuuu uuu1

uuuu uuuu uuuu uuuu

0000 0000 0000 0000

dsPIC30F6010

YMODEND 004E YE<15:1> 1

XBREV 0050 BREN XB<14:0>

— — DISICNT<13:0>

DISICNT 0052

Legend: u = uninitialized bit

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

(Home)

Address

SFR Name

XMODSRT 0048 XS<15:1> 0

XMODEND 004A XE<15:1> 1

TABLE 3-3: CORE REGISTER MAP (CONTINUED)

YMODSRT 004C YS<15:1> 0

 2004 Microchip Technology Inc. Advance Information DS70119B-page 29

dsPIC30F6010

NOTES:

DS70119B-page 30 Advance Information  2004 Microchip Technology Inc.

dsPIC30F6010

4.0 ADDRESS GENERATOR UNITS

The dsPIC core contains two independent address generator units: the X AGU and Y AGU. The Y AGU supports word sized data reads for the DSP MAC class of instructions only. The dsPIC AGUs support three types of data addressing:

• Linear Addressing

• Modulo (Circular) Addressing

• Bit-Reversed Addressing

Linear and Modulo Data Addressing modes can be applied to data space or program space. Bit-Reversed addressing is only applicable to data space addresses.

4.1 Instruction Addressing Modes

The addressing modes in Table 4-1 form the basis of the addressing modes optimized to support the specific features of individual instructions. The addressing modes provided in the MAC class of instructions are somewhat different from those in the other instruction types.

TABLE 4-1: FUNDAMENTAL ADDRESSING MODES SUPPORTED

Addressing Mode Description

File Register Direct The address of the file register is specified explicitly.

decremented) by a constant value.

to form the EA.

4.1.1 FILE REGISTER INSTRUCTIONS

Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space). Most file register instructions employ a working register W0, which is denoted as WREG in these instructions. The destination is typically either the same file register, or WREG (with the exception of the MUL instruction), which writes the result to a register or register pair. The MOV instruction allows additional flexibility and can access the entire data space during file register operation.

4.1.2 MCU INSTRUCTIONS

The three-operand MCU instructions are of the form:

Operand 3 = Operand 1 <function> Operand 2

where Operand 1 is always a working register (i.e., the addressing mode can only be register direct), which is referred to as Wb. Operand 2 can be a W register, fetched from data memory, or a 5-bit literal. The result location can be either a W register or an address location. The following addressing modes are supported by MCU instructions:

• Register Direct

• Register Indirect

• Register Indirect Post-modified

• Register Indirect Pre-modified

• 5-bit or 10-bit Literal

Note: Not all instructions support all the address-

ing modes given above. Individual instructions may support different subsets of these addressing modes.

 2004 Microchip Technology Inc. Advance Information DS70119B-page 31

dsPIC30F6010

4.1.3 MOVE AND ACCUMULATOR INSTRUCTIONS

Move instructions and the DSP Accumulator class of instructions provide a greater degree of addressing flexibility than other instructions. In addition to the addressing modes supported by most MCU instructions, Move and Accumulator instructions also support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode.

Note: For the MOV instructions, the addressing

mode specified in the instruction can differ for the source and destination EA. However, the 4-bit Wb (Register Offset) field is shared between both source and destination (but typically only used by one).

In summary, the following addressing modes are supported by Move and Accumulator instructions:

• Register Direct

• Register Indirect

• Register Indirect Post-modified

• Register Indirect Pre-modified

• Register Indirect with Register Offset (Indexed)

• Register Indirect with Literal Offset

• 8-bit Literal

• 16-bit Literal

Note: Not all instructions support all the address-

ing modes given above. Individual instructions may support different subsets of these addressing modes.

4.1.4 MAC INSTRUCTIONS

The dual source operand DSP instructions (CLR, ED, EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also

referred to as MAC instructions, utilize a simplified set of addressing modes to allow the user to effectively manipulate the data pointers through register indirect tables.

The two source operand pre-fetch registers must be a member of the set {W8, W9, W10, W11}. For data reads, W8 and W9 will always be directed to the X RAGU and W10 and W11 will always be directed to the Y AGU. The effective addresses generated (before and after modification) must, therefore, be valid addresses within X data space for W8 and W9 and Y data space for W10 and W11.

In summary, the following addressing modes are supported by the MAC class of instructions:

• Register Indirect

• Register Indirect Post-modified by 2

• Register Indirect Post-modified by 4

• Register Indirect Post-modified by 6

• Register Indirect with Register Offset (Indexed)

4.1.5 OTHER INSTRUCTIONS

Besides the various addressing modes outlined above, some instructions use literal constants of various sizes. For example, BRA (branch) instructions use 16-bit signed literals to specify the branch destination directly, whereas the DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ADD Acc, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands.

4.2 Modulo Addressing

Modulo addressing is a method of providing an automated means to support circular data buffers using hardware. The objective is to remove the need for software to perform data address boundary checks when executing tightly looped code, as is typical in many DSP algorithms.

Modulo addressing can operate in either data or program space (since the data pointer mechanism is essentially the same for both). One circular buffer can be supported in each of the X (which also provides the pointers into Program space) and Y data spaces. Modulo addressing can operate on any W register pointer. However, it is not advisable to use W14 or W15 for Modulo addressing, since these two registers are used as the Stack Frame Pointer and Stack Pointer, respectively.

In general, any particular circular buffer can only be configured to operate in one direction, as there are certain restrictions on the buffer start address (for incrementing buffers) or end address (for decrementing buffers) based upon the direction of the buffer.

The only exception to the usage restrictions is for buffers which have a power-of-2 length. As these buffers satisfy the start and end address criteria, they may operate in a Bi-directional mode, (i.e., address boundary checks will be performed on both the lower and upper address boundaries).

Note: Register Indirect with Register Offset

Addressing is only available for W9 (in X space) and W11 (in Y space).

DS70119B-page 32 Advance Information  2004 Microchip Technology Inc.

dsPIC30F6010

4.2.1 START AND END ADDRESS

The Modulo addressing scheme requires that a starting and an end address be specified and loaded into the 16-bit modulo buffer address registers: XMODSRT, XMODEND, YMODSRT and YMODEND (see Table 3-3)..

Note: Y-space modulo addressing EA calcula-

tions assume word-sized data (LS bit of every EA is always clear).

The length of a circular buffer is not directly specified. It is determined by the difference between the corresponding start and end addresses. The maximum possible length of the circular buffer is 32K words (64 Kbytes).

4.2.2 W ADDRESS REGISTER SELECTION

The Modulo and Bit-Reversed Addressing Control register MODCON<15:0> contains enable flags as well as a W register field to specify the W address registers. The XWM and YWM fields select which registers will operate with modulo addressing. If XWM = 15, X RAGU and X WAGU modulo addressing are disabled. Similarly, if YWM = 15, Y AGU modulo addressing is disabled.

The X Address Space Pointer W register (XWM) to which modulo addressing is to be applied, is stored in MODCON<3:0> (see Table 3-3). Modulo addressing is enabled for X data space when XWM is set to any value other than 15 and the XMODEN bit is set at MODCON<15>.

The Y Address Space Pointer W register (YWM) to which modulo addressing is to be applied, is stored in MODCON<7:4>. Modulo addressing is enabled for Y data space when YWM is set to any value other than 15 and the YMODEN bit is set at MODCON<14>.

FIGURE 4-1: MODULO ADDRESSING OPERATION EXAMPLE

Byte Address

0x1100

MOV #0x1100,W0 MOV W0, XMODSRT ;set modulo start address MOV #0x1163,W0 MOV W0,MODEND ;set modulo end address MOV #0x8001,W0 MOV W0,MODCON ;enable W1, X AGU for modulo MOV #0x0000,W0 ;W0 holds buffer fill value MOV #0x1110,W1 ;point W1 to buffer DO AGAIN,#0x31 ;fill the 50 buffer locations MOV W0, [W1++] ;fill the next location AGAIN: INC W0,W0 ;increment the fill value

0x1163

Start Addr = End Addr = Length =

 2004 Microchip Technology Inc. Advance Information DS70119B-page 33

0x1100 0x1163

0x0032

words

dsPIC30F6010

4.2.3 MODULO ADDRESSING APPLICABILITY

Modulo addressing can be applied to the effective address (EA) calculation associated with any W register. It is important to realize that the address boundaries check for addresses less than or greater than the upper (for incrementing buffers) and lower (for decrementing buffers) boundary addresses (not just equal to). Address changes may, therefore, jump beyond boundaries and still be adjusted correctly.

Note: The modulo corrected effective address is

written back to the register only when PreModify or Post-Modify Addressing mode is used to compute the Effective Address. When an address offset (e.g., [W7+W2]) is used, modulo address correction is performed, but the contents of the register remains unchanged.

4.3 Bit-Reversed Addressing

Bit-Reversed addressing is intended to simplify data reordering for radix-2 FFT algorithms. It is supported by the X AGU for data writes only.

The modifier, which may be a constant value or register contents, is regarded as having its bit order reversed. The address source and destination are kept in normal order. Thus, the only operand requiring reversal is the modifier.

4.3.1 BIT-REVERSED ADDRESSING IMPLEMENTATION

Bit-Reversed addressing is enabled when:

1. BWM (W register selection) in the MODCON

2. the BREN bit is set in the XBREV register and

3. the addressing mode used is Register Indirect

with Pre-Increment or Post-Increment.

If the length of a bit-reversed buffer is M = 2 then the last ’N’ bits of the data buffer start address must be zeros.

XB<14:0> is the bit-reversed address modifier or ‘pivot point’ which is typically a constant. In the case of an FFT computation, its value is equal to half of the FFT data buffer size.

Note: All Bit-Reversed EA calculations assume

word sized data (LS bit of every EA is always clear). The XB value is scaled accordingly to generate compatible (byte) addresses.

When enabled, bit-reversed addressing will only be executed for register indirect with pre-increment or post-increment addressing and word sized data writes. It will not function for any other addressing mode or for byte-sized data, and normal addresses will be generated instead. When bit-reversed addressing is active, the W address pointer will always be added to the address modifier (XB) and the offset associated with the Register Indirect Addressing mode will be ignored. In addition, as word sized data is a requirement, the LS bit of the EA is ignored (and always clear).

Note: Modulo addressing and bit-reversed

addressing should not be enabled together. In the event that the user attempts to do this, bit reversed addressing will assume priority when active for the X WAGU, and X WAGU modulo addressing will be disabled. However, modulo addressing will continue to function in the X RAGU.

If bit-reversed addressing has already been enabled by setting the BREN (XBREV<15>) bit, then a write to the XBREV register should not be immediately followed by an indirect read operation using the W register that has been designated as the bit-reversed pointer.

bytes,

FIGURE 4-2: BIT-REVERSED ADDRESS EXAMPLE

Sequential Address

b15 b14 b13 b12

DS70119B-page 34 Advance Information  2004 Microchip Technology Inc.

b11 b10 b9 b8

b7 b6 b5 b4

b7 b6 b5 b1

Pivot Point

b3 b2 b1 0

Bit Locations Swapped Left-to-Right Around Center of Binary Value

b2 b3 b4 0

Bit-Reversed Address

XB = 0x0008 for a 16-word Bit-Reversed Buffer

dsPIC30F6010

TABLE 4-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)

Normal

Address

A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal

0000 0 0000 0

0001 1 1000 8

0010 2 0100 4

0011 3 1100 12

0100 4 0010 2

0101 5 1010 10

0110 6 0110 6

0111 7 1110 14

1000 8 0001 1

1001 9 1001 9

1010 10 0101 5

1011 11 1101 13

1100 12 0011 3

1101 13 1011 11

1110 14 0111 7

1111 15 1111 15

Bit-Reversed

Address

TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER

Buffer Size (Words) XB<14:0> Bit-Reversed Address Modifier Value

32768 0x4000

16384 0x2000

8192 0x1000

4096 0x0800

2048 0x0400

1024 0x0200

512 0x0100

256 0x0080

128 0x0040

64 0x0020

32 0x0010

16 0x0008

8 0x0004

4 0x0002

2 0x0001

 2004 Microchip Technology Inc. Advance Information DS70119B-page 35

dsPIC30F6010

NOTES:

DS70119B-page 36 Advance Information  2004 Microchip Technology Inc.

dsPIC30F6010

5.0 INTERRUPTS

The dsPIC30F6010 has 44 interrupt sources and 4 processor exceptions (traps), which must be arbitrated based on a priority scheme.

The CPU is responsible for reading the Interrupt Vector Table (IVT) and transferring the address contained in the interrupt vector to the program counter. The interrupt vector is transferred from the program data bus into the program counter, via a 24-bit wide multiplexer on the input of the program counter.

The Interrupt Vector Table (IVT) and Alternate Interrupt Vector Table (AIVT) are placed near the beginning of program memory (0x000004). The IVT and AIVT are shown in Figure 5-1.

The interrupt controller is responsible for preprocessing the interrupts and processor exceptions, prior to their being presented to the processor core. The peripheral interrupts and traps are enabled, prioritized and controlled using centralized special function registers:

• IFS0<15:0>, IFS1<15:0>, IFS2<15:0> All interrupt request flags are maintained in these three registers. The flags are set by their respective peripherals or external signals, and they are cleared via software.

• IEC0<15:0>, IEC1<15:0>, IEC2<15:0> All Interrupt Enable Control bits are maintained in these three registers. These control bits are used to individually enable interrupts from the peripherals or external signals.

• IPC0<15:0>... IPC11<7:0> The user assignable priority level associated with each of these 44 interrupts is held centrally in these twelve registers.

• IPL<3:0> The current CPU priority level is explicitly stored in the IPL bits. IPL<3> is present in the CORCON register, whereas IPL<2:0> are present in the status register (SR) in the processor core.

• INTCON1<15:0>, INTCON2<15:0> Global interrupt control functions are derived from these two registers. INTCON1 contains the control and status flags for the processor exceptions. The INTCON2 register controls the external interrupt request signal behavior and the use of the alternate vector table.

Note: Interrupt Flag bits get set when an inter-

rupt condition occurs, regardless of the state of its corresponding Enable bit. User software should ensure the appropriate Interrupt Flag bits are clear prior to enabling an interrupt.

All interrupt sources can be user assigned to one of 7 priority levels, 1 through 7, via the IPCx registers. Each interrupt source is associated with an interrupt vector, as shown in Table 5-1. Levels 7 and 1 represent the highest and lowest maskable priorities, respectively.

Note: Assigning a priority level of 0 to an inter-

rupt source is equivalent to disabling that interrupt.

If the NSTDIS bit (INTCON1<15>) is set, nesting of interrupts is prevented. Thus, if an interrupt is currently being serviced, processing of a new interrupt is prevented, even if the new interrupt is of higher priority than the one currently being serviced.

Note: The IPL bits become read-only whenever

the NSTDIS bit has been set to ‘1’.

Certain interrupts have specialized control bits for features like edge or level triggered interrupts, interrupton-change, etc. Control of these features remains within the peripheral module which generates the interrupt.

The DISI instruction can be used to disable the processing of interrupts of priorities 6 and lower for a certain number of instructions, during which the DISI bit (INTCON2<14>) remains set.

When an interrupt is serviced, the PC is loaded with the address stored in the vector location in Program Memory that corresponds to the interrupt. There are 63 different vectors within the IVT (refer to Figure 5-2). These vectors are contained in locations 0x000004 through 0x0000FE of program memory (refer to Figure 5-2). These locations contain 24-bit addresses, and in order to preserve robustness, an address error trap will take place should the PC attempt to fetch any of these words during normal execution. This prevents execution of random data as a result of accidentally decrementing a PC into vector space, accidentally mapping a data space address into vector space, or the PC rolling over to 0x000000 after reaching the end of implemented program memory space. Execution of a GOTO instruction to this vector space will also generate an address error trap.

 2004 Microchip Technology Inc. Advance Information DS70119B-page 37

dsPIC30F6010

5.1 Interrupt Priority

The user assignable Interrupt Priority (IP<2:0>) bits for each individual interrupt source are located in the LS 3bits of each nibble, within the IPCx register(s). Bit 3 of each nibble is not used and is read as a ‘0’. These bits define the priority level assigned to a particular interrupt by the user.

Note: The user selectable priority levels start at

0, as the lowest priority, and level 7, as the highest priority.

Since more than one interrupt request source may be assigned to a specific user specified priority level, a means is provided to assign priority within a given level. This method is called “Natural Order Priority”.

Natural Order Priority is determined by the position of an interrupt in the vector table, and only affects interrupt operation when multiple interrupts with the same user-assigned priority become pending at the same time.

Table 5-1 lists the interrupt numbers and interrupt sources for the dsPIC devices and their associated vector numbers.

Note 1: The natural order priority scheme has 0

as the highest priority and 53 as the lowest priority.

2: The natural order priority number is the

same as the INT number.

The ability for the user to assign every interrupt to one of seven priority levels implies that the user can assign a very high overall priority level to an interrupt with a low natural order priority. For example, the PLVD (Low Voltage Detect) can be given a priority of 7. The INT0 (external interrupt 0) may be assigned to priority level 1, thus giving it a very low effective priority.

TABLE 5-1: INTERRUPT VECTOR TABLE

INT

Number

Highest Natural Order Priority

0 8 INT0 - External Interrupt 0 1 9 IC1 - Input Capture 1 2 10 OC1 - Output Compare 1 3 11 T1 - Timer 1 4 12 IC2 - Input Capture 2 5 13 OC2 - Output Compare 2 6 14 T2 - Timer 2 7 15 T3 - Timer 3 8 16 SPI1

9 17 U1RX - UART1 Receiver 10 18 U1TX - UART1 Transmitter 11 19 ADC - ADC Convert Done 12 20 NVM - NVM Write Complete 13 21 SI2C - I 14 22 MI2C - I 15 23 Input Change Interrupt 16 24 INT1 - External Interrupt 1 17 25 IC7 - Input Capture 7 18 26 IC8 - Input Capture 8 19 27 OC3 - Output Compare 3 20 28 OC4 - Output Compare 4 21 29 T4 - Timer 4 22 30 T5 - Timer 5 23 31 INT2 - External Interrupt 2 24 32 U2RX - UART2 Receiver 25 33 U2TX - UART2 Transmitter 26 34 SPI2 27 35 C1 - Combined IRQ for CAN1 28 36 IC3 - Input Capture 3 29 37 IC4 - Input Capture 4 30 38 IC5 - Input Capture 5 31 39 IC6 - Input Capture 6 32 40 OC5 - Output Compare 5 33 41 OC6 - Output Compare 6 34 42 OC7 - Output Compare 7 35 43 OC8 - Output Compare 8 36 44 INT3 - External Interrupt 3 37 45 INT4 - External Interrupt 4 38 46 C2 - Combined IRQ for CAN2 39 47 PWM - PWM Period Match 40 48 QEI - QEI Interrupt 41 49 Reserved 42 50 LVD - Low Voltage Detect 43 51 FLTA - PWM Fault A 44 52 FLTB - PWM Fault B

45-53 53-61 Reserved

Lowest Natural Order Priority

Vector

Number

Interrupt Source

C Slave Interrupt

C Master Interrupt

DS70119B-page 38 Advance Information  2004 Microchip Technology Inc.

dsPIC30F6010

5.2 Reset Sequence

A Reset is not a true exception, because the interrupt controller is not involved in the Reset process. The processor initializes its registers in response to a Reset, which forces the PC to zero. The processor then begins program execution at location 0x000000. A GOTO instruction is stored in the first program memory location, immediately followed by the address target for the GOTO instruction. The processor executes the GOTO to the specified address and then begins operation at the specified target (start) address.

5.2.1 RESET SOURCES

There are 6 sources of error which will cause a device reset.

• Watchdog Time-out: The watchdog has timed out, indicating that the processor is no longer executing the correct flow of code.

• Uninitialized W Register Trap: An attempt to use an uninitialized W register as an address pointer will cause a Reset.

• Illegal Instruction Trap: Attempted execution of any unused opcodes will result in an illegal instruction trap. Note that a fetch of an illegal instruction does not result in an illegal instruction trap if that instruction is flushed prior to execution due to a flow change.

• Brown-out Reset (BOR): A momentary dip in the power supply to the device has been detected, which may result in malfunction.

• Trap Lockout: Occurrence of multiple Trap conditions simultaneously will cause a Reset.

5.3 Traps

Traps can be considered as non-maskable interrupts indicating a software or hardware error, which adhere to a predefined priority as shown in Figure 5-1. They are intended to provide the user a means to correct erroneous operation during debug and when operating within the application.

Note: If the user does not intend to take correc-

tive action in the event of a trap error condition, these vectors must be loaded with the address of a default handler that simply contains the RESET instruction. If, on the other hand, one of the vectors containing an invalid address is called, an address error trap is generated.

Note that many of these trap conditions can only be detected when they occur. Consequently, the questionable instruction is allowed to complete prior to trap exception processing. If the user chooses to recover from the error, the result of the erroneous action that caused the trap may have to be corrected.

There are 8 fixed priority levels for traps: Level 8 through Level 15, which implies that the IPL3 is always set during processing of a trap.

If the user is not currently executing a trap, and he sets the IPL<3:0> bits to a value of ‘0111’ (Level 7), then all interrupts are disabled, but traps can still be processed.

5.3.1 TRAP SOURCES

The following traps are provided with increasing priority. However, since all traps can be nested, priority has little effect.

Math Error Trap:

The Math Error trap executes under the following three circumstances:

1. Should an attempt be made to divide by zero, the divide operation will be aborted on a cycle boundary and the trap taken.

2. If enabled, a Math Error trap will be taken when an arithmetic operation on either accumulator A or B causes an overflow from bit 31 and the Accumulator Guard bits are not utilized.

3. If enabled, a Math Error trap will be taken when an arithmetic operation on either accumulator A or B causes a catastrophic overflow from bit 39 and all saturation is disabled.

4. If the shift amount specified in a shift instruction is greater than the maximum allowed shift amount, a trap will occur.

 2004 Microchip Technology Inc. Advance Information DS70119B-page 39

dsPIC30F6010

Address Error Trap:

This trap is initiated when any of the following circumstances occurs:

1. A misaligned data word access is attempted.

2. A data fetch from our unimplemented data memory location is attempted.

3. A data access of an unimplemented program memory location is attempted.

4. An instruction fetch from vector space is attempted.

Note: In the MAC class of instructions, wherein

the data space is split into X and Y data space, unimplemented X space includes all of Y space, and unimplemented Y space includes all of X space.

5. Execution of a “BRA #literal” instruction or a “GOTO #literal” instruction, where literal is an unimplemented program memory address.

6. Executing instructions after modifying the PC to point to unimplemented program memory addresses. The PC may be modified by loading a value into the stack and executing a RETURN instruction.

Stack Error Trap:

This trap is initiated under the following conditions:

1. The stack pointer is loaded with a value which is greater than the (user programmable) limit value written into the SPLIM register (stack overflow).

2. The stack pointer is loaded with a value which is less than 0x0800 (simple stack underflow).

Oscillator Fail Trap:

This trap is initiated if the external oscillator fails and operation becomes reliant on an internal RC backup.

5.3.2 HARD AND SOFT TRAPS

It is possible that multiple traps can become active within the same cycle (e.g., a misaligned word stack write to an overflowed address). In such a case, the fixed priority shown in Figure 5-2 is implemented, which may require the user to check if other traps are pending, in order to completely correct the fault.

‘Soft’ traps include exceptions of priority level 8 through level 11, inclusive. The arithmetic error trap (level 11) falls into this category of traps.

‘Hard’ traps include exceptions of priority level 12 through level 15, inclusive. The address error (level

12), stack error (level 13) and oscillator error (level 14) traps fall into this category.

Each hard trap that occurs must be acknowledged before code execution of any type may continue. If a lower priority hard trap occurs while a higher priority trap is pending, acknowledged, or is being processed, a hard trap conflict will occur.

The device is automatically Reset in a hard trap conflict condition. The TRAPR status bit (RCON<15>) is set when the Reset occurs, so that the condition may be detected in software.

FIGURE 5-1: TRAP VECTORS

IVT

Priority

Decreasing

AIVT

Reset - GOTO Instruction

Reset - GOTO Address

Reserved

Oscillator Fail Trap Vector

Address Error Trap Vector

Stack Error Trap Vector

Math Error Trap Vector

Reserved Vector Reserved Vector

Reserved Vector Interrupt 0 Vector Interrupt 1 Vector

— —

— Interrupt 52 Vector Interrupt 53 Vector

Reserved Reserved Reserved

Oscillator Fail Trap Vector

Stack Error Trap Vector

Address Error Trap Vector

Math Error Trap Vector

Reserved Vector Reserved Vector

Reserved Vector Interrupt 0 Vector Interrupt 1 Vector

— — —

Interrupt 52 Vector Interrupt 53 Vector

0x000000

0x000002 0x000004

0x000014

0x00007E

0x000080 0x000082 0x000084

0x000094

0x0000FE

DS70119B-page 40 Advance Information  2004 Microchip Technology Inc.

dsPIC30F6010

5.4 Interrupt Sequence

All interrupt event flags are sampled in the beginning of each instruction cycle by the IFSx registers. A pending interrupt request (IRQ) is indicated by the flag bit being equal to a ‘1’ in an IFSx register. The IRQ will cause an interrupt to occur if the corresponding bit in the interrupt enable (IECx) register is set. For the remainder of the instruction cycle, the priorities of all pending interrupt requests are evaluated.

If there is a pending IRQ with a priority level greater than the current processor priority level in the IPL bits, the processor will be interrupted.

The processor then stacks the current program counter and the low byte of the processor status register (SRL), as shown in Figure 5-2. The low byte of the status register contains the processor priority level at the time, prior to the beginning of the interrupt cycle. The processor then loads the priority level for this interrupt into the status register. This action will disable all lower priority interrupts until the completion of the Interrupt Service Routine.

FIGURE 5-2: INTERRUPT STACK

FRAME

0x0000

PC<15:0>

SRL IPL3 PC<22:16>

Higher Address

Stack Grows Towards

015

W15 (before CALL)

W15 (after CALL)

POP : [--W15] PUSH : [W15++]

5.5 Alternate Vector Table

In Program Memory, the Interrupt Vector Table (IVT) is followed by the Alternate Interrupt Vector Table (AIVT), as shown in Figure 5-1. Access to the Alternate Vector Table is provided by the ALTIVT bit in the INTCON2 register. If the ALTIVT bit is set, all interrupt and exception processes will use the alternate vectors instead of the default vectors. The alternate vectors are organized in the same manner as the default vectors. The AIVT supports emulation and debugging efforts by providing a means to switch between an application and a support environment, without requiring the interrupt vectors to be reprogrammed. This feature also enables switching between applications for evaluation of different software algorithms at run time.

If the AIVT is not required, the program memory allocated to the AIVT may be used for other purposes. AIVT is not a protected section and may be freely programmed by the user.

5.6 Fast Context Saving

A context saving option is available using shadow registers. Shadow registers are provided for the DC, N, OV, Z and C bits in SR, and the registers W0 through W3. The shadows are only one level deep. The shadow registers are accessible using the PUSH.S and POP.S instructions only.

When the processor vectors to an interrupt, the PUSH.S instruction can be used to store the current value of the aforementioned registers into their respective shadow registers.

If an ISR of a certain priority uses the PUSH.S and POP.S instructions for fast context saving, then a higher priority ISR should not include the same instructions. Users must save the key registers in software during a lower priority interrupt, if the higher priority ISR uses fast context saving.

Note 1: The user can always lower the priority level

by writing a new value into SR. The Interrupt Service Routine must clear the interrupt flag bits in the IFSx register before lowering the processor interrupt priority, in order to avoid recursive interrupts.

2: The IPL3 bit (CORCON<3>) is always clear

when interrupts are being processed. It is set only during execution of traps.

The RETFIE (Return from Interrupt) instruction will unstack the program counter and status registers to return the processor to its state prior to the interrupt sequence.

 2004 Microchip Technology Inc. Advance Information DS70119B-page 41

5.7 External Interrupt Requests

The interrupt controller supports five external interrupt request signals, INT0-INT4. These inputs are edge sensitive; they require a low-to-high or a high-to-low transition to generate an interrupt request. The INTCON2 register has five bits, INT0EP-INT4EP, that select the polarity of the edge detection circuitry.

5.8 Wake-up from Sleep and Idle

The interrupt controller may be used to wake up the processor from either Sleep or Idle modes, if Sleep or Idle mode is active when the interrupt is generated.

If an enabled interrupt request of sufficient priority is received by the interrupt controller, then the standard interrupt request is presented to the processor. At the same time, the processor will wake-up from Sleep or Idle and begin execution of the Interrupt Service Routine (ISR) needed to process the interrupt request.

dsPIC30F6010

0000 0000 0000 0000

0100 0100 0100 0100

0100 0100 0000 0100

0000 0000 0000 0100

— — — — OVATE OVBTE COVTE — — — MATHERR ADDRERR STKERR OSCFAIL —

— — — — — — — — — — INT4EP INT3EP INT2EP INT1EP INT0EP

— — — FLTBI F FLTA IF LV DIF — QEIIF PWMIF C2IF INT4IF INT3IF OC8IF OC7IF OC6IF OC5IF

ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

SFR

Name

INTCON1 0080 NSTDIS

IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF U1TXIF U1RXIF SPI1IF T3IF T2IF OC2IF IC2IF T1IF OC1IF IC1IF INT0IF

IFS1 0086 IC6IF IC5IF IC4IF IC3IF C1IF SPI2IF U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF IC8IF IC7IF INT1IF

TABLE 5-2: INTERRUPT CONTROLLER REGISTER MAP

INTCON2 0082 ALTIVT

IFS2 0088

IEC0 008C CNIE MI2CIE SI2CIE NVMIE ADIE U1TXIE U1RXIE SPI1IE T3IE T2IE OC2IE IC2IE T1IE OC1IE IC1IE INT0IE

IEC1 008E IC6IE IC5IE IC4IE IC3IE C1IE SPI2IE U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE IC8IE IC7IE INT1IE

— — — F LTBIE F LTAIE LVD IE — QEIIE PWMIE C2IE INT4IE INT3IE OC8IE OC7IE OC6IE OC5IE

IEC2 0090

IPC0 0094 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0>

— T31P<2:0> — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0>

— ADIP<2:0> — U1TXIP<2:0> — U1RXIP<2:0> — SPI1IP<2:0>

IPC1 0096

IPC2 0098

IPC3 009A — CNIP<2:0> — MI2CIP<2:0> — SI2CIP<2:0> — NVMIP<2:0>

— OC3IP<2:0> — IC8IP<2:0> — IC7IP<2:0> — INT1IP<2:0>

— INT2IP<2:0> — T5IP<2:0> — T4IP<2:0> — OC4IP<2:0>

IPC4 009C

IPC5 009E

IPC6 00A0 — C1IP<2:0> — SPI2IP<2:0> — U2TXIP<2:0> — U2RXIP<2:0>

— IC6IP<2:0> — IC5IP<2:0> — IC4IP<2:0> — IC3IP<2:0>

— OC8IP<2:0> — OC7IP<2:0> — OC6IP<2:0> — OC5IP<2:0>

IPC7 00A2

IPC8 00A4

IPC9 00A6 — PWMIP<2:0> — C2IP<2:0> — INT41IP<2:0> — INT3IP<2:0>

— FLTAIP<2:0> — LVDIP<2:0> — — — — — QEIIP<2:0>

IPC10 00A8

IPC11 00AA — — — — — — — — — — — — — FLTBIP<2:0>

Legend: u = uninitialized bit

DS70119B-page 42 Advance Information  2004 Microchip Technology Inc.

dsPIC30F6010

6.0 FLASH PROGRAM MEMORY

The dsPIC30F family of devices contains internal program Flash memory for executing user code. There are two methods by which the user can program this memory:

1. In-Circuit Serial Programming™ (ICSP™)

2. Run Time Self-Programming (RTSP)

6.1 In-Circuit Serial Programming (ICSP)

dsPIC30F devices can be serially programmed while in the end application circuit. This is simply done with two lines for Programming Clock and Programming Data (which are named PGC and PGD respectively), and three other lines for Power (V Master Clear (MCLR

). this allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed.

DD), Ground (VSS) and

6.2 Run Time Self-Programming (RTSP)

RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions.

With RTSP, the user may erase program memory, 32 instructions (96 bytes) at a time and can write program memory data, 32 instructions (96 bytes) at a time.

6.3 Table Instruction Operation Summary

The TBLRDL and the TBLWTL instructions are used to read or write to bits <15:0> of program memory. TBLRDL and TBLWTL can access program memory in Word or Byte mode.

The TBLRDH and TBLWTH instructions are used to read or write to bits<23:16> of program memory. TBLRDH and TBLWTH can access program memory in Word or Byte mode.

A 24-bit program memory address is formed using bits<7:0> of the TBLPAG register and the effective address (EA) from a W register specified in the table instruction, as shown in Figure 6-1.

FIGURE 6-1: ADDRESSING FOR TABLE AND NVM REGISTERS

Using NVMADR Addressing

Using Ta bl e Instruction

User/Configuration Space Select

Using Program Counter

1/0

NVMADRU Reg

1/0

TBLPAG Reg

24 bits

NVMADR Reg EA

8 bits 16 bits

Working Reg EA

8 bits

24-bit EA

16 bits

0Program Counter

Byte Select

 2004 Microchip Technology Inc. Advance Information DS70119B-page 43

dsPIC30F6010

6.4 RTSP Operation

The dsPIC30F Flash program memory is organized into rows and panels. Each row consists of 32 instructions, or 96 bytes. Each panel consists of 128 rows, or 4K x 24 instructions. RTSP allows the user to erase one row (32 instructions) at a time and to program 32 instructions at one time.

Each panel of program memory contains write latches that hold 32 instructions of programming data. Prior to the actual programming operation, the write data must be loaded into the panel write latches. The data to be programmed into the panel is loaded in sequential order into the write latches; instruction 0, instruction 1, etc. The addresses loaded must always be from an even group of 32 boundary.

The basic sequence for RTSP programming is to set up a table pointer, then do a series of TBLWT instructions to load the write latches. Programming is performed by setting the special bits in the NVMCON register. 32 TBLWTL and four TBLWTH instructions are required to load the 32 instructions.

All of the table write operations are single word writes (2 instruction cycles), because only the table latches are written.

After the latches are written, a programming operation needs to be initiated to program the data.

The Flash Program Memory is readable, writable and erasable during normal operation over the entire V range.

6.5 RTSP Control Registers

The four SFRs used to read and write the program Flash memory are:

•NVMCON

•NVMADR

• NVMADRU

•NVMKEY

6.5.1 NVMCON REGISTER

The NVMCON register controls which blocks are to be erased, which memory type is to be programmed, and start of the programming cycle.

6.5.2 NVMADR REGISTER

The NVMADR register is used to hold the lower two bytes of the effective address. The NVMADR register captures the EA<15:0> of the last table instruction that has been executed and selects the row to write.

6.5.3 NVMADRU REGISTER

The NVMADRU register is used to hold the upper byte of the effective address. The NVMADRU register captures the EA<23:16> of the last table instruction that has been executed.

6.5.4 NVMKEY REGISTER

NVMKEY is a write-only register that is used for write protection. To start a programming or an erase sequence, the user must consecutively write 0x55 and 0xAA to the NVMKEY register. Refer to Section 6.6 for further details.

Note: The user can also directly write to the

NVMADR and NVMADRU registers to specify a program memory address for erasing or programming.

DS70119B-page 44 Advance Information  2004 Microchip Technology Inc.

dsPIC30F6010

6.6 Programming Operations

A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. A programming operation is nominally 2 msec in duration and the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON<15>) starts the operation, and the WR bit is automatically cleared when the operation is finished.

6.6.1 PROGRAMMING ALGORITHM FOR PROGRAM FLASH

The user can erase or program one row of program Flash memory at a time. The general process is:

1. Read one row of program Flash (32 instruction

words) and store into data RAM as a data “image”.

2. Update the data image with the desired new

data.

3. Erase program Flash row.

a) Setup NVMCON register for multi-word,

program Flash, erase, and set WREN bit.

b) Write address of row to be erased into

NVMADRU/NVMDR. c) Write ‘55’ to NVMKEY. d) Write ‘AA’ to NVMKEY. e) Set the WR bit. This will begin erase cycle. f) CPU will stall for the duration of the erase

cycle. g) The WR bit is cleared when erase cycle

ends.

4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches.

5. Program 32 instruction words into program Flash.

a) Setup NVMCON register for multi-word,

program Flash, program, and set WREN

bit. b) Write ‘55’ to NVMKEY. c) Write ‘AA’ to NVMKEY. d) Set the WR bit. This will begin program

cycle. e) CPU will stall for duration of the program

cycle. f) The WR bit is cleared by the hardware

when program cycle ends.

6. Repeat steps 1 through 5 as needed to program desired amount of program Flash memory.

6.6.2 ERASING A ROW OF PROGRAM

MEMORY

Example 6-1 shows a code sequence that can be used to erase a row (32 instructions) of program memory.

EXAMPLE 6-1: ERASING A ROW OF PROGRAM MEMORY

; Setup NVMCON for erase operation, multi word write ; program memory selected, and writes enabled

MOV #0x4041,W0 ;

; Init pointer to row to be ERASED

MOV W0

MOV #tblpage(PROG_ADDR),W0 ; MOV W0 MOV #tbloffset(PROG_ADDR),W0 ; Intialize in-page EA[15:0] pointer MOV W0, NVMADR ; Intialize NVMADR SFR DISI #5 ; Block all interrupts with priority <7

MOV #0x55,W0 MOV W0 MOV #0xAA,W1 ; MOV W1 BSET NVMCON,#WR ; Start the erase sequence NOP ; Insert two NOPs after the erase NOP ; command is asserted

NVMCON ; Init NVMCON SFR

NVMADRU ; Initialize PM Page Boundary SFR

; for next 5 instructions

NVMKEY ; Write the 0x55 key

NVMKEY ; Write the 0xAA key

 2004 Microchip Technology Inc. Advance Information DS70119B-page 45

dsPIC30F6010

6.6.3 LOADING WRITE LATCHES

Example 6-2 shows a sequence of instructions that can be used to load the 96 bytes of write latches. 32 TBLWTL and 32 TBLWTH instructions are needed to load the write latches selected by the table pointer.

EXAMPLE 6-2: LOADING WRITE LATCHES

; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled

MOV #0x0000,W0 ; MOV W0

MOV #0x6000,W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word

MOV #LOW_WORD_0,W2 ;

MOV #HIGH_BYTE_0,W3 ;

TBLWTL W2

TBLWTH W3 ; 1st_program_word

MOV #LOW_WORD_1,W2 ;

MOV #HIGH_BYTE_1,W3 ;

TBLWTL W2

TBLWTH W3 ; 2nd_program_word

MOV #LOW_WORD_2,W2 ;

MOV #HIGH_BYTE_2,W3 ;

TBLWTL W2

TBLWTH W3

•

; 31st_program_word

MOV #LOW_WORD_31,W2 ;

MOV #HIGH_BYTE_31,W3 ;

TBLWTL W2

TBLWTH W3

TBLPAG ; Initialize PM Page Boundary SFR

[W0] ; Write PM low word into program latch

[W0++] ; Write PM high byte into program latch

[W0] ; Write PM low word into program latch

[W0++] ; Write PM high byte into program latch

[W0] ; Write PM low word into program latch

[W0++] ; Write PM high byte into program latch

[W0] ; Write PM low word into program latch

[W0++] ; Write PM high byte into program latch

Note: In Example 6-2, the contents of the upper byte of W3 has no effect.

6.6.4 INITIATING THE PROGRAMMING SEQUENCE

For protection, the write initiate sequence for NVMKEY must be used to allow any erase or program operation to proceed. After the programming command has been executed, the user must wait for the programming time until programming is complete. The two instructions following the start of the programming sequence should be NOPs.

EXAMPLE 6-3: INITIATING A PROGRAMMING SEQUENCE

DISI #5 ; Block all interrupts with priority <7

; for next 5 instructions MOV #0x55,W0 MOV W0 MOV #0xAA,W1 ; MOV W1 BSET NVMCON,#WR ; Start the erase sequence NOP ; Insert two NOPs after the erase NOP ; command is asserted

NVMKEY ; Write the 0x55 key

NVMKEY ; Write the 0xAA key

DS70119B-page 46 Advance Information  2004 Microchip Technology Inc.

0000 0000 uuuu uuuu

0000 0000 0000 0000

uuuu uuuu uuuu uuuu

dsPIC30F6010

— PROGOP<6:0> 0000 0000 0000 0000

TWRI

— — — —

— — — — — — — — NVMADR<23:16>

— — — — — — — — KEY<7:0>

File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All RESETS

NVMCON 0760 WR WREN WRERR

TABLE 6-1: NVM REGISTER MAP

 2004 Microchip Technology Inc. Advance Information DS70119B-page 47

NVMKEY 0766

NVMADR 0762 NVMADR<15:0>

Legend: u = uninitialized bit

NVMADRU 0764

dsPIC30F6010

NOTES:

DS70119B-page 48 Advance Information  2004 Microchip Technology Inc.

dsPIC30F6010

7.0 DATA EEPROM MEMORY

The Data EEPROM Memory is readable and writable during normal operation over the entire V data EEPROM memory is directly mapped in the program memory address space.

The four SFRs used to read and write the program Flash memory are used to access data EEPROM memory, as well. As described in Section 4.0, these registers are:

•NVMCON

•NVMADR

• NVMADRU

•NVMKEY

The EEPROM data memory allows read and write of single words and 16-word blocks. When interfacing to data memory, NVMADR, in conjunction with the NVMADRU register, is used to address the EEPROM location being accessed. TBLRDL and TBLWTL instructions are used to read and write data EEPROM. The dsPIC30F6010 device has 8 Kbytes (4K words) of data EEPROM, with an address range from 0x7FF000 to 0x7FFFFE.

A word write operation should be preceded by an erase of the corresponding memory location(s). The write typically requires 2 ms to complete, but the write time will vary with voltage and temperature.

A program or erase operation on the data EEPROM does not stop the instruction flow. The user is responsible for waiting for the appropriate duration of time before initiating another data EEPROM write/erase operation. Attempting to read the data EEPROM while a programming or erase operation is in progress results in unspecified data.

DD range. The

Control bit WR initiates write operations, similar to program Flash writes. This bit cannot be cleared, only set, in software. This bit is cleared in hardware at the completion of the write operation. The inability to clear the WR bit in software prevents the accidental or premature termination of a write operation.

The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a MCLR Reset, or a WDT Time-out Reset, during normal operation. In these situations, following Reset, the user can check the WRERR bit and rewrite the location. The address register NVMADR remains unchanged.

Note: Interrupt flag bit NVMIF in the IFS0 regis-

ter is set when write is complete. It must be cleared in software.

7.1 Reading the Data EEPROM

A TBLRD instruction reads a word at the current program word address. This example uses W0 as a pointer to data EEPROM. The result is placed in register W4, as shown in Example 7-1.

EXAMPLE 7-1: DATA EEPROM READ

MOV #LOW_ADDR_WORD,W0 ; Init Pointer MOV #HIGH_ADDR_WORD,W1 MOV W1 TBLRDL [ W0 ], W4 ; read data EEPROM

TBLPAG

 2004 Microchip Technology Inc. Advance Information DS70119B-page 49

dsPIC30F6010

7.2 Erasing Data EEPROM

7.2.1 ERASING A BLOCK OF DATA EEPROM

In order to erase a block of data EEPROM, the NVMADRU and NVMADR registers must initially point to the block of memory to be erased. Configure NVMCON for erasing a block of data EEPROM, and set the ERASE and WREN bits in NVMCON register. Setting the WR bit initiates the erase, as shown in Example 7-2.

EXAMPLE 7-2: DATA EEPROM BLOCK ERASE

; Select data EEPROM block, ERASE, WREN bits

MOV #4045,W0 MOV W0

; Start erase cycle by setting WR after writing key sequence

DISI #5 ; Block all interrupts with priority <7

MOV #0x55,W0 ; MOV W0

MOV #0xAA,W1 ;

MOV W1

BSET NVMCON,#WR ; Initiate erase sequence NOP NOP ; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete

NVMCON ; Initialize NVMCON SFR

; for next 5 instructions

NVMKEY ; Write the 0x55 key

NVMKEY ; Write the 0xAA key

7.2.2 ERASING A WORD OF DATA EEPROM

The TBLPAG and NVMADR registers must point to the block. Select erase a block of data Flash, and set the ERASE and WREN bits in NVMCON register. Setting the WR bit initiates the erase, as shown in Example 7-3.

EXAMPLE 7-3: DATA EEPROM WORD ERASE

; Select data EEPROM word, ERASE, WREN bits

MOV #4044,W0 MOV W0

; Start erase cycle by setting WR after writing key sequence

DISI #5 ; Block all interrupts with priority <7

MOV #0x55,W0 ; MOV W0 MOV #0xAA,W1 ; MOV W1

NVMCON

; for next 5 instructions

NVMKEY ; Write the 0x55 key

NVMKEY ; Write the 0xAA key

DS70119B-page 50 Advance Information  2004 Microchip Technology Inc.

dsPIC30F6010

7.3 Writing to the Data EEPROM

To write an EEPROM data location, the following sequence must be followed:

1. Erase data EEPROM word. a) Select word, data EEPROM, erase and set

WREN bit in NVMCON register.

b) Write address of word to be erased into

NVMADRU/NVMADR. c) Enable NVM interrupt (optional). d) Write ‘55’ to NVMKEY. e) Write ‘AA’ to NVMKEY. f) Set the WR bit. This will begin erase cycle. g) Either poll NVMIF bit or wait for NVMIF

interrupt. h) The WR bit is cleared when the erase cycle

ends.

2. Write data word into data EEPROM write latches.

3. Program 1 data word into data EEPROM. a) Select word, data EEPROM, program, and

set WREN bit in NVMCON register. b) Enable NVM write done interrupt (optional). c) Write ‘55’ to NVMKEY. d) Write ‘AA’ to NVMKEY. e) Set The WR bit. This will begin program

cycle. f) Either poll NVMIF bit or wait for NVM

interrupt. g) The WR bit is cleared when the write cycle

ends.

The write will not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word. It is strongly recommended that interrupts be disabled during this code segment.

Additionally, the WREN bit in NVMCON must be set to enable writes. This mechanism prevents accidental writes to data EEPROM, due to unexpected code execution. The WREN bit should be kept clear at all times, except when updating the EEPROM. The WREN bit is not cleared by hardware.

After a write sequence has been initiated, clearing the WREN bit will not affect the current write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. The WREN bit must be set on a previous instruction. Both WR and WREN cannot be set with the same instruction.

At the completion of the write cycle, the WR bit is cleared in hardware and the Non-Volatile Memory Write Complete Interrupt Flag bit (NVMIF) is set. The user may either enable this interrupt, or poll this bit. NVMIF must be cleared by software.

7.3.1 WRITING A WORD OF DATA EEPROM

Once the user has erased the word to be programmed, then a table write instruction is used to write one write latch, as shown in Example 7-4.

EXAMPLE 7-4: DATA EEPROM WORD WRITE

; Point to data memory

MOV #LOW_ADDR_WORD,W0 ; Init pointer MOV #HIGH_ADDR_WORD,W1 MOV W1 MOV #LOW(WORD),W2 ; Get data

TBLWTL W2 ; The NVMADR captures last table access address ; Select data EEPROM for 1 word op

MOV #0x4004,W0

MOV W0

; Operate key to allow write operation

DISI #5 ; Block all interrupts with priority <7

MOV #0x55,W0

MOV W0

MOV #0xAA,W1

MOV W1

BSET NVMCON,#WR ; Initiate program sequence NOP NOP ; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete

TBLPAG

[ W0] ; Write data

NVMCON

; for next 5 instructions

NVMKEY ; Write the 0x55 key

NVMKEY ; Write the 0xAA key

 2004 Microchip Technology Inc. Advance Information DS70119B-page 51

dsPIC30F6010

7.3.2 WRITING A BLOCK OF DATA EEPROM

To write a block of data EEPROM, write to all sixteen latches first, then set the NVMCON register and program the block.

EXAMPLE 7-5: DATA EEPROM BLOCK WRITE

MOV #LOW_ADDR_WORD,W0 ; Init pointer MOV #HIGH_ADDR_WORD,W1 MOV W1 MOV #data1,W2 ; Get 1st data TBLWTL W2 MOV #data2,W2 ; Get 2nd data TBLWTL W2 MOV #data3,W2 ; Get 3rd data TBLWTL W2 MOV #data4,W2 ; Get 4th data TBLWTL W2 MOV #data5,W2 ; Get 5th data TBLWTL W2 MOV #data6,W2 ; Get 6th data TBLWTL W2 MOV #data7,W2 ; Get 7th data TBLWTL W2 MOV #data8,W2 ; Get 8th data TBLWTL W2 MOV #data9,W2 ; Get 9th data TBLWTL W2 MOV #data10,W2 ; Get 10th data TBLWTL W2 MOV #data11,W2 ; Get 11th data TBLWTL W2 MOV #data12,W2 ; Get 12th data TBLWTL W2 MOV #data13,W2 ; Get 13th data TBLWTL W2 MOV #data14,W2 ; Get 14th data TBLWTL W2 MOV #data15,W2 ; Get 15th data TBLWTL W2 MOV #data16,W2 ; Get 16th data TBLWTL W2 MOV #0x400A,W0 ; Select data EEPROM for multi word op

MOV W0 DISI #5 ; Block all interrupts with priority <7

MOV #0x55,W0 MOV W0 MOV #0xAA,W1 MOV W1 BSET NVMCON,#WR ; Start write cycle NOP NOP

TBLPAG

[ W0]++ ; write data

[ W0]++ ; write data. The NVMADR captures last table access address.

NVMCON ; Operate Key to allow program operation

; for next 5 instructions

NVMKEY ; Write the 0x55 key

NVMKEY ; Write the 0xAA key

7.4 Write Verify

Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit.

7.5 Protection Against Spurious Write

There are conditions when the device may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built-in. On power-up, the WREN bit is cleared; also, the Power-up Timer prevents EEPROM write.

The write initiate sequence and the WREN bit together, help prevent an accidental write during brown-out, power glitch or software malfunction.

DS70119B-page 52 Advance Information  2004 Microchip Technology Inc.

dsPIC30F6010

8.0 I/O PORTS

All of the device pins (except VDD, VSS, MCLR and OSC1/CLKIN) are shared between the peripherals and the parallel I/O ports.

All I/O input ports feature Schmitt Trigger inputs for improved noise immunity.

8.1 Parallel I/O (PIO) Ports

When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the Parallel Port bit will be disabled. If a peripheral is enabled, but the peripheral is not actively driving a pin, that pin may be driven by a port.

All port pins have three registers directly associated with the operation of the port pin. The data direction register (TRISx) determines whether the pin is an input or an output. If the Data Direction bit is a ‘1’, then the pin is an input. All port pins are defined as inputs after a Reset. Reads from the latch (LATx), read the latch. Writes to the latch, write the latch (LATx). Reads from the port (PORTx), read the port pins, and writes to the port pins, write the latch (LATx).

Any bit and its associated data and control registers that are not valid for a particular device will be disabled. That means the corresponding LATx and TRISx registers and the port pin will read as zeros.

When a pin is shared with another peripheral or function that is defined as an input only, it is nevertheless regarded as a dedicated port because there is no other competing source of outputs. An example is the INT4 pin.

The format of the registers for PORTA are shown in Ta bl e 8 -1 .

The TRISA (Data Direction Control) register controls the direction of the RA<7:0> pins, as well as the INTx pins and the V

REF pins. The LATA register supplies

data to the outputs, and is readable/writable. Reading the PORTA register yields the state of the input pins, while writing the PORTA register modifies the contents of the LATA register.

A parallel I/O (PIO) port that shares a pin with a peripheral is, in general, subservient to the peripheral. The peripheral’s output buffer data and control signals are provided to a pair of multiplexers. The multiplexers select whether the peripheral or the associated port has ownership of the output data and control signals of the I/O pad cell. Figure 8-2 shows how ports are shared with other peripherals, and the associated I/O cell (pad) to which they are connected. Table 8-1 shows the formats of the registers for the shared ports, PORTB through PORTG.

FIGURE 8-1: BLOCK DIAGRAM OF A DEDICATED PORT STRUCTURE

Dedicated Port Module

Data Bus

WR TRIS

WR LAT + WR Port

Read LAT

Read Port

Read TRIS

TRIS Latch

Data Latch

I/O Cell

I/O Pad

 2004 Microchip Technology Inc. Advance Information DS70119B-page 53

dsPIC30F6010

FIGURE 8-2: BLOCK DIAGRAM OF A SHARED PORT STRUCTURE

Data Bus

WR TRIS

WR LAT + WR Port

Peripheral Module

Peripheral Input Data

Peripheral Module Enable

Peripheral Output Enable

Peripheral Output Data

PIO Module

Read TRIS

TRIS Latch

Data Latch

Read LAT

Read Port

Output Multiplexers

Output Enable

Output Data

Input Data

I/O Cell

I/O Pad

8.2 Configuring Analog Port Pins

The use of the ADPCFG and TRIS registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bit set (input). If the TRIS bit is cleared (output), the digital output level (V converted.

OH or VOL) will be

When reading the PORT register, all pins configured as analog input channel will read as cleared (a low level).

Pins configured as digital inputs will not convert an analog input. Analog levels on any pin that is defined as a digital input (including the ANx pins), may cause the input buffer to consume current that exceeds the device specifications.

DS70119B-page 54 Advance Information  2004 Microchip Technology Inc.

dsPIC30F6010

0000 0000 0000 0000

1111 1111 1111 1111

1100 0110 0000 0000

0000 0000 0000 0000

— 1110 0000 0000 1010

TRISC1

—

TRISC3

1111 1111 1111 1111

— 0000 0000 0000 0000

RC1

LATC1

—

RC3

LATC3

0000 0011 1111 1111

0000 0000 0000 0000

0000 0001 1111 1111

0000 0000 0000 0000

RF8 RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0

LATF8 LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0

TRISF8 TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0

— — — — — — — — —

— — — TRISA10 TRISA9 — — — — — — — — —

— — —RA10RA9— — — — — — — — —

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

SFR

Name

TRISA 02C0 TRISA15 TRISA14

PORTA 02C2 RA15 RA14

LATA 02C4 LATA15 LATA14 — — — LATA10 LATA9 — — — — — — — — —

TABLE 8-1: dsPIC30F6010 PORT REGISTER MAP

TRISB 02C6 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0

PORTB 02C8 RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0

LATB 02CB LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0

TRISC 02CC TRISC15 TRISC14 TRISC13

PORTC 02CE RC15 RC14 RC13

LATC 02D0 LATC15 LATC14 LATC13

TRISD 02D2 TRISD15 TRISD14 TRISD13 TRISD12 TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0

PORTD 02D4 RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0

LATD 02D6 LATD15 LATD14 LATD13 LATD12 LATD11 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0

TRISE9 TRISE8 TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0

— — — — — —

TRISE 02D8

RE9 RE8 RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0

— — — — — —

PORTE 02DA

LATE9 LATE8 LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0

— — — — — —

LATE 02DC

— — — — — — —

TRISF 02EE

— — — — — — —

— — — — — — TRISG9 TRISG8 TRISG7 TRISG6 — — TRISG3 TRISG2 TRISG1 TRISG0 0000 0011 1100 1111

— — — — — — RG9 RG8 RG7 RG6 — — RG3 RG2 RG1 RG0 0000 0000 0000 0000

— — — — — — LATG9 LATG8 LATG7 LATG6 — — LATG3 LATG2 LATG1 LATG0 0000 0000 0000 0000

PORTF 02E0

LATF 02E2

TRISG 02E4

PORTG 02E6

LATG 02E8

Legend: u = uninitialized bit

 2004 Microchip Technology Inc. Advance Information DS70119B-page 55

dsPIC30F6010

8.3 Input Change Notification Module

The Input Change Notification module provides the dsPIC30F devices the ability to generate interrupt requests to the processor in response to a change-ofstate on selected input pins. This module is capable of detecting input change-of-states even in Sleep mode, when the clocks are disabled. There are 22 external signals (CN0 through CN21) that may be selected (enabled) for generating an interrupt request on a change-of-state.

Please refer to the Pin Diagram on page 3 for CN pin locations.

TABLE 8-2: INPUT CHANGE NOTIFICATION REGISTER MAP (BITS 15-8)

SFR

Name

CNEN1 00C0 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE

CNEN2 00C2

CNPU1 00C4 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE

CNPU2 00C6

Legend: u = uninitialized bit

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reset State

— — — — — — — — 0000 0000 0000 0000

0000 0000 0000 0000

TABLE 8-3: INPUT CHANGE NOTIFICATION REGISTER MAP (BITS 7-0)

SFR

Name

CNEN1 00C0 CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE

CNEN2 00C2

CNPU1 00C4 CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE

CNPU2 00C6

Legend: u = uninitialized bit

Addr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

— —

CN21IE CN20IE CN19IE CN18IE CN17IE CN16IE

CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE

0000 0000 0000 0000

DS70119B-page 56 Advance Information  2004 Microchip Technology Inc.

dsPIC30F6010

9.0 TIMER1 MODULE

This section describes the 16-bit General Purpose (GP) Timer1 module and associated operational modes. Figure 9-1 depicts the simplified block diagram of the 16-bit Timer1 Module.

Note: Timer1 is a ‘Type A’ timer. Please refer to

the specifications for a Type A timer in Section 24.0 Electrical Characteristics of this document.

The following sections provide a detailed description, including setup and control registers along with associated block diagrams for the operational modes of the timers.

The Timer1 module is a 16-bit timer which can serve as the time counter for the real-time clock, or operate as a free running interval timer/counter. The 16-bit timer has the following modes:

• 16-bit Timer

• 16-bit Synchronous Counter

• 16-bit Asynchronous Counter

Further, the following operational characteristics are supported:

• Timer gate operation

• Selectable prescaler settings

• Timer operation during CPU Idle and Sleep modes

• Interrupt on 16-bit period register match or falling edge of external gate signal

These operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1 presents a block diagram of the 16-bit timer module.

16-bit Timer Mode: In the 16-bit Timer mode, the timer increments on every instruction cycle up to a match value, preloaded into the period register PR1, then resets to 0 and continues to count.

When the CPU goes into the Idle mode, the timer will stop incrementing, unless the TSIDL (T1CON<13>) bit = 0. If TSIDL = 1, the timer module logic will resume the incrementing sequence upon termination of the CPU Idle mode.

16-bit Synchronous Counter Mode: In the 16-bit Synchronous Counter mode, the timer increments on the rising edge of the applied external clock signal, which is synchronized with the internal phase clocks. The timer counts up to a match value preloaded in PR1, then resets to 0 and continues.

When the CPU goes into the Idle mode, the timer will stop incrementing, unless the respective TSIDL bit = 0. If TSIDL = 1, the timer module logic will resume the incrementing sequence upon termination of the CPU Idle mode.

16-bit Asynchronous Counter Mode: In the 16-bit Asynchronous Counter mode, the timer increments on every rising edge of the applied external clock signal. The timer counts up to a match value preloaded in PR1, then resets to 0 and continues.

When the timer is configured for the Asynchronous mode of operation and the CPU goes into the Idle mode, the timer will stop incrementing if TSIDL = 1.

FIGURE 9-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM (TYPE A TIMER)

PR1

Equal

T1IF

Event Flag

SOSCO/

T1CK

SOSCI

TGATE

Reset

LPOSCEN

Comparator x 16

TMR1

TGATE

TCS

1 X

Gate Sync

0 1

0 0

TGATE

TON

TSYNC

(3)

TCKPS<1:0>

1, 8, 64, 256

Sync

Prescaler

 2004 Microchip Technology Inc. Advance Information DS70119B-page 57

dsPIC30F6010

9.1 Timer Gate Operation

The 16-bit timer can be placed in the Gated Time Accumulation mode. This mode allows the internal T increment the respective timer when the gate input signal (T1CK pin) is asserted high. Control bit TGATE (T1CON<6>) must be set to enable this mode. The timer must be enabled (TON = 1) and the timer clock source set to internal (TCS = 0).

When the CPU goes into the Idle mode, the timer will stop incrementing, unless TSIDL = 0. If TSIDL = 1, the timer will resume the incrementing sequence upon termination of the CPU Idle mode.

CY to

9.2 Timer Prescaler

The input clock (FOSC/4 or external clock) to the 16-bit Timer, has a prescale option of 1:1, 1:8, 1:64, and 1:256 selected by control bits TCKPS<1:0> (T1CON<5:4>). The prescaler counter is cleared when any of the following occurs:

• a write to the TMR1 register

• clearing of the TON bit (T1CON<15>)

• device Reset such as POR and BOR

However, if the timer is disabled (TON = 0), then the timer prescaler cannot be reset since the prescaler clock is halted.

TMR1 is not cleared when T1CON is written. It is cleared by writing to the TMR1 register.

9.3 Timer Operation During Sleep Mode

During CPU Sleep mode, the timer will operate if:

• The timer module is enabled (TON = 1) and

• The timer clock source is selected as external

(TCS = 1) and

• The TSYNC bit (T1CON<2>) is asserted to a logic

0, which defines the external clock source as asynchronous

When all three conditions are true, the timer will continue to count up to the period register and be reset to 0x0000.

When a match between the timer and the period register occurs, an interrupt can be generated, if the respective Timer Interrupt Enable bit is asserted.

9.4 Timer Interrupt

The 16-bit timer has the ability to generate an interrupt on period match. When the timer count matches the period register, the T1IF bit is asserted and an interrupt will be generated, if enabled. The T1IF bit must be cleared in software. The timer interrupt flag T1IF is located in the IFS0 control register in the Interrupt Controller.

When the Gated Time Accumulation mode is enabled, an interrupt will also be generated on the falling edge of the gate signal (at the end of the accumulation cycle).

Enabling an interrupt is accomplished via the respective Timer Interrupt Enable bit, T1IE. The Timer Interrupt Enable bit is located in the IEC0 control register in the Interrupt Controller.

9.5 Real-Time Clock

Timer1, when operating in Real-Time Clock (RTC) mode, provides time-of-day and event time stamping capabilities. Key operational features of the RTC are:

• Operation from 32 kHz LP oscillator

• 8-bit prescaler

•Low power

• Real-Time Clock Interrupts

These Operating modes are determined by setting the appropriate bit(s) in the T1CON Control register

FIGURE 9-2: RECOMMENDED

COMPONENTS FOR TIMER1 LP OSCILLATOR RTC

SOSCI

32.768 kHz XTAL

C1 = C2 = 18 pF; R = 100K

dsPIC30FXXXX

SOSCO

DS70119B-page 58 Advance Information  2004 Microchip Technology Inc.

dsPIC30F6010

9.5.1 RTC OSCILLATOR OPERATION

When the TON = 1, TCS = 1 and TGATE = 0, the timer increments on the rising edge of the 32 kHz LP oscillator output signal, up to the value specified in the period register, and is then reset to ‘0’.

The TSYNC bit must be asserted to a logic ‘0’ (Asynchronous mode) for correct operation.

Enabling LPOSCEN (OSCCON<1>) will disable the normal Timer and Counter modes and enable a timer carry-out wake-up event.

When the CPU enters Sleep mode, the RTC will continue to operate, provided the 32 kHz external crystal oscillator is active and the control bits have not been changed. The TSIDL bit should be cleared to ‘0’ in order for RTC to continue operation in Idle mode.

9.5.2 RTC INTERRUPTS

When an interrupt event occurs, the respective interrupt flag, T1IF, is asserted and an interrupt will be generated, if enabled. The T1IF bit must be cleared in software. The respective Timer interrupt flag, T1IF, is located in the IFS0 status register in the Interrupt Controller.

Enabling an interrupt is accomplished via the respective Timer Interrupt Enable bit, T1IE. The Timer Interrupt Enable bit is located in the IEC0 control register in the Interrupt Controller.

 2004 Microchip Technology Inc. Advance Information DS70119B-page 59

dsPIC30F6010

1111 1111 1111 1111

uuuu uuuu uuuu uuuu

0000 0000 0000 0000

—TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — TSYNC TCS —

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

TABLE 9-1: TIMER1 REGISTER MAP

DS70119B-page 60 Advance Information  2004 Microchip Technology Inc.

T1CON 0104 TON

TMR1 0100 Timer 1 Register

PR1 0102 Period Register 1

Legend: u = uninitialized bit

dsPIC30F6010

10.0 TIMER2/3 MODULE

This section describes the 32-bit General Purpose (GP) Timer module (Timer2/3) and associated operational modes. Figure 10-1 depicts the simplified block diagram of the 32-bit Timer2/3 module. Figure 10-2 and Figure 10-3 show Timer2/3 configured as two independent 16-bit timers; Timer2 and Timer3, respectively.

Note: Timer2 is a ‘Type B’ timer and Timer3 is a

‘Type C’ timer. Please refer to the appropriate timer type in Section 24.0 Electrical Characteristics of this document.

The Timer2/3 module is a 32-bit timer, which can be configured as two 16-bit timers, with selectable operating modes. These timers are utilized by other peripheral modules such as:

• Input Capture

• Output Compare/Simple PWM

The following sections provide a detailed description, including setup and control registers, along with associated block diagrams for the operational modes of the timers.

The 32-bit timer has the following modes:

• Two independent 16-bit timers (Timer2 and Timer3) with all 16-bit operating modes (except Asynchronous Counter mode)

• Single 32-bit Timer operation

• Single 32-bit Synchronous Counter

Further, the following operational characteristics are supported:

• ADC Event Trigger

• Timer Gate Operation

• Selectable Prescaler Settings

• Timer Operation during Idle and Sleep modes

• Interrupt on a 32-bit Period Register Match

These operating modes are determined by setting the appropriate bit(s) in the 16-bit T2CON and T3CON SFRs.

For 32-bit timer/counter operation, Timer2 is the LS Word and Timer3 is the MS Word of the 32-bit timer.

16-bit Mode: In the 16-bit mode, Timer2 and Timer3 can be configured as two independent 16-bit timers. Each timer can be set up in either 16-bit Timer mode or 16-bit Synchronous Counter mode. See Section 9.0, Timer1 Module, for details on these two operating modes.

The only functional difference between Timer2 and Timer3 is that Timer2 provides synchronization of the clock prescaler output. This is useful for high frequency external clock inputs.

32-bit Timer Mode: In the 32-bit Timer mode, the timer increments on every instruction cycle up to a match value, preloaded into the combined 32-bit period register PR3/PR2, then resets to 0 and continues to count.

For synchronous 32-bit reads of the Timer2/Timer3 pair, reading the LS word (TMR2 register) will cause the MS word to be read and latched into a 16-bit holding register, termed TMR3HLD.

For synchronous 32-bit writes, the holding register (TMR3HLD) must first be written to. When followed by a write to the TMR2 register, the contents of TMR3HLD will be transferred and latched into the MSB of the 32-bit timer (TMR3).

32-bit Synchronous Counter Mode: In the 32-bit Synchronous Counter mode, the timer increments on the rising edge of the applied external clock signal, which is synchronized with the internal phase clocks. The timer counts up to a match value preloaded in the combined 32-bit period register PR3/PR2, then resets to ‘0’ and continues.

When the timer is configured for the Synchronous Counter mode of operation and the CPU goes into the Idle mode, the timer will stop incrementing, unless the TSIDL (T2CON<13>) bit = 0. If TSIDL = 1, the timer module logic will resume the incrementing sequence upon termination of the CPU Idle mode.

Note: For 32-bit timer operation, T3CON control

bits are ignored. Only T2CON control bits are used for setup and control. Timer 2 clock and gate inputs are utilized for the 32-bit timer module, but an interrupt is generated with the Timer3 interrupt flag (T3IF) and the interrupt is enabled with the Timer3 Interrupt Enable bit (T3IE).

 2004 Microchip Technology Inc. Advance Information DS70119B-page 61

dsPIC30F6010

FIGURE 10-1: 32-BIT TIMER2/3 BLOCK DIAGRAM

Data Bus<15:0>

Write TMR2

Read TMR2

ADC Event Trigger

T3IF Event Flag

T2CK

TGATE

(T2CON<6>)

Reset

Equal

TMR3HLD

TMR3

MSB

Comparator x 32

PR3 PR2

TMR2

LSB

TGATE(T2CON<6>)

TCS

1 X

Sync

TGATE

TON

TCKPS<1:0>

Gate Sync

TCY

Note: Timer Configuration bit T32, T2CON(<3>) must be set to 1 for a 32-bit timer/counter operation. All control

bits are respective to the T2CON register.

0 1

0 0

Prescaler

1, 8, 64, 256

DS70119B-page 62 Advance Information  2004 Microchip Technology Inc.

FIGURE 10-2: 16-BIT TIMER2 BLOCK DIAGRAM (TYPE B TIMER)

dsPIC30F6010

T2IF

Event Flag

T2CK

TGATE

Equal

Reset

PR2

Comparator x 16

TMR2

Gate Sync

TGATE

1 X

0 1

0 0

TCS

TGATE

FIGURE 10-3: 16-BIT TIMER3 BLOCK DIAGRAM (TYPE C TIMER)

TON

Sync

TCKPS<1:0>

Prescaler

1, 8, 64, 256

ADC Event Trigger

T3IF

Event Flag

TGATE

T3CK

Equal

Reset

PR3

Comparator x 16

TMR3

Sync

TGATE

TCS

1 X

0 1

0 0

TGATE

TON

TCKPS<1:0>

Prescaler

1, 8, 64, 256

 2004 Microchip Technology Inc. Advance Information DS70119B-page 63

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10.1 Timer Gate Operation

The 32-bit timer can be placed in the Gated Time Accumulation mode. This mode allows the internal T increment the respective timer when the gate input signal (T2CK pin) is asserted high. Control bit TGATE (T2CON<6>) must be set to enable this mode. When in this mode, Timer2 is the originating clock source. The TGATE setting is ignored for Timer3. The timer must be enabled (TON = 1) and the timer clock source set to internal (TCS = 0).

The falling edge of the external signal terminates the count operation, but does not reset the timer. The user must reset the timer in order to start counting from zero.

CY to

10.2 ADC Event Trigger

When a match occurs between the 32-bit timer (TMR3/ TMR2) and the 32-bit combined period register (PR3/ PR2), a special ADC trigger event signal is generated by Timer3.

10.3 Timer Prescaler

The input clock (FOSC/4 or external clock) to the timer has a prescale option of 1:1, 1:8, 1:64, and 1:256 selected by control bits TCKPS<1:0> (T2CON<5:4> and T3CON<5:4>). For the 32-bit timer operation, the originating clock source is Timer2. The prescaler operation for Timer3 is not applicable in this mode. The prescaler counter is cleared when any of the following occurs:

• a write to the TMR2/TMR3 register

• clearing either of the TON (T2CON<15> or

T3CON<15>) bits to ‘0’

• device Reset such as POR and BOR

However, if the timer is disabled (TON = 0), then the Timer 2 prescaler cannot be reset, since the prescaler clock is halted.

TMR2/TMR3 is not cleared when T2CON/T3CON is written.

10.4 Timer Operation During Sleep Mode

During CPU Sleep mode, the timer will not operate, because the internal clocks are disabled.

10.5 Timer Interrupt

The 32-bit timer module can generate an interrupt on period match, or on the falling edge of the external gate signal. When the 32-bit timer count matches the respective 32-bit period register, or the falling edge of the external “gate” signal is detected, the T3IF bit (IFS0<7>) is asserted and an interrupt will be generated if enabled. In this mode, the T3IF interrupt flag is used as the source of the interrupt. The T3IF bit must be cleared in software.

Enabling an interrupt is accomplished via the respective Timer Interrupt Enable bit, T3IE (IEC0<7>).

DS70119B-page 64 Advance Information  2004 Microchip Technology Inc.

uuuu uuuu uuuu uuuu

1111 1111 1111 1111

0000 0000 0000 0000

dsPIC30F6010

—TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T32 —TCS —

—TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — —TCS —

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

TMR2 0106 Timer2 Register

TMR3HLD 0108 Timer3 Holding Register (For 32-bit timer operations only)

TMR3 010A Timer3 Register

PR2 010C Period Register 2

PR3 010E Period Register 3

T2CON 0110 TON

T3CON 0112 TON

TABLE 10-1: TIMER2/3 REGISTER MAP

Legend: u = uninitialized bit

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dsPIC30F6010

11.0 TIMER4/5 MODULE

This section describes the second 32-bit General Purpose (GP) Timer module (Timer4/5) and associated operational modes. Figure 11-1 depicts the simplified block diagram of the 32-bit Timer4/5 Module. Figure 11-2 and Figure 11-3 show Timer4/5 configured as two independent 16-bit timers, Timer4 and Timer5, respectively.

Note: Timer4 is a ‘Type B’ timer and Timer5 is a

‘Type C’ timer. Please refer to the appropriate timer type in Section 24.0 Electrical Characteristics of this document.

The Timer4/5 module is similar in operation to the Timer 2/3 module. However, there are some differences, which are listed below:

• The Timer4/5 module does not support the ADC Event Trigger feature

• Timer4/5 can not be utilized by other peripheral modules such as Input Capture and Output Compare

FIGURE 11-1: 32-BIT TIMER4/5 BLOCK DIAGRAM

Data Bus<15:0>

The operating modes of the Timer4/5 module are determined by setting the appropriate bit(s) in the 16-bit T4CON and T5CON SFRs.

For 32-bit timer/counter operation, Timer4 is the LS Word and Timer5 is the MS Word of the 32-bit timer.

Note: For 32-bit timer operation, T5CON control

bits are ignored. Only T4CON control bits are used for setup and control. Timer4 clock and gate inputs are utilized for the 32-bit timer module, but an interrupt is generated with the Timer5 interrupt flag (T5IF) and the interrupt is enabled with the Timer5 Interrupt Enable bit (T5IE).

T5IF Event Flag

T4CK

Write TMR4

Read TMR4

Reset

TGATE

(T4CON<6>)

Equal

TMR5HLD

TMR5

MSB

Comparator x 32

PR5 PR4

TMR4

LSB

TGATE(T4CON<6>)

Gate Sync

1 X

0 1

TCS

Sync

TGATE

TON

TCKPS<1:0>

Prescaler

1, 8, 64, 256

Note: Timer Configuration bit T32, T4CON(<3>) must be set to ‘1’ for a 32-bit timer/counter operation. All

control bits are respective to the T4CON register.

 2004 Microchip Technology Inc. Advance Information DS70119B-page 67

0 0

dsPIC30F6010

FIGURE 11-2: 16-BIT TIMER4 BLOCK DIAGRAM (TYPE B TIMER)

PR4

Equal

Comparator x 16

T4IF

Event Flag

T4CK

TGATE

Reset

TMR4

TGATE

TCS

TGATE

TON

1 X

Gate Sync

0 1

0 0

FIGURE 11-3: 16-BIT TIMER5 BLOCK DIAGRAM (TYPE C TIMER)

PR5

ADC Event Trigger

Equal

Comparator x 16

Sync

TCKPS<1:0>

Prescaler

1, 8, 64, 256

T5IF

Event Flag

T5CK

TGATE

Reset

TMR5

Sync

TGATE

TCS

1 X

0 1

0 0

TGATE

TON

TCKPS<1:0>

Prescaler

1, 8, 64, 256

DS70119B-page 68 Advance Information  2004 Microchip Technology Inc.

uuuu uuuu uuuu uuuu

1111 1111 1111 1111

0000 0000 0000 0000

dsPIC30F6010

—TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T45 —TCS —

—TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — —TCS —

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

TMR4 0114 Timer 4 Register

TMR5HLD 0116 Timer 5 Holding Register (For 32-bit operations only)

TMR5 0118 Timer 5 Register

PR4 011A Period Register 4

PR5 011C Period Register 5

T4CON 011E TON

T5CON 0120 TON

TABLE 11-1: TIMER4/5 REGISTER MAP

Legend: u = uninitialized bit

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NOTES:

DS70119B-page 70 Advance Information  2004 Microchip Technology Inc.

dsPIC30F6010

12.0 INPUT CAPTURE MODULE

The key operational features of the Input Capture module are:

This section describes the Input Capture module and associated operational modes. The features provided by this module are useful in applications requiring Frequency (Period) and Pulse measurement. Figure 12-1 depicts a block diagram of the Input Capture module. Input capture is useful for such modes as:

• Frequency/Period/Pulse Measurements

• Simple Capture Event mode

• Timer2 and Timer3 mode selection

• Interrupt on input capture event

These operating modes are determined by setting the appropriate bits in the ICxCON register (where x = 1,2,...,N). The dsPIC30F6010 device has 8 capture channels.

• Additional sources of External Interrupts

FIGURE 12-1: INPUT CAPTURE MODE BLOCK DIAGRAM

From GP Timer Module

ICx Pin

Prescaler

1, 4, 16

Synchronizer

ICM<2:0>

Mode Select

ICBNE, ICOV

ICxCON

Clock

ICI<1:0>

Edge

Detection

Logic

Interrupt

Logic

FIFO

R/W

Logic

T2_CNT

T3_CNT

16 16

ICxBUF

ICTMR

Set Flag

Data Bus

Set Flag ICxIF

ICxIF

Note: Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input

capture channels 1 through N.

12.1 Simple Capture Event Mode

The simple capture events in the dsPIC30F product family are:

• Capture every falling edge

• Capture every rising edge

12.1.1 CAPTURE PRESCALER

There are four input capture prescaler settings, specified by bits ICM<2:0> (ICxCON<2:0>). Whenever the capture channel is turned off, the prescaler counter will be cleared. In addition, any Reset will clear the prescaler counter.

• Capture every 4th rising edge

• Capture every 16th rising edge

• Capture every rising and falling edge

These simple Input Capture modes are configured by setting the appropriate bits ICM<2:0> (ICxCON<2:0>).

12.1.2 CAPTURE BUFFER OPERATION

Each capture channel has an associated FIFO buffer, which is four 16-bit words deep. There are two status flags, which provide status on the FIFO buffer:

• ICBFNE - Input Capture Buffer Not Empty

• ICOV - Input Capture Overflow

The ICBFNE will be set on the first input capture event and remain set until all capture events have been read from the FIFO. As each word is read from the FIFO, the remaining words are advanced by one position within the buffer.

 2004 Microchip Technology Inc. Advance Information DS70119B-page 71

dsPIC30F6010

In the event that the FIFO is full with four capture events and a fifth capture event occurs prior to a read of the FIFO, an overflow condition will occur and the ICOV bit will be set to a logic ‘1’. The fifth capture event is lost and is not stored in the FIFO. No additional events will be captured till all four events have been read from the buffer.

If a FIFO read is performed after the last read and no new capture event has been received, the read will yield indeterminate results.

12.1.3 TIMER2 AND TIMER3 SELECTION MODE

Each capture channel can select between one of two timers for the time base, Timer2 or Timer3.

Selection of the timer resource is accomplished through SFR bit ICTMR (ICxCON<7>). Timer3 is the default timer resource available for the input capture module.

12.1.4 HALL SENSOR MODE

When the input capture module is set for capture on every edge, rising and falling, ICM<2:0> = 001, the following operations are performed by the input capture logic:

• The input capture interrupt flag is set on every

edge, rising and falling.

• The interrupt on Capture Mode Setting bits,

ICI<1:0>, is ignored, since every capture generates an interrupt.

• A capture overflow condition is not generated in

this mode.

12.2 Input Capture Operation During

Sleep and Idle Modes

An input capture event will generate a device wake-up or interrupt, if enabled, if the device is in CPU Idle or Sleep mode.

Independent of the timer being enabled, the input capture module will wake-up from the CPU Sleep or Idle mode when a capture event occurs, if ICM<2:0> = 111 and the Interrupt Enable bit is asserted. The same wake-up can generate an interrupt, if the conditions for processing the interrupt have been satisfied. The wake-up feature is useful as a method of adding extra external pin interrupts.

12.2.1 INPUT CAPTURE IN CPU SLEEP MODE

CPU Sleep mode allows input capture module operation with reduced functionality. In the CPU Sleep mode, the ICI<1:0> bits are not applicable, and the input capture module can only function as an external interrupt source.

The capture module must be configured for interrupt only on the rising edge (ICM<2:0> = 111), in order for the input capture module to be used while the device is in Sleep mode. The prescale settings of 4:1 or 16:1 are not applicable in this mode.

12.2.2 INPUT CAPTURE IN CPU IDLE MODE

CPU Idle mode allows input capture module operation with full functionality. In the CPU Idle mode, the interrupt mode selected by the ICI<1:0> bits are applicable, as well as the 4:1 and 16:1 capture prescale settings, which are defined by control bits ICM<2:0>. This mode requires the selected timer to be enabled. Moreover, the ICSIDL bit must be asserted to a logic ‘0’.

If the input capture module is defined as ICM<2:0> = 111 in CPU Idle mode, the input capture pin will serve only as an external interrupt pin.

12.3 Input Capture Interrupts

The input capture channels have the ability to generate an interrupt, based upon the selected number of capture events. The selection number is set by control bits ICI<1:0> (ICxCON<6:5>).

Each channel provides an interrupt flag (ICxIF) bit. The respective capture channel interrupt flag is located in the corresponding IFSx Status register.

Enabling an interrupt is accomplished via the respective capture channel interrupt enable (ICxIE) bit. The Capture Interrupt Enable bit is located in the corresponding IEC Control register.

DS70119B-page 72 Advance Information  2004 Microchip Technology Inc.

uuuu uuuu uuuu uuuu

0000 0000 0000 0000

uuuu uuuu uuuu uuuu

0000 0000 0000 0000

uuuu uuuu uuuu uuuu

0000 0000 0000 0000

uuuu uuuu uuuu uuuu

0000 0000 0000 0000

uuuu uuuu uuuu uuuu

0000 0000 0000 0000

uuuu uuuu uuuu uuuu

0000 0000 0000 0000

uuuu uuuu uuuu uuuu

0000 0000 0000 0000

uuuu uuuu uuuu uuuu

0000 0000 0000 0000

dsPIC30F6010

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

IC1BUF 0140 Input 1 Capture Register

IC1CON 0142 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>

IC2BUF 0144 Input 2 Capture Register

IC2CON 0146 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>

IC3BUF 0148 Input 3 Capture Register

IC3CON 014A — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>

IC4BUF 014C Input 4 Capture Register

IC4CON 014E — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>

IC5BUF 0150 Input 5 Capture Register

IC5CON 0152 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>

IC6BUF 0154 Input 6 Capture Register

IC6CON 0156 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>

IC7BUF 0158 Input 7 Capture Register

IC7CON 015A — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>

IC8BUF 015C Input 8 Capture Register

IC8CON 015E — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>

TABLE 12-1: INPUT CAPTURE REGISTER MAP

Legend: u = uninitialized bit

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13.0 OUTPUT COMPARE MODULE

The key operational features of the Output Compare module include:

This section describes the Output Compare module and associated operational modes. The features provided by this module are useful in applications requiring operational modes such as:

• Generation of Variable Width Output Pulses

• Power Factor Correction

Figure 13-1 depicts a block diagram of the Output Compare module.

• Timer2 and Timer3 Selection mode

• Simple Output Compare Match mode

• Dual Output Compare Match mode

• Simple PWM mode

• Output Compare during Sleep and Idle modes

• Interrupt on Output Compare/PWM Event

These operating modes are determined by setting the appropriate bits in the 16-bit OCxCON SFR (where x = 1,2,3,...,N). The dsPIC30F6010 device has 8 compare channels.

OCxRS and OCxR in the figure represent the Dual Compare registers. In the dual compare mode, the OCxR register is used for the first compare and OCxRS is used for the second compare.

FIGURE 13-1: OUTPUT COMPARE MODE BLOCK DIAGRAM

Set Flag bit

OCxIF

OCxRS

From GP Timer Module

TMR2<15:0

Comparator

OCxR

OCTSEL

TMR3<15:0>

T2P2_MATCH

OCM<2:0>

Mode Select

T3P3_MATCH

Output

Logic

Output Enable

OCx

OCFA

(for x = 1, 2, 3 or 4)

or OCFB

(for x = 5, 6, 7 or 8)

Note: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare

channels 1 through N.

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dsPIC30F6010

13.1 Timer2 and Timer3 Selection Mode

Each output compare channel can select between one of two 16-bit timers; Timer2 or Timer3.

The selection of the timers is controlled by the OCTSEL bit (OCxCON<3>). Timer2 is the default timer resource for the Output Compare module.

13.2 Simple Output Compare Match Mode

When control bits OCM<2:0> (OCxCON<2:0>) = 001, 010 or 011, the selected output compare channel is

configured for one of three simple Output Compare Match modes:

• Compare forces I/O pin low

• Compare forces I/O pin high

• Compare toggles I/O pin

The OCxR register is used in these modes. The OCxR register is loaded with a value and is compared to the selected incrementing timer count. When a compare occurs, one of these Compare Match modes occurs. If the counter resets to zero before reaching the value in OCxR, the state of the OCx pin remains unchanged.

13.3 Dual Output Compare Match Mode

When control bits OCM<2:0> (OCxCON<2:0>) = 100 or 101, the selected output compare channel is configured for one of two Dual Output Compare modes, which are:

• Single Output Pulse mode

• Continuous Output Pulse mode

13.3.1 SINGLE PULSE MODE

For the user to configure the module for the generation of a single output pulse, the following steps are required (assuming timer is off):

• Determine instruction cycle time T

• Calculate desired pulse width value based on T

• Calculate time to start pulse from timer start value

of 0x0000.

• Write pulse width start and stop times into OCxR

and OCxRS compare registers (x denotes channel 1, 2, ...,N).

• Set timer period register to value equal to, or

greater than, value in OCxRS compare register.

• Set OCM<2:0> = 100.

• Enable timer, TON (TxCON<15>) = 1.

To initiate another single pulse, issue another write to set OCM<2:0> = 100.

CY.

13.3.2 CONTINUOUS PULSE MODE

For the user to configure the module for the generation of a continuous stream of output pulses, the following steps are required:

• Determine instruction cycle time T

• Calculate desired pulse value based on T

• Calculate timer to start pulse width from timer start value of 0x0000.

• Write pulse width start and stop times into OCxR and OCxRS (x denotes channel 1, 2, ...,N) compare registers, respectively.

• Set timer period register to value equal to, or greater than, value in OCxRS compare register.

• Set OCM<2:0> = 101.

• Enable timer, TON (TxCON<15>) = 1.

CY.

13.4 Simple PWM Mode

When control bits OCM<2:0> (OCxCON<2:0>) = 110 or 111, the selected output compare channel is configured for the PWM mode of operation. When configured for the PWM mode of operation, OCxR is the Main latch (read only) and OCxRS is the Secondary latch. This enables glitchless PWM transitions.

The user must perform the following steps in order to configure the output compare module for PWM operation:

1. Set the PWM period by writing to the appropriate

period register.

2. Set the PWM duty cycle by writing to the OCxRS

3. Configure the output compare module for PWM

operation.

4. Set the TMRx prescale value and enable the

Timer, TON (TxCON<15>) = 1.

13.4.1 INPUT PIN FAULT PROTECTION

FOR PWM

When control bits OCM<2:0> (OCxCON<2:0>) = 111, the selected output compare channel is again configured for the PWM mode of operation, with the additional feature of input fault protection. While in this mode, if a logic 0 is detected on the OCFA/B pin, the respective PWM output pin is placed in the high impedance input state. The OCFLT bit (OCxCON<4>) indicates whether a FAULT condition has occurred. This state will be maintained until both of the following events have occurred:

• The external FAULT condition has been removed.

• The PWM mode has been re-enabled by writing to the appropriate control bits.

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dsPIC30F6010

13.4.2 PWM PERIOD

The PWM period is specified by writing to the PRx register. The PWM period can be calculated using Equation 13-1.

EQUATION 13-1: PWM PERIOD

PWM period = [(PRx) + 1] • 4 • T

(TMRx prescale value)

PWM frequency is defined as 1 / [PWM period].

OSC •

FIGURE 13-1: PWM OUTPUT TIMING

Period

Duty Cycle

TMR3 = PR3

T3IF = 1

(Interrupt Flag)

OCxR = OCxRS

TMR3 = Duty Cycle (OCxR)

When the selected TMRx is equal to its respective period register, PRx, the following four events occur on the next increment cycle:

• TMRx is cleared.

• The OCx pin is set.

- Exception 1: If PWM duty cycle is 0x0000,

- Exception 2: If duty cycle is greater than PRx,

• The PWM duty cycle is latched from OCxRS into OCxR.

• The corresponding timer interrupt flag is set.

See Figure 13-1 for key PWM period comparisons. Timer3 is referred to in the figure for clarity.

TMR3 = PR3 T3IF = 1

(Interrupt Flag)

OCxR = OCxRS

TMR3 = Duty Cycle (OCxR)

the OCx pin will remain low.

the pin will remain high.

13.5 Output Compare Operation During CPU Sleep Mode

When the CPU enters the Sleep mode, all internal clocks are stopped. Therefore, when the CPU enters the Sleep state, the output compare channel will drive the pin to the active state that was observed prior to entering the CPU Sleep state.

For example, if the pin was high when the CPU entered the Sleep state, the pin will remain high. Likewise, if the pin was low when the CPU entered the Sleep state, the pin will remain low. In either case, the output compare module will resume operation when the device wakes up.

13.6 Output Compare Operation During CPU Idle Mode

When the CPU enters the Idle mode, the output compare module can operate with full functionality.

The output compare channel will operate during the CPU Idle mode if the OCSIDL bit (OCxCON<13>) is at logic 0 and the selected time base (Timer2 or Timer3) is enabled and the TSIDL bit of the selected timer is set to logic 0.

13.7 Output Compare Interrupts

The output compare channels have the ability to generate an interrupt on a compare match, for whichever Match mode has been selected.

For all modes except the PWM mode, when a compare event occurs, the respective interrupt flag (OCxIF) is asserted and an interrupt will be generated, if enabled. The OCxIF bit is located in the corresponding IFS Status register, and must be cleared in software. The interrupt is enabled via the respective compare interrupt enable (OCxIE) bit, located in the corresponding IEC Control register.

For the PWM mode, when an event occurs, the respective timer interrupt flag (T2IF or T3IF) is asserted and an interrupt will be generated, if enabled. The IF bit is located in the IFS0 Status register, and must be cleared in software. The interrupt is enabled via the respective Timer Interrupt Enable bit (T2IE or T3IE), located in the IEC0 Control register. The output compare interrupt flag is never set during the PWM mode of operation.

 2004 Microchip Technology Inc. Advance Information DS70119B-page 77

dsPIC30F6010

0000 0000 0000 0000

— —OCSIDL— — — — — — — — OCFLT OCTSEL OCM<2:0>

01A8

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

OC1RS 0180 Output Compare 1 Secondary Register

OC1R 0182 Output Compare 1 Main Register

OC1CON 0184

OC2RS 0186 Output Compare 2 Secondary Register

OC2R 0188 Output Compare 2 Main Register

OC2CON 018A — —OCSIDL— — — — — — — — OCFLT OCTSE OCM<2:0>

OC3RS 018C Output Compare 3 Secondary Register

OC3R 018E Output Compare 3 Main Register

OC3CON 0190

OC4RS 0192 Output Compare 4 Secondary Register

OC4R 0194 Output Compare 4 Main Register

OC4CON 0196

OC5RS 0198 Output Compare 5 Secondary Register

OC5R 019A Output Compare 5 Main Register

OC5CON 019C

OC6RS 019E Output Compare 6 Secondary Register

OC6R 01A0 Output Compare 6 Main Register

OC6CON 01A2

OC7RS 01A4 Output Compare 7 Secondary Register

OC7R 01A6 Output Compare 7 Main Register

OC7CON

OC8RS 01AA Output Compare 8 Secondary Register

OC8R 01AC Output Compare 8 Main Register

OC8CON 01AE

TABLE 13-1: OUTPUT COMPARE REGISTER MAP

Legend: u = uninitialized bit

DS70119B-page 78 Advance Information  2004 Microchip Technology Inc.

dsPIC30F6010

14.0 QUADRATURE ENCODER INTERFACE (QEI) MODULE

This section describes the Quadrature Encoder Interface (QEI) module and associated operational modes. The QEI module provides the interface to incremental encoders for obtaining mechanical position data.

The operational features of the QEI include:

• Three input channels for two phase signals and

• Count direction status

• Position Measurement (x2 and x4) mode

• Programmable digital noise filters on inputs

• Alternate 16-bit Timer/Counter mode

• Quadrature Encoder Interface interrupts

These operating modes are determined by setting the appropriate bits QEIM<2:0> (QEICON<10:8>). Figure 14-1 depicts the Quadrature Encoder Interface block diagram.

index pulse

• 16-bit up/down position counter

FIGURE 14-1: QUADRATURE ENCODER INTERFACE BLOCK DIAGRAM

Sleep Input

Synchronize

Det

TQCS

QEIM<2:0>

TQGATE

TQCKPS<1:0>

Prescaler

1, 8, 64, 256

QEIIF Event Flag

QEA

QEB

INDX

UPDN

Programmable

Digital Filter

UPDN_SRC

Programmable

Digital Filter

Programmable

Digital Filter

PCDOUT

QEICON<11>

Existing Pin Logic

Up/Down

Quadrature Encoder Interface Logic

QEIM<2:0>

Mode Select

16-bit Up/Down Counter

(POSCNT)

Comparator/

Zero Detect

Max Count Register

(MAXCNT)

Reset

Equal

 2004 Microchip Technology Inc. Advance Information DS70119B-page 79

dsPIC30F6010

14.1 Quadrature Encoder Interface Logic

A typical incremental (a.k.a. optical) encoder has three outputs: Phase A, Phase B, and an index pulse. These signals are useful and often required in position and speed control of ACIM and SR motors.

The two channels, Phase A (QEA) and Phase B (QEB), have a unique relationship. If Phase A leads Phase B, then the direction (of the motor) is deemed positive or forward. If Phase A lags Phase B, then the direction (of the motor) is deemed negative or reverse.

A third channel, termed index pulse, occurs once per revolution and is used as a reference to establish an absolute position. The index pulse coincides with Phase A and Phase B, both low.

14.2 16-bit Up/Down Position Counter Mode

The 16-bit Up/Down Counter counts up or down on every count pulse, which is generated by the difference of the Phase A and Phase B input signals. The counter acts as an integrator, whose count value is proportional to position. The direction of the count is determined by the UPDN signal, which is generated by the Quadrature Encoder Interface Logic.

14.2.1 POSITION COUNTER ERROR

CHECKING

Position count error checking in the QEI is provided for and indicated by the CNTERR bit (QEICON<15>). The error checking only applies when the position counter is configured for Reset on the Index Pulse modes (QEIM<2:0> = ‘110’ or ‘100’). In these modes, the contents of the POSCNT register is compared with the values (0xFFFF or MAXCNT+1, depending on direction). If these values are detected, an error condition is generated by setting the CNTERR bit and a QEI count error interrupt is generated. The QEI count error interrupt can be disabled by setting the CEID bit (DFLTCON<8>). The position counter continues to count encoder edges after an error has been detected. The POSCNT register continues to count up/down until a natural rollover/underflow. No interrupt is generated for the natural rollover/underflow event. The CNTERR bit is a Read/Write bit and reset in software by the user.

14.2.2 POSITION COUNTER RESET

The Position Counter Reset Enable bit, POSRES (QEI<2>) controls whether the position counter is reset when the index pulse is detected. This bit is only applicable when QEIM<2:0> = ‘100’ or ‘110’.

If the POSRES bit is set to ‘1’, then the position counter is reset when the index pulse is detected. If the POSRES bit is set to ‘0’, then the position counter is not reset when the index pulse is detected. The position counter will continue counting up or down, and will be reset on the rollover or underflow condition.

The interrupt is still generated on the detection of the index pulse and not on the position counter overflow/ underflow.

14.2.3 COUNT DIRECTION STATUS

As mentioned in the previous section, the QEI logic generates an UPDN signal, based upon the relationship between Phase A and Phase B. In addition to the output pin, the state of this internal UPDN signal is supplied to a SFR bit UPDN (QEICON<11>) as a read only bit. To place the state of this signal on an I/O pin, the SFR bit PCDOUT (QEICON<6>) must be 1.

14.3 Position Measurement Mode

There are two Measurement modes which are supported and are termed x2 and x4. These modes are selected by the QEIM<2:0> mode select bits located in SFR QEICON<10:8>.

When control bits QEIM<2:0> = 100 or 101, the x2 Measurement mode is selected and the QEI logic only looks at the Phase A input for the position counter increment rate. Every rising and falling edge of the Phase A signal causes the position counter to be incremented or decremented. The Phase B signal is still utilized for the determination of the counter direction, just as in the x4 mode.

Within the x2 Measurement mode, there are two variations of how the position counter is reset:

1. Position counter reset by detection of index

pulse, QEIM<2:0> = 100.

2. Position counter reset by match with MAXCNT,

QEIM<2:0> = 101.

When control bits QEIM<2:0> = 110 or 111, the x4 Measurement mode is selected and the QEI logic looks at both edges of the Phase A and Phase B input signals. Every edge of both signals causes the position counter to increment or decrement.

Within the x4 Measurement mode, there are two variations of how the position counter is reset:

1. Position counter reset by detection of index

pulse, QEIM<2:0> = 110.

2. Position counter reset by match with MAXCNT,

QEIM<2:0> = 111.

The x4 Measurement mode provides for finer resolution data (more position counts) for determining motor position.

DS70119B-page 80 Advance Information  2004 Microchip Technology Inc.

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14.4 Programmable Digital Noise Filters

The digital noise filter section is responsible for rejecting noise on the incoming capture or quadrature signals. Schmitt Trigger inputs and a three-clock cycle delay filter combine to reject low level noise and large, short duration noise spikes that typically occur in noise prone applications, such as a motor system.

The filter ensures that the filtered output signal is not permitted to change until a stable value has been registered for three consecutive clock cycles.

For the QEA, QEB and INDX pins, the clock divide frequency for the digital filter is programmed by bits QECK<2:0> (DFLTCON<6:4>) and are derived from the base instruction cycle T

To enable the filter output for channels QEA, QEB and INDX, the QEOUT bit must be ‘1’. The filter network for all channels is disabled on POR and BOR.

CY.

14.5 Alternate 16-bit Timer/Counter

When the QEI module is not configured for the QEI mode QEIM<2:0> = 001, the module can be configured as a simple 16-bit timer/counter. The setup and control of the auxiliary timer is accomplished through the QEICON SFR register. This timer functions identically to Timer1. The QEA pin is used as the timer clock input.

When configured as a timer, the POSCNT register serves as the Timer Count Register and the MAXCNT register serves as the Period Register. When a timer/ period register match occur, the QEI interrupt flag will be asserted.

The only exception between the general purpose timers and this timer is the added feature of external Up/ Down input select. When the UPDN pin is asserted high, the timer will increment up. When the UPDN pin is asserted low, the timer will be decremented.

Note: Changing the operational mode (i.e., from

QEI to Timer or vice versa), will not affect the Timer/Position Count Register contents.

The UPDN Control/Status bit (QEICON<11>) can be used to select the count direction state of the Timer register. When UPDN = 1, the timer will count up. When UPDN = 0, the timer will count down.

In addition, control bit UPDN_SRC (QEICON<0>) determines whether the timer count direction state is based on the logic state, written into the UPDN Control/ Status bit (QEICON<11>), or the QEB pin state. When UPDN_SRC = 1, the timer count direction is controlled from the QEB pin. Likewise, when UPDN_SRC = 0, the timer count direction is controlled by the UPDN bit.

Note: This Timer does not support the External

Asynchronous Counter mode of operation. If using an external clock source, the clock will automatically be synchronized to the internal instruction cycle.

14.6 QEI Module Operation During CPU Sleep Mode

14.6.1 QEI OPERATION DURING CPU

SLEEP MODE

The QEI module will be halted during the CPU Sleep mode.

14.6.2 TIMER OPERATION DURING CPU

SLEEP MODE

During CPU Sleep mode, the timer will not operate, because the internal clocks are disabled.

14.7 QEI Module Operation During CPU Idle Mode

Since the QEI module can function as a quadrature encoder interface, or as a 16-bit timer, the following section describes operation of the module in both modes.

14.7.1 QEI OPERATION DURING CPU IDLE

MODE

When the CPU is placed in the Idle mode, the QEI module will operate if the QEISIDL bit (QEICON<13>) = 0. This bit defaults to a logic ‘0’ upon executing POR and BOR. For halting the QEI module during the CPU Idle mode, QEISIDL should be set to ‘1’.

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14.7.2 TIMER OPERATION DURING CPU IDLE MODE

When the CPU is placed in the Idle mode and the QEI module is configured in the 16-bit Timer mode, the 16-bit timer will operate if the QEISIDL bit (QEICON<13>) = 0. This bit defaults to a logic ‘0’ upon executing POR and BOR. For halting the timer module during the CPU Idle mode, QEISIDL should be set to ‘1’.

If the QEISIDL bit is cleared, the timer will function normally, as if the CPU Idle mode had not been entered.

14.8 Quadrature Encoder Interface Interrupts

The quadrature encoder interface has the ability to generate an interrupt on occurrence of the following events:

• Interrupt on 16-bit up/down position counter

rollover/underflow

• Detection of qualified index pulse, or if CNTERR

bit is set

• Timer period match event (overflow/underflow)

• Gate accumulation event

The QEI Interrupt Flag bit, QEIIF, is asserted upon occurrence of any of the above events. The QEIIF bit must be cleared in software. QEIIF is located in the IFS2 Status register.

Enabling an interrupt is accomplished via the respective Enable bit, QEIIE. The QEIIE bit is located in the IEC2 Control register.

DS70119B-page 82 Advance Information  2004 Microchip Technology Inc.

0000 0000 0000 0000

1111 1111 1111 1111

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— QEISIDL INDX UPDN QEIM2 QEIM1 QEIM0 SWPAB PCDOUT TQGATE TQCKPS1 TQCKPS0 POSRES TQCS UPDN_SRC

— — — — — IMV1 IMV0 CEID QEOUT QECK2 QECK1 QECK0 — — — —

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

SFR

Name

QEICON 0122 CNTERR

DFLTCON 0124

POSCNT 0126 Position Counter<15:0>

MAXCNT 0128 Maximun Count<15:0>

TABLE 14-1: QEI REGISTER MAP

 2004 Microchip Technology Inc. Advance Information DS70119B-page 83

Legend: u = uninitialized bit

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NOTES:

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15.0 MOTOR CONTROL PWM MODULE

This module simplifies the task of generating multiple, synchronized Pulse Width Modulated (PWM) outputs. In particular, the following power and motion control applications are supported by the PWM module:

• Three Phase AC Induction Motor

• Switched Reluctance (SR) Motor

• Brushless DC (BLDC) Motor

• Uninterruptible Power Supply (UPS)

The PWM module has the following features:

• 8 PWM I/O pins with 4 duty cycle generators

• Up to 16-bit resolution

• ‘On-the-Fly’ PWM frequency changes

• Edge and Center Aligned Output modes

• Single Pulse Generation mode

• Interrupt support for asymmetrical updates in Center Aligned mode

• Output override control for Electrically Commutative Motor (ECM) operation

• ‘Special Event’ comparator for scheduling other peripheral events

• FAULT pins to optionally drive each of the PWM output pins to a defined state

This module contains 4 duty cycle generators, numbered 1 through 4. The module has 8 PWM output pins, numbered PWM1H/PWM1L through PWM4H/PWM4L. The eight I/O pins are grouped into high/low numbered pairs, denoted by the suffix H or L, respectively. For complementary loads, the low PWM pins are always the complement of the corresponding high I/O pin.

The PWM module allows several modes of operation which are beneficial for specific power control applications.

 2004 Microchip Technology Inc. Advance Information DS70119B-page 85

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FIGURE 15-1: PWM MODULE BLOCK DIAGRAM

PWMCON1

PWM Enable and Mode SFRs

PWMCON2

DTCON1 Dead-Time Control SFRs

DTCON2

FLTACON FAULT Pin Control SFRs

FLTBCON

16-bit Data Bus

OVDCON

PTMR

Comparator

PTPER

PTPER Buffer

PTCON

PWM Manual Control SFR

PWM Generator #4

PWM Generator

PDC4 Buffer

PDC4

Comparator

Channel 4 Dead-Time

Generator and Override Logic

Channel 3 Dead-Time

Generator and

Override Logic

Channel 2 Dead-Time

Generator and

Override Logic

Channel 1 Dead-Time

Generator and

Override Logic

Output

Driver

Block

PWM4H

PWM4L

PWM3H

PWM3L

PWM2H

PWM2L

PWM1H

PWM1L

FLTA

FLTB

Comparator

SEVTCMP

SEVTDIR

PTDIR

Special Event

Postscaler

Special Event Trigger

PWM time base

Note: Details of PWM Generator #1, #2, and #3 not shown for clarity.

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15.1 PWM Time Base

The PWM time base is provided by a 15-bit timer with a prescaler and postscaler. The time base is accessible via the PTMR SFR. PTMR<15> is a Read Only Status bit, PTDIR, that indicates the present count direction of the PWM time base. If PTDIR is cleared, PTMR is counting upwards. If PTDIR is set, PTMR is counting downwards. The PWM time base is configured via the PTCON SFR. The time base is enabled/disabled by setting/clearing the PTEN bit in the PTCON SFR. PTMR is not cleared when the PTEN bit is cleared in software.

The PTPER SFR sets the counting period for PTMR. The user must write a 15-bit value to PTPER<14:0>. When the value in PTMR<14:0> matches the value in PTPER<14:0>, the time base will either reset to 0, or reverse the count direction on the next occurring clock cycle. The action taken depends on the operating mode of the time base.

Note: If the period register is set to 0x0000, the

timer will stop counting, and the interrupt and the special event trigger will not be generated, even if the special event value is also 0x0000. The module will not update the period register, if it is already at 0x0000; therefore, the user must disable the module in order to update the period register.

The PWM time base can be configured for four different modes of operation:

• Free Running mode

• Single Shot mode

• Continuous Up/Down Count mode

• Continuous Up/Down Count mode with interrupts for double updates

These four modes are selected by the PTMOD<1:0> bits in the PTCON SFR. The Up/Down Counting modes support center aligned PWM generation. The Single Shot mode allows the PWM module to support pulse control of certain Electronically Commutative Motors (ECMs).

The interrupt signals generated by the PWM time base depend on the mode selection bits (PTMOD<1:0>) and the postscaler bits (PTOPS<3:0>) in the PTCON SFR.

15.1.1 FREE RUNNING MODE

In the Free Running mode, the PWM time base counts upwards until the value in the Time Base Period register (PTPER) is matched. The PTMR register is reset on the following input clock edge and the time base will continue to count upwards as long as the PTEN bit remains set.

When the PWM time base is in the Free Running mode (PTMOD<1:0> = 00), an interrupt event is generated each time a match with the PTPER register occurs and the PTMR register is reset to zero. The postscaler selection bits may be used in this mode of the timer to reduce the frequency of the interrupt events.

15.1.2 SINGLE SHOT MODE

In the Single Shot Counting mode, the PWM time base begins counting upwards when the PTEN bit is set. When the value in the PTMR register matches the PTPER register, the PTMR register will be reset on the following input clock edge and the PTEN bit will be cleared by the hardware to halt the time base.

When the PWM time base is in the Single Shot mode (PTMOD<1:0> = 01), an interrupt event is generated when a match with the PTPER register occurs, the PTMR register is reset to zero on the following input clock edge, and the PTEN bit is cleared. The postscaler selection bits have no effect in this mode of the timer.

15.1.3 CONTINUOUS UP/DOWN COUNTING MODES

In the Continuous Up/Down Counting modes, the PWM time base counts upwards until the value in the PTPER register is matched. The timer will begin counting downwards on the following input clock edge. The PTDIR bit in the PTCON SFR is read only and indicates the counting direction The PTDIR bit is set when the timer counts downwards.

In the Up/Down Counting mode (PTMOD<1:0> = 10), an interrupt event is generated each time the value of the PTMR register becomes zero and the PWM time base begins to count upwards. The postscaler selection bits may be used in this mode of the timer to reduce the frequency of the interrupt events.

 2004 Microchip Technology Inc. Advance Information DS70119B-page 87

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15.1.4 DOUBLE UPDATE MODE

In the Double Update mode (PTMOD<1:0> = 11), an interrupt event is generated each time the PTMR register is equal to zero, as well as each time a period match occurs. The postscaler selection bits have no effect in this mode of the timer.

The Double Update mode provides two additional functions to the user. First, the control loop bandwidth is doubled because the PWM duty cycles can be updated, twice per period. Second, asymmetrical center-aligned PWM waveforms can be generated, which are useful for minimizing output waveform distortion in certain motor control applications.

Note: Programming a value of 0x0001 in the

period register could generate a continuous interrupt pulse, and hence, must be avoided.

15.1.5 PWM TIME BASE PRESCALER

The input clock to PTMR (FOSC/4), has prescaler options of 1:1, 1:4, 1:16, or 1:64, selected by control bits PTCKPS<1:0> in the PTCON SFR. The prescaler counter is cleared when any of the following occurs:

• a write to the PTMR register

• a write to the PTCON register

• any device Reset

The PTMR register is not cleared when PTCON is written.

15.1.6 PWM TIME BASE POSTSCALER

The match output of PTMR can optionally be postscaled through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling).

The postscaler counter is cleared when any of the following occurs:

• a write to the PTMR register

• a write to the PTCON register

• any device Reset

The PTMR register is not cleared when PTCON is written.

The PWM period can be determined using Equation 15-1:

EQUATION 15-1: PWM PERIOD

CY • (PTPER + 1)

TPWM =

If the PWM time base is configured for one of the Up/ Down Count modes, the PWM period will be twice the value provided by Equation 15-1.

The maximum resolution (in bits) for a given device oscillator and PWM frequency can be determined using Equation 15-2:

(PTMR Prescale Value)

EQUATION 15-2: PWM RESOLUTION

log (2

Resolution =

log (2)

• TPWM / TCY)

15.3 Edge Aligned PWM

Edge aligned PWM signals are produced by the module when the PWM time base is in the Free Running or Single Shot mode. For edge aligned PWM outputs, the output has a period specified by the value in PTPER and a duty cycle specified by the appropriate duty cycle register (see Figure 15-2). The PWM output is driven active at the beginning of the period (PTMR = 0) and is driven inactive when the value in the duty cycle register matches PTMR.

If the value in a particular duty cycle register is zero, then the output on the corresponding PWM pin will be inactive for the entire PWM period. In addition, the output on the PWM pin will be active for the entire PWM period if the value in the duty cycle register is greater than the value held in the PTPER register.

FIGURE 15-2: EDGE ALIGNED PWM

New Duty Cycle Latched

15.2 PWM Period

PTPER is a 15-bit register and is used to set the counting period for the PWM time base. PTPER is a double buffered register. The PTPER buffer contents are loaded into the PTPER register at the following instants:

• Free Running and Single Shot modes: PTMR register is reset to zero after a match with the PTPER register.

• Up/Down Counting modes register is zero.

The value held in the PTPER buffer is automatically loaded into the PTPER register when the PWM time base is disabled (PTEN = 0).

DS70119B-page 88 Advance Information  2004 Microchip Technology Inc.

: When the PTMR

When the

PTPER

PTMR Value

Duty Cycle

Period

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15.4 Center Aligned PWM

Center aligned PWM signals are produced by the module when the PWM time base is configured in an Up/ Down Counting mode (see Figure 15-3).

The PWM compare output is driven to the active state when the value of the duty cycle register matches the value of PTMR and the PWM time base is counting downwards (PTDIR = 1). The PWM compare output is driven to the inactive state when the PWM time base is counting upwards (PTDIR = 0) and the value in the PTMR register matches the duty cycle value.

FIGURE 15-3: CENTER ALIGNED PWM

Period/2

PTPER

Duty Cycle

PTMR Value

15.5.1 DUTY CYCLE REGISTER BUFFERS

The four PWM duty cycle registers are double buffered to allow glitchless updates of the PWM outputs. For each duty cycle, there is a duty cycle register that is accessible by the user and a second duty cycle register that holds the actual compare value used in the present PWM period.

For edge aligned PWM output, a new duty cycle value will be updated whenever a match with the PTPER register occurs and PTMR is reset. The contents of the duty cycle buffers are automatically loaded into the duty cycle registers when the PWM time base is disabled (PTEN = 0) and the UDIS bit is cleared in PWMCON2.

When the PWM time base is in the Up/Down Counting mode, new duty cycle values are updated when the value of the PTMR register is zero and the PWM time base begins to count upwards. The contents of the duty cycle buffers are automatically loaded into the duty cycle registers when the PWM time base is disabled (PTEN = 0).

When the PWM time base is in the Up/Down Counting mode with double updates, new duty cycle values are updated when the value of the PTMR register is zero, and when the value of the PTMR register matches the value in the PTPER register. The contents of the duty cycle buffers are automatically loaded into the duty cycle registers when the PWM time base is disabled (PTEN = 0).

Period

15.5 PWM Duty Cycle Comparison Units

There are four 16-bit special function registers (PDC1, PDC2, PDC3 and PDC4) used to specify duty cycle values for the PWM module.

The value in each duty cycle register determines the amount of time that the PWM output is in the active state. The duty cycle registers are 16-bits wide. The LS bit of a duty cycle register determines whether the PWM edge occurs in the beginning. Thus, the PWM resolution is effectively doubled.

15.6 Complementary PWM Operation

In the Complementary mode of operation, each pair of PWM outputs is obtained by a complementary PWM signal. A dead-time may be optionally inserted during device switching, when both outputs are inactive for a short period (Refer to Section 15.7).

In Complementary mode, the duty cycle comparison units are assigned to the PWM outputs as follows:

• PDC1 register controls PWM1H/PWM1L outputs

• PDC2 register controls PWM2H/PWM2L outputs

• PDC3 register controls PWM3H/PWM3L outputs

• PDC4 register controls PWM4H/PWM4L outputs

The Complementary mode is selected for each PWM I/O pin pair by clearing the appropriate PMODx bit in the PWMCON1 SFR. The PWM I/O pins are set to Complementary mode by default upon a device Reset.

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15.7 Dead-Time Generators

Dead-time generation may be provided when any of the PWM I/O pin pairs are operating in the Complementary Output mode. The PWM outputs use PushPull drive circuits. Due to the inability of the power output devices to switch instantaneously, some amount of time must be provided between the turn off event of one PWM output in a complementary pair and the turn on event of the other transistor.

The PWM module allows two different dead-times to be programmed. These two dead-times may be used in one of two methods described below to increase user flexibility:

• The PWM output signals can be optimized for different turn off times in the high side and low side transistors in a complementary pair of transistors. The first dead-time is inserted between the turn off event of the lower transistor of the complementary pair and the turn on event of the upper transistor. The second dead-time is inserted between the turn off event of the upper transistor and the turn on event of the lower transistor.

• The two dead-times can be assigned to individual PWM I/O pin pairs. This Operating mode allows the PWM module to drive different transistor/load combinations with each complementary PWM I/O pin pair.

15.7.1 DEAD-TIME GENERATORS

Each complementary output pair for the PWM module has a 6-bit down counter that is used to produce the dead-time insertion. As shown in Figure 15-4, each dead-time unit has a rising and falling edge detector connected to the duty cycle comparison output.

15.7.2 DEAD-TIME ASSIGNMENT

The DTCON2 SFR contains control bits that allow the dead-times to be assigned to each of the complementary outputs. Table 15-1 summarizes the function of each dead-time selection control bit.

TABLE 15-1: DEAD-TIME SELECTION BITS

Bit Function

DTS1A Selects PWM1L/PWM1H active edge dead-time.

DTS1I Selects PWM1L/PWM1H inactive edge

dead-time.

DTS2A Selects PWM2L/PWM2H active edge dead-time.

DTS2I Selects PWM2L/PWM2H inactive edge

dead-time.

DTS3A Selects PWM3L/PWM3H active edge dead-time.

DTS3I Selects PWM3L/PWM3H inactive edge

dead-time.

DTS4A Selects PWM4L/PWM4H active edge dead-time.

DTS4I Selects PWM4L/PWM4H inactive edge

dead-time.

15.7.3 DEAD-TIME RANGES

The amount of dead-time provided by each dead-time unit is selected by specifying the input clock prescaler value and a 6-bit unsigned value. The amount of deadtime provided by each unit may be set independently.

Four input clock prescaler selections have been provided to allow a suitable range of dead-times, based on the device operating frequency. The clock prescaler option may be selected independently for each of the two dead-time values. The dead-time clock prescaler values are selected using the DTAPS<1:0> and DTBPS<1:0> control bits in the DTCON1 SFR. One of four clock prescaler options (T may be selected for each of the dead-time values.

After the prescaler values are selected, the dead-time for each unit is adjusted by loading two 6-bit unsigned values into the DTCON1 SFR.

The dead-time unit prescalers are cleared on the following events:

• On a load of the down timer due to a duty cycle comparison edge event.

• On a write to the DTCON1 or DTCON2 registers.

• On any device Reset.

Note: The user should not modify the DTCON1

or DTCON2 values while the PWM module is operating (PTEN = 1). Unexpected results may occur.

CY, 2TCY, 4TCY or 8TCY)

DS70119B-page 90 Advance Information  2004 Microchip Technology Inc.

FIGURE 15-4: DEAD-TIME TIMING DIAGRAM

Duty Cycle Generator

PWMxH

PWMxL

Time selected by DTSxA bit (A or B) Time selected by DTSxI bit (A or B)

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15.8 Independent PWM Output

An independent PWM Output mode is required for driving certain types of loads. A particular PWM output pair is in the Independent Output mode when the corresponding PMOD bit in the PWMCON1 register is set. No dead-time control is implemented between adjacent PWM I/O pins when the module is operating in the Independent mode and both I/O pins are allowed to be active simultaneously.

In the Independent mode, each duty cycle generator is connected to both of the PWM I/O pins in an output pair. By using the associated duty cycle register and the appropriate bits in the OVDCON register, the user may select the following signal output options for each PWM I/O pin operating in the Independent mode:

• I/O pin outputs PWM signal

• I/O pin inactive

• I/O pin active

15.9 Single Pulse PWM Operation

The PWM module produces single pulse outputs when the PTCON control bits PTMOD<1:0> = 10. Only edge aligned outputs may be produced in the Single Pulse mode. In Single Pulse mode, the PWM I/O pin(s) are driven to the active state when the PTEN bit is set. When a match with a duty cycle register occurs, the PWM I/O pin is driven to the inactive state. When a match with the PTPER register occurs, the PTMR register is cleared, all active PWM I/O pins are driven to the inactive state, the PTEN bit is cleared, and an interrupt is generated.

15.10 PWM Output Override

The PWM output override bits allow the user to manually drive the PWM I/O pins to specified logic states, independent of the duty cycle comparison units.

All control bits associated with the PWM output override function are contained in the OVDCON register. The upper half of the OVDCON register contains eight bits, POVDxH<4:1> and POVDxL<4:1>, that determine which PWM I/O pins will be overridden. The lower half of the OVDCON register contains eight bits, POUTxH<4:1> and POUTxL<4:1>, that determine the state of the PWM I/O pins when a particular output is overridden via the POVD bits.

15.10.1 COMPLEMENTARY OUTPUT MODE

When a PWMxL pin is driven active via the OVDCON register, the output signal is forced to be the complement of the corresponding PWMxH pin in the pair. Dead-time insertion is still performed when PWM channels are overridden manually.

15.10.2 OVERRIDE SYNCHRONIZATION

If the OSYNC bit in the PWMCON2 register is set, all output overrides performed via the OVDCON register are synchronized to the PWM time base. Synchronous output overrides occur at the following times:

• Edge Aligned mode, when PTMR is zero.

• Center Aligned modes, when PTMR is zero and when the value of PTMR matches PTPER.

 2004 Microchip Technology Inc. Advance Information DS70119B-page 91

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15.11 PWM Output and Polarity Control

There are three device configuration bits associated with the PWM module that provide PWM output pin control:

• HPOL configuration bit

• LPOL configuration bit

• PWMPIN configuration bit

These three bits in the FPORBOR configuration register (see Section 21) work in conjunction with the four PWM Enable bits (PWMEN<4:1>) located in the PWMCON1 SFR. The configuration bits and PWM Enable bits ensure that the PWM pins are in the correct states after a device Reset occurs. The PWMPIN configuration fuse allows the PWM module outputs to be optionally enabled on a device Reset. If PWMPIN = 0, the PWM outputs will be driven to their inactive states at Reset. If PWMPIN = 1 (default), the PWM outputs will be tri-stated. The HPOL bit specifies the polarity for the PWMxH outputs, whereas the LPOL bit specifies the polarity for the PWMxL outputs.

15.11.1 OUTPUT PIN CONTROL

The PEN<4:1>H and PEN<4:1>L control bits in the PWMCON1 SFR enable each high PWM output pin and each low PWM output pin, respectively. If a particular PWM output pin not enabled, it is treated as a general purpose I/O pin.

15.12 PWM FAULT Pins

There are two FAULT pins (FLTA and FLTB) associated with the PWM module. When asserted, these pins can optionally drive each of the PWM I/O pins to a defined state.

15.12.1 FAULT PIN ENABLE BITS

The FLTACON and FLTBCON SFRs each have 4 control bits that determine whether a particular pair of PWM I/O pins is to be controlled by the FAULT input pin. To enable a specific PWM I/O pin pair for FAULT overrides, the corresponding bit should be set in the FLTACON or FLTBCON register.

If all enable bits are cleared in the FLTACON or FLTBCON registers, then the corresponding FAULT input pin has no effect on the PWM module and the pin may be used as a general purpose interrupt or I/O pin.

Note: The FAULT pin logic can operate indepen-

dent of the PWM logic. If all the enable bits in the FLTACON/FLTBCON register are cleared, then the FAULT pin(s) could be used as general purpose interrupt pin(s). Each FAULT pin has an interrupt vector, Interrupt Flag bit and Interrupt Priority bits associated with it.

15.12.2 FAULT STATES

The FLTACON and FLTBCON special function registers have 8 bits each that determine the state of each PWM I/O pin when it is overridden by a FAULT input. When these bits are cleared, the PWM I/O pin is driven to the inactive state. If the bit is set, the PWM I/O pin will be driven to the active state. The active and inactive states are referenced to the polarity defined for each PWM I/O pin (HPOL and LPOL polarity control bits).

A special case exists when a PWM module I/O pair is in the Complementary mode and both pins are programmed to be active on a FAULT condition. The PWMxH pin always has priority in the Complementary mode, so that both I/O pins cannot be driven active simultaneously.

15.12.3 FAULT PIN PRIORITY

If both FAULT input pins have been assigned to control a particular PWM I/O pin, the FAULT state programmed for the FAULT A input pin will take priority over the FAULT B input pin.

15.12.4 FAULT INPUT MODES

Each of the FAULT input pins has two modes of operation:

• Latched Mode: When the FAULT pin is driven low, the PWM outputs will go to the states defined in the FLTACON/FLTBCON register. The PWM outputs will remain in this state until the FAULT pin is driven high and the corresponding interrupt flag has been cleared in software. When both of these actions have occurred, the PWM outputs will return to normal operation at the beginning of the next PWM cycle or half-cycle boundary. If the interrupt flag is cleared before the FAULT condition ends, the PWM module will wait until the FAULT pin is no longer asserted, to restore the outputs.

• Cycle-by-Cycle Mode: When the FAULT input pin is driven low, the PWM outputs remain in the defined FAULT states for as long as the FAULT pin is held low. After the FAULT pin is driven high, the PWM outputs return to normal operation at the beginning of the following PWM cycle or half-cycle boundary.

The Operating mode for each FAULT input pin is selected using the FLTAM and FLTBM control bits in the FLTACON and FLTBCON Special Function Registers.

Each of the FAULT pins can be controlled manually in software.

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15.13 PWM Update Lockout

For a complex PWM application, the user may need to write up to four duty cycle registers and the time base period register, PTPER, at a given time. In some applications, it is important that all buffer registers be written before the new duty cycle and period values are loaded for use by the module.

The PWM update lockout feature is enabled by setting the UDIS control bit in the PWMCON2 SFR. The UDIS bit affects all duty cycle buffer registers and the PWM time base period buffer, PTPER. No duty cycle changes or period value changes will have effect while UDIS = 1.

15.14 PWM Special Event Trigger

The PWM module has a special event trigger that allows A/D conversions to be synchronized to the PWM time base. The A/D sampling and conversion time may be programmed to occur at any point within the PWM period. The special event trigger allows the user to minimize the delay between the time when A/D conversion results are acquired and the time when the duty cycle value is updated.

The PWM special event trigger has an SFR named SEVTCMP, and five control bits to control its operation. The PTMR value for which a special event trigger should occur is loaded into the SEVTCMP register. When the PWM time base is in an Up/Down Counting mode, an additional control bit is required to specify the counting phase for the special event trigger. The count phase is selected using the SEVTDIR control bit in the SEVTCMP SFR. If the SEVTDIR bit is cleared, the special event trigger will occur on the upward counting cycle of the PWM time base. If the SEVTDIR bit is set, the special event trigger will occur on the downward count cycle of the PWM time base. The SEVTDIR control bit has no effect unless the PWM time base is configured for an Up/Down Counting mode.

15.14.1 SPECIAL EVENT TRIGGER POSTSCALER

The PWM special event trigger has a postscaler that allows a 1:1 to 1:16 postscale ratio. The postscaler is configured by writing the SEVOPS<3:0> control bits in the PWMCON2 SFR.

The special event output postscaler is cleared on the following events:

• Any write to the SEVTCMP register

• Any device Reset

15.15 PWM Operation During CPU Sleep

Mode

The FAULT A and FAULT B input pins have the ability to wake the CPU from Sleep mode. The PWM module generates an interrupt if either of the FAULT pins is driven low while in Sleep.

15.16 PWM Operation During CPU Idle

Mode

The PTCON SFR contains a PTSIDL control bit. This bit determines if the PWM module will continue to operate or stop when the device enters Idle mode. If PTSIDL = 0, the module will continue to operate. If PTSIDL = 1, the module will stop operation as long as the CPU remains in Idle mode.

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0000 0000 0000 0000

0000 0000 1111 1111

0000 0000 0000 0000

1111 1111 0000 0000

0000 0000 0000 0000

—PTSIDL— — — — — PTOPS<3:0> PTCKPS<1:0> PTMOD<1:0>

— — — FAEN4 FAEN3 FAEN2 FAEN1

— — — FBEN4 FBEN3 FBEN2 FBEN1

— PWM Time Base Period Register

— — — — PTMOD4 PTMOD3 PTMOD2 PTMOD1 PEN4H PEN3H PEN2H PEN1H PEN4L PEN3L PEN2L PEN1L

— — — — SEVOPS<3:0> — — — — — — OSYNC UDIS

— — — — — — — — DTS4A DTS4I DTS3A DTS3I DTS2A DTS2I DTS1A DTS1I

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

SFR Name

PTCON 01C0 PTEN

TABLE 15-2: 8-OUTPUT PWM REGISTER MAP

PTMR 01C2 PTDIR PWM Timer Count Value

SEVTCMP 01C6 SEVTDIR PWM Special Event Compare Register

PTPER 01C4

PWMCON1 01C8

PWMCON2 01CA

DTCON1 01CC DTBPS<1:0> Dead-Time B Value DTAPS<1:0> Dead-Time A Value

DTCON2 01CE

FLTACON 01D0 FAOV4H FAOV4L FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L FLTAM

FLTBCON 01D2 FBOV4H FBOV4L FBOV3H FBOV3L FBOV2H FBOV2L FBOV1H FBOV1L FLTBM

OVDCON 01D4 POVD4H POVD4L POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L POUT4H POUT4L POUT3H POUT3L POUT2H POUT2L POUT1H POUT1L

PDC1 01D6 PWM Duty Cycle #1 Register

PDC2 01D8 PWM Duty Cycle #2 Register

Legend: u = uninitialized bit

PDC3 01DA PWM Duty Cycle #3 Register

PDC4 01DC PWM Duty Cycle #4 Register

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16.0 SPI™ MODULE

The Serial Peripheral Interface (SPI) module is a synchronous serial interface. It is useful for communicating with other peripheral devices such as EEPROMs, shift registers, display drivers and A/D converters, or other microcontrollers. It is compatible with Motorola's SPI and SIOP interfaces.

16.1 Operating Function Description

Each SPI module consists of a 16-bit shift register, SPIxSR (where x = 1 or 2), used for shifting data in and out, and a buffer register, SPIxBUF. A control register, SPIxCON, configures the module. Additionally, a status register, SPIxSTAT, indicates various status conditions.

The serial interface consists of 4 pins: SDIx (serial data input), SDOx (serial data output), SCKx (shift clock input or output), and SSx select).

In Master mode operation, SCK is a clock output, but in Slave mode, it is a clock input.

A series of eight (8) or sixteen (16) clock pulses shifts out bits from the SPIxSR to SDOx pin and simultaneously shifts in data from SDIx pin. An interrupt is generated when the transfer is complete and the corresponding Interrupt Flag bit (SPI1IF or SPI2IF) is set. This interrupt can be disabled through an Interrupt Enable bit (SPI1IE or SPI2IE).

The receive operation is double buffered. When a complete byte is received, it is transferred from SPIxSR to SPIxBUF.

If the receive buffer is full when new data is being transferred from SPIxSR to SPIxBUF, the module will set the SPIROV bit, indicating an overflow condition. The transfer of the data from SPIxSR to SPIxBUF will not be completed and the new data will be lost. The module will not respond to SCL transitions while SPIROV is 1, effectively disabling the module until SPIxBUF is read by user software.

Transmit writes are also double buffered. The user writes to SPIxBUF. When the master or slave transfer is completed, the contents of the shift register (SPIxSR) is moved to the receive buffer. If any transmit data has been written to the buffer register, the contents of the transmit buffer are moved to SPIxSR. The received data is thus placed in SPIxBUF and the transmit data in SPIxSR is ready for the next transfer.

(active low slave

In Slave mode, data is transmitted and received as external clock pulses appear on SCK. Again, the interrupt is generated when the last bit is latched. If SSx control is enabled, then transmission and reception are enabled only when SSx will be disabled in SSx

The clock provided to the module is (F clock is then prescaled by the primary (PPRE<1:0>) and the secondary (SPRE<2:0>) prescale factors. The CKE bit determines whether transmit occurs on transition from active clock state to Idle clock state, or vice versa. The CKP bit selects the Idle state (high or low) for the clock.

= low. The SDOx output

mode with SSx high.

OSC/4). This

16.1.1 WORD AND BYTE COMMUNICATION

A control bit, MODE16 (SPIxCON<10>), allows the module to communicate in either 16-bit or 8-bit mode. 16-bit operation is identical to 8-bit operation, except that the number of bits transmitted is 16 instead of 8.

The user software must disable the module prior to changing the MODE16 bit. The SPI module is reset when the MODE16 bit is changed by the user.

A basic difference between 8-bit and 16-bit operation is that the data is transmitted out of bit 7 of the SPIxSR for 8-bit operation, and data is transmitted out of bit 15 of the SPIxSR for 16-bit operation. In both modes, data is shifted into bit 0 of the SPIxSR.

16.1.2 SDOx DISABLE

A control bit, DISSDO, is provided to the SPIxCON register to allow the SDOx output to be disabled. This will allow the SPI module to be connected in an input only configuration. SDO can also be used for general purpose I/O.

16.2 Framed SPI Support

The module supports a basic framed SPI protocol in Master or Slave mode. The control bit FRMEN enables framed SPI support and causes the SSx the frame synchronization pulse (FSYNC) function. The control bit SPIFSD determines whether the SSx pin is an input or an output (i.e., whether the module receives or generates the frame synchronization pulse). The frame pulse is an active high pulse for a single SPI clock cycle. When frame synchronization is enabled, the data transmission starts only on the subsequent transmit edge of the SPI clock.

pin to perform

Note: Both the transmit buffer (SPIxTXB) and

the receive buffer (SPIxRXB) are mapped to the same register address, SPIxBUF.

In Master mode, the clock is generated by prescaling the system clock. Data is transmitted as soon as a value is written to SPIxBUF. The interrupt is generated at the middle of the transfer of the last bit.

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FIGURE 16-1: SPI BLOCK DIAGRAM

Read Write

Internal

Data Bus

Shift

clock

Clock

Control

SPIxBUF

Transmit

Edge

Select

SDIx

SDOx

SSx

SCKx

Note: x = 1 or 2.

SPIxBUF

Receive

SPIxSR

bit0

SS & FSYNC

Control

FIGURE 16-2: SPI MASTER/SLAVE CONNECTION

SPI Master

SDOx

Secondary

Prescaler

1,2,4,6,8

Enable Master Clock

SDIy

SPI Slave

Primary

Prescaler

1, 4, 16, 64

Serial Input Buffer

(SPIxBUF)

Shift Register

(SPIxSR)

MSb

PROCESSOR 1

Note: x = 1 or 2, y = 1 or 2.

LSb

SDIx

SCKx

Serial Clock

SDOy

SCKy

Serial Input Buffer

(SPIyBUF)

Shift Register

(SPIySR)

MSb

PROCESSOR 2

LSb

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16.3 Slave Select Synchronization

The SSx pin allows a Synchronous Slave mode. The SPI must be configured in SPI Slave mode, with SSx pin control enabled (SSEN = 1). When the SSx pin is low, transmission and reception are enabled, and the SDOx pin is driven. When SSx pin is no longer driven. Also, the SPI module is resynchronized, and all counters/control circuitry are reset. Therefore, when the SSx again, transmission/reception will begin at the MS bit, even if SSx transmit/receive.

had been de-asserted in the middle of a

pin goes high, the SDOx

pin is asserted low

16.4 SPI Operation During CPU Sleep

Mode

During Sleep mode, the SPI module is shut-down. If the CPU enters Sleep mode while an SPI transaction is in progress, then the transmission and reception is aborted.

The transmitter and receiver will stop in Sleep mode. However, register contents are not affected by entering or exiting Sleep mode.

16.5 SPI Operation During CPU Idle

Mode

When the device enters Idle mode, all clock sources remain functional. The SPISIDL bit (SPIxSTAT<13>) selects if the SPI module will stop or continue on Idle. If SPISIDL = 0, the module will continue to operate when the CPU enters Idle mode. If SPISIDL = 1, the module will stop when the CPU enters Idle mode.

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0000 0000 0000 0000

— SPISIDL — — — — — — SPIROV — — — — SPITBF SPIRBF

— FRMEN SPIFSD — DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

SFR

Name

SPI1STAT 0220 SPIEN

SPI1BUF 0224 Transmit and Receive Buffer

Legend: u = uninitialized bit

TABLE 16-1: SPI1 REGISTER MAP

SPI1CON 0222

—SPISIDL— — — — — —SPIROV — — — — SPITBF SPIRBF

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

TABLE 16-2: SPI2 REGISTER MAP

SPI2STAT 0226 SPIEN

SPI2CON 0228 — FRMEN SPIFSD — DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0

SPI2BUF 022A Transmit and Receive Buffer

Legend: u = uninitialized bit

DS70119B-page 98 Advance Information  2004 Microchip Technology Inc.

Microchip Technology dsPIC30F6010 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1.0 DEVICE OVERVIEW

2.0 CPU ARCHITECTURE OVERVIEW

2.1 Core Overview

2.2 Programmer’s Model

2.3 Divide Support

2.4 DSP Engine

3.0 MEMORY ORGANIZATION

3.1 Program Address Space

3.2 Data Address Space

4.0 ADDRESS GENERATOR UNITS

4.1 Instruction Addressing Modes

4.2 Modulo Addressing

4.3 Bit-Reversed Addressing

5.0 INTERRUPTS

5.1 Interrupt Priority

5.2 Reset Sequence

5.3 Traps

5.4 Interrupt Sequence

5.5 Alternate Vector Table

5.6 Fast Context Saving

5.7 External Interrupt Requests

5.8 Wake-up from Sleep and Idle

6.0 FLASH PROGRAM MEMORY

6.1 In-Circuit Serial Programming (ICSP)

6.2 Run Time Self-Programming (RTSP)

6.3 Table Instruction Operation Summary

6.4 RTSP Operation

6.5 RTSP Control Registers

6.6 Programming Operations

7.0 DATA EEPROM MEMORY

7.1 Reading the Data EEPROM

7.2 Erasing Data EEPROM

7.3 Writing to the Data EEPROM

7.4 Write Verify

7.5 Protection Against Spurious Write

8.0 I/O PORTS

8.1 Parallel I/O (PIO) Ports

8.2 Configuring Analog Port Pins

8.3 Input Change Notification Module

9.0 TIMER1 MODULE

9.1 Timer Gate Operation

9.2 Timer Prescaler

9.3 Timer Operation During Sleep Mode

9.4 Timer Interrupt

9.5 Real-Time Clock

10.0 TIMER2/3 MODULE

10.1 Timer Gate Operation

10.2 ADC Event Trigger

10.3 Timer Prescaler

10.4 Timer Operation During Sleep Mode

10.5 Timer Interrupt

11.0 TIMER4/5 MODULE

12.0 INPUT CAPTURE MODULE

12.1 Simple Capture Event Mode

12.3 Input Capture Interrupts

13.0 OUTPUT COMPARE MODULE

13.1 Timer2 and Timer3 Selection Mode

13.2 Simple Output Compare Match Mode

13.3 Dual Output Compare Match Mode

13.4 Simple PWM Mode

13.5 Output Compare Operation During CPU Sleep Mode

13.6 Output Compare Operation During CPU Idle Mode

13.7 Output Compare Interrupts

14.0 QUADRATURE ENCODER INTERFACE (QEI) MODULE

14.1 Quadrature Encoder Interface Logic

14.2 16-bit Up/Down Position Counter Mode

14.3 Position Measurement Mode

14.4 Programmable Digital Noise Filters

14.5 Alternate 16-bit Timer/Counter

14.6 QEI Module Operation During CPU Sleep Mode

14.7 QEI Module Operation During CPU Idle Mode

14.8 Quadrature Encoder Interface Interrupts

15.0 MOTOR CONTROL PWM MODULE

15.1 PWM Time Base

15.3 Edge Aligned PWM

15.2 PWM Period