Microchip Technology dsPIC33, dsPIC24 Reference Manual

HIGHLIGHTS

Liquid Crystal Display (LCD)

This section of the manual contains the following major topics:

1.0 Introduction ....................................................................................................................... 2

2.0 LCD Registers................................................................................................................... 3

3.0 LCD Segment Pins Configuration..................................................................................... 6

4.0 LCD Clock Source Selection............................................................................................. 8

5.0 LCD Bias Types ................................................................................................................ 9

6.0 LCD Multiplex Types....................................................................................................... 21

7.0 Segment Enables............................................................................................................ 22

8.0 Pixel Control.................................................................................................................... 22

9.0 LCD Frame Frequency ................................................................................................... 22

10.0 LCD Waveform Generation............................................................................................. 22

11.0 LCD Interrupts................................................................................................................. 36

12.0 Configuring the LCD Module........................................................................................... 38

13.0 Operation During Sleep .................................................................................................. 39

14.0 Registers......................................................................................................................... 40

15.0 Revision History.............................................................................................................. 41

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dsPIC33/PIC24 Family Reference Manual

COM<7:0>

Timing Control

Data Bus

SOSC

FRC Oscillator

LPRC Oscillator

512

to

64

MUX

SEG<63:0>

To I/O Pins

32 x 16 (= 8x 64)

LCD DATA

LCDCON

LCDPS

LCDSEx

LCDDATA0

LCDDATA1

LCDDATA30

LCDDATA31

.
.
.

LCD Bias Generation

LCD Clock

Source Select

LCD

Charge Pump

64

8

Bias

Voltage

16

(Secondary Oscillator)

Resistor Ladder

1.0 INTRODUCTION

The Liquid Crystal Display (LCD) driver module generates the timing control to drive a Static or
Multiplexed LCD panel. In the 100-pin devices (PIC24FJXXXGA3XX), the module drives panels
of up to eight commons and up to 60 segments when 5 to 8 commons are used, and up to
64 segments when 1 to 4 commons are used. It also provides control of the LCD pixel data.

The LCD driver module supports:

• Direct driving of LCD panel

• Three LCD clock sources with selectable prescaler

• Up to eight commons:

- Static (one common)

- 1/2 Multiplex (two commons)

- 1/3 Multiplex (three commons)

- 1/8 Multiplex (eight commons)

• Up to 60 segments (in 100-pin devices when 1/5-1/8 Multiplex is selected), 64 (in 100-pin
devices when up to 1/4 Multiplex is selected), 46 (in 80-pin devices when 1/5-1/8 Multiplex
is selected), 50 (in 80-pin devices when up to 1/4 Multiplex is selected), 30 (in 64-pin
devices when 1/5-1/8 Multiplex is selected) and 34 (in 64-pin devices when up to
1/4 Multiplex is selected)

• Static, 1/2 or 1/3 LCD Bias

• On-chip Bias generator with dedicated charge pump to support a range of fixed and
variable Bias options

• Internal resistors for Bias voltage generation

• Software contrast control for LCD using the internal biasing

A simplified block diagram of the module is shown in Figure 1-1.

Figure 1-1: LCD Driver Module Block Diagram

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2.0 LCD REGISTERS

The LCD driver module has 40 registers:

• LCD Control Register (LCDCON)

• LCD Phase Register (LCDPS)

• LCD Voltage Regulator Control Register (LCDREG)

• LCD Reference Ladder Control Register (LCDREF)

• Four LCD Segment Enable Registers (LCDSE3:LCDSE0)

• 32 LCD Data Registers (LCDDATA31:LCDDATA0)

The LCDCON register, shown in Register 2-1, controls the overall operation of the module. Once
the module is configured, the LCDEN (LCDCON<15>) bit is used to enable or disable the LCD
module. The LCD panel can also operate during Sleep by clearing the SLPEN (LCDCON<6>) bit.

The LCDPS register, shown in Register 2-2, configures the LCD clock source prescaler and the

type of waveform: Type-A or Type-B. For details on these features, see Section 4.0 “L CD Clock

Source Selection”, Table 14-1 and Section 10.0 “LCD Waveform Generation”.

Liquid Crystal Display (LCD)

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LMUX<2:0> Multiplex Bias

111 1/8 MUX (COM<7:0>) 1/3
110 1/7 MUX (COM<6:0>) 1/3
101 1/6 MUX (COM<5:0>) 1/3
100 1/5 MUX (COM<4:0>) 1/3
011 1/4 MUX (COM<3:0>) 1/3
010 1/3 MUX (COM<2:0>) 1/2 or 1/3
001 1/2 MUX (COM<1:0>) 1/2 or 1/3
000 Static (COM0) Static

Register 2-1: LCDCON: LCD Control Register

R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

LCDEN

bit 15 bit 8

U-0 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— SLPEN WERR CS1 CS0 LMUX2 LMUX1 LMUX0

bit 7 bit 0

Legend: C = Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 LCDEN: LCD Driver Enable bit

bit 14 Unimplemented: Read as ‘0’
bit 13 LCDSIDL: LCD Stop in CPU Idle Mode Control bit

bit 12-7 Unimplemented: Read as ‘0’
bit 6 SLPEN: LCD Driver Enable in Sleep Mode bit

bit 5 WERR: LCD Write Failed Error bit

bit 4-3 CS<1:0>: Clock Source Select bits

bit 2-0 LMUX<2:0>: LCD Commons Select bits

— LCDSIDL — — — — —

1 = LCD driver module is enabled
0 = LCD driver module is disabled

1 = LCD driver halts in CPU Idle mode
0 = LCD driver continues to operate in CPU Idle mode

1 = LCD driver module is disabled in Sleep mode
0 = LCD driver module is enabled in Sleep mode

1 = LCDDATAx register is written while WA (LCDPS<4>) = 0 (must be cleared in software)
0 = No LCD write error

00 =FRC
01 =LPRC
1x =SOSC

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Liquid Crystal Display (LCD)

Register 2-2: LCDPS: LCD Phase Register

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

WFT BIASMD LCDA WA LP3 LP2 LP1 LP0

bit 7 bit 0

Legend: r = Reserved bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-8 Unimplemented: Read as ‘0’
bit 7 WFT: Waveform Type Select bit

1 = Type-B waveform (phase changes on each frame boundary)
0 = Type-A waveform (phase changes within each common type)

bit 6 BIASMD: Bias Mode Select bit

When LMUX<2:0> =
0 = Static Bias mode/1/3 Bias mode (do not set this bit to ‘1’)

When LMUX<2:0> = 001 or 010:

1 = 1/2 Bias mode
0 = 1/3 Bias mode

bit 5 LCDA: LCD Active Status bit

1 = LCD driver module is active
0 = LCD driver module is inactive

bit 4 WA: LCD Write Allow Status bit

1 = Write into the LCDDATAx registers is allowed
0 = Write into the LCDDATAx registers is not allowed

bit 3-0 LP<3:0>: LCD Prescaler Select bits

1111 = 1:16
1110 = 1:15
1101 = 1:14
1100 = 1:13
1011 = 1:12
1010 = 1:11
1001 = 1:10
1000 = 1:9
0111 = 1:8
0110 = 1:7
0101 = 1:6
0100 = 1:5
0011 = 1:4
0010 = 1:3
0001 = 1:2
0000 = 1:1

000 or 011-111:

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3.0 LCD SEGMENT PINS CONFIGURATION

The LCDSEx registers configure the functions of the port pins. Setting the segment enable bit for
a particular segment configures that pin as an LCD driver. There are four LCD Segment Enable
registers, as shown in Table 3-1. The prototype LCDSEx register is shown in Register 3-1.

Table 3-1: LCDSEx Registers and Associated Segments

Register Segments

LCDSE0 Seg 15:Seg 0

LCDSE1 Seg 31:Seg 16

LCDSE2 Seg 47:Seg 32

LCDSE3 Seg 63:Seg 48

Once the module is initialized for the LCD panel, the individual bits of the LCDDATAx registers
are cleared, or set, to represent a clear or dark pixel, respectively.

Specific sets of LCDDATAx registers are used with specific segments and common signals. Each
bit represents a unique combination of a specific segment connected to a specific common.

Individual LCDDATAx bits are named by the convention, “SxxCy”, with “xx” as the segment
number and “y” as the common number. The relationship is summarized in Register 2-2. The
prototype LCDDATAx register is shown in Register 3-2.

Note: Not all LCDSEx and LCDDATAx registers are implemented in all devices. Refer to

the specific device data sheet for more details.

Register 3-1: LCDSEx: LCD Segment x Enable Register

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SE(n+15) SE(n+14) SE(n+13) SE(n+12) SE(n+11) SE(n+10) SE(n+9) SE(n+8)

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SE(n+7) SE(n+6) SE(n+5) SE(n+4) SE(n+3) SE(n+2) SE(n+1) SE(n)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 SE(n + 15):SE(n): Segment Enable bits

For LCDSE0: n = 0
For LCDSE1: n = 16
For LCDSE2: n = 32
For LCDSE3: n = 48

1 = Segment function of the pin is enabled; digital I/O is disabled
0 = Segment function of the pin is disabled

DS30009740B-page 6  2010-2013 Microchip Technology Inc.

Liquid Crystal Display (LCD)

Register 3-2: LCDDATAx: LCD Data x Register

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

S(n+15)Cy S(n+14)Cy S(n+13)Cy S(n+12)Cy S(n+11)Cy S(n+10)Cy S(n+9)Cy S(n+8)Cy

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

S(n+7)Cy S(n+6)Cy S(n+5)Cy S(n+4)Cy S(n+3)Cy S(n+2)Cy S(n+1)Cy S(n)Cy

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 S(n + 15)Cy:S(n)Cy: Pixel On bits

For registers, LCDDATA0 through LCDDATA3: n = (16x), y = 0
For registers, LCDDATA4 through LCDDATA7: n = (16(x – 4)), y = 1
For registers, LCDDATA8 through LCDDATA11: n = (16(x – 8)), y = 2
For registers, LCDDATA12 through LCDDATA15: n = (16(x – 12)), y = 3
For registers, LCDDATA16 through LCDDATA19: n = (16(x – 16)), y = 4
For registers, LCDDATA20 through LCDDATA23: n = (16(x – 20)), y = 5
For registers, LCDDATA24 through LCDDATA27: n = (16(x – 24)), y = 6
For registers, LCDDATA28 through LCDDATA31: n = (16(x – 28)), y = 7

1 = Pixel on
0 = Pixel off

Table 3-2: LCDDATAx Registers and Bits for Segment and COM Combinations

COM Lines

0

1

2

3

4

5

6

7

0 to 15 16 to 31 32 to 47 48 to 64

LCDDATA0
S00C0:S15C0

LCDDATA4
S00C1:S15C1

LCDDATA8
S00C2:S15C2

LCDDATA12
S00C3:S15C3

LCDDATA16
S00C4:S15C4

LCDDATA20
S00C5:S15C5

LCDDATA24
S00C6:S15C6

LCDDATA28
S00C7:S15C7

LCDDATA1
S16C0:S31C0

LCDDATA5
S16C1:S31C1

LCDDATA9
S16C2:S31C2

LCDDATA13
S16C3:S31C3

LCDDATA17
S16C4:S31C4

LCDDATA21
S16C5:S31C5

LCDDATA25
S16C6:S31C6

LCDDATA29
S16C7:S31C7

Segments

LCDDATA2
S32C0:S47C0

LCDDATA6
S32C1:S47C1

LCDDATA10
S32C2:S47C2

LCDDATA14
S32C3:S47C3

LCDDATA18
S32C4:S47C4

LCDDATA22
S32C5:S47C5

LCDDATA26
S32C6:S47C6

LCDDATA30
S32C7:S47C7

LCDDATA3
S48C0:S63C0

LCDDATA7
S48C1:S63C1

LCDDATA11
S48C2:S63C2

LCDDATA15
S48C3:S63C3

LCDDATA19
S48C4:S59C4

LCDDATA23
S48C5:S69C5

LCDDATA27
S48C6:S59C6

LCDDATA31
S48C7:S59C7

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dsPIC33/PIC24 Family Reference Manual

CS<1:0>

SOSC Oscillator

(32 kHz)

LPRC Oscillator

(31.25 kHz)

÷4

LMUX<2:0>

4-Bit Prog Prescaler

÷1, 2, 3....8

Ring Counter

LMUX<2:0>

COM0

COM1

COM2

COM7

÷8192

(8 MH

Z)

÷2

÷32

÷32

LP<2:0>

(LCDCON<4:3>)

(LCDCON<2:0>)

(LCDCON< 2:0>)

(LCDPS<2:0>)

FRC Oscillator

STAT

1/2 MUX

MUX

4.0 LCD CLOCK SOURCE SELECTION

The LCD driver module has three possible clock sources:

• FRC/8192

• SOSC Clock/32

•LPRC/32

The first clock source is the 8 MHz Fast Internal RC (FRC) oscillator, divided by 8,192. This
divider ratio is chosen to provide about 1 kHz output. The divider is not programmable. Instead,
the LCD Prescaler bits, LCDPS<3:0>, are used to set the LCD frame clock rate.

The second clock source is the SOSC oscillator/32. This also outputs about 1 kHz when a

32.768 kHz crystal is used with the SOSC oscillator. To use the SOSC oscillator as a clock

source, set the SOSCEN (OSCCON<1>) bit.

The third clock source is a 31.25 kHz internal LPRC oscillator/32 that provides approximately
1 kHz output.

The second and third clock sources may be used to continue running the LCD while the
processor is in Sleep.

These clock sources are selected through the bits, CS<1:0> (LCDCON<4:3>).

4.1 LCD Prescaler

A 16-bit counter is available as a prescaler for the LCD clock. The prescaler is not directly read­able or writable. Its value is set by the LP<2:0> bits (LCDPS<2:0>) that determine the prescaler
assignment and prescale ratio.

Selectable prescale values are from 1:1 through 1:16, in increments of one.

Figure 4-1: LCD Clock Generation

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5.0 LCD BIAS TYPES

The LCD module can be configured in one of three Bias types:

• Static Bias (Two Voltage Levels: V

• 1/2 Bias (Three Voltage Levels: VSS, 1/2 VDD and VDD)

• 1/3 Bias (Four Voltage Levels: VSS, 1/3 VDD, 2/3 VDD and VDD)

LCD Bias voltages can be generated with an internal resistor ladder, internal Bias generator or
external resistor ladder.

5.1 Internal Resistor Biasing

This mode does not use external resistors, but rather internal resistor ladders that are configured
to generate the Bias voltage.

The internal reference ladder actually consists of three separate ladders. Disabling the internal
reference ladder disconnects all of the ladders, allowing external voltages to be supplied.

Depending on the total resistance of the resistor ladders, the biasing can be classified as low,
medium or high power.

Table 5-1 shows the total resistance of each of the ladders. Figure 5-1 shows the internal resister

ladder connections. When the internal resistor ladder is selected, the Bias voltage will be internal;
it can also provide software contrast control (using LCDCST<2:0>).

Table 5-1: Internal Resistance Ladder Power Modes

Liquid Crystal Display (LCD)

SS and VDD)

Nominal

Power Mode

Low 3 MΩ 1 µA

Medium 300 kΩ 10 µA

High 30 kΩ 100 µA

Resistance of
Entire Ladder

DD

I

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LCDBIAS3

LCDBIAS2

LCDBIAS1

VLCD3PE

VLCD2PE

VLCD1PE

LCDCST<2:0>

LCDIRE

LRLAT<2:0>

A Power Mode

B Power Mode

LRLAP<1:0> LRLBP<1:0>

Low

Resistor

Ladder

Medium
Resistor

Ladder

High

Resistor

Ladder

VDD

Figure 5-1: LCD Bias Internal Resistor Ladder Connection Diagram

There are two power modes, designated as “Mode A” and “Mode B”. Mode A is set by the bits,
LRLAP<1:0>, and Mode B by the LRLBP<1:0> bits. The resistor ladder to use for Modes A and
B are selected by the bits, LRLAP<1:0> and LRLBP<1:0>, respectively.

Each ladder has a matching contrast control ladder, tuned to the nominal resistance of the refer­ence ladder. This contrast control resistor can be controlled by the LCDCST<2:0> bits
(LCDREF<13:11>). Disabling the internal reference ladder results in all of the ladders being
disconnected, allowing external voltages to be supplied.

To get additional current in High-Power mode, when LRLAP<1:0> (LCDREF<7:6>) = 11, both
the medium and high-power resistor ladders are activated.

Whenever the LCD module is inactive (LCDA (LCDPS<5>) = 0), the reference ladder will be
turned off.

DS30009740B-page 10  2010-2013 Microchip Technology Inc.

Liquid Crystal Display (LCD)

Single Segment Time

‘H00 ‘H01 ‘H02 ‘H03 ‘H04 ‘H05 ‘H06 ‘H07 ‘H1E ‘H1F ‘H00 ‘H01

‘H3

Power Mode A Power Mode B Mode A

LRLAT<2:0>

lcd_32x_clk

cnt<4:0>

lcd_clk

LRLAT<2:0>

Segment Data

Power Mode

5.1.1 AUTOMATIC POWER MODE SWITCHING

As an LCD segment is electrically only a capacitor, current is drawn only during the interval when
the voltage is switching. To minimize total device current, the LCD reference ladder can be oper­ated in a different power mode for the transition portion of the duration. This is controlled by the
LCDREF register.

Mode A Power mode is active for a programmable time, beginning at the time when the LCD
segment waveform is transitioning. The LRLAT<2:0> (LCDREF<2:0>) bits select how long the
transition or if the Mode A is active. Mode B Power mode is active for the remaining time before
the segments or commons change again.

As shown in Figure 5-2, there are 32 counts in a single segment time. Type-A can be chosen
during the time when the waveform is in transition. Type-B can be used when the clock is stable
or not in transition.

By using this feature of automatic power switching using Type-A/Type-B, the power consumption
can be optimized for a given contrast.

Figure 5-2: LCD Reference Ladder Power Mode Switching Diagram

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LCDCST<2:0>

Analog

RR RR

7 Stages

MUX

To Top of
Reference Ladder

7

0

3

VDD

Internal Reference

Contrast Control

5.1.2 CONTRAST CONTROL

The LCD contrast control circuit consists of a 7-tap resistor ladder, controlled by the
LCDCST<2:0> bits (see Figure 5-3).

Figure 5-3: Internal Reference and Contrast Control Block Diagram

5.1.3 INTERNAL REFERENCE

Under firmware control, an internal reference for the LCD Bias voltages can be enabled. When
enabled, the source of this voltage can be V

When no internal reference is selected, the LCD contrast control circuit is disabled and the LCD
Bias must be provided externally. Whenever the LCD module is inactive (LCDA = 0), the internal
reference will be turned off.

DD.

5.1.4 VLCDxPE PINS

The VLCD3PE, VLCD2PE and VLCD1PE pins provide the ability for an external LCD Bias
network to be used instead of the internal ladder. Use of the VLCDxPE pins does not prevent use
of the internal ladder.

Each VLCDxPE pin has an independent control in the LCDREF register, allowing access to any
or all of the LCD Bias signals.

This architecture allows for maximum flexibility in different applications. The VLCDxPE pins could
be used to add capacitors to the internal reference ladder for increasing the drive capacity. For
applications where the internal contrast control is insufficient, the firmware can choose to enable
only the VLCD3PE pin, allowing an external contrast control circuit to use the internal reference
divider.

DS30009740B-page 12  2010-2013 Microchip Technology Inc.

Liquid Crystal Display (LCD)

Register 5-1: LCDREF: LCD Reference Ladder Control Register

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

LCDIRE

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0

LRLAP1 LRLAP0 LRLBP1 LRLBP0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 LCDIRE: LCD Internal Reference Enable bit

bit 14 Unimplemented: Read as ‘0’
bit 13-11 LCDCST<2:0>: LCD Contrast Control bits

bit 10 VLCD3PE: LCD Bias 3 Pin Enable bit

bit 9 VLCD2PE: LCD Bias 2 Pin Enable bit

bit 8 VLCD1PE: LCD Bias 1 Pin Enable bit

bit 7-6 LRLAP<1:0>: LCD Reference Ladder A Time Power Control bits

bit 5-4 LRLBP<1:0>: LCD Reference Ladder B Time Power Control bits

bit 3 Unimplemented: Read as ‘0’

— LCDCST2 LCDCST1 LCDCST0 VLCD3PE VLCD2PE VLCD1PE

— LRLAT2 LRLAT1 LRLAT0

1 = Internal LCD reference is enabled and connected to the internal contrast control circuit
0 = Internal LCD reference is disabled

Selects the Resistance of the LCD Contrast Control Resistor Ladder:

111 = Resistor ladder is at maximum resistance (minimum contrast)
110 = Resistor ladder is at 6/7th of maximum resistance
101 = Resistor ladder is at 5/7th of maximum resistance
100 = Resistor ladder is at 4/7th of maximum resistance
011 = Resistor ladder is at 3/7th of maximum resistance
010 = Resistor ladder is at 2/7th of maximum resistance
001 = Resistor ladder is at 1/7th of maximum resistance
000 = Minimum resistance (maximum contrast); resistor ladder is shorted

1 = Bias 3 level is connected to the external pin, LCDBIAS3
0 = Bias 3 level is internal (internal resistor ladder)

1 = Bias 2 level is connected to the external pin, LCDBIAS2
0 = Bias 2 level is internal (internal resistor ladder)

1 = Bias 1 level is connected to the external pin, LCDBIAS1
0 = Bias 1 level is internal (internal resistor ladder)

During Time Interval A:

11 = Internal LCD reference ladder is powered in High-Power mode
10 = Internal LCD reference ladder is powered in Medium Power mode
01 = Internal LCD reference ladder is powered in Low-Power mode
00 = Internal LCD reference ladder is powered down and unconnected

During Time Interval B:

11 = Internal LCD reference ladder is powered in High-Power mode
10 = Internal LCD reference ladder is powered in Medium Power mode
01 = Internal LCD reference ladder is powered in Low-Power mode
00 = Internal LCD reference ladder is powered down and unconnected

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Register 5-1: LCDREF: LCD Reference Ladder Control Register (Continued)

bit 2-0 LRLAT<2:0>: LCD Reference Ladder A Time Interval Control bits

Sets the number of 32 clock counts when the A Time Interval Power mode is active.
For Type-A Waveforms (WFT =

111 = Internal LCD reference ladder is in A Power mode for 7 clocks and B Power mode for 9 clocks
110 = Internal LCD reference ladder is in A Power mode for 6 clocks and B Power mode for 10 clocks
101 = Internal LCD reference ladder is in A Power mode for 5 clocks and B Power mode for 11 clocks
100 = Internal LCD reference ladder is in A Power mode for 4 clocks and B Power mode for 12 clocks
011 = Internal LCD reference ladder is in A Power mode for 3 clocks and B Power mode for 13 clocks
010 = Internal LCD reference ladder is in A Power mode for 2 clocks and B Power mode for 14 clocks
001 = Internal LCD reference ladder is in A Power mode for 1 clock and B Power mode for 15 clocks
000 = Internal LCD reference ladder is always in B Power mode

For Type-B Waveforms (WFT =

111 = Internal LCD reference ladder is in A Power mode for 7 clocks and B Power mode for 25 clocks
110 = Internal LCD reference ladder is in A Power mode for 6 clocks and B Power mode for 26 clocks
101 = Internal LCD reference ladder is in A Power mode for 5 clocks and B Power mode for 27 clocks
100 = Internal LCD reference ladder is in A Power mode for 4 clocks and B Power mode for 28 clocks
011 = Internal LCD reference ladder is in A Power mode for 3 clocks and B Power mode for 29 clocks
010 = Internal LCD reference ladder is in A Power mode for 2 clocks and B Power mode for 30 clocks
001 = Internal LCD reference ladder is in A Power mode for 1 clock and B Power mode for 31 clocks
000 = Internal LCD reference ladder is always in B Power mode

0):

1):

5.2 LCD Bias Generation

The LCD driver module is capable of generating the required Bias voltages for LCD operation
with a minimum of external components. This includes the ability to generate the different voltage
levels required by the different Bias types that are required by the LCD. The driver module can
also provide Bias voltages, both above and below the microcontroller V
on-chip LCD voltage regulator.

5.2.1 LCD BIAS TYPES

There is support for three Bias types based on the waveforms generated to control segments and
commons:

• Static (two discrete levels)

• 1/2 Bias (three discrete levels

• 1/3 Bias (four discrete levels)

The use of different waveforms in driving the LCD is discussed in more detail in Section 10.0

“LCD Waveform Generation”.

5.2.2 LCD VOLTAGE REGULATOR

The purpose of the LCD regulator is to provide proper Bias voltage and good contrast for the
LCD, regardless of V
ence. The regulator can be configured by using external components to boost Bias voltage above
V

DD. It can also operate a display at a constant voltage below VDD. The regulator can also be

selectively disabled to allow Bias voltages to be generated by an external resistor network.

The LCD regulator is controlled through the LCDREG register (Register 5-2). It is enabled or dis­abled using the CKSEL<1:0> bits, while the charge pump can be selectively enabled using the
CPEN bit. When the regulator is enabled, the MODE13 bit is used to select the Bias type. The
peak LCD Bias voltage, measured as a difference between the potentials of LCDBIAS3 and
LCDBIAS0, is configured with the BIAS<2:0> bits.

DD levels. This module contains a charge pump and internal voltage refer-

DD, through the use of an

DS30009740B-page 14  2010-2013 Microchip Technology Inc.