Microchip Technology CY92024C User Manual

NETWORK MEDIA MODULE

CY920

Operating Conditions

• 3.3V, 2.5V, 1.8V, 1.2V supply voltage

• Operating frequency up to 400 MHz

• Operating temperature: 0ºC to 70ºC

Features

• Audio networking system on a small footprint module

•Wi-Fi

• Integrated Ethernet + USB 2.0 OTG

• Optional Bluetooth

• Diversity enabled external antenna connectors

• Glueless audio, video, and control ports

• FCC certification is planned for production version

• Ideal for enabling network and USB audio playback

certified 802.11 a/b/g/n

v2.1 + EDR

for iPod active speaker systems, internet radios, network playback adapters

docks, audio systems, AV receivers,

WLAN

• Integrated 802.11 a/b/g/n MAC, Baseband Processor (BBP) and radio frequency (RF) transceiver

• Wi-Fi certified 802.11 a/b/g/n supporting both

2.4 GHz and 5 GHz bands

• On-chip wideband sniffer which enables applications that benefit from efficient interference management algorithms

• 1x1 dual band with Tx and Rx antenna diversity

• Supports Wi-Fi Direct

• Two Ultra Small Miniature RF Connector (U.FL) type external antenna connectors

Memory Interfaces

• 16 MB on-board serial Flash memory

• 64 MB on-board DDR2 SDRAM

• Off-board serial Flash memory via extended connector

Communication Interfaces

• 10/100 Mbps Ethernet support with Ethernet PHY on-board

• USB 2.0 OTG with integrated PHY

• Serial Peripheral Interface (SPI), Inter-Integrated Circuit™ (I Receiver Transmitter (UART) peripheral ports

• 3.3V tolerance on all digital IOs (GPIO, I SPDIF, SPI, UART, HDMI)

C™), Universal Asynchronous

Audio and Graphics Interface

•I2S support with external Digital-to-Analog Converter (DAC)/Power Amplifier (PA)

• Built-in Digital Signal Processor (DSP) with dual core 300 MHz each

• HDMI support with in-built 24-bit HD port and external HDMI transmitter

• Supports analog video (composite, component and S-Video) using external video encoder

Input/Output

• General Purpose Input Outputs (GPIOs) for different Stock Keeping Units (SKUs):

- CY920-A: 11 GPIOs

- CY920-B: 13 GPIOs

- CY920-C: 9 GPIOs

Bluetooth (Optional)

• Compliant with Bluetooth (BT) v2.1 + EDR specification

• A2DP and AVRCP profiles

• WLAN and Bluetooth co-existence using Packet Traffic Arbitration (PTA) and Adaptive Frequency Hopping (AFH)

• Utilizes same antenna as Wi-Fi system

• Supports Class 2 power output

• Low-power consumption

Applications

• JukeBlox®: DLNA™, AirPlay® Speaker, network audio DMR/ DMP, Internet radio, mini/micro system

• Audio Video Receivers (AVR)

• Sound Bars

• PC OEM, TV and gaming consoles

• Operating as an access point (Wi-Fi Direct Host)

CY920

NOTES:

CY920

System Overview .................................................................................................................................................................................. 5

CY920 Board Layout and Features .................................................................................................................................................... 15

Application Guidelines ........................................................................................................................................................................ 19

Wi-Fi Specification .............................................................................................................................................................................. 21

Bluetooth Specifications ...................................................................................................................................................................... 23

Packaging Information ........................................................................................................................................................................ 25

Electrical Characteristics ..................................................................................................................................................................... 29

Regulatory Compliance and Quality ................................................................................................................................................... 33

Ordering Guide ................................................................................................................................................................................... 35

Appendix A: Certification Notices ........................................................................................................................................................ 37

Appendix B: Revision History .............................................................................................................................................................. 39

The Microchip Web Site ...................................................................................................................................................................... 41

Customer Change Notification Service ............................................................................................................................................... 41

Customer Support ............................................................................................................................................................................... 41

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Most Current Data Sheet

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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

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• Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

CY920

NOTES:

CY920

Ethernet

PHY

DM920 SoC

DDR2 SDRAM

64 MByte

DDR2

Controller

USB 2.0

OTG

GPIO

40.000 MHz

Serial Flash

16 MByte

2.4/5 GHz FEM

802.11 a/b/g/n

Ethernet

Controller

UART 1

3.3V RTC

CY920 Network Media Module

1.2V

Wi-Fi/BT Antenna

Socket

1.8V

SPI 1

I2C

JTAG

RST

Reset In

AV Ports

SPI 0

Wi-Fi

Antenna

Socket

2.5V

I2S, S/PDIF

Bluetooth

Baseband and

UART 0

GPIO

3.3V

HD Ports

HD Data

Apple

Coprocessor

Optional External

Serial Flash

Host

Controller

RJ-45

Transformer

USB

Type-A/Lightning

HDMI Tx

Audio A/D,

D/A

10/100

Mbps

Debug Port

Antenna Switch

26.000 MHz

1.0 SYSTEM OVERVIEW

The CY920 module can be connected to standard I/O components in various audio, video, and control

Note: This data sheet summarizes the features

of the CY920 network media module. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the various application notes available on the Microchip web site www.microchip.com.

The CY920 module is a single-board network media module based on Microchip's DM920 network media processor. It enables faster product development with

formats. The CY920 module and the JukeBlox SDK form a turnkey solution which enables rapid product development by the Original Equipment Manufacturers (OEMs) and Original Design Manufacturers (ODMs). The software packages feature an intuitive Application Programming Interface (API) that enables easy customization result in faster time-to-market.

Figure 1-1 illustrates a typical example of the CY920

module based system block diagram.

Ethernet, USB, Wi-Fi, and Bluetooth connectivity.

FIGURE 1-1: CY920 BASED SYSTEM BLOCK DIAGRAM

CY920

1.1 Connectors and Connections

The following sections provide information on different connectors and connections in the CY920 module.

1.1.1 MODULE CONNECTORS

The CY920 module uses two board-to-board connectors, basic and extended, as interfaces to the product main board. Some of the module versions have only the basic connector installed.

The CY920 module uses female connectors and the product main board uses male connectors.

Table 1-1 provides part numbers for the male

connectors needed on the product main board that mate to the female connectors on the CY920 module.

TABLE 1-1: MODULE CONNECTORS

Connector

Number

J301

(Basic)

J300

(Extended)

Connector Type

64-pin B2B

connector

2 x 32 x 1.27 mm

Mating Connector Part

Numbers

S1210-64SVB-S01-1R/C

S1210-64SVB-S01-1R/C 1.27*5.7-2*32P

Manufacturer

XINYA

Alternate Part

Number

1.27*5.7-2*32P

Alternate

Manufacturer

Shen Zhen Hua

Xin Sheng

Electronic Co Ltd

CY920

Table 1-2 provides the function of the pins in the

J301-basic connector.

TABLE 1-2: J301-BASIC CONNECTOR

Number

1 VIN (1.2V) —

3 VIN (1.2V) — 4 VIN (2.5V) —

5GND— 6 GND —

7 VIN (1.8V) — 8 VIN (3.3V) —

9 VIN (1.8V) — 10 VIN (3.3V) —

11 GND — 12 VIN(3.3V RTC) —

13 SPF0 GPIO-16 iPod Access

15 NRESET — System Reset 16 UART_RXD1 —

17 SPF1 GPIO-17 Ethernet

19 MII_TXD3 GPIO-09 IR input 20 AV4DATA1 — SPDIF input

21 GND — Power supply 22 AV4DATA0 — SPDIF output

23 SPI_DIN —

25 SPI_DOUT — 26 AV2CTRL1 — MCLK

27 SPI_CLK — 28 AV2CTRL0 — LRCK

29 SPI_NCS0 — 30 AV2CLK — SCLK

31 GND — Power supply 32 AV2DATA1 — A/D data 0

33 MII_TXD2 GPIO-08 Factory Reset 34 AV2DATA0 — D/A data 0

35 I2C_SDA —

37 I2C_SCL — 38 ETH_LED_SPEED — Ethernet

39 AV2DATA2 — D/A Data 1 40 AV2DATA3 — D/A data 2

41 MII_RXD2 GPIO-10 SPI_REQ 42 ETH_LED_ACT — Ethernet

43 AV3CTRL0 GPIO-05 — 44 GND — Power supply

45 GND — Power supply 46 ETH_TXP —

47 AV3CLK GPIO-04 — 48 ETH_TXN —

49 HDDATA14 GPIO-14 — 50 ETH_RXP —

51 HDDATA15 GPIO-15 — 52 ETH_RXN —

53 GND — Power supply 54 GND — Power supply

55 USB_OTG_DN —

57 USB_OTG_DP — 58 MII_RXD3 GPIO-11 —

59 USB_PWR_EN — 60 AV3CTRL1 GPIO-06 Chip Select for

61 USB_VBUS — 62 EXP_PA_EN1_24 GPIO-18 HD_INT

63 USB_ID — 64 GND — Power supply

Note 1: The connector definitions are subject to change in future revisions of this document.

Signal GPIO Function

Power supply

Power

Reset

SPI

USB

Number

2 VIN (2.5V) —

14 GND —

18 UART_TXD1 —

24 GND — Power supply

36 GND — Power supply

56 EXT_PA_EN1_5 GPIO-19 Reserved

Signal GPIO Function

Power supply

Debug UART

Ethernet

external Flash

CY920

Table 1-3 provides the function of the pins in the

J300-extended connector.

TABLE 1-3: J300-EXTENDED CONNECTOR

Number

1 HDDATA12 GPIO-12 HDDATA12 2 AV0DATA0 — AV0DATA0

3 HDDATA13 GPIO-13 HDDATA13 4 AV0DATA1 — AV0DATA1

5 HDDATA14 GPIO-14 HDDATA14 6 AV0DATA2 — AV0DATA2

7 HDDATA15 GPIO-15 HDDATA15 8 AV0DATA3 — AV0DATA3

9 GND — Power supply 10 GND — GND

11 HDDATA11 — HDDATA11 12 AV1DATA0 — AV1DATA0

13 HDDATA10 — HDDATA10 14 AV1DATA1 — AV1DATA1

15 HDDATA9 — HDDATA9 16 AV1DATA2 — AV1DATA2

17 HDDATA8 — HDDATA8 18 AV1DATA3 — AV1DATA3

19 GND — Power supply 20 GND — GND

21 HDDATA7 — HDDATA7 22 AV0CLK — AV0CLK

23 HDDATA6 — HDDATA6 24 AV0CTRL0 — AV0CTRL0

25 HDDATA5 — HDDATA5 26 AV0CTRL1 — AV0CTRL1

27 HDDATA4 — HDDATA4 28 AV0CTRL2 — AV0CTRL2

29 GND — Power supply 30 GND GND

31 HDDATA0 — HDDATA0 32 NC — NC

33 HDDATA1 — HDDATA1 34 NC — NC

35 HDDATA2 — HDDATA2 36 NC — NC

37 HDDATA3 — HDDATA3 38 GND — GND

39 GND — Power supply 40 GND — GND

41 TCK — JTAG 42 NC — NC

43 UART_RXD0 — Shared with

45 UART_TXD0 — Shared with

47 TDI —

49 TDO — 50 MII_COL GPIO-01 MII_COL

51 TMS — 52 MII_CRS GPIO-00 MII_CRS

53 SPI1CLK —

55 SPI1DIN — 56 AV3DATA1 — AV3DATA1

57 GND — Power supply 58 GND — GND

59 SPI1DOUT —

61 SPI1CS0 — 62 SPI1WPROT — SPI1WPROT

63 GND — Power supply 64 NC — NC

Note 1: The connector definitions are subject to change in future revisions of this document.

Signal GPIO Function

JTAG

Flash interface

Number

44 SPI_NCS1 — SPI_NCS1

46 MII_TX_ER GPIO-02 MII_TX_ER

48 MII_TX_CLK GPIO-03 MII_TX_CLK

54 AV 3DATA0 — AV 3DATA0

60 SPI1HOLDB — SPI1HOLDB

Signal GPIO Function

Table 1-4 provides the GPIO assignment on the CY920

module.

TABLE 1-4: CY920 GPIO MAPPING

GPIO

Number

Note 1: The GPIO assignments are subject to change in future revisions of this document.

DM920 Pin Name Connected To Assigned Function

0 MIICRS BT/extended connector WLAN_ACTIVE

1 MIICOL BT/extended connector BT_PRIORITY

2 MIITXER BT/extended connector BT_ACTIVE

3 MIITXCLK BT/extended connector BT_LDO_ON

4 AV3CLK Basic connector Available

5 AV3CTRL0 Basic connector Available

6 AV3CTRL1 Basic connector Chip select for expansion Flash

7 AV0CTRL2 Extended connector Available

8 MIITXD2 Basic connector Factory Reset

9 MIITXD3 Basic connector IR input

10 MIIRXD2 Basic connector SPI_REQ for Host controller

11 MIIRXD3 Basic connector Available

12 HDDATA12 Extended connector Available

13 HDDATA13 Extended connector Available

14 HDDATA14 Extended connector Available

15 HDDATA15 Extended connector Available

16 SPF0 Basic connector HD_INT

17 SPF1 Basic connector Ethernet Reset

18 EXT_PA_EN1_5 Basic connector FEM BSEL

19 EXT_PA_EN1_24 Basic connector Available

CY920

1.1.2 ANTENNA CONNECTOR

In the CY920 module two external antenna sockets are used to enable diversity operation. During the diversity operation, the firmware selects one antenna at a time through the on-board Tx/Rx diversity RF switch.

The surface-mounted antenna socket used in the CY920 module is Ultra Small Surface Mount Coaxial (U.FL) type.

Note: Do not use the CY920 module that has

two external antenna sockets with only one external antenna connected. This will degrade the Wi-Fi or BT performance.

CY920

1.2 Pin Description

Table 1-5 through Ta bl e 1 -1 5 provide an overview of

the important control and interface signals. It also covers pinouts and signal names.

TABLE 1-5: POWER

Signal Type Description

3.3V P Power input +3.3V

1.2V P Power input +1.2V

1.8V P Power input +1.8V

2.5V P Power input +2.5V

3.3V RTC P Power input +3.3V for Real-Time Clock (RTC). Power can be provided by battery or external Supercap.

GND P Ground (GND) connection for power supply, signal returns and shielding

Legend: O = Output I /O = Input /Output I = Input P = Power

TABLE 1-6: SERIAL PERIPHERAL INTERFACE (SPI)

Signal T ype Description

SPI_DOUT O SPI data from DM920 to Host controller

SPI_DIN I SPI data from Host controller to DM920

SPI_CLK I SPI clock from Host controller to DM920 (maximum recommended

frequency is 2 MHz and typical frequency is 1 MHz, see Note 1)

SPI_NCS0 I SPI Chip Select from Host controller to DM920

MII_RXD2 O • This GPIO signal is used as SPI_REQ (SPI request signal) from DM920 to

Host controller for eDMP applications.

• Logic 1 indicates there is an SPI message waiting to be read. The Host controller should start the SPI clock and read any changed registers.

• Logic 0 indicates that all changed register messages have been read and the message buffer is empty.

Legend: O = Output I /O = Input /Output I = Input P = Power Note 1: For SPI timing diagram for eDMP applications, refer to “MCHP-JB -

Device_Control_Protocol_Registers_v_6_5” or later version. For detailed setup and hold timing details,

refer to the “DM920 Data Sheet” (DS60001278).

TABLE 1-7: SPI FLASH INTERFACE

Signal Type Description

SPI1CS0 O Chip Select input for on-board Flash

AV3CTRL1 (GPIO6) O Chip Select for external Flash. For more information on how to connect

and access external Flash, refer to the Chapter 18. External Flash Interface chapter in the “JukeBlox

(DS70005181).

SPI1CLK O Clock signal to drive serial Flash

SPI1DIN I Data line from Flash output to DM920 input

SPI1DOUT O Data line from DM920 output to Flash input

SPI1HOLDB O Serial Flash control input

SPI1WPROT O Write protect input to serial Flash

Legend: O = Output I /O = Input /Output I = Input P = Power

Technology 4.X SDK User's Guide”

CY920

TABLE 1-8: UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART)

Signal Type Description

UART_RXD1 I UART1 input to the DM920, used for shell access. Microchip recommends

providing a connection to an external RS-232 transceiver and a DB9 connector to connect to a PC COM port. This connection can be used for the product development debugging, module programming control on the product manufacturing line, and module control during certification procedures.

UART_TXD1 O UART1 output from the DM920, used for shell access. Microchip recommends

UART_RXD0 I UART0 input, used for Bluetooth (BT) in BT SKU. It can be used as an additional

UART in non-BT SKU.

UART_TXD0 O UART0 output, used for Bluetooth in case of BT SKU. It can be used as an

additional UART in non-BT SKU

Legend: O = Output I /O = Input /Output I = Input P = Power

TABLE 1-9: AUDIO

Signal Type Description

AV2D ATA0 AV2D ATA2 AV2D ATA3

AV2D ATA1

AV2CTRL0 O LRCK, audio data word clock at the audio sample rate (Fs) (currently, maximum

AV2CTRL1 O MCLK, audio master clock at 256 Fs. It can be used to clock an external D/A

AV2CLK O SCLK, audio data bit clock at 64 Fs. It allows up to 32 audio data bits per sample

AV4DATA0 O SPDIF format output. It can support sample rate up to 192 kHz. Consequently, the

AV4DATA1 I SPDIF input. Currently it is not used, do not connect.

AV3D ATA0 AV3D ATA1

Legend: O = Output I /O = Input /Output I = Input P = Power Note 1:

For the audio port timing diagrams, setup and hold timing details, refer to the (DS60001278)

I/O Used for I

S or left justified audio data output. It is typically connected to an external D/A converter input or an external DSP for further audio processing. AV2DATA0 is used for the main left and right channel audio output data. AV2DATA2 and AV2DATA3 may be used for surround sound rear channels and sub-woofer.

See Note 1.

S or left justified audio data input. It can be driven from an optional external A/D converter used to interface to iPod analog output or other analog audio sources, or aux in jack. If not used, leave it open.

supported frequency is 192 kHz).

converter or an external DSP. The Fs multiplier may vary at sample rates more than 48 kHz.

word.

maximum instantaneous frequency on this pin is 24.576 MHz.

S or left justified audio data, depend on firmware and use case. The AV3 port control and clock signals are defined as GPIOs, see Table 1-15. If required, succeeding use cases may use AV3 control and clock signals as audio clocks.

“DM920 Data Sheet”

CY920

TABLE 1-10: CONTROL

Signal Type Description

MII_TXD2 I Factory Reset, GPIO-08. An active-high input with internal pull-down. Pull to

GND with a 10 k Ω resistor, unless return to factory settings from a hardware control is needed. Generally, return to factory settings is controlled from the Host controller through SPI register. This pin is monitored only during the boot up process.

MII_TXD3

I2C_SDA, I2C_SCL I/O No internal pull-ups, use maximum 4.7 kΩ pull-up resistor on each pin to +3.3V.

NRESET I Low-active input to reset the module. This signal must be driven by an external

Legend: O = Output I /O = Input /Output I = Input P = Power

TABLE 1-11: ETHERNET

Signal Type Description

ETH_RXN, ETH_RXP, ETH_TXN ETH_TXP

ETH_LED_SPEED, ETH_LED_ACT

SPF1 O Ethernet PHY Reset signal, GPIO-17. Do not connect if module Ethernet is

Legend: O = Output I /O = Input /Output I = Input P = Power

I Infrared sensor input, GPIO-09. A Schmitt Trigger input which can handle inputs

with slow slopes. It is used for aDMP firmware builds for infrared remote control sensor output connection to DM920. For applications with a Host controller, pull this pin to +3.3V through a 10 k Ω resistor.

The maximum frequency is 400 kHz.

Reset generator or by a GPIO output from a Host controller.

See Section 3.0 “Application Guidelines” for the timing requirements of

NRESET signal. The CY920 module includes internal 10K pull-up resistor to +3.3V.

M Ethernet signals between the PHY on the module and the external magnetics

(transformer). The maximum bit rate is 100 Mbps.

O • 3.3V push-pull outputs from PHY (max. ±12 mA) to drive the Ethernet LEDs

• 100 Mbps speed mode and activity are indicated by the outputs being low

• Connect ETH_LED_SPEED to LED through 330Ω resistor to +3.3V

• Connect ETH_LED_ACT to LED through 330Ω resistor to 0V

used. If Ethernet is not available on the module, it can be used as a GPIO.

TABLE 1-12: USB

Signal Type Description

USB_OTG_DN, USB_OTG_DP

USB_VBUS M Analog input for monitoring the USB type A connector power. Connect to the +5V

USB_PWR_EN O Logic output to control an external MOSFET, that is in series with the USB type A

USB_ID I Determines whether the USB port is USB Host or USB device. Pull low for the

Legend: O = Output I /O = Input /Output I = Input P = Power

M USB data signals. It is usually connected to the type A connector, USB switch,

iPod dock connector, or Lightning connector. Maximum bit rate is high-speed USB at 480 Mbps.

power which is driving the USB type A connector power pins. If this pin drops below 4.6V, then the DM920 module will drive the USB_PWR_EN signal low to control an external power MOSFET to disconnect +5V power from the USB type A connector.

connector power.

Host and pull high for the device.

CY920

TABLE 1-13: JTAG

Signal Type Description

TMS,TCK,TDI, TDO I/O JTAG ports for the DM920 SoC. Do not connect these pins.

Legend: O = Output I /O = Input /Output I = Input P = Power

TABLE 1-14: VIDEO

Signal Type Description

AV0CLK O HD Clock

AV0CTRL0 O HD HSYNC

AV0CTRL1 O HD VSYNC

AV0CTRL2 O HD data enable, GPIO-07. This GPIO is available if HD interface is not

used.

HDDATA [15:0] O Lower 16 bits of HD video data

AV0DATA [3:0] O HDDATA [19:16]

AV1DATA [3:0] O HDDATA [23:20]

Legend: O = Output I /O = Input /Output I = Input P = Power

TABLE 1-15: GPIO (MISCELLANEOUS)

Signal Type Description

MII_CRS, MII_COL, MII_TX_ER,MII_TXCLK

AV3CLK I/O GPIO-04, see Note 1 AV3CTRL0 I/O GPIO-05, see Note 1 MII_RXD3 I/O GPIO-11, see Note 1 HDDATA12 I/O GPIO-12, see Note 2 HDDATA13 I/O GPIO-13, see Note 2 HDDATA14 I/O GPIO-14, see Note 2 HDDATA15 I/O GPIO-15, see Note 2

SPF0 I/O GPIO-16, HD_INT (for systems with HDMI transmitter)

EXT_PA_EN1_5 I/O GPIO-18, FEM BSEL

EXT_PA_EN1_24 I/O GPIO-19, see Note 1

Legend: O = Output I /O = Input /Output I = Input P = Power Note 1: These GPIOs are available.

2: These GPIOs are available if HD interface is not used.

I/O GPIO-00, 01, 02, 03. It is used for Bluetooth control signals. For a

non-BT module, these signals can be used for other functions.

Microchip has a set of example schematics that shows how the external circuitry is typically connected to the module. Please contact Microchip sales team for any related documents or for any assistance.

CY920

NOTES:

+ 30 hidden pages

Microchip Technology CY92024C User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Operating Conditions

Features

WLAN

Memory Interfaces

Communication Interfaces

Audio and Graphics Interface

Input/Output

Bluetooth (Optional)

Applications

Table of Contents

Most Current Data Sheet

Errata

Customer Notification System

1.0 SYSTEM OVERVIEW

FIGURE 1-1: CY920 BASED SYSTEM BLOCK DIAGRAM

1.1 Connectors and Connections

1.1.1 MODULE CONNECTORS

TABLE 1-1: MODULE CONNECTORS

TABLE 1-2: J301-BASIC CONNECTOR

TABLE 1-3: J300-EXTENDED CONNECTOR

TABLE 1-4: CY920 GPIO MAPPING

1.1.2 ANTENNA CONNECTOR

1.2 Pin Description

TABLE 1-5: POWER

TABLE 1-6: SERIAL PERIPHERAL INTERFACE (SPI)

TABLE 1-7: SPI FLASH INTERFACE

TABLE 1-8: UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART)

TABLE 1-9: AUDIO

TABLE 1-10: CONTROL

TABLE 1-11: ETHERNET

TABLE 1-12: USB

TABLE 1-13: JTAG

TABLE 1-14: VIDEO

TABLE 1-15: GPIO (MISCELLANEOUS)