Microchip Technology ay-3-8910, AY-3-8912 Data Manual
Untitled
30-OCT-1999
This is the General Instruments AY-3-8910 / 8912
Programmable Sound Generator (PSG) data Manual.
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and adobe acrobat to convert it into a .pdf.
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Page 1
AY-3-8910/8912
PROGRAMMABLE
SOUND GENERATOR
DATA MANUAL
Note: Registers are in Octal. Chart shown on page 11 shows
Channel A amplitude as “RIO”. In reality it is addressed as an “8”.
“RI1” is really “9”;
“R12” is really “A” etc.
It has been found that the PSG works well in SIOO Buss
Applications using the system clock which by definition is 2MHZ.
“The 2MHZ should be divided by 2 to yield 1 MHZ to allow for lower
noise frequencies. This eliminates the need for an external clock as
shown on page 33.
Note: Pages 3-4; 30, 31, 60-64 have been excluded. The booklet
does include all information available at this time.
Portions of this book have been reprinted with permission from the
original General Instrument Ay-3-8910/8912 DATA MANUAL.
Neither General Instruments nor this company assume
responsibility for the accuracy or use of any of the information
described herein.
1 INTRODUCTION
It is apparent that any microprocessor is capable of producing
acceptable sounds with only a transducer if the processor has no
other tasks to perform while the sound is sustained. In real world
microprocessor use, however, video games need refreshing, key-
boards need scanning, etc. For example, in order to produce a single
channel of ninth octave C (8372 Hz) the signal needs attention every
sixty microseconds. Software required to produce this simple effect
and still perform other activities would in the least be very complex if
not impossible. In the extreme, random noise requires periodic attention even more frequently.
This need for software-produced sounds without the constant
attention of the processor is now satisfied with the availability of the
General Instrument AY-3-8910 and AY-3-8912 Programmable Sound
Generators.
1.1
Description
The AY-3-8910/8912 Programmable Sound Generator (PSG) is a
Large Scale Integrated Circuit which can produce a wide variety of
complex sounds under software control. The AY-3-8910/8912 is
manufactured in Gl’s N-Channel Ion Implant Process. Operation
requires a single 5V power supply, a TTL compatible clock, and a
microprocessor controller such as the GI 16-bit CP1600/1610 or one
of Gl’s PIC 1650 series of b-bit microcomputers.
The PSG is easily interfaced to any bus oriented system. Its flexibility
makes it useful in applications such as music synthesis, sound
effects generation, audible alarms, tonesignalling and FSK modems.
The analog sound outputs can each provide 4 bits of logarithmic
digital to analog conversion, greatly enhancing the dynamic range of
the sounds produced.
In order to perform sound effects while allowing the processor to
continue its other tasks, the PSG can continue to produce sound
after the initial commands have been given by the control processor.
The fact that realistic sound production often involves more than one
effect is satisfied by the three independently controllable channels
available in the PSG.
All of the circuit control signals are digital in nature and intended to
be provided directly by a microprocessor/microcomputer. This
means that one PSG can produce the full range of required sounds
with no change in external circuitry. Since the frequency responseof
the PSG ranges from sub-audible at its lowest frequency to postaudible at its highest frequency, there are few sounds which are
beyond reproduction with only the simplest electrical connections.
Since most applications of a microprocessor/PSG system would also
require interfacing between the outside world and the microprocessor, this facility has been designed into the PSG. The AY-3-8910 has
two general purpose 8-bit I/O ports and is supplied in a 40 lead
package; the AY-3-8912 has one port and 28 leads.
1.2 > Full software control of sound generation.
> Interfaces to most 8-bit and 16-bit microprocessors.
Features q Three independently programmed analog outputs.
> Two 8-bit general purpose I/O ports (AY-3-8910).
> One 8-bit general purpose I/O port (AY-3-8912).
> Single +5 Volt Supply.
13 This Data Manual is intended to introduce the techniques needed to
Scope
cause the AY-3-8910/8912 Programmable Sound Generator to per-
form in its intended fashion. All of the programs, programming, and
hardware designs have been tested to ensure that the methods are
practical rather than purely theoretical.
Although the techniquesdescribed will produce powerful results, the
range of sounds to be synthesized is so vast and the PSG capabilities
so varied that this guide should be viewed merely as an introduction
to the applications possibilities of the PSG.
Fig. 1 TYPICAL SYSTEM DIAGRAM
2 ARCHITECTURE
The AY-3-8910/8912 is a register oriented Programmable Sound
Generator (PSG). Communication between the processor and the
PSG is based on the concept of memory-mapped I/O. Control
commands are issued to the PSG by writing to 16 memory-mapped
registers. Each of the 16 registers within the PSG is also readable so
that the microprocessor can determine, as necessary, present states
or stored data values.
All functions of the PSG are controlled through its 16 registers which
once programmed, generate and sustain thesounds, thus freeing the
system processor for other tasks.
2.1
An internal block diagram of the PSG showing the various functional
Basic
blocks and data flow is shown in Fig. 2.
Functional
Blocks
2.1.1 REGISTER ARRAY
The principal element of the PSG is the array of 16 read/write control
registers. These 16 registers look to the CPU as a block of memory
and as such occupy a 16 word block out of 1,024 possible addresses.
The 10 address bits (8 bits on the common data/address bus, and 2
separate address bits A8 and *A9) are decoded as follows:
i
The four low order address bits select one of the 16 registers
(RO--
R17*).
The six high order address bits function as “chip selects” to
control the tri-state bidirectional buffers (when the high order
address bits are “incorrect”, the bidirectional bulfers are forced to a
high impedance state). High order address bits A9 A8 are fixed in the
PSG design to recognize a 01 code; high order address bits
DA7--
DA4 may be mask-programmed to any 4-bit code by a special order
factory mask modification. Unless otherwise specified, address bits
DA7--DA4
are programmed to recognize only a 0000 code. A valid
high order address latches the register address (the low order 4 bits)
in the Register Address Latch/Decoder block. A latched address will
remain valid until the receipt of a new address, enabling multiple
reads and writes of the same register contents without the need for
redundant re-addressing.
21
Basic
Functional
Blocks
(cont.)
Conditioning of the Register Address Latch/Decoder and the Bidirectional Buffers to recognize the bus function required (inactive,
latch address, write data, or read data) is accomplished by the Bus
Control Decode block.
The function of each of the 16 PSG registers and the data flow of each
register’s contents are shown in context in Fig. 2 and explained in
detail in Section 3, “Operation”. For reference purposes, the Register
Array details are reproduced in Fig. 3.
2.1.2 SOUND GENERATING BLOCKS
The basic blocks in the PSG which produce the programmed sounds
include:
Tone Generators
Noise Generator
Mixers
Amplitude Control
Envelope Generator
D/A Converters
produce the basic square wave tone frequencies for each channel (A,B,C)
produces a frequency modulated pseudo
random pulse width square wave output.
combine the outputs of the Tone Generators
and the Noise Generator. One for each channel (A,B,C).
provides the D/A Converters with either a
fixed or variable amplitude pattern. The fixed
amplitude is under‘ direct ‘CPU control; the
variable amplitude is accomplished by using
the output of the Envelope Generator.
produces an envelope pattern which can be
used to amplitude modulate the output of
each Mixer.
the three D/A Converters each produce up to
a 16 level output signal as determined by the
Amplitude Control.
2.1.3 I/O PORTS
Two additional blocks are shown in the PSG Block Diagram which
have nothing directly to do with the production of sound-these are
the two I/O Ports (A and B). Since virtually all uses of microprocessor-based sound. would require interfacing between the outside
world and the processor, this facility has been included in the PSG.
Data to/from the CPU bus may be read/written to either of two 8-bit
I/O Ports without affecting any other function of the PSG. The I/O
Ports are TTL-compatible and are provided with internal pull-ups on
each pin. Both Ports are available on the AY-3-8910; only I/O Port A is
available on the AY-3-8912.
2.2
PIN Assignments
The AY-3-8910 is supplied in a 40 lead dual in-line package with the
pm assignments as shown in Fig. 4. The AY-3-8912 is supplied in a28
lead dual in-line package with the pin assignments as shown in Fig. 5.
Fig. 4 AY-3-8910 PIN ASSIGNMENTS
/kage
with the
R
pplied in a 28
own in Fig. 5.
IANNEL
C
2.3 DA7--DA0 (input/output/high impedance): pins30--37 (AY-3-8910)
Pin Functions Data/Address 7-0:
pins 21--28 (AY-3-8912)
These 8 lines comprise the 8-bit bidirectional bus used by the
microprocessor to send both data and addresses to the PSG and to
receive data from the PSG. In the data mode, DA7--DA0 correspond
to Register Array bits B7--B0. In the address mode, DA3-DA0 select
the register # (O--178) and DA7--DA4 in conjunction with address
inputs A9 and A8 form the high order address (chip select).
A8 (input): pin 25 (AY-3-8910)
pin 17 (AY-3-8912)
*A9 (input): pin 24 (AY-3-8910)
(not provided on AY-3-8912)
*Address 9, Address 8
These “extra” address bits are made available to enable the positioning of the PSG (assigning a 16 word memory space) in a total 1,024
word memory area rather than in a 256 word memory area as defined
by address bits DA7--DA0 alone. If the memory size does not require
the use of these extra address lines they may be leftunconnected as
each is provided with either an on-chip pull down (A9) or pull-up (A8)
resistor. In “noisy” environments, however, it is recommended that
A9 and A8 be tied to an external ground and +5V, respectively, if they
are not to be used.
RESET
(input): pin 23 (AY-3-8910)
pin 16 (AY-3-8912)
For initialization/power-on purposes, applying logic “0” (ground)
to the Reset pin will reset all registers to “0”. The Reset pin is provided
with an on-chip pull-up resistor.
CLOCK (input): pin 22 (AY-3-8910)
pin 15 (AY-3-8912)
This TTL-compatible input supplies the timing reference for the
Tone, Noise and Envelope Generators.
BDIR, BC2, BCl (inputs): pins 27,28,29 (AY-3-8910)
pins 18,19,20 (AY-3-8912)
Bus DIRection, Bus Control 2,l
These bus control signals are generated directly by Gl’s CP1600
series of microprocessors to control all external and internal bus
operations in the PSG. When using a processor other than the
CP1600, these signals can be provided either by comparable bus
signalsor by simulating the signals on I/O lines of the processor. The
PSG decodes these signals as illustrated in the-following:
2.3
Pin Functions
(cont.)
While interfacing to a processor other than the CP1600 would simply
require simulating the above decoding, the redundancies in the PSG
functions vs. bus control signals can be used to advantage in that
only four of the eight possibledecoded bus functions are required by
the PSG. This could simplify the programming of the bus control
signals to the following, which would only require that the processor
generate two bus control signals (BDIR and BCl, with BC2 tied to
+5v):
Each of these signals is the output of its corresponding D/A
Converter, and provides an up to 1V peak-peak signal representing
the complex sound waveshape generated by the PSG.
IOA7--IOAO (input/output): pins 14--21 (AY-3-8910)
pins 7--14 (AY-3-8912)
IOB7--1OB0 (input/output): pins 6--13 (AY-3-8910)
(not provided on AY-3-8912)
Input/Output A7-- AO, B7-- B0
Each of these two parallel input/output ports provides 8 bits of
parallel data to/from the PSG/CPU bus from/to any external devices
connected to the IOA or IOB pins. Each pin is provided with an onchip pull-up resistor, so that when in the “input” mode, all pins will
read normally high. Therefore, the recommended method for scanning external switches, for example, would be to ground the input bit.
.
TEST 1:
pin 39 (AY-3-8910)
pin 2 (AY-3-8912)
TEST
2: pin 26 (AY-3-8910)
(not connected on AY-3-8912)
These pins are for GI test purposes only and should be left open-&
not use as tie-points.
Vcc:
pin 40 (AY-3-8910)
pin 3 (AY-3-8912)
Nominal +5Volt power supply to the PSG.
Vss:
pin 1 (AY-3-8910)
pin 6 (AY-3-8912)
Ground reference for the PSG.
2.4 Since the PSG functions are controlled by commands from the
Bus Timing
system processor, the common data/address bus (DA7--DAO) requires definition as to its function at any particular time. This is
accomplished by the processor issuing bus control signals, previously described, defining the state of the bus; the PSG then decodes
these signals to perform the requested task.
The conditioning of these bus control signals by the processor is the
same as if the processor were interacting with RAM: (1) the processor
outputs a memory address; and (2) the processor either outputs or
inputs data to/from the memory. The “memory” in this case is the
PSG’s array of 16 read/write control registers.
The timing relationships in issuing the bus control signals relative to
the data or address signals on the bus are reviewed in general in the
following section, and in detail in Section 7, Electrical Specifications.
2.5 While the state flow for many microprocessors can be somewhat
State Timing
involved for certain operations, the sequence of events necessary to
control the PSG is simple and straightforward. Each of the three
major state sequences (Latch Address, Write to PSG, and Read from
PSG) consists of several operations (indicated below by rectangular
blocks), defined by the pattern of bus control signals (BDIR, BC2,
BCl).
The functional operation and relative timing of the PSG control
sequences are described in the following paragraphs (in all examples, BC2 has been assumed to be tied to logic “1”, +5V).
2.5.1 ADDRESS PSG REGISTER SEQUENCE
The “Latch Address.“. sequence is normally an integral part of the
write or read sequences, but for simplicity is illustrated here as an
individual sequence. Depending on the processor used the program
sequence will normally require four principal microstates: (1) send
NACT (inactive); (2) send INTAK (latch address); (3) put address on
bus: (4) send NACT (inactive). [Note: within the timing constraints
detailed in Section 7, steps (2) and (3) may be interchanged.]
2.5.2 WRITE DATA TO PSG SEQUENCE
The “Write to PSG” sequence, which would normally follow immedi-
ately after an address sequence, requires four principal microstates:
(1) send NACT (inactive); (2) put data on bus; (3) send DWS (write to
PSG); (4) send NACT (inactive).
2.5.3 READ DATA FROM PSG SEQUENCE
As with the “Write to PSG” sequence, the ”Read from PSG” sequence
would also normally follow immediately after an address sequence.
The four principal microstates of the read sequence are: (1) send
NACT (inactive); (2) send DTB (read from PSG); (3) read data on bus;
(4) send NACT (inactive).
2.5.4 WRITE TO/READ FROM l/O PORT SEQUENCE
Since the two I/O Ports (A and B) each have an 8-bit register assigned
as a data store, writing to or reading from either port is identical to
writing or reading to any other register. Hence, the state sequences
are exactly-the same as described in the preceding paragraphs.
3 OPERATION
Since all functions of the PSG are controlled by the host processor
via a series of register loads, a detailed description of the PSG
operation can best be accomplished by relating each PSG function to
the control of its corresponding register. The function of creating or
programming a specific sound or sound effect logically follows the
control sequence listed:
Section
3.1
3.2
3.3
3.4
3.5
Operation
Registers
Function
Tone Generator Control
R0--R5
Program tone periods.
Noise Generator Control
R6
Program noise period.
Mixer Control
R7
Enable tone and/or noise
on selected channels.
Amplitude Control
R10--R12 Select “fixed” or “envelope-
variable” amplitudes.
Envelope Generator
R13--R15
Program envelope period
Control
and select envelope pattern.
3.1 The frequency of each square wave generated by the three Tone
Tone Generator
Generators (one each for Channels A, B, and C) is obtained in the
PSG by first counting down the input clock by 16, then by further
Control
counting down the result by the programmed 12-bit Tone Period
value. Each 12-bit value is obtained in the PSG by combining the
(Registers R1, R2, R3, R4, R5)
contents of the relative Coarse and Fine Tune registers, as illustrated
in the
following.
12-bit Tone Period (TP) to Tone Generator
Note that the 12-bit value programmed in the combined Coarse and
Fine Tune registers is a period value-the higher the value in the
registers, the lower the resultant tone-frequency.
Note also that due to the design technique used in the Tone Period
count-down, the lowest period value is 000000000001 (divide by 1)
and the hiqhest period value is 1111111‘11111 (divide by 4,09510).
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