Microchip Technology ATmega48A, ATmega48PA, ATmega88A, ATmega88PA, ATmega168A User Manual
...
ATmega48A/PA/88A/PA/168A/PA/328/P
megaAVR® Data Sheet
Introduction
The ATmega48A/PA/88A/PA/168A/PA/328/P is a low power, CMOS 8-bit microcontrollers based on the
®
AVR
enhanced RISC architecture. By executing instructions in a single clock cycle, the devices achieve
CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed.
Features
High Performance, Low Power AVR
Advanced RISC Architecture
®
8-Bit Microcontroller Family
131 Powerful Instructions – Most Single Clock Cycle Execution
32 x 8 General Purpose Working Registers
Fully Static Operation
Up to 20 MIPS Throughput at 20MHz
On-chip 2-cycle Multiplier
High Endurance Non-volatile Memory Segments
4/8/16/32KBytes of In-System Self-Programmable Flash program memory
256/512/512/1KBytes EEPROM
512/1K/1K/2KBytes Internal SRAM
Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
Data retention: 20 years at 85°C/100 years at 25°C
(1)
Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
Programming Lock for Software Security
QTouch
®
library support
Capacitive touch buttons, sliders and wheels
QTouch and QMatrix™ acquisition
Up to 64 sense channels
Peripheral Features
Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 1
ATmega48A/PA/88A/PA/168A/PA/328/P
Real Time Counter with Separate Oscillator
Six PWM Channels
8-channel 10-bit ADC in TQFP and VQFN package
Temperature Measurement
6-channel 10-bit ADC in SPDIP Package
Temperature Measurement
Programmable Serial USART
Master/Slave SPI Serial Interface
Byte-oriented 2-wire Serial Interface (Philips I
Programmable Watchdog Timer with Separate On-chip Oscillator
On-chip Analog Comparator
Interrupt and Wake-up on Pin Change
Special Microcontroller Features
Power-on Reset and Programmable Brown-out Detection
2
C compatible)
Internal Calibrated Oscillator
External and Internal Interrupt Sources
Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby
I/O and Packages
23 Programmable I/O Lines
28-pin SPDIP, 32-lead TQFP, 28-pad VQFN and 32-pad VQFN
Operating Voltage:
1.8 - 5.5V
Temperature Range:
-40°C to 85°C
Speed Grade:
0 - 4MHz@1.8 - 5.5V, 0 - 10MHz@2.7 - 5.5.V, 0 - 20MHz @ 4.5 - 5.5V
Power Consumption at 1MHz, 1.8V, 25°C
Active Mode: 0.2mA
Power-down Mode: 0.1µA
• Power-save Mode: 0.75µA (Including 32kHz RTC)
Note: 1. See “Data Retention” on page 17 for details.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 2
ATmega48A/PA/88A/PA/168A/PA/328/P
Table of Contents
1 Pin Configurations .............................................................................................................. 12
1.1 Pin Descriptions............................................................................................... 13
2Overview .................................................................................................................................... 15
2.1 Block Diagram ................................................................................................. 15
2.2 Comparison Between Processors ................................................................... 16
3 Resources ................................................................................................................................ 17
4 Data Retention ....................................................................................................................... 17
5 About Code Examples ...................................................................................................... 17
6 Capacitive Touch Sensing ............................................................................................. 17
7 AVR CPU Core ....................................................................................................................... 18
7.1 Overview.......................................................................................................... 18
7.2 ALU – Arithmetic Logic Unit............................................................................. 19
7.3 Status Register ................................................................................................ 19
7.4 General Purpose Register File ........................................................................ 20
7.5 Stack Pointer ................................................................................................... 22
7.6 Instruction Execution Timing ........................................................................... 23
7.7 Reset and Interrupt Handling........................................................................... 23
8 AVR Memories ....................................................................................................................... 26
8.1 Overview.......................................................................................................... 26
8.2 In-System Reprogrammable Flash Program Memory ..................................... 26
8.3 SRAM Data Memory........................................................................................ 28
8.4 EEPROM Data Memory .................................................................................. 29
8.5 I/O Memory...................................................................................................... 30
8.6 Register Description ........................................................................................ 31
9 System Clock and Clock Options .............................................................................. 36
9.1 Clock Systems and their Distribution............................................................... 36
9.2 Clock Sources ................................................................................................. 37
9.3 Low Power Crystal Oscillator........................................................................... 38
9.4 Full Swing Crystal Oscillator ............................................................................ 39
9.5 Low Frequency Crystal Oscillator .................................................................... 42
9.6 Calibrated Internal RC Oscillator ..................................................................... 43
9.7 128kHz Internal Oscillator ............................................................................... 43
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 3
ATmega48A/PA/88A/PA/168A/PA/328/P
9.8 External Clock ................................................................................................. 44
9.9 Clock Output Buffer ......................................................................................... 45
9.10 Timer/Counter Oscillator.................................................................................. 45
9.11 System Clock Prescaler .................................................................................. 45
9.12 Register Description ........................................................................................ 46
10 Power Management and Sleep Modes ................................................................... 48
10.1 Sleep Modes.................................................................................................... 48
10.2 BOD Disable
10.3 Idle Mode......................................................................................................... 49
10.4 ADC Noise Reduction Mode............................................................................ 49
10.5 Power-down Mode........................................................................................... 49
10.6 Power-save Mode............................................................................................ 50
10.7 Standby Mode ................................................................................................. 50
10.8 Extended Standby Mode ................................................................................. 51
(1)
................................................................................................ 49
10.9 Power Reduction Register ............................................................................... 51
10.10 Minimizing Power Consumption ...................................................................... 51
10.11 Register Description ........................................................................................ 53
11 System Control and Reset ............................................................................................. 56
11.1 Resetting the AVR ........................................................................................... 56
11.2 Reset Sources ................................................................................................. 56
11.3 Power-on Reset............................................................................................... 57
11.4 External Reset ................................................................................................. 58
11.5 Brown-out Detection ........................................................................................ 58
11.6 Watchdog System Reset ................................................................................. 59
11.7 Internal Voltage Reference .............................................................................. 59
11.8 Watchdog Timer .............................................................................................. 60
11.9 Register Description ........................................................................................ 63
12 Interrupts ................................................................................................................................... 66
12.1 Interrupt Vectors in ATmega48A and ATmega48PA ....................................... 66
12.2 Interrupt Vectors in ATmega88A and ATmega88PA ....................................... 68
12.3 Interrupt Vectors in ATmega168A and ATmega168PA ................................... 71
12.4 Interrupt Vectors in ATmega328 and ATmega328P........................................ 74
12.5 Register Description ........................................................................................ 77
13 External Interrupts .............................................................................................................. 79
13.1 Pin Change Interrupt Timing............................................................................ 79
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 4
ATmega48A/PA/88A/PA/168A/PA/328/P
13.2 Register Description ........................................................................................ 80
14 I/O-Ports ..................................................................................................................................... 84
14.1 Overview.......................................................................................................... 84
14.2 Ports as General Digital I/O ............................................................................. 85
14.3 Alternate Port Functions .................................................................................. 89
14.4 Register Description ...................................................................................... 100
15 8-bit Timer/Counter0 with PWM ................................................................................ 102
15.1 Features ........................................................................................................ 102
15.2 Overview........................................................................................................ 102
15.3 Timer/Counter Clock Sources ....................................................................... 103
15.4 Counter Unit .................................................................................................. 103
15.5 Output Compare Unit..................................................................................... 104
15.6 Compare Match Output Unit .......................................................................... 106
15.7 Modes of Operation ....................................................................................... 107
15.8 Timer/Counter Timing Diagrams ................................................................... 111
15.9 Register Description ...................................................................................... 113
16 16-bit Timer/Counter1 with PWM ............................................................................. 120
16.1 Features ........................................................................................................ 120
16.2 Overview........................................................................................................ 120
16.3 Accessing 16-bit Registers ............................................................................ 122
16.4 Timer/Counter Clock Sources ....................................................................... 125
16.5 Counter Unit .................................................................................................. 125
16.6 Input Capture Unit ......................................................................................... 126
16.7 Output Compare Units ................................................................................... 128
16.8 Compare Match Output Unit .......................................................................... 130
16.9 Modes of Operation ....................................................................................... 131
16.10 Timer/Counter Timing Diagrams ................................................................... 138
16.11 Register Description ...................................................................................... 140
17 Timer/Counter0 and Timer/Counter1 Prescalers ........................................... 147
17.1 Internal Clock Source .................................................................................... 147
17.2 Prescaler Reset ............................................................................................. 147
17.3 External Clock Source ................................................................................... 147
17.4 Register Description ...................................................................................... 149
18 8-bit Timer/Counter2 with PWM and Asynchronous Operation ........... 150
18.1 Features ........................................................................................................ 150
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 5
ATmega48A/PA/88A/PA/168A/PA/328/P
18.2 Overview........................................................................................................ 150
18.3 Timer/Counter Clock Sources ....................................................................... 151
18.4 Counter Unit .................................................................................................. 151
18.5 Output Compare Unit..................................................................................... 152
18.6 Compare Match Output Unit .......................................................................... 154
18.7 Modes of Operation ....................................................................................... 155
18.8 Timer/Counter Timing Diagrams ................................................................... 159
18.9 Asynchronous Operation of Timer/Counter2 ................................................. 160
18.10 Timer/Counter Prescaler ............................................................................... 161
18.11 Register Description ...................................................................................... 162
19 SPI – Serial Peripheral Interface ............................................................................... 169
19.1 Features ........................................................................................................ 169
19.2 Overview........................................................................................................ 169
19.3 SS Pin Functionality ...................................................................................... 174
19.4 Data Modes ................................................................................................... 174
19.5 Register Description ...................................................................................... 176
20 USART0 .................................................................................................................................... 179
20.1 Features ........................................................................................................ 179
20.2 Overview........................................................................................................ 179
20.3 Clock Generation........................................................................................... 180
20.4 Frame Formats .............................................................................................. 183
20.5 USART Initialization....................................................................................... 184
20.6 Data Transmission – The USART Transmitter .............................................. 185
20.7 Data Reception – The USART Receiver ....................................................... 188
20.8 Asynchronous Data Reception ...................................................................... 192
20.9 Multi-processor Communication Mode .......................................................... 195
20.10 Examples of Baud Rate Setting..................................................................... 196
20.11 Register Description ...................................................................................... 200
21 USART in SPI Mode .......................................................................................................... 205
21.1 Features ........................................................................................................ 205
21.2 Overview........................................................................................................ 205
21.3 Clock Generation........................................................................................... 205
21.4 SPI Data Modes and Timing.......................................................................... 206
21.5 Frame Formats .............................................................................................. 206
21.6 Data Transfer................................................................................................. 209
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 6
ATmega48A/PA/88A/PA/168A/PA/328/P
21.7 AVR USART MSPIM vs. AVR SPI ................................................................ 211
21.8 Register Description ...................................................................................... 212
22 2-wire Serial Interface ..................................................................................................... 215
22.1 Features ........................................................................................................ 215
22.2 2-wire Serial Interface Bus Definition ............................................................ 215
22.3 Data Transfer and Frame Format .................................................................. 216
22.4 Multi-master Bus Systems, Arbitration and Synchronization ......................... 219
22.5 Overview of the TWI Module ......................................................................... 221
22.6 Using the TWI................................................................................................ 223
22.7 Transmission Modes ..................................................................................... 225
22.8 Multi-master Systems and Arbitration............................................................ 238
22.9 Register Description ...................................................................................... 239
23 Analog Comparator .......................................................................................................... 243
23.1 Overview........................................................................................................ 243
23.2 Analog Comparator Multiplexed Input ........................................................... 243
23.3 Register Description ...................................................................................... 244
24 Analog-to-Digital Converter ........................................................................................246
24.1 Features ........................................................................................................ 246
24.2 Overview........................................................................................................ 246
24.3 Starting a Conversion .................................................................................... 248
24.4 Prescaling and Conversion Timing................................................................ 249
24.5 Changing Channel or Reference Selection ................................................... 251
24.6 ADC Noise Canceler ..................................................................................... 252
24.7 ADC Conversion Result................................................................................. 256
24.8 Temperature Measurement ........................................................................... 256
24.9 Register Description ...................................................................................... 257
25 debugWIRE On-chip Debug System ...................................................................... 262
25.1 Features ........................................................................................................ 262
25.2 Overview........................................................................................................ 262
25.3 Physical Interface .......................................................................................... 262
25.4 Software Break Points ................................................................................... 263
25.5 Limitations of debugWIRE ............................................................................. 263
25.6 Register Description ...................................................................................... 263
26 Self-Programming the Flash, ATmega 48A/48PA .......................................... 264
26.1 Overview........................................................................................................ 264
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 7
ATmega48A/PA/88A/PA/168A/PA/328/P
26.2 Addressing the Flash During Self-Programming ........................................... 265
26.3 Register Description ...................................................................................... 270
27 Boot Loader Support – Read-While-Write Self-Programming ............... 272
27.1 Features ........................................................................................................ 272
27.2 Overview........................................................................................................ 272
27.3 Application and Boot Loader Flash Sections ................................................. 272
27.4 Read-While-Write and No Read-While-Write Flash Sections........................ 273
27.5 Boot Loader Lock Bits ................................................................................... 275
27.6 Entering the Boot Loader Program................................................................ 276
27.7 Addressing the Flash During Self-Programming ........................................... 277
27.8 Self-Programming the Flash.......................................................................... 278
27.9 Register Description ...................................................................................... 287
28 Memory Programming .................................................................................................... 289
28.1 Program And Data Memory Lock Bits ........................................................... 289
28.2 Fuse Bits........................................................................................................ 290
28.3 Signature Bytes ............................................................................................. 293
28.4 Calibration Byte ............................................................................................. 293
28.5 Page Size ...................................................................................................... 294
28.6 Parallel Programming Parameters, Pin Mapping, and Commands ............... 294
28.7 Parallel Programming .................................................................................... 296
28.8 Serial Downloading........................................................................................ 303
29 Electrical Characteristics – (TA = -40°C to 85°C) ........................................... 308
29.1 Absolute Maximum Ratings* ......................................................................... 308
29.2 DC Characteristics......................................................................................... 308
29.3 Speed Grades ............................................................................................... 312
29.4 Clock Characteristics ..................................................................................... 313
29.5 System and Reset Characteristics ................................................................ 314
29.6 SPI Timing Characteristics ............................................................................ 315
29.7 Two-wire Serial Interface Characteristics ...................................................... 317
29.8 ADC Characteristics ...................................................................................... 319
29.9 Parallel Programming Characteristics ........................................................... 320
30 Electrical Characteristics (TA = -40°C to 105°C) ............................................ 322
30.1 Absolute Maximum Ratings* ......................................................................... 322
30.2 DC Characteristics......................................................................................... 322
31 Typical Characteristics – (TA = -40°C to 85°C) ................................................ 326
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 8
ATmega48A/PA/88A/PA/168A/PA/328/P
31.1 ATmega48A Typical Characteristics ............................................................. 327
31.2 ATmega48PA Typical Characteristics ........................................................... 352
31.3 ATmega88A Typical Characteristics ............................................................. 377
31.4 ATmega88PA Typical Characteristics ........................................................... 401
31.5 ATmega168A Typical Characteristics ........................................................... 427
31.6 ATmega168PA Typical Characteristics ......................................................... 451
31.7 ATmega328 Typical Characteristics .............................................................. 477
31.8 ATmega328P Typical Characteristics ........................................................... 501
32 ATmega48PA Typical Characteristics – (TA = -40°C to 105°C) ............. 526
32.1 Active Supply Current .................................................................................... 526
32.2 Idle Supply Current........................................................................................ 529
32.3 Power-down Supply Current.......................................................................... 531
32.4 Standby Supply Current ................................................................................ 532
32.5 Pin Pull-Up..................................................................................................... 533
32.6 Pin Driver Strength ........................................................................................ 536
32.7 Pin Threshold and Hysteresis........................................................................ 538
32.8 BOD Threshold.............................................................................................. 541
32.9 Internal Oscillator Speed ............................................................................... 542
32.10 Current Consumption of Peripheral Units ...................................................... 545
32.11 Current Consumption in Reset and Reset Pulsewidth .................................. 547
33 ATmega88PA Typical Characteristics – (TA = -40°C to 105°C) ............. 549
33.1 Active Supply Current .................................................................................... 549
33.2 Idle Supply Current........................................................................................ 552
33.3 Power-down Supply Current.......................................................................... 554
33.4 Power-save Supply Current........................................................................... 555
33.5 Pin Pull-Up..................................................................................................... 556
33.6 Pin Driver Strength ........................................................................................ 559
33.7 Pin Threshold and Hysteresis........................................................................ 561
33.8 BOD Threshold.............................................................................................. 564
33.9 Internal Oscillator Speed ............................................................................... 565
33.10 Current Consumption of Peripheral Units ...................................................... 568
33.11 Current Consumption in Reset and Reset Pulsewidth .................................. 570
34 ATmega168PA Typical Characteristics – (TA = -40°C to 105°C) .......... 572
34.1 Active Supply Current .................................................................................... 572
34.2 Idle Supply Current........................................................................................ 575
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 9
ATmega48A/PA/88A/PA/168A/PA/328/P
34.3 Power-down Supply Current.......................................................................... 577
34.4 Power-save Supply Current........................................................................... 578
34.5 Standby Supply Current ................................................................................ 579
34.6 Pin Pull-Up..................................................................................................... 579
34.7 Pin Driver Strength ........................................................................................ 582
34.8 Pin Threshold and Hysteresis........................................................................ 584
34.9 BOD Threshold.............................................................................................. 587
34.10 Internal Oscillator Speed ............................................................................... 590
34.11 Current Consumption of Peripheral Units ...................................................... 592
34.12 Current Consumption in Reset and Reset Pulsewidth .................................. 595
35 ATmega328P Typical Characteristics – (TA = -40°C to 105°C) .............. 597
35.1 ATmega328P Active Supply Current............................................................. 597
35.2 Idle Supply Current........................................................................................ 600
35.3 Power-down Supply Current.......................................................................... 602
35.4 Power-save Supply Current........................................................................... 603
35.5 Standby Supply Current ................................................................................ 604
35.6 Pin Pull-Up..................................................................................................... 604
35.7 Pin Driver Strength ........................................................................................ 607
35.8 Pin Threshold and Hysteresis........................................................................ 609
35.9 BOD Threshold.............................................................................................. 612
35.10 Internal Oscillator Speed ............................................................................... 614
35.11 Current Consumption of Peripheral Units ...................................................... 617
35.12 Current Consumption in Reset and Reset Pulsewidth .................................. 619
36 Register Summary ............................................................................................................. 621
37 Instruction Set Summary .............................................................................................. 625
38 Ordering Information ....................................................................................................... 628
38.1 ATmega48A .................................................................................................. 628
38.2 ATmega48PA ................................................................................................ 629
38.3 ATmega88A................................................................................................... 630
38.4 ATmega88PA ................................................................................................ 631
38.5 ATmega168A................................................................................................. 632
38.6 ATmega168PA ............................................................................................. 633
38.7 ATmega328 .................................................................................................. 634
38.8 ATmega328P ................................................................................................ 635
39 Packaging Information ................................................................................................... 636
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 10
ATmega48A/PA/88A/PA/168A/PA/328/P
39.1 32A ................................................................................................................ 636
39.2 28M1.............................................................................................................. 638
39.3 32M1-A .......................................................................................................... 641
39.4 28P3 .............................................................................................................. 644
40 Errata ......................................................................................................................................... 645
41 Datasheet Revision History ......................................................................................... 646
41.1 Rev. B – 08/2020 ........................................................................................... 646
41.2 Rev. A – 10/2018 ........................................................................................... 646
41.3 Rev. 8271J – 11/2015 ................................................................................... 646
41.4 Rev. 8271I – 10/2014 .................................................................................... 646
41.5 Rev. 8271H – 08/2014................................................................................... 647
41.6 Rev. 8271G – 02/2013 .................................................................................. 647
41.7 Rev. 8271F – 08/2012 ................................................................................... 647
41.8 Rev. 8271E – 07/2012................................................................................... 647
41.9 Rev. 8271D – 05/11....................................................................................... 648
41.10 Rev. 8271C – 08/10....................................................................................... 648
41.11 Rev. 8271B – 04/10....................................................................................... 648
41.12 Rev. 8271A – 12/09....................................................................................... 649
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 11
ATmega48A/PA/88A/PA/168A/PA/328/P
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
(PCINT19/OC2B/INT1) PD3
(PCINT20/XCK/T0) PD4
GND
VCC
GND
VCC
(PCINT6/XTAL1/TOSC1) PB6
(PCINT7/XTAL2/TOSC2) PB7
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
ADC7
GND
AREF
ADC6
AVCC
PB5 (SCK/PCINT5)
32313029282726
25
9101112131415
16
(PCINT21/OC0B/T1) PD5
(PCINT22/OC0A/AIN0) PD6
(PCINT23/AIN1) PD7
(PCINT0/CLKO/ICP1) PB0
(PCINT1/OC1A) PB1
(PCINT2/SS/OC1B) PB2
(PCINT3/OC2A/MOSI) PB3
(PCINT4/MISO) PB4
PD2 (INT0/PCINT18)
PD1 (TXD/PCINT17)
PD0 (RXD/PCINT16)
PC6 (RESET/PCINT14)
PC5 (ADC5/SCL/PCINT13)
PC4 (ADC4/SDA/PCINT12)
PC3 (ADC3/PCINT11)
PC2 (ADC2/PCINT10)
32 TQFP Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
(PCINT14/RESET) PC6
(PCINT16/RXD) PD0
(PCINT17/TXD) PD1
(PCINT18/INT0) PD2
(PCINT19/OC2B/INT1) PD3
(PCINT20/XCK/T0) PD4
VCC
GND
(PCINT6/XTAL1/TOSC1) PB6
(PCINT7/XTAL2/TOSC2) PB7
(PCINT21/OC0B/T1) PD5
(PCINT22/OC0A/AIN0) PD6
(PCINT23/AIN1) PD7
(PCINT0/CLKO/ICP1) PB0
PC5 (ADC5/SCL/PCINT13)
PC4 (ADC4/SDA/PCINT12)
PC3 (ADC3/PCINT11)
PC2 (ADC2/PCINT10)
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
GND
AREF
AVCC
PB5 (SCK/PCINT5)
PB4 (MISO/PCINT4)
PB3 (MOSI/OC2A/PCINT3)
PB2 (SS/OC1B/PCINT2)
PB1 (OC1A/PCINT1)
28 6PDIP
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32313029282726
25
9101112131415
16
32 94)1 Top View
(PCINT19/OC2B/INT1) PD3
(PCINT20/XCK/T0) PD4
GND
VCC
GND
VCC
(PCINT6/XTAL1/TOSC1) PB6
(PCINT7/XTAL2/TOSC2) PB7
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
ADC7
GND
AREF
ADC6
AVCC
PB5 (SCK/PCINT5)
(PCINT21/OC0B/T1) PD5
(PCINT22/OC0A/AIN0) PD6
(PCINT23/AIN1) PD7
(PCINT0/CLKO/ICP1) PB0
(PCINT1/OC1A) PB1
(PCINT2/SS/OC1B) PB2
(PCINT3/OC2A/MOSI) PB3
(PCINT4/MISO) PB4
PD2 (INT0/PCINT18)
PD1 (TXD/PCINT17)
PD0 (RXD/PCINT16)
PC6 (RESET/PCINT14)
PC5 (ADC5/SCL/PCINT13)
PC4 (ADC4/SDA/PCINT12)
PC3 (ADC3/PCINT11)
PC2 (ADC2/PCINT10)
NOTE: Bottom pad should be soldered to ground.
1
2
3
4
5
6
7
21
20
19
18
17
16
15
28272625242322
891011121314
28 94)1 Top View
(PCINT19/OC2B/INT1) PD3
(PCINT20/XCK/T0) PD4
VCC
GND
(PCINT6/XTAL1/TOSC1) PB6
(PCINT7/XTAL2/TOSC2) PB7
(PCINT21/OC0B/T1) PD5
(PCINT22/OC0A/AIN0) PD6
(PCINT23/AIN1) PD7
(PCINT0/CLKO/ICP1) PB0
(PCINT1/OC1A) PB1
(PCINT2/SS/OC1B) PB2
(PCINT3/OC2A/MOSI) PB3
(PCINT4/MISO) PB4
PD2 (INT0/PCINT18)
PD1 (TXD/PCINT17)
PD0 (RXD/PCINT16)
PC6 (RESET/PCINT14)
PC5 (ADC5/SCL/PCINT13)
PC4 (ADC4/SDA/PCINT12)
PC3 (ADC3/PCINT11)
PC2 (ADC2/PCINT10)
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
GND
AREF
AVCC
PB5 (SCK/PCINT5)
NOTE: Bottom pad should be soldered to ground.
1. Pin Configurations
Figure 1-1. Pinout ATmega48A/PA/88A/PA/168A/PA/328/P
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 12
ATmega48A/PA/88A/PA/168A/PA/328/P
1.1 Pin Descriptions
1.1.1 VCC
Digital supply voltage.
1.1.2 GND
Ground.
1.1.3 Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output
buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tristated when a reset condition becomes active, even if the clock is not running.
Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscillator amplifier
and input to the internal clock operating circuit.
Depending on the clock selection fuse settings, PB7 can be used as output from the inverting Oscillator
amplifier.
If the Internal Calibrated RC Oscillator is used as chip clock source, PB7...6 is used as TOSC2...1 input for the
Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.
The various special features of Port B are elaborated in ”Alternate Functions of Port B” on page 91 and ”System
Clock and Clock Options” on page 36.
1.1.4 Port C (PC5:0)
Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The PC5...0 output
buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tristated when a reset condition becomes active, even if the clock is not running.
1.1.5 PC6/RESET
If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics of PC6
differ from those of the other pins of Port C.
If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin for longer than
the minimum pulse length will generate a Reset, even if the clock is not running. The minimum pulse length is
given in Table 29-11 on page 314. Shorter pulses are not ensured to generate a Reset.
The various special features of Port C are elaborated in ”Alternate Functions of Port C” on page 94.
1.1.6 Port D (PD7:0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output
buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tristated when a reset condition becomes active, even if the clock is not running.
The various special features of Port D are elaborated in ”Alternate Functions of Port D” on page 97.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 13
ATmega48A/PA/88A/PA/168A/PA/328/P
1.1.7 AV
CC
AVCC is the supply voltage pin for the A/D Converter, PC3:0, and ADC7:6. It should be externally connected to
V
, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter.
CC
Note that PC6...4 use digital supply voltage, V
1.1.8 AREF
AREF is the analog reference pin for the A/D Converter.
1.1.9 ADC7:6 (TQFP and VQFN Package Only)
In the TQFP and VQFN package, ADC7:6 serve as analog inputs to the A/D converter. These pins are powered
from the analog supply and serve as 10-bit ADC channels.
CC
.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 14
2. Overview
The ATmega48A/PA/88A/PA/168A/PA/328/P is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the
ATmega48A/PA/88A/PA/168A/PA/328/P achieves throughputs approaching 1 MIPS per MHz allowing the
system designer to optimize power consumption versus processing speed.
2.1 Block Diagram
Figure 2-1. Block Diagram
ATmega48A/PA/88A/PA/168A/PA/328/P
Powe r
RESET
Comp.
VCC
debugWIRE
PROGRAM
CPU
Internal
Bandgap
LOGIC
SRAMFlash
AVC C
AREF
GND
2
6
GND
Watchdog
Timer
Watchdog
Oscillator
Oscillator
Circuits /
Clock
Generation
EEPROM
8bit T/C 2
DATA B US
Supervision
POR / BOD &
16bit T/C 18bit T/C 0 A/D Conv.
Analog
USART 0
SPI TWI
PORT C (7)PORT B (8)PORT D (8)
RESET
XTAL[1..2]
ADC[6..7]PC[0..6]PB[0..7]PD[0..7]
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are
directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one
single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 15
ATmega48A/PA/88A/PA/168A/PA/328/P
The ATmega48A/PA/88A/PA/168A/PA/328/P provides the following features: 4K/8Kbytes of In-System
Programmable Flash with Read-While-Write capabilities, 256/512/512/1Kbytes EEPROM, 512/1K/1K/2Kbytes
SRAM, 23 general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Counters with
compare modes, internal and external interrupts, a serial programmable USART, a byte-oriented 2-wire Serial
Interface, an SPI serial port, a 6-channel 10-bit ADC (8 channels in TQFP and VQFN packages), a
programmable Watchdog Timer with internal Oscillator, and five software selectable power saving modes. The
Idle mode stops the CPU while allowing the SRAM, Timer/Counters, USART, 2-wire Serial Interface, SPI port,
and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the
Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, the
asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is
sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and
ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is
running while the rest of the device is sleeping. This allows very fast start-up combined with low power
consumption.
Microchip offers the QTouch library for embedding capacitive touch buttons, sliders and wheels functionality into
®
AVR
microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully
debounced reporting of touch keys and includes Adjacent Key Suppression
unambiguous detection of key events. The easy-to-use QTouch Suite toolchain allows you to explore, develop
and debug your own touch applications.
The device is manufactured using Microchip’s high density non-volatile memory technology. The On-chip ISP
Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a
conventional non-volatile memory programmer, or by an On-chip Boot program running on the AVR core. The
Boot program can use any interface to download the application program in the Application Flash memory.
Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing
true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on
a monolithic chip, the ATmega48A/PA/88A/PA/168A/PA/328/P is a powerful microcontroller that provides a
highly flexible and cost effective solution to many embedded control applications.
The ATmega48A/PA/88A/PA/168A/PA/328/P AVR is supported with a full suite of program and system
development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit
Emulators, and Evaluation kits.
™ (AKS™) technology for
2.2 Comparison Between Processors
The ATmega48A/PA/88A/PA/168A/PA/328/P differ only in memory sizes, boot loader support, and interrupt
vector sizes. Table 2-1 summarizes the different memory and interrupt vector sizes for the devices.
Table 2-1. Memory Size Summary
Device Flash EEPROM RAM Interrupt Vector Size
ATmega48A 4KBytes 256Bytes 512Bytes 1 instruction word/vector
ATmega48PA 4KBytes 256Bytes 512Bytes 1 instruction word/vector
ATmega88A 8KBytes 512Bytes 1KBytes 1 instruction word/vector
ATmega88PA 8KBytes 512Bytes 1KBytes 1 instruction word/vector
ATmega168A 16KBytes 512Bytes 1KBytes 2 instruction words/vector
ATmega168PA 16KBytes 512Bytes 1KBytes 2 instruction words/vector
ATmega328 32KBytes 1KBytes 2KBytes 2 instruction words/vector
ATmega328P 32KBytes 1KBytes 2KBytes 2 instruction words/vector
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 16
ATmega48A/PA/88A/PA/168A/PA/328/P support a real Read-While-Write Self-Programming mechanism.
There is a separate Boot Loader Section, and the SPM instruction can only execute from there. In ATmega
48A/48PA there is no Read-While-Write support and no separate Boot Loader Section. The SPM instruction can
execute from the entire Flash
3. Resources
A comprehensive set of development tools, application notes and data sheets are available for download on
www.microchip.com
Note: 1.
4. Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over
20 years at 85°C or 100 years at 25°C.
5. About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the device.
These code examples assume that the part specific header file is included before compilation. Be aware that not
all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler
dependent. Confirm with the C compiler documentation for more details.
ATmega48A/PA/88A/PA/168A/PA/328/P
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must
be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with
“SBRS”, “SBRC”, “SBR”, and “CBR”.
6. Capacitive Touch Sensing
The QTouch Library provides a simple to use solution to realize touch sensitive interfaces on most AVR
microcontrollers. The QTouch Library includes support for the QTouch and QMatrix
Touch sensing can be added to any application by linking the appropriate QTouch Library for the AVR
Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then
calling the touch sensing APIs to retrieve the channel information and determine the touch sensor states.
The QTouch Library is FREE and downloadable from the Microchip website at the following location
http://www.microchip.com. For implementation details and other information, refer to the QTouch Library User
Guide - also available for download from the Microchip website.
™ acquisition methods.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 17
7. AVR CPU Core
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registrers
ALU
Status
and Control
I/O Lines
EEPROM
Data Bus 8-bit
Data
SRAM
Direct Addressing
Indirect Addressing
Interrupt
Unit
SPI
Unit
Watchdog
Timer
Analog
Comparator
I/O Module 2
I/O Module1
I/O Module n
7.1 Overview
This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure
correct program execution. The CPU must therefore be able to access memories, perform calculations, control
peripherals, and handle interrupts.
Figure 7-1. Block Diagram of the AVR Architecture
ATmega48A/PA/88A/PA/168A/PA/328/P
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate
memories and buses for program and data. Instructions in the program memory are executed with a single level
pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory.
This concept enables instructions to be executed in every clock cycle. The program memory is In-System
Reprogrammable Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle
access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 18
ATmega48A/PA/88A/PA/168A/PA/328/P
operands are output from the Register File, the operation is executed, and the result is stored back in the
Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing
– enabling efficient address calculations. One of the these address pointers can also be used as an address
pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Zregister, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a register.
Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is
updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the
whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address
contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and the Application Program
section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that
writes into the Application Flash memory section must reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The
Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the
total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine
(before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space.
The data SRAM can easily be accessed through the five different addressing modes supported in the AVR
architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit
in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts
have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the
higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other
I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the
Register File, 0x20 - 0x5F. In addition, the ATmega48A/PA/88A/PA/168A/PA/328/P has Extended I/O space
from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.
7.2 ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers.
Within a single clock cycle, arithmetic operations between general purpose registers or between a register and
an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and
bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both
signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.
7.3 Status Register
The Status Register contains information about the result of the most recently executed arithmetic instruction.
This information can be used for altering program flow in order to perform conditional operations. Note that the
Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in
many cases remove the need for using the dedicated compare instructions, resulting in faster and more
compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored when returning
from an interrupt. This must be handled by software.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 19
7.3.1 SREG – AVR Status Register
The AVR Status Register – SREG – is defined as:
Bit 76543210
0x3F (0x5F)
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
• Bit 7 – I: Global Interrupt Enable
I T H S V N Z C SREG
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable
control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of
the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by
hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.
The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the
instruction set reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the
operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T
can be copied into a bit in a register in the Register File by the BLD instruction.
ATmega48A/PA/88A/PA/168A/PA/328/P
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD
arithmetic. See the “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V.
See the “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetic. See the “Instruction Set
Description” for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set
Description” for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description”
for detailed information.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for
detailed information.
7.4 General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required
performance and flexibility, the following input/output schemes are supported by the Register File:
One 8-bit output operand and one 8-bit result input
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 20
ATmega48A/PA/88A/PA/168A/PA/328/P
Two 8-bit output operands and one 8-bit result input
Two 8-bit output operands and one 16-bit result input
One 16-bit output operand and one 16-bit result input
Figure 7-2 shows the structure of the 32 general purpose working registers in the CPU.
Figure 7-2. AVR CPU General Purpose Working Registers
70Addr.
R0 0x00
R1 0x01
R2 0x02
…
R13 0x0D
General R14 0x0E
Purpose R15 0x0F
Working R16 0x10
Registers R17 0x11
…
R26 0x1A X-register Low Byte
R27 0x1B X-register High Byte
R28 0x1C Y-register Low Byte
R29 0x1D Y-register High Byte
R30 0x1E Z-register Low Byte
R31 0x1F Z-register High Byte
Most of the instructions operating on the Register File have direct access to all registers, and most of them are
single cycle instructions.
As shown in Figure 7-2, each register is also assigned a data memory address, mapping them directly into the
first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this
memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers
can be set to index any register in the file.
7.4.1 The X-register, Y-register, and Z-register
The registers R26...R31 have some added functions to their general purpose usage. These registers are 16-bit
address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are
defined as described in Figure 7-3.
Figure 7-3. The X-, Y-, and Z-registers
15 XH XL 0
X-register 7 0 7 0
R27 (0x1B) R26 (0x1A)
15 YH YL 0
Y-register 7 0 7 0
R29 (0x1D) R28 (0x1C)
15 ZH ZL 0
Z-register 7 0 7 0
R31 (0x1F) R30 (0x1E)
In the different addressing modes these address registers have functions as fixed displacement, automatic
increment, and automatic decrement (see the instruction set reference for details).
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 21
7.5 Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses
after interrupts and subroutine calls. Note that the Stack is implemented as growing from higher to lower
memory locations. The Stack Pointer Register always points to the top of the Stack. The Stack Pointer points to
the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. A Stack PUSH command will
decrease the Stack Pointer.
The Stack in the data SRAM must be defined by the program before any subroutine calls are executed or
interrupts are enabled. Initial Stack Pointer value equals the last address of the internal SRAM and the Stack
Pointer must be set to point above start of the SRAM, see Table 8-3 on page 28.
See Table 7-1 for Stack Pointer details.
Table 7-1. Stack Pointer instructions
Instruction Stack pointer Description
PUSH Decremented by 1 Data is pushed onto the stack
CALL
ICALL
RCALL
POP Incremented by 1 Data is popped from the stack
RET
RETI
Decremented by 2
Incremented by 2 Return address is popped from the stack with return from
ATmega48A/PA/88A/PA/168A/PA/328/P
Return address is pushed onto the stack with a subroutine call or
interrupt
subroutine or return from interrupt
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used
is implementation dependent. Note that the data space in some implementations of the AVR architecture is so
small that only SPL is needed. In this case, the SPH Register will not be present.
7.5.1 SPH and SPL – Stack Pointer High and Stack Pointer Low Register
Bit 151413121110 9 8
0x3E (0x5E)
0x3D (0x5D)
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value
SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
76543210
R/W R/W R/W R/W R/W R/W R/W R/W
RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND
RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 22
7.6 Instruction Execution Timing
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
clk
CPU
This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by
the CPU clock clk
used.
Figure 7-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture
and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz
with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.
Figure 7-4. The Parallel Instruction Fetches and Instruction Executions
, directly generated from the selected clock source for the chip. No internal clock division is
CPU
ATmega48A/PA/88A/PA/168A/PA/328/P
Figure 7-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using
two register operands is executed, and the result is stored back to the destination register.
Figure 7-5. Single Cycle ALU Operation
7.7 Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each
have a separate program vector in the program memory space. All interrupts are assigned individual enable bits
which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to
enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when
Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section
”Memory Programming” on page 289 for details.
The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors.
The complete list of vectors is shown in ”Interrupts” on page 66. The list also determines the priority levels of the
different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and
next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot
Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to ”Interrupts” on page 66
for more information. The Reset Vector can also be moved to the start of the Boot Flash section by
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 23
ATmega48A/PA/88A/PA/168A/PA/328/P
programming the BOOTRST Fuse, see ”Boot Loader Support – Read-While-Write Self-Programming” on page
272.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user
software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the
current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is
executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For
these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt
handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by
writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the
corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is
enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global
Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global
Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not
necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the
interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one more
instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when
returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will
be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following
example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.
Assembly Code Example
in r16, SREG ; store SREG value
cli ; disable interrupts during timed
sequence
sbi EECR, EEMPE ; start EEPROM write
sbi EECR, EEPE
out SREG, r16 ; restore SREG value (I-
bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1<<EEMPE); /* start EEPROM write */
EECR |= (1<<EEPE);
SREG = cSREG; /* restore SREG value (I-bit) */
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any
pending interrupts, as shown in this example.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 24
Assembly Code Example
sei ; set Global Interrupt Enable
sleep ; enter sleep, waiting for interrupt
; note: will enter sleep before any pending interrupt(s)
C Code Example
__enable_interrupt(); /* set Global Interrupt Enable */
__sleep(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
7.7.1 Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four
clock cycles the program vector address for the actual interrupt handling routine is executed. During this four
clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt
routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle
instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in
sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in
addition to the start-up time from the selected sleep mode.
A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program
Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in
SREG is set.
ATmega48A/PA/88A/PA/168A/PA/328/P
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 25
ATmega48A/PA/88A/PA/168A/PA/328/P
8. AVR Memories
8.1 Overview
This section describes the different memories in the ATmega48A/PA/88A/PA/168A/PA/328/P. The AVR
architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the
ATmega48A/PA/88A/PA/168A/PA/328/P features an EEPROM Memory for data storage. All three memory
spaces are linear and regular.
8.2 In-System Reprogrammable Flash Program Memory
The ATmega48A/PA/88A/PA/168A/PA/328/P contains 4/8/16/32Kbytes On-chip In-System Reprogrammable
Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as
2/4/8/16K x 16. For software security, the Flash Program memory space is divided into two sections, Boot
Loader Section and Application Program Section in ATmega88PA and ATmega168PA. See SPMEN description
in section ”SPMCSR – Store Program Memory Control and Status Register” on page 287 for more details.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The
ATmega48A/PA/88A/PA/168A/PA/328/P Program Counter (PC) is 11/12/13/14 bits wide, thus addressing the
2/4/8/16K program memory locations. The operation of Boot Program section and associated Boot Lock bits for
software protection are described in detail in ”Self-Programming the Flash, ATmega 48A/48PA” on page 264
and ”Boot Loader Support – Read-While-Write Self-Programming” on page 272. ”Memory Programming” on
page 289 contains a detailed description on Flash Programming in SPI- or Parallel Programming mode.
Constant tables can be allocated within the entire program memory address space (see the LPM – Load
Program Memory instruction description).
Timing diagrams for instruction fetch and execution are presented in ”Instruction Execution Timing” on page 23.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 26
ATmega48A/PA/88A/PA/168A/PA/328/P
Figure 8-1. Program Memory Map ATmega 48A/48PA
Program Memory
Application Flash Section
0x0000
0x7FF
Figure 8-2. Program Memory Map ATmega88A, ATmega88PA, ATmega168A, ATmega168PA, ATmega328 and
ATmega328P
Program Memory
0x0000
Application Flash Section
Boot Flash Section
0x0FFF/0x1FFF/0x3FFF
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 27
8.3 SRAM Data Memory
Figure 8-3 shows how the ATmega48A/PA/88A/PA/168A/PA/328/P SRAM Memory is organized.
The ATmega48A/PA/88A/PA/168A/PA/328/P is a complex microcontroller with more peripheral units than can
be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended
I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
The lower 768/1280/1280/2303 data memory locations address both the Register File, the I/O memory,
Extended I/O memory, and the internal data SRAM. The first 32 locations address the Register File, the next 64
location the standard I/O memory, then 160 locations of Extended I/O memory, and the next
512/1024/1024/2048 locations address the internal data SRAM.
The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect,
Indirect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature
the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Zregister.
When using register indirect addressing modes with automatic pre-decrement and post-increment, the address
registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and the
512/1024/1024/2048 bytes of internal data SRAM in the ATmega48A/PA/88A/PA/168A/PA/328/P are all
accessible through all these addressing modes. The Register File is described in ”General Purpose Register
File” on page 20.
ATmega48A/PA/88A/PA/168A/PA/328/P
Figure 8-3. Data Memory Map
Data Memory
32 Registers
64 I/O Registers
160 Ext I/O Reg.
Internal SRAM
(512/1024/1024/2048 x 8)
0x0000 - 0x001F
0x0020 - 0x005F
0x0060 - 0x00FF
0x0100
0x02FF/0x04FF/0x4FF/0x08FF
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 28
8.3.1 Data Memory Access Times
clk
WR
RD
Data
Data
Address
Address valid
T1 T2 T3
Compute Address
Read
Write
CPU
Memory Access Instruction
Next Instruction
This section describes the general access timing concepts for internal memory access. The internal data SRAM
access is performed in two clk
Figure 8-4. On-chip Data SRAM Access Cycles
ATmega48A/PA/88A/PA/168A/PA/328/P
cycles as described in Figure 8-4.
CPU
8.4 EEPROM Data Memory
The ATmega48A/PA/88A/PA/168A/PA/328/P contains 256/512/512/1Kbytes of data EEPROM memory. It is
organized as a separate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described
in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM
Control Register.
”Memory Programming” on page 289 contains a detailed description on EEPROM Programming in SPI or
Parallel Programming mode.
8.4.1 EEPROM Read/Write Access
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 8-2. A self-timing function, however, lets the user
software detect when the next byte can be written. If the user code contains instructions that write the EEPROM,
some precautions must be taken. In heavily filtered power supplies, V
up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for
the clock frequency used. See ”Preventing EEPROM Corruption” on page 30 for details on how to avoid
problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the
description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed.
When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.
is likely to rise or fall slowly on power-
CC
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 29
8.4.2 Preventing EEPROM Corruption
ATmega48A/PA/88A/PA/168A/PA/328/P
During periods of low V
CPU and the EEPROM to operate properly. These issues are the same as for board level systems using
EEPROM, and the same design solutions should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write
sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can
execute instructions incorrectly, if the supply voltage is too low.
EEPROM data corruption can easily be avoided by following this design recommendation:
Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by
enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the
needed detection level, an external low V
operation is in progress, the write operation will be completed provided that the power supply voltage is
sufficient.
8.5 I/O Memory
The I/O space definition of the ATmega48A/PA/88A/PA/168A/PA/328/P is shown in ”Register Summary” on
page 621.
All ATmega48A/PA/88A/PA/168A/PA/328/P I/Os and peripherals are placed in the I/O space. All I/O locations
may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general
purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bitaccessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by
using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O
specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers
as data space using LD and ST instructions, 0x20 must be added to these addresses. The
ATmega48A/PA/88A/PA/168A/PA/328/P is a complex microcontroller with more peripheral units than can be
supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O
space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory
addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the
CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing
such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
the EEPROM data can be corrupted because the supply voltage is too low for the
CC,
reset Protection circuit can be used. If a reset occurs while a write
CC
8.5.1 General Purpose I/O Registers
The ATmega48A/PA/88A/PA/168A/PA/328/P contains three General Purpose I/O Registers. These registers
can be used for storing any information, and they are particularly useful for storing global variables and Status
Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the
SBI, CBI, SBIS, and SBIC instructions.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 30
ATmega48A/PA/88A/PA/168A/PA/328/P
8.6 Register Description
8.6.1 EEARH and EEARL – The EEPROM Address Register
Bit 151413121110 9 8
0x22 (0x42)
0x21 (0x41)
Read/WriteRRRRRR RR/W
Initial Value000000 0 X
––––––EEAR9
EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0
765432 1 0
R/W R/W R/W R/W R/W R/W R/W R/W
XXXXXX X X
• Bits [15:10] – Reserved
These bits are reserved bits in the ATmega48A/PA/88A/PA/168A/PA/328/P and will always read as zero.
• Bits 9:0 – EEAR[9:0]: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the
256/512/512/1Kbytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and
255/511/511/1023. The initial value of EEAR is undefined. A proper value must be written before the EEPROM
may be accessed.
Note: 1. EEAR9 and EEAR8 are unused bits in ATmega 48A/48PA and must always be written to zero.
8.6.2 EEDR – The EEPROM Data Register
Bit 76543210
0x20 (0x40)
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
MSB LSB EEDR
(1)
EEAR8
(1)
EEARH
EEARL
• Bits 7:0 – EEDR[7:0]: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the
address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out
from the EEPROM at the address given by EEAR.
8.6.3 EECR – The EEPROM Control Register
Bit 76543 2 10
0x1F (0x3F)
Read/Write R R R/W R/W R/W R/W R/W R/W
Initial Value 0 0 X X 0 0 X 0
– – EEPM1 EEPM0 EERIE EEMPE EEPE EERE EECR
• Bits 7:6 – Reserved
These bits are reserved bits in the ATmega48A/PA/88A/PA/168A/PA/328/P and will always read as zero.
• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits
The EEPROM Programming mode bit setting defines which programming action that will be triggered when
writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new
value) or to split the Erase and Write operations in two different operations. The Programming times for the
different modes are shown in Table 8-1. While EEPE is set, any write to EEPMn will be ignored. During reset,
the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 31
ATmega48A/PA/88A/PA/168A/PA/328/P
Table 8-1. EEPROM Mode Bits
Programming
EEPM1 EEPM0
0 0 3.4ms Erase and Write in one operation (Atomic Operation)
0 1 1.8ms Erase Only
1 0 1.8ms Write Only
1 1 – Reserved for future use
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero
disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEPE is cleared. The
interrupt will not be generated during EEPROM write or SPM.
• Bit 2 – EEMPE: EEPROM Master Write Enable
The EEMPE bit determines whether setting EEPE to one causes the EEPROM to be written. When EEMPE is
set, setting EEPE within four clock cycles will write data to the EEPROM at the selected address If EEMPE is
zero, setting EEPE will have no effect. When EEMPE has been written to one by software, hardware clears the
bit to zero after four clock cycles. See the description of the EEPE bit for an EEPROM write procedure.
Time Operation
• Bit 1 – EEPE: EEPROM Write Enable
The EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. When address and data are
correctly set up, the EEPE bit must be written to one to write the value into the EEPROM. The EEMPE bit must
be written to one before a logical one is written to EEPE, otherwise no EEPROM write takes place. The
following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential):
1. Wait until EEPE becomes zero.
2. Wait until SPMEN in SPMCSR becomes zero.
3. Write new EEPROM address to EEAR (optional).
4. Write new EEPROM data to EEDR (optional).
5. Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR.
6. Within four clock cycles after setting EEMPE, write a logical one to EEPE.
The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that
the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the
software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being updated by
the CPU, step 2 can be omitted. See ”Boot Loader Support – Read-While-Write Self-Programming” on page 272
for details about Boot programming.
Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write
Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the
EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to
have the Global Interrupt Flag cleared during all the steps to avoid these problems.
When the write access time has elapsed, the EEPE bit is cleared by hardware. The user software can poll this
bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is halted for two cycles
before the next instruction is executed.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 32
ATmega48A/PA/88A/PA/168A/PA/328/P
• Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set
up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The
EEPROM read access takes one instruction, and the requested data is available immediately. When the
EEPROM is read, the CPU is halted for four cycles before the next instruction is executed.
The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it is
neither possible to read the EEPROM, nor to change the EEAR Register.
The calibrated Oscillator is used to time the EEPROM accesses. Table 8-2 lists the typical programming time for
EEPROM access from the CPU.
Table 8-2. EEPROM Programming Time
Symbol Number of Calibrated RC Oscillator Cycles Typ Programming Time
EEPROM write
(from CPU)
The following code examples show one assembly and one C function for writing to the EEPROM. The examples
assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during
execution of these functions. The examples also assume that no Flash Boot Loader is present in the software. If
such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.
26,368 3.3ms
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 33
Assembly Code Example
EEPROM_write:
; Wait for completion of previous write
sbic EECR,EEPE
rjmp EEPROM_write
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Write data (r16) to Data Register
out EEDR,r16
; Write logical one to EEMPE
sbi EECR,EEMPE
; Start eeprom write by setting EEPE
sbi EECR,EEPE
ret
C Code Example
void EEPROM_write(unsigned int uiAddress, unsigned char ucData)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEPE))
;
/* Set up address and Data Registers */
EEAR = uiAddress;
EEDR = ucData;
/* Write logical one to EEMPE */
EECR |= (1<<EEMPE);
/* Start eeprom write by setting EEPE */
EECR |= (1<<EEPE);
}
ATmega48A/PA/88A/PA/168A/PA/328/P
The next code examples show assembly and C functions for reading the EEPROM. The examples assume that
interrupts are controlled so that no interrupts will occur during execution of these functions.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 34
Assembly Code Example
EEPROM_read:
; Wait for completion of previous write
sbic EECR,EEPE
rjmp EEPROM_read
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Start eeprom read by writing EERE
sbi EECR,EERE
; Read data from Data Register
in r16,EEDR
ret
C Code Example
unsigned char EEPROM_read(unsigned int uiAddress)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEPE))
;
/* Set up address register */
EEAR = uiAddress;
/* Start eeprom read by writing EERE */
EECR |= (1<<EERE);
/* Return data from Data Register */
return EEDR;
}
ATmega48A/PA/88A/PA/168A/PA/328/P
8.6.4 GPIOR2 – General Purpose I/O Register 2
Bit 76543210
0x2B (0x4B)
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
MSB LSB GPIOR2
8.6.5 GPIOR1 – General Purpose I/O Register 1
Bit 76543210
0x2A (0x4A)
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
MSB LSB GPIOR1
8.6.6 GPIOR0 – General Purpose I/O Register 0
Bit 76543210
0x1E (0x3E)
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
MSB LSB GPIOR0
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 35
ATmega48A/PA/88A/PA/168A/PA/328/P
9. System Clock and Clock Options
9.1 Clock Systems and their Distribution
Figure 9-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be
active at a given time. In order to reduce power consumption, the clocks to modules not being used can be
halted by using different sleep modes, as described in ”Power Management and Sleep Modes” on page 48. The
clock systems are detailed below.
Figure 9-1. Clock Distribution
Asynchronous
Timer/Counter
Timer/Counter
Oscillator
General I/O
Modules
clk
I/O
clk
ASY
External Clock
ADC
clk
AVR Clock
Control Unit
System Clock
Prescaler
Source clock
Clock
Multiplexer
Oscillator
ADC
Crystal
CPU Core RAM
clk
CPU
clk
FLASH
Reset Logic
Watchdog Timer
Watchdog clock
Watchdog
Oscillator
Low-frequency
Crystal Oscillator
Flash and
EEPROM
Calibrated RC
Oscillator
9.1.1 CPU Clock – clk
The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such
modules are the General Purpose Register File, the Status Register and the data memory holding the Stack
Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations.
9.1.2 I/O Clock – clk
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART. The I/O clock is
also used by the External Interrupt module, but note that start condition detection in the USI module is carried
out asynchronously when clk
Note: Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be held long
enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of
the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the
SUT and CKSEL Fuses as described in ”System Clock and Clock Options” on page 36.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 36
I/O
CPU
is halted, TWI address recognition in all sleep modes.
I/O
ATmega48A/PA/88A/PA/168A/PA/328/P
9.1.3 Flash Clock – clk
FLASH
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with
the CPU clock.
9.1.4 Asynchronous Timer Clock – clk
The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external
clock or an external 32kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a realtime counter even when the device is in sleep mode.
9.1.5 ADC Clock – clk
ADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to
reduce noise generated by digital circuitry. This gives more accurate ADC conversion results.
9.2 Clock Sources
The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock
from the selected source is input to the AVR clock generator, and routed to the appropriate modules.
Table 9-1. Device Clocking Options Select
Device Clocking Option CKSEL3...0
Low Power Crystal Oscillator 1111 - 1000
Full Swing Crystal Oscillator 0111 - 0110
Low Frequency Crystal Oscillator 0101 - 0100
ASY
(1)
Internal 128kHz RC Oscillator 0011
Calibrated Internal RC Oscillator 0010
External Clock 0000
Reserved 0001
Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.
9.2.1 Default Clock Source
The device is shipped with internal RC oscillator at 8.0MHz and with the fuse CKDIV8 programmed, resulting in
1.0MHz system clock. The startup time is set to maximum and time-out period enabled. (CKSEL = "0010", SUT
= "10", CKDIV8 = "0"). The default setting ensures that all users can make their desired clock source setting
using any available programming interface.
9.2.2 Clock Startup Sequence
Any clock source needs a sufficient V
can be considered stable.
To ensure sufficient V
, the device issues an internal reset with a time-out delay (t
CC
released by all other reset sources. ”System Control and Reset” on page 56 describes the start conditions for
the internal reset. The delay (t
is set by the SUTx and CKSELx fuse bits. The selectable delays are shown in Table 9-2. The frequency of the
Watchdog Oscillator is voltage dependent as shown in ”Typical Characteristics – (TA = -40°C to 85°C)” on page
326.
to start oscillating and a minimum number of oscillating cycles before it
CC
) after the device reset is
TOUT
) is timed from the Watchdog Oscillator and the number of cycles in the delay
TOUT
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 37
ATmega48A/PA/88A/PA/168A/PA/328/P
XTAL2 (TOSC2)
XTAL1 (TOSC1)
GND
C2
C1
Table 9-2. Number of Watchdog Oscillator Cycles
Typ Time-out (VCC = 5.0V) Typ Time-out (VCC = 3.0V) Number of Cycles
0ms 0ms 0
4.1ms 4.3ms 512
65ms 69ms 8K (8,192)
Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum VCC. The delay will not
monitor the actual voltage and it will be required to select a delay longer than the V
possible, an internal or external Brown-Out Detection circuit should be used. A BOD circuit will ensure sufficient
V
before it releases the reset, and the time-out delay can be disabled. Disabling the time-out delay without
CC
utilizing a Brown-Out Detection circuit is not recommended.
The oscillator is required to oscillate for a minimum number of cycles before the clock is considered stable. An
internal ripple counter monitors the oscillator output clock, and keeps the internal reset active for a given
number of clock cycles. The reset is then released and the device will start to execute. The recommended
oscillator start-up time is dependent on the clock type, and varies from 6 cycles for an externally applied clock to
32K cycles for a low frequency crystal.
The start-up sequence for the clock includes both the time-out delay and the start-up time when the device
starts up from reset. When starting up from Power-save or Power-down mode, V
sufficient level and only the start-up time is included.
rise time. If this is not
CC
is assumed to be at a
CC
9.3 Low Power Crystal Oscillator
Pins XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for
use as an On-chip Oscillator, as shown in Figure 9-2 on page 38. Either a quartz crystal or a ceramic resonator
may be used.
This Crystal Oscillator is a low power oscillator, with reduced voltage swing on the XTAL2 output. It gives the
lowest power consumption, but is not capable of driving other clock inputs, and may be more susceptible to
noise in noisy environments. In these cases, refer to the ”Full Swing Crystal Oscillator” on page 39.
C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors
depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of
the environment. Some initial guidelines for choosing capacitors for use with crystals are given in Table 9-3 on
page 39. For ceramic resonators, the capacitor values given by the manufacturer should be used.
Figure 9-2. Crystal Oscillator Connections
The Low Power Oscillator can operate in three different modes, each optimized for a specific frequency range.
The operating mode is selected by the fuses CKSEL3...1 as shown in Table 9-3 on page 39.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 38
ATmega48A/PA/88A/PA/168A/PA/328/P
Table 9-3. Low Power Crystal Oscillator Operating Modes
Frequency Range
(MHz)
Recommended Range for
Capacitors C1 and C2 (pF) CKSEL3...1
0.4 - 0.9 – 100
(3)
(1)
(2)
0.9 - 3.0 12 - 22 101
3.0 - 8.0 12 - 22 110
8.0 - 16.0 12 - 22 111
Notes: 1. This is the recommended CKSEL settings for the difference frequency ranges.
2. This option should not be used with crystals, only with ceramic resonators.
3. If the crystal frequency exceeds the specification of the device (depends on V
), the CKDIV8 Fuse can be
CC
programmed in order to divide the internal frequency by 8. It must be ensured that the resulting divided clock
meets the frequency specification of the device.
The CKSEL0 Fuse together with the SUT1...0 Fuses select the start-up times as shown in Table 9-4.
Table 9-4. Start-up Times for the Low Power Crystal Oscillator Clock Selection
Oscillator Source /
Power Conditions
Ceramic resonator, fast
rising power
Ceramic resonator, slowly
rising power
Ceramic resonator, BOD
enabled
Start-up Time from
Power-down and
Power-save
258 CK 14CK + 4.1ms
258 CK 14CK + 65ms
1K CK 14CK
Additional Delay
from Reset
(V
= 5.0V) CKSEL0 SUT1...0
CC
(1)
(1)
(2)
0 00
0 01
0 10
Ceramic resonator, fast
rising power
Ceramic resonator, slowly
rising power
Crystal Oscillator, BOD
enabled
Crystal Oscillator, fast
rising power
Crystal Oscillator, slowly
rising power
16K CK 14CK 1 01
16K CK 14CK + 4.1ms 1 10
16K CK 14CK + 65ms 1 11
Notes: 1. These options should only be used when not operating close to the maximum frequency of the device, and
only if frequency stability at start-up is not important for the application. These options are not suitable for
crystals.
2. These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They
can also be used with crystals when not operating close to the maximum frequency of the device, and if
frequency stability at start-up is not important for the application.
9.4 Full Swing Crystal Oscillator
Pins XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for
use as an On-chip Oscillator, as shown in Figure 9-2 on page 38. Either a quartz crystal or a ceramic resonator
may be used.
1K CK 14CK + 4.1ms
1K CK 14CK + 65ms
(2)
(2)
0 11
1 00
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 39
ATmega48A/PA/88A/PA/168A/PA/328/P
XTAL2 (TOSC2)
XTAL1 (TOSC1)
GND
C2
C1
This Crystal Oscillator is a full swing oscillator, with rail-to-rail swing on the XTAL2 output. This is useful for
driving other clock inputs and in noisy environments. The current consumption is higher than the ”Low Power
Crystal Oscillator” on page 38. Note that the Full Swing Crystal Oscillator will only operate for V
volts.
C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors
depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of
the environment. Some initial guidelines for choosing capacitors for use with crystals are given in Table 9-6 on
page 40. For ceramic resonators, the capacitor values given by the manufacturer should be used.
The operating mode is selected by the fuses CKSEL3...1 as shown in Table 9-5.
Table 9-5. Full Swing Crystal Oscillator operating modes
Frequency Range
(MHz)
0.4 - 20 12 - 22 011
Notes: 1. If the cryatal frequency exceeds the specification of the device (depends on VCC), the CKDIV8 Fuse can be
Figure 9-3. Crystal Oscillator Connections
(1)
programmed in order to divide the internal frequency by 8. It must be ensured that the resulting divided clock
meets the frequency specification of the device.
Recommended Range for
Capacitors C1 and C2 (pF)
CKSEL3...1
= 2.7 - 5.5
CC
Table 9-6. Start-up Times for the Full Swing Crystal Oscillator Clock Selection
Oscillator Source /
Power Conditions
Ceramic resonator, fast
rising power
Ceramic resonator, slowly
rising power
Ceramic resonator, BOD
enabled
Ceramic resonator, fast
rising power
Ceramic resonator, slowly
rising power
Start-up Time from
Power-down and
Power-save
258 CK 14CK + 4.1ms
258 CK 14CK + 65ms
1K CK 14CK
1K CK 14CK + 4.1ms
1K CK 14CK + 65ms
Additional Delay
from Reset
= 5.0V) CKSEL0 SUT1...0
(V
CC
(1)
(1)
(2)
(2)
(2)
0 00
0 01
0 10
0 11
1 00
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 40
ATmega48A/PA/88A/PA/168A/PA/328/P
Table 9-6. Start-up Times for the Full Swing Crystal Oscillator Clock Selection (Continued)
Oscillator Source /
Power Conditions
Crystal Oscillator, BOD
enabled
Start-up Time from
Power-down and
Power-save
16K CK 14CK 1 01
Additional Delay
from Reset
= 5.0V) CKSEL0 SUT1...0
(V
CC
Crystal Oscillator, fast
rising power
Crystal Oscillator, slowly
rising power
Notes: 1. These options should only be used when not operating close to the maximum frequency of the device, and
only if frequency stability at start-up is not important for the application. These options are not suitable for
crystals.
2. These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They
can also be used with crystals when not operating close to the maximum frequency of the device, and if
frequency stability at start-up is not important for the application.
16K CK 14CK + 4.1ms 1 10
16K CK 14CK + 65ms 1 11
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 41
ATmega48A/PA/88A/PA/168A/PA/328/P
C 2 CL Cs–=
9.5 Low Frequency Crystal Oscillator
The Low-frequency Crystal Oscillator is optimized for use with a 32.768kHz watch crystal. When selecting
crystals, load capacitance and crystal’s Equivalent Series Resistance, ESR must be taken into consideration.
Both values are specified by the crystal vendor. ATmega48A/PA/88A/PA/168A/PA/328/P oscillator is optimized
for very low power consumption, and thus when selecting crystals, see Table 9-7 for maximum ESR
recommendations on 6.5pF, 9.0pF and 12.5pF crystals
Table 9-7. Maximum ESR Recommendation for 32.768kHz Crystal
Crystal CL (pF) Max ESR [k]
6.5 75
9.0 65
12.5 30
Note: 1. Maximum ESR is typical value based on characterization
The Low-frequency Crystal Oscillator provides an internal load capacitance, see Table 9-8 at each TOSC pin.
Table 9-8. Capacitance for Low-frequency Oscillator
Device 32kHz Osc. Type Cap(Xtal1/Tosc1) Cap(Xtal2/Tosc2)
ATmega48A/PA/88A/PA/168A/PA/3
28/P
System Osc. 18pF 8pF
Timer Osc. 18pF 8pF
(1)
The capacitance (Ce+Ci) needed at each TOSC pin can be calculated by using:
where:
Ce - is optional external capacitors as described in Figure 9-2 on page 38
Ci - is the pin capacitance in Table 9-8
CL - is the load capacitance for a 32.768kHz crystal specified by the crystal vendor
CS - is the total stray capacitance for one TOSC pin.
Crystals specifying load capacitance (CL) higher than 6 pF, require external capacitors applied as described in
Figure 9-2 on page 38.
The Low-frequency Crystal Oscillator must be selected by setting the CKSEL Fuses to “0110” or “0111”, as
shown in Table 9-10 on page 42. Start-up times are determined by the SUT Fuses as shown in Table 9-9.
Table 9-9. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection
SUT1...0 Additional Delay from Reset (VCC = 5.0V) Recommended Usage
00 4 CK Fast rising power or BOD enabled
01 4 CK + 4.1ms Slowly rising power
10 4 CK + 65ms Stable frequency at start-up
11 Reserved
Table 9-10. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection
CKSEL3...
0
(1)
0100
0101 32K CK Stable frequency at start-up
Start-up Time from
Power-down and Power-save
1K CK
Recommended Usage
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 42
ATmega48A/PA/88A/PA/168A/PA/328/P
Note: 1. This option should only be used if frequency stability at start-up is not important for the application
9.6 Calibrated Internal RC Oscillator
By default, the Internal RC Oscillator provides an approximate 8.0MHz clock. Though voltage and temperature
dependent, this clock can be very accurately calibrated by the user. See Table 29-9 on page 313 for more
details. The device is shipped with the CKDIV8 Fuse programmed. See ”System Clock Prescaler” on page 45
for more details.
This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 9-11. If
selected, it will operate with no external components. During reset, hardware loads the pre-programmed
calibration value into the OSCCAL Register and thereby automatically calibrates the RC Oscillator. The
accuracy of this calibration is shown as Factory calibration in Table 29-9 on page 313.
By changing the OSCCAL register from SW, see ”OSCCAL – Oscillator Calibration Register” on page 46, it is
possible to get a higher calibration accuracy than by using the factory calibration. The accuracy of this
calibration is shown as User calibration in Table 29-9 on page 313.
When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer
and for the Reset Time-out. For more information on the pre-programmed calibration value, see the section
”Calibration Byte” on page 293.
Table 9-11. Internal Calibrated RC Oscillator Operating Modes
Frequency Range
7.3 - 8.1 0010
(2)
(MHz) CKSEL3...0
(1)
Notes: 1. The device is shipped with this option selected.
2. If 8MHz frequency exceeds the specification of the device (depends on V
programmed in order to divide the internal frequency by 8.
When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 9-12.
Table 9-12. Start-up times for the internal calibrated RC Oscillator clock selection
Start-up Time from Power-
Power Conditions
BOD enabled 6 CK 14CK
Fast rising power 6 CK 14CK + 4.1ms 01
Slowly rising power 6 CK 14CK + 65ms
Note: 1. If the RSTDISBL fuse is programmed, this start-up time will be increased to
14CK + 4.1ms to ensure programming mode can be entered.
The device is shipped with this option selected.
2.
9.7 128kHz Internal Oscillator
The 128kHz internal Oscillator is a low power Oscillator providing a clock of 128kHz. The frequency is nominal
at 3V and 25C. This clock may be select as the system clock by programming the CKSEL Fuses to “11” as
shown in Table 9-13.
Additional Delay from
down and Power-save
Reserved 11
Reset (V
= 5.0V) SUT1...0
CC
(1)
), the CKDIV8 Fuse can be
CC
00
(2)
10
Table 9-13. 128kHz Internal Oscillator Operating Modes
Nominal Frequency
128kHz 0011
Note: 1. Note that the 128kHz oscillator is a very low power clock source, and is not designed for high accuracy.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 43
(1)
CKSEL3...0
ATmega48A/PA/88A/PA/168A/PA/328/P
PB7
EXTERNAL
CLOCK
SIGNAL
XTAL2
XTAL1
GND
When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 9-14.
Table 9-14. Start-up Times for the 128kHz Internal Oscillator
Power Conditions
BOD enabled 6 CK 14CK
Fast rising power 6 CK 14CK + 4ms 01
Slowly rising power 6 CK 14CK + 64ms 10
Note: 1. If the RSTDISBL fuse is programmed, this start-up time will be increased to
14CK + 4.1ms to ensure programming mode can be entered.
9.8 External Clock
To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 9-4. To run the
device on an external clock, the CKSEL Fuses must be programmed to “0000” (see Table 9-15).
Table 9-15. Crystal Oscillator Clock Frequency
Figure 9-4. External Clock Drive Configuration
Start-up Time from Power-
down and Power-save
Reserved 11
Frequency CKSEL3...0
0 - 20MHz 0000
Additional Delay from
Reset SUT1...0
(1)
00
When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 9-16.
Table 9-16. Start-up Times for the External Clock Selection
Start-up Time from Power-
Power Conditions
BOD enabled 6 CK 14CK 00
Fast rising power 6 CK 14CK + 4.1ms 01
Slowly rising power 6 CK 14CK + 65ms 10
down and Power-save
Reserved 11
Additional Delay from
Reset (VCC = 5.0V) SUT1...0
When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to
ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next
can lead to unpredictable behavior. If changes of more than 2% is required, ensure that the MCU is kept in
Reset during the changes.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 44
Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock
frequency while still ensuring stable operation. Refer to ”System Clock Prescaler” on page 45 for details.
9.9 Clock Output Buffer
The device can output the system clock on the CLKO pin. To enable the output, the CKOUT Fuse has to be
programmed. This mode is suitable when the chip clock is used to drive other circuits on the system. The clock
also will be output during reset, and the normal operation of I/O pin will be overridden when the fuse is
programmed. Any clock source, including the internal RC Oscillator, can be selected when the clock is output on
CLKO. If the System Clock Prescaler is used, it is the divided system clock that is output.
9.10 Timer/Counter Oscillator
ATmega48A/PA/88A/PA/168A/PA/328/P uses the same crystal oscillator for Low-frequency Oscillator and
Timer/Counter Oscillator. See ”Low Frequency Crystal Oscillator” on page 42 for details on the oscillator and
crystal requirements.
ATmega48A/PA/88A/PA/168A/PA/328/P share the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) with
XTAL1 and XTAL2. When using the Timer/Counter Oscillator, the system clock needs to be four times the
oscillator frequency. Due to this and the pin sharing, the Timer/Counter Oscillator can only be used when the
Calibrated Internal RC Oscillator is selected as system clock source.
ATmega48A/PA/88A/PA/168A/PA/328/P
Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR Register is written to logic
one. See ”Asynchronous Operation of Timer/Counter2” on page 160 for further description on selecting external
clock as input instead of a 32.768kHz watch crystal.
9.11 System Clock Prescaler
The ATmega48A/PA/88A/PA/168A/PA/328/P has a system clock prescaler, and the system clock can be
divided by setting the ”CLKPR – Clock Prescale Register” on page 46. This feature can be used to decrease the
system clock frequency and the power consumption when the requirement for processing power is low. This can
be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous
peripherals. clk
When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occurs in the
clock system. It also ensures that no intermediate frequency is higher than neither the clock frequency
corresponding to the previous setting, nor the clock frequency corresponding to the new setting. The ripple
counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the
CPU's clock frequency. Hence, it is not possible to determine the state of the prescaler - even if it were
readable, and the exact time it takes to switch from one clock division to the other cannot be exactly predicted.
From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2 * T2 before the new clock
frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the previous clock period,
and T2 is the period corresponding to the new prescaler setting.
To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the
CLKPS bits:
I/O
, clk
ADC
, clk
CPU
, and clk
are divided by a factor as shown in Table 29-11 on page 314.
FLASH
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero.
2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 45
ATmega48A/PA/88A/PA/168A/PA/328/P
9.12 Register Description
9.12.1 OSCCAL – Oscillator Calibration Register
Bit 76543210
(0x66) CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value Device Specific Calibration Value
• Bits 7:0 – CAL[7:0]: Oscillator Calibration Value
The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process
variations from the oscillator frequency. A pre-programmed calibration value is automatically written to this
register during chip reset, giving the Factory calibrated frequency as specified in Table 29-9 on page 313. The
application software can write this register to change the oscillator frequency. The oscillator can be calibrated to
frequencies as specified in Table 29-9 on page 313. Calibration outside that range is not ensured.
Note that this oscillator is used to time EEPROM and Flash write accesses, and these write times will be
affected accordingly. If the EEPROM or Flash are written, do not calibrate to more than 8.8MHz. Otherwise, the
EEPROM or Flash write may fail.
The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the lowest frequency
range, setting this bit to 1 gives the highest frequency range. The two frequency ranges are overlapping, in other
words a setting of OSCCAL = 0x7F gives a higher frequency than OSCCAL = 0x80.
The CAL6...0 bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest
frequency in that range, and a setting of 0x7F gives the highest frequency in the range.
9.12.2 CLKPR – Clock Prescale Register
Bit 76543210
(0x61)
Read/Write R/W R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 See Bit Description
CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPR
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only
updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four
cycles after it is written or when CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period
does neither extend the time-out period, nor clear the CLKPCE bit.
• Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal system clock. These bits
can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides
the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is
used. The division factors are given in Table 9-17 on page 47.
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits
will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor of 8 at
start up. This feature should be used if the selected clock source has a higher frequency than the maximum
frequency of the device at the present operating conditions. Note that any value can be written to the CLKPS
bits regardless of the CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor
is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the
present operating conditions. The device is shipped with the CKDIV8 Fuse programmed.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 46
ATmega48A/PA/88A/PA/168A/PA/328/P
Table 9-17. Clock Prescaler Select
CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor
0 0 0 0 1
0 0 0 1 2
0 0 1 0 4
0 0 1 1 8
0 1 0 0 16
0 1 0 1 32
0 1 1 0 64
0 1 1 1 128
1 0 0 0 256
1 0 0 1 Reserved
1 0 1 0 Reserved
1 0 1 1 Reserved
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 47
ATmega48A/PA/88A/PA/168A/PA/328/P
10. Power Management and Sleep Modes
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR
provides various sleep modes allowing the user to tailor the power consumption to the application’s
requirements.
When enabled, the Brown-out Detector (BOD) actively monitors the power supply voltage during the sleep
periods. To further save power, it is possible to disable the BOD in some sleep modes. See ”BOD Disable
page 49 for more details.
10.1 Sleep Modes
Figure 9-1 on page 36 presents the different clock systems in the ATmega48A/PA/88A/PA/168A/PA/328/P, and
their distribution. The figure is helpful in selecting an appropriate sleep mode. Table 10-1 shows the different
sleep modes, their wake up sources BOD disable ability.
Note: 1. BOD disable is only available for ATmega48PA/88PA/168PA/328P.
Table 10-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes
Active Clock Domains Oscillators Wake-up Sources
CPU
FLASH
clk
Sleep Mode
clk
Idle X X X X X
ADC Noise
Reduction
ADC
ASY
clkIOclk
clk
X X X X
Main Clock
Source Enabled
(1)
Timer Oscillator
Enabled
INT1, INT0 and
Pin Change
TWI Address
Match
(2)
(2)
X X X X X X X
X X X
(1)
” on
Software
Timer2
(2)
SPM/EEPROM
Ready
ADC
X X X
WDT
Other I/O
BOD Disable
Power-down X X X X
Power-save X X
Standby
Extended
Standby
Notes: 1. Only recommended with external crystal or resonator selected as clock source.
(1)
(2)
X
2. If Timer/Counter2 is running in asynchronous mode.
X X X X X
X X
(2)
(2)
X X X X X
X X X X X
To enter any of the six sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP instruction
must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select which sleep mode (Idle, ADC
Noise Reduction, Power-down, Power-save, Standby, or Extended Standby) will be activated by the SLEEP
instruction. See Table 10-2 on page 53 for a summary.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for
four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the
instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes
up from sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 48
ATmega48A/PA/88A/PA/168A/PA/328/P
10.2 BOD Disable
When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses - see Table 28-7 on page 291 and
onwards, the BOD is actively monitoring the power supply voltage during a sleep period. To save power, it is
possible to disable the BOD by software for some of the sleep modes, see Table 10-1 on page 48. The sleep
mode power consumption will then be at the same level as when BOD is globally disabled by fuses. If BOD is
disabled in software, the BOD function is turned off immediately after entering the sleep mode. Upon wake-up
from sleep, BOD is automatically enabled again. This ensures safe operation in case the V
during the sleep period.
When the BOD has been disabled, the wake-up time from sleep mode will be approximately 60 µs to ensure
that the BOD is working correctly before the MCU continues executing code.
BOD disable is controlled by bit 6, BODS (BOD Sleep) in the control register MCUCR, see ”MCUCR – MCU
Control Register” on page 54. Writing this bit to one turns off the BOD in relevant sleep modes, while a zero in
this bit keeps BOD active. Default setting keeps BOD active, i.e. BODS set to zero.
Writing to the BODS bit is controlled by a timed sequence and an enable bit, see ”MCUCR – MCU Control
Register” on page 54.
Note: 1. BOD disable only available in picoPower® devices ATmega48PA/88PA/168PA/328P
10.3 Idle Mode
When the SM2...0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the
CPU but allowing the SPI, USART, Analog Comparator, ADC, 2-wire Serial Interface, Timer/Counters,
Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clk
while allowing the other clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer
Overflow and USART Transmit Complete interrupts. If wake-up from the Analog Comparator interrupt is not
required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator
Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a
conversion starts automatically when this mode is entered.
(1)
level has dropped
CC
and clk
CPU
FLASH
,
10.4 ADC Noise Reduction Mode
When the SM2...0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC Noise Reduction
mode, stopping the CPU but allowing the ADC, the external interrupts, the 2-wire Serial Interface address
watch, Timer/Counter2
clk
I/O
, clk
CPU
, and clk
(1)
, and the Watchdog to continue operating (if enabled). This sleep mode basically halts
, while allowing the other clocks to run.
FLASH
This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is
enabled, a conversion starts automatically when this mode is entered. Apart from the ADC Conversion
Complete interrupt, only an External Reset, a Watchdog System Reset, a Watchdog Interrupt, a Brown-out
Reset, a 2-wire Serial Interface address match, a Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt,
an external level interrupt on INT0 or INT1 or a pin change interrupt can wake up the MCU from ADC Noise
Reduction mode.
Note: 1. Timer/Counter2 will only keep running in asynchronous mode, see ”8-bit Timer/Counter2 with PWM and Asyn-
chronous Operation” on page 150 for details.
10.5 Power-down Mode
When the SM2...0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-down mode. In
this mode, the external Oscillator is stopped, while the external interrupts, the 2-wire Serial Interface address
watch, and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog System Reset, a
Watchdog Interrupt, a Brown-out Reset, a 2-wire Serial Interface address match, an external level interrupt on
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 49
INT0 or INT1, or a pin change interrupt can wake up the MCU. This sleep mode basically halts all generated
clocks, allowing operation of asynchronous modules only.
Note: If a level triggered interrupt is used for wake-up from Power-down, the required level must be held long enough for
the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the Start-up
Time, the MCU will still wake up, but no interrupt will be generated. ”External Interrupts” on page 79. The start-up
time is defined by the SUT and CKSEL Fuses as described in ”System Clock and Clock Options” on page 36.
When waking up from Power-down mode, there is a delay from the wake-up condition occurs until the wake-up
becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up
period is defined by the same CKSEL Fuses that define the Reset Time-out period, as described in ”Clock
Sources” on page 37.
10.6 Power-save Mode
When the SM2...0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-save mode. This
mode is identical to Power-down, with one exception:
If Timer/Counter2 is enabled, it will keep running during sleep. The device can wake up from either Timer
Overflow or Output Compare event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable
bits are set in TIMSK2, and the Global Interrupt Enable bit in SREG is set.
If Timer/Counter2 is not running, Power-down mode is recommended instead of Power-save mode.
ATmega48A/PA/88A/PA/168A/PA/328/P
The Timer/Counter2 can be clocked both synchronously and asynchronously in Power-save mode. If
Timer/Counter2 is not using the asynchronous clock, the Timer/Counter Oscillator is stopped during sleep. If
Timer/Counter2 is not using the synchronous clock, the clock source is stopped during sleep. Note that even if
the synchronous clock is running in Power-save, this clock is only available for Timer/Counter2.
10.7 Standby Mode
When the SM2...0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction
makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the
Oscillator is kept running. From Standby mode, the device wakes up in six clock cycles.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 50
ATmega48A/PA/88A/PA/168A/PA/328/P
10.8 Extended Standby Mode
When the SM2...0 bits are 111 and an external crystal/resonator clock option is selected, the SLEEP instruction
makes the MCU enter Extended Standby mode. This mode is identical to Power-save with the exception that
the Oscillator is kept running. From Extended Standby mode, the device wakes up in six clock cycles.
10.9 Power Reduction Register
The Power Reduction Register (PRR), see ”PRR – Power Reduction Register” on page 54, provides a method
to stop the clock to individual peripherals to reduce power consumption. The current state of the peripheral is
frozen and the I/O registers can not be read or written. Resources used by the peripheral when stopping the
clock will remain occupied, hence the peripheral should in most cases be disabled before stopping the clock.
Waking up a module, which is done by clearing the bit in PRR, puts the module in the same state as before
shutdown.
Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power
consumption. In all other sleep modes, the clock is already stopped.
10.10 Minimizing Power Consumption
There are several possibilities to consider when trying to minimize the power consumption in an AVR controlled
system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected
so that as few as possible of the device’s functions are operating. All functions not needed should be disabled.
In particular, the following modules may need special consideration when trying to achieve the lowest possible
power consumption.
10.10.1 Analog to Digital Converter
If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before
entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended
conversion. Refer to ”Analog-to-Digital Converter” on page 246 for details on ADC operation.
10.10.2 Analog Comparator
When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise
Reduction mode, the Analog Comparator should be disabled. In other sleep modes, the Analog Comparator is
automatically disabled. However, if the Analog Comparator is set up to use the Internal Voltage Reference as
input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference
will be enabled, independent of sleep mode. Refer to ”Analog Comparator” on page 243 for details on how to
configure the Analog Comparator.
10.10.3 Brown-out Detector
If the Brown-out Detector is not needed by the application, this module should be turned off. If the Brown-out
Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always consume
power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to
”Brown-out Detection” on page 58 for details on how to configure the Brown-out Detector.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 51
10.10.4 Internal Voltage Reference
The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the Analog
Comparator or the ADC. If these modules are disabled as described in the sections above, the internal voltage
reference will be disabled and it will not be consuming power. When turned on again, the user must allow the
reference to start up before the output is used. If the reference is kept on in sleep mode, the output can be used
immediately. Refer to ”Internal Voltage Reference” on page 59 for details on the start-up time.
10.10.5 Watchdog Timer
If the Watchdog Timer is not needed in the application, the module should be turned off. If the Watchdog Timer
is enabled, it will be enabled in all sleep modes and hence always consume power. In the deeper sleep modes,
this will contribute significantly to the total current consumption. Refer to ”Watchdog Timer” on page 60 for
details on how to configure the Watchdog Timer.
10.10.6 Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power. The most important is
then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clk
clock (clk
) are stopped, the input buffers of the device will be disabled. This ensures that no power is
ADC
consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up
conditions, and it will then be enabled. Refer to the section ”Digital Input Enable and Sleep Modes” on page 88
for details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or have an
analog signal level close to V
For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to
V
/2 on an input pin can cause significant current even in active mode. Digital input buffers can be disabled by
CC
writing to the Digital Input Disable Registers (DIDR1 and DIDR0). Refer to ”DIDR1 – Digital Input Disable
Register 1” on page 245 and ”DIDR0 – Digital Input Disable Register 0” on page 260 for details.
ATmega48A/PA/88A/PA/168A/PA/328/P
/2, the input buffer will use excessive power.
CC
) and the ADC
I/O
10.10.7 On-chip Debug System
If the On-chip debug system is enabled by the DWEN Fuse and the chip enters sleep mode, the main clock
source is enabled and hence always consumes power. In the deeper sleep modes, this will contribute
significantly to the total current consumption.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 52
ATmega48A/PA/88A/PA/168A/PA/328/P
10.11 Register Description
10.11.1 SMCR – Sleep Mode Control Register
The Sleep Mode Control Register contains control bits for power management.
Bit 76543210
0x33 (0x53)
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
• Bits [7:4]: Reserved
These bits are unused in the ATmega48A/PA/88A/PA/168A/PA/328/P, and will always be read as zero.
• Bits 3:1 – SM[2:0]: Sleep Mode Select Bits 2, 1, and 0
These bits select between the five available sleep modes as shown in Table 10-2.
Table 10-2. Sleep Mode Select
SM2 SM1 SM0 Sleep Mode
0 0 0 Idle
0 0 1 ADC Noise Reduction
––––SM2SM1SM0SESMCR
0 1 0 Power-down
0 1 1 Power-save
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Standby
1 1 1 External Standby
Note: 1. Standby mode is only recommended for use with external crystals or resonators.
• Bit 0 – SE: Sleep Enable
(1)
(1)
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is
executed. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose, it is recommended
to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it
immediately after waking up.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 53
10.11.2 MCUCR – MCU Control Register
ATmega48A/PA/88A/PA/168A/PA/328/P
Bit 7 6 5 4 3 2 1 0
0x35 (0x55) –
Read/Write R R/W R/W R/W R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0
• Bit 6 – BODS: BOD Sleep
BODS
(1)
(1)
The BODS bit must be written to logic one in order to turn off BOD during sleep, see Table 10-1 on page 48.
Writing to the BODS bit is controlled by a timed sequence and an enable bit, BODSE in MCUCR. To disable
BOD in relevant sleep modes, both BODS and BODSE must first be set to one. Then, to set the BODS bit,
BODS must be set to one and BODSE must be set to zero within four clock cycles.
The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed while BODS is
active in order to turn off the BOD for the actual sleep mode. The BODS bit is automatically cleared after three
clock cycles.
• Bit 5 – BODSE: BOD Sleep Enable
BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disable is controlled by
a timed sequence.
Note: 1. BODS and BODSE only available for picoPower devices ATmega48PA/88PA/168PA/328P
10.11.3 PRR – Power Reduction Register
Bit 7 6 5 4 3 2 1 0
(0x64)
Read/Write R/W R/W R/W R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
PRTWI PRTIM2 PRTIM0 – PRTIM1 PRSPI PRUSART0 PRADC PRR
BODSE
(1)
(1)
PUD – – IVSEL IVCE MCUCR
• Bit 7 – PRTWI: Power Reduction TWI
Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When waking up the TWI
again, the TWI should be re initialized to ensure proper operation.
• Bit 6 – PRTIM2: Power Reduction Timer/Counter2
Writing a logic one to this bit shuts down the Timer/Counter2 module in synchronous mode (AS2 is 0). When the
Timer/Counter2 is enabled, operation will continue like before the shutdown.
• Bit 5 – PRTIM0: Power Reduction Timer/Counter0
Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled,
operation will continue like before the shutdown.
• Bit 4 – Reserved
This bit is reserved in ATmega48A/PA/88A/PA/168A/PA/328/P and will always read as zero.
• Bit 3 – PRTIM1: Power Reduction Timer/Counter1
Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled,
operation will continue like before the shutdown.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 54
ATmega48A/PA/88A/PA/168A/PA/328/P
• Bit 2 – PRSPI: Power Reduction Serial Peripheral Interface
If using debugWIRE On-chip Debug System, this bit should not be written to one. Writing a logic one to this bit
shuts down the Serial Peripheral Interface by stopping the clock to the module. When waking up the SPI again,
the SPI should be re initialized to ensure proper operation.
• Bit 1 – PRUSART0: Power Reduction USART0
Writing a logic one to this bit shuts down the USART by stopping the clock to the module. When waking up the
USART again, the USART should be re initialized to ensure proper operation.
• Bit 0 – PRADC: Power Reduction ADC
Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog
comparator cannot use the ADC input MUX when the ADC is shut down.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 55
11. System Control and Reset
11.1 Resetting the AVR
During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset
Vector. For ATmega168A/168PA/328/328P the instruction placed at the Reset Vector must be a JMP –
Absolute Jump – instruction to the reset handling routine. For the ATmega 48A/48PA and ATmega88A/88PA,
the instruction placed at the Reset Vector must be an RJMP – Relative Jump – instruction to the reset handling
routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular
program code can be placed at these locations. This is also the case if the Reset Vector is in the Application
section while the Interrupt Vectors are in the Boot section or vice versa
(ATmega88A/88PA/168A/168PA/328/328P only). The circuit diagram in Figure 11-1 on page 57 shows the
reset logic. Table 29-11 on page 314 defines the electrical parameters of the reset circuitry.
The I/O ports of the AVR are immediately reset to their initial state when a reset source goes active. This does
not require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows
the power to reach a stable level before normal operation starts. The time-out period of the delay counter is
defined by the user through the SUT and CKSEL Fuses. The different selections for the delay period are
presented in ”Clock Sources” on page 37.
ATmega48A/PA/88A/PA/168A/PA/328/P
11.2 Reset Sources
The ATmega48A/PA/88A/PA/168A/PA/328/P has four sources of reset:
Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold
(V
).
POT
External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the
minimum pulse length.
Watchdog System Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog
System Reset mode is enabled.
Brown-out Reset. The MCU is reset when the supply voltage V
(V
) and the Brown-out Detector is enabled.
BOT
is below the Brown-out Reset threshold
CC
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 56
Figure 11-1. Reset Logic
MCU Status
Register (MCUSR)
Brown-out
Reset Circuit
BODLEVEL [2..0]
Delay Counters
CKSEL[3:0]
CK
TIMEOUT
WDRF
BORF
EXTRF
PORF
DATA BU S
Clock
Generator
SPIKE
FILTER
Pull-up Resistor
Watchdog
Oscillator
SUT[1:0]
Power-on Reset
Circuit
RSTDISBL
V
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST
CC
ATmega48A/PA/88A/PA/168A/PA/328/P
11.3 Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in
”System and Reset Characteristics” on page 314. The POR is activated whenever V
is below the detection
CC
level. The POR circuit can be used to trigger the start-up Reset, as well as to detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset
threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after V
rise. The RESET signal is activated again, without any delay, when V
Figure 11-2. MCU Start-up, RESET Tied to V
CC
decreases below the detection level.
CC
CC
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 57
Figure 11-3. MCU Start-up, RESET Extended Externally
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST
V
CC
CC
11.4 External Reset
An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse
width (see ”System and Reset Characteristics” on page 314) will generate a reset, even if the clock is not
running. Shorter pulses are not ensured to generate a reset. When the applied signal reaches the Reset
Threshold Voltage – V
t
has expired. The External Reset can be disabled by the RSTDISBL fuse, see Table 28-7 on page 291.
TOUT –
ATmega48A/PA/88A/PA/168A/PA/328/P
– on its positive edge, the delay counter starts the MCU after the Time-out period –
RST
Figure 11-4. External Reset During Operation
11.5 Brown-out Detection
ATmega48A/PA/88A/PA/168A/PA/328/P has an On-chip Brown-out Detection (BOD) circuit for monitoring the
V
level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected
CC
by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The
hysteresis on the detection level should be interpreted as V
V
/2.When the BOD is enabled, and VCC decreases to a value below the trigger level (V
HYST
page 59), the Brown-out Reset is immediately activated. When V
Figure 11-5 on page 59), the delay counter starts the MCU after the Time-out period t
The BOD circuit will only detect a drop in V
given in ”System and Reset Characteristics” on page 314.
= V
BOT+
if the voltage stays below the trigger level for longer than t
CC
+ V
BOT
increases above the trigger level (V
CC
HYST
/2 and V
TOUT
= V
BOT-
BOT
in Figure 11-5 on
BOT-
has expired.
-
BOT+
BOD
in
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 58
Figure 11-5. Brown-out Reset During Operation
V
CC
RESET
TIME-OUT
INTERNAL
RESET
V
BOT-
V
BOT+
t
TOUT
CK
CC
11.6 Watchdog System Reset
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge
of this pulse, the delay timer starts counting the Time-out period t
of the Watchdog Timer.
Figure 11-6. Watchdog System Reset During Operation
ATmega48A/PA/88A/PA/168A/PA/328/P
. Refer to page 60 for details on operation
TOUT
11.7 Internal Voltage Reference
ATmega48A/PA/88A/PA/168A/PA/328/P features an internal bandgap reference. This reference is used for
Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC.
11.7.1 Voltage Reference Enable Signals and Start-up Time
The voltage reference has a start-up time that may influence the way it should be used. The start-up time is
given in ”System and Reset Characteristics” on page 314. To save power, the reference is not always turned on.
The reference is on during the following situations:
1. When the BOD is enabled (by programming the BODLEVEL [2:0] Fuses).
2. When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in ACSR).
3. When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user must always allow
the reference to start up before the output from the Analog Comparator or ADC is used. To reduce power
consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference
is turned off before entering Power-down mode.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 59
11.8 Watchdog Timer
128kHz
OSCILLATOR
OSC/2K
OSC/4K
OSC/8K
OSC/16K
OSC/32K
OSC/64K
OSC/128K
OSC/256K
OSC/512K
OSC/1024K
WDP0
WDP1
WDP2
WDP3
WATCHDOG
RESET
WDE
WDIF
WDIE
MCU RESET
INTERRUPT
11.8.1 Features
Clocked from separate On-chip Oscillator
•
• 3 Operating modes
– Interrupt
– System Reset
– Interrupt and System Reset
• Selectable Time-out period from 16ms to 8s
• Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode
11.8.2 Overview
ATmega48A/PA/88A/PA/168A/PA/328/P has an Enhanced Watchdog Timer (WDT). The WDT is a timer
counting cycles of a separate on-chip 128kHz oscillator. The WDT gives an interrupt or a system reset when the
counter reaches a given time-out value. In normal operation mode, it is required that the system uses the WDR
- Watchdog Timer Reset - instruction to restart the counter before the time-out value is reached. If the system
doesn't restart the counter, an interrupt or system reset will be issued.
Figure 11-7. Watchdog Timer
ATmega48A/PA/88A/PA/168A/PA/328/P
In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used to wake the
device from sleep-modes, and also as a general system timer. One example is to limit the maximum time
allowed for certain operations, giving an interrupt when the operation has run longer than expected. In System
Reset mode, the WDT gives a reset when the timer expires. This is typically used to prevent system hang-up in
case of runaway code. The third mode, Interrupt and System Reset mode, combines the other two modes by
first giving an interrupt and then switch to System Reset mode. This mode will for instance allow a safe
shutdown by saving critical parameters before a system reset.
The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to System Reset mode.
With the fuse programmed the System Reset mode bit (WDE) and Interrupt mode bit (WDIE) are locked to 1
and 0 respectively. To further ensure program security, alterations to the Watchdog set-up must follow timed
sequences. The sequence for clearing WDE and changing time-out configuration is as follows:
1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE. A logic
one must be written to WDE regardless of the previous value of the WDE bit.
2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as desired, but with
the WDCE bit cleared. This must be done in one operation.
The following code example shows one assembly and one C function for turning off the Watchdog Timer. The
example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will
occur during the execution of these functions.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 60
ATmega48A/PA/88A/PA/168A/PA/328/P
Assembly Code Example
WDT_off:
; Turn off global interrupt
cli
; Reset Watchdog Timer
wdr
; Clear WDRF in MCUSR
in r16, MCUSR
andi r16, ~(1<<WDRF)
out MCUSR, r16
; Write logical one to WDCE and WDE
; Keep old prescaler setting to prevent unintentional
time-out
lds r16, WDTCSR
ori r16, (1<<WDCE) | (1<<WDE)
sts WDTCSR, r16
; Turn off WDT
ldi r16, (0<<WDE)
sts WDTCSR, r16
; Turn on global interrupt
sei
ret
C Code Example
(1)
(1)
void WDT_off(void)
{
__disable_interrupt();
__watchdog_reset();
/* Clear WDRF in MCUSR */
MCUSR &= ~(1<<WDRF);
/* Write logical one to WDCE and WDE */
/* Keep old prescaler setting to prevent unintentional
time-out */
WDTCSR |= (1<<WDCE) | (1<<WDE);
/* Turn off WDT */
WDTCSR = 0x00;
__enable_interrupt();
}
Note: 1. See ”About Code Examples” on page 17.
Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the
device will be reset and the Watchdog Timer will stay enabled. If the code is not set up to handle the Watchdog,
this might lead to an eternal loop of time-out resets. To avoid this situation, the application software should
always clear the Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialization routine,
even if the Watchdog is not in use.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 61
ATmega48A/PA/88A/PA/168A/PA/328/P
The following code example shows one assembly and one C function for changing the time-out value of the
Watchdog Timer.
Assembly Code Example
WDT_Prescaler_Change:
; Turn off global interrupt
cli
; Reset Watchdog Timer
wdr
; Start timed sequence
lds r16, WDTCSR
ori r16, (1<<WDCE) | (1<<WDE)
sts WDTCSR, r16
; -- Got four cycles to set the new values from here ; Set new prescaler(time-out) value = 64K cycles (~0.5 s)
ldi r16, (1<<WDE) | (1<<WDP2) | (1<<WDP0)
sts WDTCSR, r16
; -- Finished setting new values, used 2 cycles ; Turn on global interrupt
sei
ret
C Code Example
(1)
(1)
void WDT_Prescaler_Change(void)
{
__disable_interrupt();
__watchdog_reset();
/* Start timed sequence */
WDTCSR |= (1<<WDCE) | (1<<WDE);
/* Set new prescaler(time-out) value = 64K cycles (~0.5
s) */
WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0);
__enable_interrupt();
}
Note: 1. See ”About Code Examples” on page 17.
Note: The Watchdog Timer should be reset before any change of the WDP bits, since a change in the WDP bits
can result in a time-out when switching to a shorter time-out period.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 62
11.9 Register Description
11.9.1 MCUSR – MCU Status Register
The MCU Status Register provides information on which reset source caused an MCU reset.
Bit 76543210
0x34 (0x54)
Read/Write R R R R R/W R/W R/W R/W
Initial Value0000 See Bit Description
• Bit 7:4: Reserved
These bits are unused bits in the ATmega48A/PA/88A/PA/168A/PA/328/P, and will always read as zero.
• Bit 3 – WDRF: Watchdog System Reset Flag
This bit is set if a Watchdog System Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic
zero to the flag.
• Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the
flag.
––––WDRFBORFEXTRFPORFMCUSR
ATmega48A/PA/88A/PA/168A/PA/328/P
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the
flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.
To make use of the Reset Flags to identify a reset condition, the user should read and then Reset the MCUSR
as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset
can be found by examining the Reset Flags.
11.9.2 WDTCSR – Watchdog Timer Control Register
Bit 76543210
(0x60)
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value0000X000
WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 WDTCSR
• Bit 7 – WDIF: Watchdog Interrupt Flag
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt.
WDIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is
cleared by writing a logic one to the flag. When the I-bit in SREG and WDIE are set, the Watchdog Time-out
Interrupt is executed.
• Bit 6 – WDIE: Watchdog Interrupt Enable
When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is enabled. If
WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt Mode, and the
corresponding interrupt is executed if time-out in the Watchdog Timer occurs. If WDE is set, the Watchdog
Timer is in Interrupt and System Reset Mode. The first time-out in the Watchdog Timer will set WDIF. Executing
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 63
ATmega48A/PA/88A/PA/168A/PA/328/P
the corresponding interrupt vector will clear WDIE and WDIF automatically by hardware (the Watchdog goes to
System Reset Mode). This is useful for keeping the Watchdog Timer security while using the interrupt. To stay
in Interrupt and System Reset Mode, WDIE must be set after each interrupt. This should however not be done
within the interrupt service routine itself, as this might compromise the safety-function of the Watchdog System
Reset mode. If the interrupt is not executed before the next time-out, a System Reset will be applied.
Table 11-1. Watchdog Timer Configuration
WDTON
(1)
1 0 0 Stopped None
1 0 1 Interrupt Mode Interrupt
1 1 0 System Reset Mode Reset
WDE WDIE Mode Action on Time-out
1 1 1
0 x x System Reset Mode Reset
Note: 1. WDTON Fuse set to “0” means programmed and “1” means unprogrammed.
Interrupt and System Reset
Mode
Interrupt, then go to System
Reset Mode
• Bit 4 – WDCE: Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit, and/or change
the prescaler bits, WDCE must be set.
Once written to one, hardware will clear WDCE after four clock cycles.
• Bit 3 – WDE: Watchdog System Reset Enable
WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear
WDE, WDRF must be cleared first. This feature ensures multiple resets during conditions causing failure, and a
safe start-up after the failure.
• Bit 5, 2:0 - WDP[3:0]: Watchdog Timer Prescaler 3, 2, 1 and 0
The WDP[3:0] bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. The
different prescaling values and their corresponding time-out periods are shown in Table 11-2 on page 64.
Table 11-2. Watchdog Timer Prescale Select
Number of WDT Oscillator
WDP3 WDP2 WDP1 WDP0
0 0 0 0 2K (2048) cycles 16ms
0 0 0 1 4K (4096) cycles 32ms
Cycles
Typical Time-out at
= 5.0V
V
CC
0 0 1 0 8K (8192) cycles 64ms
0 0 1 1 16K (16384) cycles 0.125 s
0 1 0 0 32K (32768) cycles 0.25 s
0 1 0 1 64K (65536) cycles 0.5 s
0 1 1 0 128K (131072) cycles 1.0 s
0 1 1 1 256K (262144) cycles 2.0 s
1 0 0 0 512K (524288) cycles 4.0 s
1 0 0 1 1024K (1048576) cycles 8.0 s
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 64
ATmega48A/PA/88A/PA/168A/PA/328/P
Table 11-2. Watchdog Timer Prescale Select (Continued)
Number of WDT Oscillator
WDP3 WDP2 WDP1 WDP0
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Cycles
Typical Time-out at
VCC = 5.0V
Reserved
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 65
ATmega48A/PA/88A/PA/168A/PA/328/P
12. Interrupts
This section describes the specifics of the interrupt handling as performed in
ATmega48A/PA/88A/PA/168A/PA/328/P. For a general explanation of the AVR interrupt handling, refer to
”Reset and Interrupt Handling” on page 23.
The interrupt vectors in ATmega 48A/48PA, ATmega88A/88PA, ATmega168A/168PA and ATmega328/328P
are generally the same, with the following differences:
Each Interrupt Vector occupies two instruction words in ATmega168A/168PA and ATmega328/328P, and
one instruction word in ATmega 48A/48PA and ATmega88A/88PA.
ATmega 48A/48PA does not have a separate Boot Loader Section. In ATmega88A/88PA,
ATmega168A/168PA and ATmega328/328P, the Reset Vector is affected by the BOOTRST fuse, and the
Interrupt Vector start address is affected by the IVSEL bit in MCUCR.
12.1 Interrupt Vectors in ATmega48A and ATmega48PA
Table 12-1. Reset and Interrupt Vectors in ATmega48A and ATmega48PA
Vecto r No. Program Address Source Interrupt Definition
1 0x000 RESET
2 0x001 INT0 External Interrupt Request 0
3 0x002 INT1 External Interrupt Request 1
External Pin, Power-on Reset, Brown-out Reset and Watchdog System Reset
4 0x003 PCINT0 Pin Change Interrupt Request 0
5 0x004 PCINT1 Pin Change Interrupt Request 1
6 0x005 PCINT2 Pin Change Interrupt Request 2
7 0x006 WDT Watchdog Time-out Interrupt
8 0x007 TIMER2_COMPA Timer/Counter2 Compare Match A
9 0x008 TIMER2_COMPB Timer/Counter2 Compare Match B
10 0x009 TIMER2_OVF Timer/Counter2 Overflow
11 0x00A TIMER1_CAPT Timer/Counter1 Capture Event
12 0x00B TIMER1_COMPA Timer/Counter1 Compare Match A
13 0x00C TIMER1_COMPB Timer/Counter1 Compare Match B
14 0x00D TIMER1_OVF Timer/Counter1 Overflow
15 0x00E TIMER0_COMPA Timer/Counter0 Compare Match A
16 0x00F TIMER0_COMPB Timer/Counter0 Compare Match B
17 0x010 TIMER0_OVF Timer/Counter0 Overflow
18 0x011 SPI_STC SPI Serial Transfer Complete
19 0x012 USART_RX USART Rx Complete
20 0x013 USART_UDRE USART, Data Register Empty
21 0x014 USART_TX USART, Tx Complete
22 0x015 ADC ADC Conversion Complete
23 0x016 EE_READY EEPROM Ready
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 66
ATmega48A/PA/88A/PA/168A/PA/328/P
Table 12-1. Reset and Interrupt Vectors in ATmega48A and ATmega48PA (Continued)
Vecto r No. Program Address Source Interrupt Definition
24 0x017 ANALOG_COMP Analog Comparator
25 0x018 TWI 2-wire Serial Interface
26 0x019 SPM_Ready Store Program Memory Ready
The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega 48A/48PA
is:
Address Labels Code Comments
0x000 rjmp RESET ; Reset Handler
0x001 rjmp EXT_INT0 ; IRQ0 Handler
0x002 rjmp EXT_INT1 ; IRQ1 Handler
0x003 rjmp PCINT0 ; PCINT0 Handler
0x004 rjmp PCINT1 ; PCINT1 Handler
0x005 rjmp PCINT2 ; PCINT2 Handler
0x006 rjmp WDT ; Watchdog Timer Handler
0x007 rjmp TIM2_COMPA ; Timer2 Compare A Handler
0x008 rjmp TIM2_COMPB ; Timer2 Compare B Handler
0x009 rjmp TIM2_OVF ; Timer2 Overflow Handler
0x00A rjmp TIM1_CAPT ; Timer1 Capture Handler
0x00B rjmp TIM1_COMPA ; Timer1 Compare A Handler
0x00C rjmp TIM1_COMPB ; Timer1 Compare B Handler
0x00D rjmp TIM1_OVF ; Timer1 Overflow Handler
0x00E rjmp TIM0_COMPA ; Timer0 Compare A Handler
0x00F rjmp TIM0_COMPB ; Timer0 Compare B Handler
0x010 rjmp TIM0_OVF ; Timer0 Overflow Handler
0x011 rjmp SPI_STC ; SPI Transfer Complete Handler
0x012 rjmp USART_RXC ; USART, RX Complete Handler
0x013 rjmp USART_UDRE ; USART, UDR Empty Handler
0x014 rjmp USART_TXC ; USART, TX Complete Handler
0x015 rjmp ADC ; ADC Conversion Complete Handler
0x016 rjmp EE_RDY ; EEPROM Ready Handler
0x017 rjmp ANA_COMP ; Analog Comparator Handler
0x018 rjmp TWI ; 2-wire Serial Interface Handler
0x019 rjmp ; SPM_RDYStore Program Memory Ready
Handler
;
0x01A RESET: ldi r16, high(RAMEND); Main program start
0x01B out SPH,r16 ; Set Stack Pointer to top of RAM
0x01C ldi r16, low(RAMEND)
0x01D out SPL,r16
0x01E sei ; Enable interrupts
0x01F <instr> xxx
... ... ... ...
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 67
ATmega48A/PA/88A/PA/168A/PA/328/P
12.2 Interrupt Vectors in ATmega88A and ATmega88PA
Table 12-2. Reset and Interrupt Vectors in ATmega88A and ATmega88PA
Program
Vector No.
1 0x000
2 0x001 INT0 External Interrupt Request 0
3 0x002 INT1 External Interrupt Request 1
4 0x003 PCINT0 Pin Change Interrupt Request 0
5 0x004 PCINT1 Pin Change Interrupt Request 1
6 0x005 PCINT2 Pin Change Interrupt Request 2
7 0x006 WDT Watchdog Time-out Interrupt
8 0x007 TIMER2_COMPA Timer/Counter2 Compare Match A
9 0x008 TIMER2_COMPB Timer/Counter2 Compare Match B
10 0x009 TIMER2_OVF Timer/Counter2 Overflow
11 0x00A TIMER1_CAPT Timer/Counter1 Capture Event
12 0x00B TIMER1_COMPA Timer/Counter1 Compare Match A
13 0x00C TIMER1_COMPB Timer/Counter1 Compare Match B
Address
(2)
(1)
Source Interrupt Definition
RESET
External Pin, Power-on Reset, Brown-out Reset and Watchdog System Reset
14 0x00D TIMER1_OVF Timer/Counter1 Overflow
15 0x00E TIMER0_COMPA Timer/Counter0 Compare Match A
16 0x00F TIMER0_COMPB Timer/Counter0 Compare Match B
17 0x010 TIMER0_OVF Timer/Counter0 Overflow
18 0x011 SPI_STC SPI Serial Transfer Complete
19 0x012 USART_RX USART Rx Complete
20 0x013 USART_UDRE USART, Data Register Empty
21 0x014 USART_TX USART, Tx Complete
22 0x015 ADC ADC Conversion Complete
23 0x016 EE_READY EEPROM Ready
24 0x017 ANALOG_COMP Analog Comparator
25 0x018 TWI 2-wire Serial Interface
26 0x019 SPM_Ready Store Program Memory Ready
Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see ”Boot Loader Support – Read-While-Write Self-
Programming” on page 272.
2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of each Interrupt Vector will then
be the address in this table added to the start address of the Boot Flash Section.
Table 12-3 on page 69 shows reset and Interrupt Vectors placement for the various combinations of BOOTRST
and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and
regular program code can be placed at these locations. This is also the case if the Reset Vector is in the
Application section while the Interrupt Vectors are in the Boot section or vice versa.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 68
ATmega48A/PA/88A/PA/168A/PA/328/P
Table 12-3. Reset and Interrupt Vectors Placement in ATmega88A and ATmega88PA
BOOTRST IVSEL Reset Address Interrupt Vectors Start Address
1 0 0x000 0x001
1 1 0x000 Boot Reset Address + 0x001
0 0 Boot Reset Address 0x001
0 1 Boot Reset Address Boot Reset Address + 0x001
Note: 1. The Boot Reset Address is shown in Table 27-7 on page 284. For the BOOTRST Fuse “1” means
unprogrammed while “0” means programmed.
(1)
The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega88A/88PA
is:
Address Labels Code Comments
0x000 rjmp RESET ; Reset Handler
0x001 rjmp EXT_INT0 ; IRQ0 Handler
0x002 rjmp EXT_INT1 ; IRQ1 Handler
0x003 rjmp PCINT0 ; PCINT0 Handler
0x004 rjmp PCINT1 ; PCINT1 Handler
0x005 rjmp PCINT2 ; PCINT2 Handler
0x006 rjmp WDT ; Watchdog Timer Handler
0x007 rjmp TIM2_COMPA ; Timer2 Compare A Handler
0X008 rjmp TIM2_COMPB ; Timer2 Compare B Handler
0x009 rjmp TIM2_OVF ; Timer2 Overflow Handler
0x00A rjmp TIM1_CAPT ; Timer1 Capture Handler
0x00B rjmp TIM1_COMPA ; Timer1 Compare A Handler
0x00C rjmp TIM1_COMPB ; Timer1 Compare B Handler
0x00D rjmp TIM1_OVF ; Timer1 Overflow Handler
0x00E rjmp TIM0_COMPA ; Timer0 Compare A Handler
0x00F rjmp TIM0_COMPB ; Timer0 Compare B Handler
0x010 rjmp TIM0_OVF ; Timer0 Overflow Handler
0x011 rjmp SPI_STC ; SPI Transfer Complete Handler
0x012 rjmp USART_RXC ; USART, RX Complete Handler
0x013 rjmp USART_UDRE ; USART, UDR Empty Handler
0x014 rjmp USART_TXC ; USART, TX Complete Handler
0x015 rjmp ADC ; ADC Conversion Complete Handler
0x016 rjmp EE_RDY ; EEPROM Ready Handler
0x017 rjmp ANA_COMP ; Analog Comparator Handler
0x018 rjmp TWI ; 2-wire Serial Interface Handler
0x019 rjmp SPM_RDY ; Store Program Memory Ready Handler
;
0x01A RESET: ldi r16, high(RAMEND); Main program start
0x01B out SPH,r16 ; Set Stack Pointer to top of RAM
0x01C ldi r16, low(RAMEND)
0x01D out SPL,r16
0x01E sei ; Enable interrupts
0x01F <instr> xxx
When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2Kbytes and the IVSEL bit in the
MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the
Reset and Interrupt Vector Addresses in ATmega88A/88PA is:
Address Labels Code Comments
0x000 RESET: ldi r16,high(RAMEND); Main program start
0x001 out SPH,r16 ; Set Stack Pointer to top of RAM
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 69
ATmega48A/PA/88A/PA/168A/PA/328/P
0x002 ldi r16,low(RAMEND)
0x003 out SPL,r16
0x004 sei ; Enable interrupts
0x005 <instr> xxx
;
.org 0xC01
0xC01 rjmp EXT_INT0 ; IRQ0 Handler
0xC02 rjmp EXT_INT1 ; IRQ1 Handler
... ... ... ;
0xC19 rjmp SPM_RDY ; Store Program Memory Ready Handler
When the BOOTRST Fuse is programmed and the Boot section size set to 2Kbytes, the most typical and
general program setup for the Reset and Interrupt Vector Addresses in ATmega88A/88PA is:
Address LabelsCodeComments
.org 0x001
0x001 rjmp EXT_INT0 ; IRQ0 Handler
0x002 rjmp EXT_INT1 ; IRQ1 Handler
... ... ... ;
0x019 rjmp SPM_RDY ; Store Program Memory Ready Handler
;
.org 0xC00
0xC00 RESET: ldi r16,high(RAMEND); Main program start
0xC01 out SPH,r16 ; Set Stack Pointer to top of RAM
0xC02 ldi r16,low(RAMEND)
0xC03 out SPL,r16
0xC04 sei ; Enable interrupts
0xC05 <instr> xxx
When the BOOTRST Fuse is programmed, the Boot section size set to 2Kbytes and the IVSEL bit in the
MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the
Reset and Interrupt Vector Addresses in ATmega88A/88PA is:
Address Labels Code Comments
;
.org 0xC00
0xC00 rjmp RESET ; Reset handler
0xC01 rjmp EXT_INT0 ; IRQ0 Handler
0xC02 rjmp EXT_INT1 ; IRQ1 Handler
... ... ... ;
0xC19 rjmp SPM_RDY ; Store Program Memory Ready Handler
;
0xC1A RESET: ldi r16,high(RAMEND); Main program start
0xC1B out SPH,r16 ; Set Stack Pointer to top of RAM
0xC1C ldi r16,low(RAMEND)
0xC1D out SPL,r16
0xC1E sei ; Enable interrupts
0xC1F <instr> xxx
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 70
ATmega48A/PA/88A/PA/168A/PA/328/P
12.3 Interrupt Vectors in ATmega168A and ATmega168PA
Table 12-4. Reset and Interrupt Vectors in ATmega168A and ATmega168PA
Program
Vecto rNo.
Address
1 0x0000
2 0x0002 INT0 External Interrupt Request 0
3 0x0004 INT1 External Interrupt Request 1
4 0x0006 PCINT0 Pin Change Interrupt Request 0
5 0x0008 PCINT1 Pin Change Interrupt Request 1
6 0x000A PCINT2 Pin Change Interrupt Request 2
7 0x000C WDT Watchdog Time-out Interrupt
8 0x000E TIMER2_COMPA Timer/Counter2 Compare Match A
9 0x0010 TIMER2_COMPB Timer/Counter2 Compare Match B
10 0x0012 TIMER2_OVF Timer/Counter2 Overflow
11 0x0014 TIMER1_CAPT Timer/Counter1 Capture Event
12 0x0016 TIMER1_COMPA Timer/Counter1 Compare Match A
13 0x0018 TIMER1_COMPB Timer/Counter1 Compare Match B
(2)
(1)
Source Interrupt Definition
RESET
External Pin, Power-on Reset, Brown-out Reset and Watchdog System Reset
14 0x001A TIMER1_OVF Timer/Counter1 Overflow
15 0x001C TIMER0_COMPA Timer/Counter0 Compare Match A
16 0x001E TIMER0_COMPB Timer/Counter0 Compare Match B
17 0x0020 TIMER0_OVF Timer/Counter0 Overflow
18 0x0022 SPI_STC SPI Serial Transfer Complete
19 0x0024 USART_RX USART Rx Complete
20 0x0026 USART_UDRE USART, Data Register Empty
21 0x0028 USART_TX USART, Tx Complete
22 0x002A ADC ADC Conversion Complete
23 0x002C EE_READY EEPROM Ready
24 0x002E ANALOG_COMP Analog Comparator
25 0x0030 TWI 2-wire Serial Interface
26 0x0032 SPM_Ready Store Program Memory Ready
Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see ”Boot Loader Support – Read-While-Write Self-
Programming” on page 272.
2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of each Interrupt Vector will then
be the address in this table added to the start address of the Boot Flash Section.
Table 12-5 on page 72 shows reset and Interrupt Vectors placement for the various combinations of BOOTRST
and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 71
ATmega48A/PA/88A/PA/168A/PA/328/P
regular program code can be placed at these locations. This is also the case if the Reset Vector is in the
Application section while the Interrupt Vectors are in the Boot section or vice versa.
Table 12-5. Reset and Interrupt Vectors Placement in ATmega168A and ATmega168PA
BOOTRST IVSEL Reset Address Interrupt Vectors Start Address
1 0 0x000 0x002
1 1 0x000 Boot Reset Address + 0x0002
0 0 Boot Reset Address 0x002
0 1 Boot Reset Address Boot Reset Address + 0x0002
Note: 1. The Boot Reset Address is shown in Table 27-7 on page 284. For the BOOTRST Fuse “1” means
unprogrammed while “0” means programmed.
(1)
The most typical and general program setup for the Reset and Interrupt Vector Addresses in
ATmega168A/168PA is:
Address Labels Code Comments
0x0000 jmp RESET ; Reset Handler
0x0002 jmp EXT_INT0 ; IRQ0 Handler
0x0004 jmp EXT_INT1 ; IRQ1 Handler
0x0006 jmp PCINT0 ; PCINT0 Handler
0x0008 jmp PCINT1 ; PCINT1 Handler
0x000A jmp PCINT2 ; PCINT2 Handler
0x000C jmp WDT ; Watchdog Timer Handler
0x000E jmp TIM2_COMPA ; Timer2 Compare A Handler
0x0010 jmp TIM2_COMPB ; Timer2 Compare B Handler
0x0012 jmp TIM2_OVF ; Timer2 Overflow Handler
0x0014 jmp TIM1_CAPT ; Timer1 Capture Handler
0x0016 jmp TIM1_COMPA ; Timer1 Compare A Handler
0x0018 jmp TIM1_COMPB ; Timer1 Compare B Handler
0x001A jmp TIM1_OVF ; Timer1 Overflow Handler
0x001C jmp TIM0_COMPA ; Timer0 Compare A Handler
0x001E jmp TIM0_COMPB ; Timer0 Compare B Handler
0x0020 jmp TIM0_OVF ; Timer0 Overflow Handler
0x0022 jmp SPI_STC ; SPI Transfer Complete Handler
0x0024 jmp USART_RXC ; USART, RX Complete Handler
0x0026 jmp USART_UDRE ; USART, UDR Empty Handler
0x0028 jmp USART_TXC ; USART, TX Complete Handler
0x002A jmp ADC ; ADC Conversion Complete Handler
0x002C jmp EE_RDY ; EEPROM Ready Handler
0x002E jmp ANA_COMP ; Analog Comparator Handler
0x0030 jmp TWI ; 2-wire Serial Interface Handler
0x0032 jmp SPM_RDY ; Store Program Memory Ready Handler
;
0x0034 RESET: ldi r16, high(RAMEND); Main program start
0x0035 out SPH,r16 ; Set Stack Pointer to top of RAM
0x0036 ldi r16, low(RAMEND)
0x0037 out SPL,r16
0x0038 sei ; Enable interrupts
0x0039 <instr> xxx
... ... ... ...
When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2Kbytes and the IVSEL bit in the
MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the
Reset and Interrupt Vector Addresses in ATmega168A/168PA is:
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 72
ATmega48A/PA/88A/PA/168A/PA/328/P
Address Labels Code Comments
0x0000 RESET: ldi r16,high(RAMEND); Main program start
0x0001 out SPH,r16 ; Set Stack Pointer to top of RAM
0x0002 ldi r16,low(RAMEND)
0x0003 out SPL,r16
0x0004 sei ; Enable interrupts
0x0005 <instr> xxx
;
.org 0x1C02
0x1C02 jmp EXT_INT0 ; IRQ0 Handler
0x1C04 jmp EXT_INT1 ; IRQ1 Handler
... ... ... ;
0x1C32 jmp SPM_RDY ; Store Program Memory Ready Handler
When the BOOTRST Fuse is programmed and the Boot section size set to 2Kbytes, the most typical and
general program setup for the Reset and Interrupt Vector Addresses in ATmega168A/168PA is:
Address Labels Code Comments
.org 0x0002
0x0002 jmp EXT_INT0 ; IRQ0 Handler
0x0004 jmp EXT_INT1 ; IRQ1 Handler
... ... ... ;
0x0032 jmp SPM_RDY ; Store Program Memory Ready Handler
;
.org 0x1C00
0x1C00 RESET: ldi r16,high(RAMEND); Main program start
0x1C01 out SPH,r16 ; Set Stack Pointer to top of RAM
0x1C02 ldi r16,low(RAMEND)
0x1C03 out SPL,r16
0x1C04 sei ; Enable interrupts
0x1C05 <instr> xxx
When the BOOTRST Fuse is programmed, the Boot section size set to 2Kbytes and the IVSEL bit in the
MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the
Reset and Interrupt Vector Addresses in ATmega168A/168PA is:
Address Labels Code Comments
;
.org 0x1C00
0x1C00 jmp RESET ; Reset handler
0x1C02 jmp EXT_INT0 ; IRQ0 Handler
0x1C04 jmp EXT_INT1 ; IRQ1 Handler
... ... ... ;
0x1C32 jmp SPM_RDY ; Store Program Memory Ready Handler
;
0x1C3 RESET: ldi r16,high(RAMEND); Main program start
0x1C35 out SPH,r16 ; Set Stack Pointer to top of RAM
0x1C36 ldi r16,low(RAMEND)
0x1C37 out SPL,r16
0x1C38 sei ; Enable interrupts
0x1C39 <instr> xxx
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 73
ATmega48A/PA/88A/PA/168A/PA/328/P
12.4 Interrupt Vectors in ATmega328 and ATmega328P
Table 12-6. Reset and Interrupt Vectors in ATmega328 and ATmega328P
Program
Vecto rNo.
Address
1 0x0000
2 0x0002 INT0 External Interrupt Request 0
3 0x0004 INT1 External Interrupt Request 1
4 0x0006 PCINT0 Pin Change Interrupt Request 0
5 0x0008 PCINT1 Pin Change Interrupt Request 1
6 0x000A PCINT2 Pin Change Interrupt Request 2
7 0x000C WDT Watchdog Time-out Interrupt
8 0x000E TIMER2_COMPA Timer/Counter2 Compare Match A
9 0x0010 TIMER2_COMPB Timer/Counter2 Compare Match B
10 0x0012 TIMER2_OVF Timer/Counter2 Overflow
11 0x0014 TIMER1_CAPT Timer/Counter1 Capture Event
12 0x0016 TIMER1_COMPA Timer/Counter1 Compare Match A
13 0x0018 TIMER1_COMPB Timer/Counter1 Compare Match B
(2)
(1)
Source Interrupt Definition
RESET
External Pin, Power-on Reset, Brown-out Reset and Watchdog System Reset
14 0x001A TIMER1_OVF Timer/Counter1 Overflow
15 0x001C TIMER0_COMPA Timer/Counter0 Compare Match A
16 0x001E TIMER0_COMPB Timer/Counter0 Compare Match B
17 0x0020 TIMER0_OVF Timer/Counter0 Overflow
18 0x0022 SPI_STC SPI Serial Transfer Complete
19 0x0024 USART_RX USART Rx Complete
20 0x0026 USART_UDRE USART, Data Register Empty
21 0x0028 USART_TX USART, Tx Complete
22 0x002A ADC ADC Conversion Complete
23 0x002C EE_READY EEPROM Ready
24 0x002E ANALOG_COMP Analog Comparator
25 0x0030 TWI 2-wire Serial Interface
26 0x0032 SPM_Ready Store Program Memory Ready
Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see ”Boot Loader Support – Read-While-Write Self-
Programming” on page 272.
2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of each Interrupt Vector will then
be the address in this table added to the start address of the Boot Flash Section.
Table 12-7 on page 75 shows reset and Interrupt Vectors placement for the various combinations of BOOTRST
and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 74
ATmega48A/PA/88A/PA/168A/PA/328/P
regular program code can be placed at these locations. This is also the case if the Reset Vector is in the
Application section while the Interrupt Vectors are in the Boot section or vice versa.
Table 12-7. Reset and Interrupt Vectors Placement in ATmega328 and ATmega328P
BOOTRST IVSEL Reset Address Interrupt Vectors Start Address
1 0 0x000 0x002
1 1 0x000 Boot Reset Address + 0x0002
0 0 Boot Reset Address 0x002
0 1 Boot Reset Address Boot Reset Address + 0x0002
Note: 1. The Boot Reset Address is shown in Table 27-7 on page 284. For the BOOTRST Fuse “1” means
unprogrammed while “0” means programmed.
(1)
The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega328/328P
is:
Address Labels Code Comments
0x0000 jmp RESET ; Reset Handler
0x0002 jmp EXT_INT0 ; IRQ0 Handler
0x0004 jmp EXT_INT1 ; IRQ1 Handler
0x0006 jmp PCINT0 ; PCINT0 Handler
0x0008 jmp PCINT1 ; PCINT1 Handler
0x000A jmp PCINT2 ; PCINT2 Handler
0x000C jmp WDT ; Watchdog Timer Handler
0x000E jmp TIM2_COMPA ; Timer2 Compare A Handler
0x0010 jmp TIM2_COMPB ; Timer2 Compare B Handler
0x0012 jmp TIM2_OVF ; Timer2 Overflow Handler
0x0014 jmp TIM1_CAPT ; Timer1 Capture Handler
0x0016 jmp TIM1_COMPA ; Timer1 Compare A Handler
0x0018 jmp TIM1_COMPB ; Timer1 Compare B Handler
0x001A jmp TIM1_OVF ; Timer1 Overflow Handler
0x001C jmp TIM0_COMPA ; Timer0 Compare A Handler
0x001E jmp TIM0_COMPB ; Timer0 Compare B Handler
0x0020 jmp TIM0_OVF ; Timer0 Overflow Handler
0x0022 jmp SPI_STC ; SPI Transfer Complete Handler
0x0024 jmp USART_RXC ; USART, RX Complete Handler
0x0026 jmp USART_UDRE ; USART, UDR Empty Handler
0x0028 jmp USART_TXC ; USART, TX Complete Handler
0x002A jmp ADC ; ADC Conversion Complete Handler
0x002C jmp EE_RDY ; EEPROM Ready Handler
0x002E jmp ANA_COMP ; Analog Comparator Handler
0x0030 jmp TWI ; 2-wire Serial Interface Handler
0x0032 jmp SPM_RDY ; Store Program Memory Ready Handler
;
0x0034 RESET: ldi r16, high(RAMEND); Main program start
0x0035 out SPH,r16 ; Set Stack Pointer to top of RAM
0x0036 ldi r16, low(RAMEND)
0x0037 out SPL,r16
0x0038 sei ; Enable interrupts
0x0039 <instr> xxx
... ... ... ...
When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2Kbytes and the IVSEL bit in the
MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the
Reset and Interrupt Vector Addresses in ATmega328/328P is:
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 75
ATmega48A/PA/88A/PA/168A/PA/328/P
Address Labels Code Comments
0x0000 RESET: ldi r16,high(RAMEND); Main program start
0x0001 out SPH,r16 ; Set Stack Pointer to top of RAM
0x0002 ldi r16,low(RAMEND)
0x0003 out SPL,r16
0x0004 sei ; Enable interrupts
0x0005 <instr> xxx
;
.org 0x3C02
0x3C02 jmp EXT_INT0 ; IRQ0 Handler
0x3C04 jmp EXT_INT1 ; IRQ1 Handler
... ... ... ;
0x3C32 jmp SPM_RDY ; Store Program Memory Ready Handler
When the BOOTRST Fuse is programmed and the Boot section size set to 2Kbytes, the most typical and
general program setup for the Reset and Interrupt Vector Addresses in ATmega328/328P is:
Address Labels Code Comments
.org 0x0002
0x0002 jmp EXT_INT0 ; IRQ0 Handler
0x0004 jmp EXT_INT1 ; IRQ1 Handler
... ... ... ;
0x0032 jmp SPM_RDY ; Store Program Memory Ready Handler
;
.org 0x3C00
0x3C00 RESET: ldi r16,high(RAMEND); Main program start
0x3C01 out SPH,r16 ; Set Stack Pointer to top of RAM
0x3C02 ldi r16,low(RAMEND)
0x3C03 out SPL,r16
0x3C04 sei ; Enable interrupts
0x3C05 <instr> xxx
When the BOOTRST Fuse is programmed, the Boot section size set to 2Kbytes and the IVSEL bit in the
MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the
Reset and Interrupt Vector Addresses in ATmega328/328P is:
Address Labels Code Comments
;
.org 0x3C00
0x3C00 jmp RESET ; Reset handler
0x3C02 jmp EXT_INT0 ; IRQ0 Handler
0x3C04 jmp EXT_INT1 ; IRQ1 Handler
... ... ... ;
0x3C32 jmp SPM_RDY ; Store Program Memory Ready Handler
;
0x3C34 RESET: ldi r16,high(RAMEND); Main program start
0x3C35 out SPH,r16 ; Set Stack Pointer to top of RAM
0x3C36 ldi r16,low(RAMEND)
0x3C37 out SPL,r16
0x3C38 sei ; Enable interrupts
0x3C39 <instr> xxx
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 76
ATmega48A/PA/88A/PA/168A/PA/328/P
12.5 Register Description
12.5.1 Moving Interrupts Between Application and Boot Space, ATmega88A/88PA, ATmega168A/168PA and ATmega328/328P
The MCU Control Register controls the placement of the Interrupt Vector table.
MCUCR – MCU Control Register
Bit 76 5 43210
0x35 (0x55)
Read/Write R R/W R/W R/W R R R/W R/W
Initial Value00 0 00000
Note: 1. BODS and BODSE only available for picoPower devices ATmega48PA/88PA/168PA/328P
– BODS
(1)
BODSE
(1)
PUD – – IVSEL IVCE MCUCR
• Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When
this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash.
The actual address of the start of the Boot Flash Section is determined by the BOOTSZ Fuses. Refer to the
section ”Boot Loader Support – Read-While-Write Self-Programming” on page 272 for details. To avoid
unintentional changes of Interrupt Vector tables, a special write procedure must be followed to change the
IVSEL bit:
1. Write the Interrupt Vector Change Enable (IVCE) bit to one.
2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle
IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not
written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic
disabling.
Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed, interrupts are
disabled while executing from the Application section. If Interrupt Vectors are placed in the Application section and
Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to
the section ”Boot Loader Support – Read-While-Write Self-Programming” on page 272 for details on Boot Lock bits.
• Bit 0 – IVCE: Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four
cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the
IVSEL description above. See Code Example below.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 77
Assembly Code Example
Move_interrupts:
; Enable change of Interrupt Vectors
ldi r16, (1<<IVCE)
out MCUCR, r16
; Move interrupts to Boot Flash section
ldi r16, (1<<IVSEL)
out MCUCR, r16
ret
C Code Example
void Move_interrupts(void)
{
/* Enable change of Interrupt Vectors */
MCUCR = (1<<IVCE);
/* Move interrupts to Boot Flash section */
MCUCR = (1<<IVSEL);
}
ATmega48A/PA/88A/PA/168A/PA/328/P
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 78
13. External Interrupts
clk
PCINT(0)
pin_lat
pin_sync
pcint_in_(0)
pcint_syn
pcint_setflag
PCIF
PCINT(0)
pin_sync
pcint_syn
pin_lat
D Q
LE
pcint_setflag
PCIF
clk
clk
PCINT(0) in PCMSK(x)
pcint_in_(0)
0
x
The External Interrupts are triggered by the INT0 and INT1 pins or any of the PCINT23...0 pins. Observe that, if
enabled, the interrupts will trigger even if the INT0 and INT1 or PCINT23...0 pins are configured as outputs. This
feature provides a way of generating a software interrupt. The pin change interrupt PCI2 will trigger if any
enabled PCINT[23:16] pin toggles. The pin change interrupt PCI1 will trigger if any enabled PCINT[14:8] pin
toggles. The pin change interrupt PCI0 will trigger if any enabled PCINT[7:0] pin toggles. The PCMSK2,
PCMSK1 and PCMSK0 Registers control which pins contribute to the pin change interrupts. Pin change
interrupts on PCINT23...0 are detected asynchronously. This implies that these interrupts can be used for
waking the part also from sleep modes other than Idle mode.
The External Interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in
the specification for the External Interrupt Control Registers – EICRA (INT2:0). When the external interrupt is
enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Low level
interrupts and the edge interrupt on INT2:0 are detected asynchronously. This implies that these interrupts can
be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep
modes except Idle mode.
Note: Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be held long
enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of
the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the
SUT and CKSEL Fuses as described in ”System Clock and Clock Options” on page 36.
ATmega48A/PA/88A/PA/168A/PA/328/P
13.1 Pin Change Interrupt Timing
An example of timing of a pin change interrupt is shown in Figure 13-1.
Figure 13-1. Timing of pin change interrupts
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 79
ATmega48A/PA/88A/PA/168A/PA/328/P
13.2 Register Description
13.2.1 EICRA – External Interrupt Control Register A
The External Interrupt Control Register A contains control bits for interrupt sense control.
Bit 76543210
(0x69)
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
• Bit 7:4 – Reserved
These bits are unused bits in the ATmega48A/PA/88A/PA/168A/PA/328/P, and will always read as zero.
• Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt
mask are set. The level and edges on the external INT1 pin that activate the interrupt are defined in Table 13-1.
The value on the INT1 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that
last longer than one clock period will generate an interrupt. Shorter pulses are not ensured to generate an
interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently
executing instruction to generate an interrupt.
– – – – ISC11 ISC10 ISC01 ISC00 EICRA
Table 13-1. Interrupt 1 Sense Control
ISC11 ISC10 Description
0 0 The low level of INT1 generates an interrupt request.
0 1 Any logical change on INT1 generates an interrupt request.
1 0 The falling edge of INT1 generates an interrupt request.
1 1 The rising edge of INT1 generates an interrupt request.
• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt
mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 13-2.
The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that
last longer than one clock period will generate an interrupt. Shorter pulses are not ensured to generate an
interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently
executing instruction to generate an interrupt.
Table 13-2. Interrupt 0 Sense Control
ISC01 ISC00 Description
0 0 The low level of INT0 generates an interrupt request.
0 1 Any logical change on INT0 generates an interrupt request.
1 0 The falling edge of INT0 generates an interrupt request.
1 1 The rising edge of INT0 generates an interrupt request.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 80
ATmega48A/PA/88A/PA/168A/PA/328/P
13.2.2 EIMSK – External Interrupt Mask Register
Bit 76543210
0x1D (0x3D)
Read/Write RRRRRRR/WR/W
Initial Value00000000
• Bit 7:2 – Reserved
These bits are unused bits in the ATmega48A/PA/88A/PA/168A/PA/328/P, and will always read as zero.
• Bit 1 – INT1: External Interrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt
is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the External Interrupt Control Register A
(EICRA) define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or level
sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The
corresponding interrupt of External Interrupt Request 1 is executed from the INT1 Interrupt Vector.
• Bit 0 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt
is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the External Interrupt Control Register A
(EICRA) define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level
sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The
corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector.
––––––INT1INT0EIMSK
13.2.3 EIFR – External Interrupt Flag Register
Bit 76543210
0x1C (0x3C)
Read/Write RRRRRRR/WR/W
Initial Value00000000
• Bit 7:2 – Reserved
––––––INTF1INTF0EIFR
These bits are unused bits in the ATmega48A/PA/88A/PA/168A/PA/328/P, and will always read as zero.
• Bit 1 – INTF1: External Interrupt Flag 1
When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the Ibit in SREG and the INT1 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector.
The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a
logical one to it. This flag is always cleared when INT1 is configured as a level interrupt.
• Bit 0 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the Ibit in SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector.
The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a
logical one to it. This flag is always cleared when INT0 is configured as a level interrupt.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 81
ATmega48A/PA/88A/PA/168A/PA/328/P
13.2.4 PCICR – Pin Change Interrupt Control Register
Bit 76543210
(0x68)
Read/Write RRRRRR/WR/WR/W
Initial Value00000000
• Bit 7:3 – Reserved
These bits are unused bits in the ATmega48A/PA/88A/PA/168A/PA/328/P, and will always read as zero.
• Bit 2 – PCIE2: Pin Change Interrupt Enable 2
When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 2 is
enabled. Any change on any enabled PCINT[23:16] pin will cause an interrupt. The corresponding interrupt of
Pin Change Interrupt Request is executed from the PCI2 Interrupt Vector. PCINT[23:16] pins are enabled
individually by the PCMSK2 Register.
• Bit 1 – PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 1 is
enabled. Any change on any enabled PCINT[14:8] pin will cause an interrupt. The corresponding interrupt of Pin
Change Interrupt Request is executed from the PCI1 Interrupt Vector. PCINT[14:8] pins are enabled individually
by the PCMSK1 Register.
– – – – – PCIE2 PCIE1 PCIE0 PCICR
• Bit 0 – PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is
enabled. Any change on any enabled PCINT[7:0] pin will cause an interrupt. The corresponding interrupt of Pin
Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT[7:0] pins are enabled individually
by the PCMSK0 Register.
13.2.5 PCIFR – Pin Change Interrupt Flag Register
Bit 76543210
0x1B (0x3B)
Read/Write RRRRRR/WR/WR/W
Initial Value00000000
–––––PCIF2PCIF1PCIF0PCIFR
• Bit 7:3 – Reserved
These bits are unused bits in the ATmega48A/PA/88A/PA/168A/PA/328/P, and will always read as zero.
• Bit 2 – PCIF2: Pin Change Interrupt Flag 2
When a logic change on any PCINT[23:16] pin triggers an interrupt request, PCIF2 becomes set (one). If the Ibit in SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector.
The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a
logical one to it.
• Bit 1 – PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT[14:8] pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit
in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector.
The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a
logical one to it.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 82
ATmega48A/PA/88A/PA/168A/PA/328/P
• Bit 0 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT[7:0] pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit
in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector.
The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a
logical one to it.
13.2.6 PCMSK2 – Pin Change Mask Register 2
Bit 76543210
(0x6D)
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
• Bit 7:0 – PCINT[23:16]: Pin Change Enable Mask 23...16
Each PCINT[23:16]-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If
PCINT[23:16] is set and the PCIE2 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O
pin. If PCINT[23:16] is cleared, pin change interrupt on the corresponding I/O pin is disabled.
13.2.7 PCMSK1 – Pin Change Mask Register 1
PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 PCMSK2
Bit 76543210
(0x6C)
Read/Write R R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
• Bit 7 – Reserved
– PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 PCMSK1
This bit is an unused bit in the ATmega48A/PA/88A/PA/168A/PA/328/P, and will always read as zero.
• Bit 6:0 – PCINT[14:8]: Pin Change Enable Mask 14...8
Each PCINT[14:8]-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If
PCINT[14:8] is set and the PCIE1 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O
pin. If PCINT[14:8] is cleared, pin change interrupt on the corresponding I/O pin is disabled.
13.2.8 PCMSK0 – Pin Change Mask Register 0
Bit 76543210
(0x6B)
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
• Bit 7:0 – PCINT[7:0]: Pin Change Enable Mask 7...0
PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 PCMSK0
Each PCINT[7:0] bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT[7:0]
is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If
PCINT[7:0] is cleared, pin change interrupt on the corresponding I/O pin is disabled.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 83
14. I/O-Ports
C
pin
Logic
R
pu
See Figure
"General Digital I/O" for
Details
Pxn
14.1 Overview
All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that
the direction of one port pin can be changed without unintentionally changing the direction of any other pin with
the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or
enabling/disabling of pull-up resistors (if configured as input). Each output buffer has symmetrical drive
characteristics with both high sink and source capability. The pin driver is strong enough to drive LED displays
directly. All port pins have individually selectable pull-up resistors with a supply-voltage invariant resistance. All
I/O pins have protection diodes to both V
Characteristics – (TA = -40°C to 85°C)” on page 308 for a complete list of parameters.
Figure 14-1. I/O Pin Equivalent Schematic
ATmega48A/PA/88A/PA/168A/PA/328/P
and Ground as indicated in Figure 14-1. Refer to ”Electrical
CC
All registers and bit references in this section are written in general form. A lower case “x” represents the
numbering letter for the port, and a lower case “n” represents the bit number. However, when using the register
or bit defines in a program, the precise form must be used. For example, PORTB3 for bit no. 3 in Port B, here
documented generally as PORTxn. The physical I/O Registers and bit locations are listed in ”Register
Description” on page 100.
Three I/O memory address locations are allocated for each port, one each for the Data Register – PORTx, Data
Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins I/O location is read only, while
the Data Register and the Data Direction Register are read/write. However, writing a logic one to a bit in the
PINx Register, will result in a toggle in the corresponding bit in the Data Register. In addition, the Pull-up Disable
– PUD bit in MCUCR disables the pull-up function for all pins in all ports when set.
Using the I/O port as General Digital I/O is described in ”Ports as General Digital I/O” on page 85. Most port pins
are multiplexed with alternate functions for the peripheral features on the device. How each alternate function
interferes with the port pin is described in ”Alternate Port Functions” on page 89. Refer to the individual module
sections for a full description of the alternate functions.
Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the
port as general digital I/O.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 84
14.2 Ports as General Digital I/O
clk
RPx
RRx
RDx
WDx
PUD
SYNCHRONIZER
WDx: WRITE DDRx
WRx: WRITE PORTx
RRx: READ PORTx REGISTER
RPx: READ PORTx PIN
PUD: PULLUP DISABLE
clk
I/O
: I/O CLOCK
RDx: READ DDRx
DLQ
Q
RESET
RESET
Q
QD
Q
Q D
CLR
PORTxn
Q
Q D
CLR
DDxn
PINxn
DATA B U S
SLEEP
SLEEP:SLEEP CONTROL
Pxn
I/O
WPx
0
1
WRx
WPx: WRITE PINx REGISTER
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 14-2 shows a functional description of
one I/O-port pin, here generically called Pxn.
ATmega48A/PA/88A/PA/168A/PA/328/P
Figure 14-2. General Digital I/O
(1)
Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
common to all ports.
14.2.1 Configuring the Pin
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in ”Register Description” on
page 100, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address,
and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is
configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To
switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output
pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If
PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero).
14.2.2 Toggling the Pin
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the
SBI instruction can be used to toggle one single bit in a port.
, SLEEP, and PUD are
I/O
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 85
14.2.3 Switching Between Input and Output
XXX in r17, PINx
0x00 0xFF
INSTRUCTIONS
SYNC LATCH
PINxn
r17
XXX
SYSTEM CLK
t
pd, max
t
pd, min
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an
intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10)
must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedance environment will not
notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the
MCUCR Register can be set to disable all pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user must use either the
tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11) as an intermediate step.
Table 14-1 summarizes the control signals for the pin value.
Table 14-1. Port Pin Configurations
PUD
DDxn PORTxn
0 0 X Input No Tri-state (Hi-Z)
0 1 0 Input Ye s Pxn will source current if ext. pulled low.
0 1 1 Input No Tri-state (Hi-Z)
1 0 X Output No Output Low (Sink)
1 1 X Output No Output High (Source)
(in MCUCR) I/O Pull-up Comment
ATmega48A/PA/88A/PA/168A/PA/328/P
14.2.4 Reading the Pin Value
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit.
As shown in Figure 14-2, the PINxn Register bit and the preceding latch constitute a synchronizer. This is
needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also
introduces a delay. Figure 14-3 shows a timing diagram of the synchronization when reading an externally
applied pin value. The maximum and minimum propagation delays are denoted t
Figure 14-3. Synchronization when Reading an Externally Applied Pin value
pd,max
and t
respectively.
pd,min
Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when
the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC
LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn
Register at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 86
ATmega48A/PA/88A/PA/168A/PA/328/P
out PORTx, r16 nop in r17, PINx
0xFF
0x00 0xFF
SYSTEM CLK
r16
INSTRUCTIONS
SYNC LATCH
PINxn
r17
t
pd
signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of
assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 14-
4. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd
through the synchronizer is 1 system clock period.
Figure 14-4. Synchronization when Reading a Software Assigned Pin Value
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins
from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but
as previously discussed, a nop instruction is included to be able to read back the value recently assigned to
some of the pins.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 87
ATmega48A/PA/88A/PA/168A/PA/328/P
Assembly Code Example
...
; Define pull-ups and set outputs high
; Define directions for port pins
ldi r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)
ldi
r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)
out PORTB,r16
out DDRB,r17
; Insert nop for synchronization
nop
; Read port pins
in r16,PINB
...
C Code Example
unsigned char i;
...
/* Define pull-ups and set outputs high */
/* Define directions for port pins */
PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);
DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);
/* Insert nop for synchronization*/
__no_operation();
/* Read port pins */
i = PINB;
...
(1)
Note: 1. For the assembly program, two temporary registers are used to minimize the time from pull-ups are set on pins
0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as
strong high drivers.
14.2.5 Digital Input Enable and Sleep Modes
As shown in Figure 14-2, the digital input signal can be clamped to ground at the input of the Schmitt Trigger.
The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save
mode, and Standby mode to avoid high power consumption if some input signals are left floating, or have an
analog signal level close to V
CC
/2.
SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not
enabled, SLEEP is active also for these pins. SLEEP is also overridden by various other alternate functions as
described in ”Alternate Port Functions” on page 89.
If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as “Interrupt on
Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the
corresponding External Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the
clamping in these sleep mode produces the requested logic change.
14.2.6 Unconnected Pins
If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of
the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to
reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and
Idle mode).
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 88
The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case,
clk
RPx
RRx
WRx
RDx
WDx
PUD
SYNCHRONIZER
WDx: WRITE DDRx
WRx: WRITE PORTx
RRx: READ PORTx REGISTER
RPx: READ PORTx PIN
PUD: PULLUP DISABLE
clk
I/O
: I/O CLOCK
RDx: READ DDRx
DLQ
Q
SET
CLR
0
1
0
1
0
1
DIxn
AIOxn
DIEOExn
PVOVxn
PVOExn
DDOVxn
DDOExn
PUOExn
PUOVxn
PUOExn: Pxn PULL-UP OVERRIDE ENABLE
PUOVxn: Pxn PULL-UP OVERRIDE VALUE
DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE
DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE
PVOExn: Pxn PORT VALUE OVERRIDE ENABLE
PVOVxn: Pxn PORT VALUE OVERRIDE VALUE
DIxn: DIGITAL INPUT PIN n ON PORTx
AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx
RESET
RESET
Q
Q
D
CLR
Q
Q
D
CLR
Q
Q
D
CLR
PINxn
PORTxn
DDxn
DATA BU
S
0
1
DIEOVxn
SLEEP
DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE
DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE
SLEEP:SLEEP CONTROL
Pxn
I/O
0
1
PTOExn
PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE
WPx: WRITE PINx
WPx
the pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended
to use an external pull-up or pull-down. Connecting unused pins directly to V
since this may cause excessive currents if the pin is accidentally configured as an output.
14.3 Alternate Port Functions
Most port pins have alternate functions in addition to being general digital I/Os. Figure 14-5 shows how the port
pin control signals from the simplified Figure 14-2 on page 85 can be overridden by alternate functions. The
overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to
all port pins in the AVR microcontroller family.
ATmega48A/PA/88A/PA/168A/PA/328/P
or GND is not recommended,
CC
(1)
, SLEEP, and PUD are
I/O
Figure 14-5. Alternate Port Functions
Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
common to all ports. All other signals are unique for each pin.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 89
ATmega48A/PA/88A/PA/168A/PA/328/P
Table 14-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 14-5 on
page 89 are not shown in the succeeding tables. The overriding signals are generated internally in the modules
having the alternate function.
Table 14-2. Generic Description of Overriding Signals for Alternate Functions
Signal Name Full Name Description
If this signal is set, the pull-up enable is controlled by the PUOV
signal. If this signal is cleared, the pull-up is enabled when
{DDxn, PORTxn, PUD} = 0b010.
If PUOE is set, the pull-up is enabled/disabled when PUOV is
set/cleared, regardless of the setting of the DDxn, PORTxn,
and PUD Register bits.
PUOE
PUOV
Pull-up Override
Enable
Pull-up Override
Val ue
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI Digital Input
AIO
Data Direction
Override Enable
Data Direction
Override Value
Port Value
Override Enable
Port Value
Override Value
Port Toggle
Override Enable
Digital Input
Enable Override
Enable
Digital Input
Enable Override
Val ue
Analog
Input/Output
If this signal is set, the Output Driver Enable is controlled by the
DDOV signal. If this signal is cleared, the Output driver is
enabled by the DDxn Register bit.
If DDOE is set, the Output Driver is enabled/disabled when
DDOV is set/cleared, regardless of the setting of the DDxn
Register bit.
If this signal is set and the Output Driver is enabled, the port
value is controlled by the PVOV signal. If PVOE is cleared, and
the Output Driver is enabled, the port Value is controlled by the
PORTxn Register bit.
If PVOE is set, the port value is set to PVOV, regardless of the
setting of the PORTxn Register bit.
If PTOE is set, the PORTxn Register bit is inverted.
If this bit is set, the Digital Input Enable is controlled by the
DIEOV signal. If this signal is cleared, the Digital Input Enable
is determined by MCU state (Normal mode, sleep mode).
If DIEOE is set, the Digital Input is enabled/disabled when
DIEOV is set/cleared, regardless of the MCU state (Normal
mode, sleep mode).
This is the Digital Input to alternate functions. In the figure, the
signal is connected to the output of the Schmitt Trigger but
before the synchronizer. Unless the Digital Input is used as a
clock source, the module with the alternate function will use its
own synchronizer.
This is the Analog Input/output to/from alternate functions. The
signal is connected directly to the pad, and can be used bidirectionally.
The following subsections shortly describe the alternate functions for each port, and relate the overriding signals
to the alternate function. Refer to the alternate function description for further details.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 90
14.3.1 Alternate Functions of Port B
The Port B pins with alternate functions are shown in Table 14-3.
Table 14-3. Port B Pins Alternate Functions
Port Pin Alternate Functions
XTAL2 (Chip Clock Oscillator pin 2)
PB7
PB6
PB5
PB4
PB3
TOSC2 (
PCINT7 (Pin Change Interrupt 7)
XTAL1 (Chip Clock Oscillator pin 1 or External clock input)
TOSC1 (
PCINT6 (Pin Change Interrupt 6)
SCK (SPI Bus Master clock Input)
PCINT5 (Pin Change Interrupt 5)
MISO (SPI Bus Master Input/Slave Output)
PCINT4 (Pin Change Interrupt 4)
MOSI (SPI Bus Master Output/Slave Input)
OC2A (Timer/Counter2 Output Compare Match A Output)
PCINT3 (Pin Change Interrupt 3)
Timer Oscillator pin 2)
Timer Oscillator pin 1)
ATmega48A/PA/88A/PA/168A/PA/328/P
SS (SPI Bus Master Slave select)
PB2
PB1
PB0
OC1B (Timer/Counter1 Output Compare Match B Output)
PCINT2 (Pin Change Interrupt 2)
OC1A (Timer/Counter1 Output Compare Match A Output)
PCINT1 (Pin Change Interrupt 1)
ICP1 (Timer/Counter1 Input Capture Input)
CLKO (Divided System Clock Output)
PCINT0 (Pin Change Interrupt 0)
The alternate pin configuration is as follows:
• XTAL2/TOSC2/PCINT7 – Port B, Bit 7
XTAL2: Chip clock Oscillator pin 2. Used as clock pin for crystal Oscillator or Low-frequency crystal Oscillator.
When used as a clock pin, the pin can not be used as an I/O pin.
TOSC2: Timer Oscillator pin 2. Used only if internal calibrated RC Oscillator is selected as chip clock source,
and the asynchronous timer is enabled by the correct setting in ASSR. When the AS2 bit in ASSR is set (one)
and the EXCLK bit is cleared (zero) to enable asynchronous clocking of Timer/Counter2 using the Crystal
Oscillator, pin PB7 is disconnected from the port, and becomes the inverting output of the Oscillator amplifier. In
this mode, a crystal Oscillator is connected to this pin, and the pin cannot be used as an I/O pin.
PCINT7: Pin Change Interrupt source 7. The PB7 pin can serve as an external interrupt source.
If PB7 is used as a clock pin, DDB7, PORTB7 and PINB7 will all read 0.
• XTAL1/TOSC1/PCINT6 – Port B, Bit 6
XTAL1: Chip clock Oscillator pin 1. Used for all chip clock sources except internal calibrated RC Oscillator.
When used as a clock pin, the pin can not be used as an I/O pin.
TOSC1: Timer Oscillator pin 1. Used only if internal calibrated RC Oscillator is selected as chip clock source,
and the asynchronous timer is enabled by the correct setting in ASSR. When the AS2 bit in ASSR is set (one) to
enable asynchronous clocking of Timer/Counter2, pin PB6 is disconnected from the port, and becomes the
input of the inverting Oscillator amplifier. In this mode, a crystal Oscillator is connected to this pin, and the pin
can not be used as an I/O pin.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 91
ATmega48A/PA/88A/PA/168A/PA/328/P
PCINT6: Pin Change Interrupt source 6. The PB6 pin can serve as an external interrupt source.
If PB6 is used as a clock pin, DDB6, PORTB6 and PINB6 will all read 0.
• SCK/PCINT5 – Port B, Bit 5
SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a Slave, this pin
is configured as an input regardless of the setting of DDB5. When the SPI is enabled as a Master, the data
direction of this pin is controlled by DDB5. When the pin is forced by the SPI to be an input, the pull-up can still
be controlled by the PORTB5 bit.
PCINT5: Pin Change Interrupt source 5. The PB5 pin can serve as an external interrupt source.
• MISO/PCINT4 – Port B, Bit 4
MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a Master, this pin
is configured as an input regardless of the setting of DDB4. When the SPI is enabled as a Slave, the data
direction of this pin is controlled by DDB4. When the pin is forced by the SPI to be an input, the pull-up can still
be controlled by the PORTB4 bit.
PCINT4: Pin Change Interrupt source 4. The PB4 pin can serve as an external interrupt source.
• MOSI/OC2/PCINT3 – Port B, Bit 3
MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a Slave, this pin
is configured as an input regardless of the setting of DDB3. When the SPI is enabled as a Master, the data
direction of this pin is controlled by DDB3. When the pin is forced by the SPI to be an input, the pull-up can still
be controlled by the PORTB3 bit.
OC2, Output Compare Match Output: The PB3 pin can serve as an external output for the Timer/Counter2
Compare Match. The PB3 pin has to be configured as an output (DDB3 set (one)) to serve this function. The
OC2 pin is also the output pin for the PWM mode timer function.
PCINT3: Pin Change Interrupt source 3. The PB3 pin can serve as an external interrupt source.
•SS
/OC1B/PCINT2 – Port B, Bit 2
SS: Slave Select input. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the
setting of DDB2. As a Slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a
Master, the data direction of this pin is controlled by DDB2. When the pin is forced by the SPI to be an input, the
pull-up can still be controlled by the PORTB2 bit.
OC1B, Output Compare Match output: The PB2 pin can serve as an external output for the Timer/Counter1
Compare Match B. The PB2 pin has to be configured as an output (DDB2 set (one)) to serve this function. The
OC1B pin is also the output pin for the PWM mode timer function.
PCINT2: Pin Change Interrupt source 2. The PB2 pin can serve as an external interrupt source.
• OC1A/PCINT1 – Port B, Bit 1
OC1A, Output Compare Match output: The PB1 pin can serve as an external output for the Timer/Counter1
Compare Match A. The PB1 pin has to be configured as an output (DDB1 set (one)) to serve this function. The
OC1A pin is also the output pin for the PWM mode timer function.
PCINT1: Pin Change Interrupt source 1. The PB1 pin can serve as an external interrupt source.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 92
ATmega48A/PA/88A/PA/168A/PA/328/P
• ICP1/CLKO/PCINT0 – Port B, Bit 0
ICP1, Input Capture Pin: The PB0 pin can act as an Input Capture Pin for Timer/Counter1.
CLKO, Divided System Clock: The divided system clock can be output on the PB0 pin. The divided system clock
will be output if the CKOUT Fuse is programmed, regardless of the PORTB0 and DDB0 settings. It will also be
output during reset.
PCINT0: Pin Change Interrupt source 0. The PB0 pin can serve as an external interrupt source.
Table 14-4 and Table 14-5 on page 94 relate the alternate functions of Port B to the overriding signals shown in
Figure 14-5 on page 89. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is
divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.
Table 14-4. Overriding Signals for Alternate Functions in PB7...PB4
Signal
Name
PUOE
PUOV 0 0 PORTB5 • PUD PORTB4 • PUD
DDOE
DDOV 0 0 0 0
PVOE 0 0 SPE • MSTR SPE • MSTR
PVOV 0 0 SCK OUTPUT
DIEOE
DIEOV
DI PCINT7 INPUT PCINT6 INPUT
AIO Oscillator Output
Notes: 1. INTRC means that one of the internal RC Oscillators are selected (by the CKSEL fuses), EXTCK means that
PB7/XTAL2/
TOSC2/PCINT7
INTRC • EXTCK+
AS2
INTRC • EXTCK+
AS2
INTRC • EXTCK +
AS2 + PCINT7 •
PCIE0
(INTRC + EXTCK) •
AS2
external clock is selected (by the CKSEL fuses)
PB6/XTAL1/
(1)
TOSC1/PCINT6
INTRC + AS2 SPE • MSTR SPE • MSTR
INTRC + AS2 SPE • MSTR SPE • MSTR
INTRC + AS2 +
PCINT6 • PCIE0
INTRC • AS2 1 1
Oscillator/Clock
Input
(1)
PB5/SCK/
PCINT5
PCINT5 • PCIE0 PCINT4 • PCIE0
PCINT5 INPUT
SCK INPUT
– –
PB4/MISO/
PCINT4
SPI SLAVE
OUTPUT
PCINT4 INPUT
SPI MSTR INPUT
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 93
ATmega48A/PA/88A/PA/168A/PA/328/P
Table 14-5. Overriding Signals for Alternate Functions in PB3...PB0
Signal
Name
PUOE SPE • MSTR SPE • MSTR 0 0
PUOV PORTB3 • PUD PORTB2 • PUD 0 0
DDOE SPE • MSTR SPE • MSTR 0 0
DDOV 0 0 0 0
PVOE
PVOV
DIEOE PCINT3 • PCIE0 PCINT2 • PCIE0 PCINT1 • PCIE0 PCINT0 • PCIE0
DIEOV 1 1 1 1
DI
AIO – – – –
PB3/MOSI/
OC2/PCINT3
SPE • MSTR +
OC2A ENABLE
SPI MSTR OUTPUT
+ OC2A
PCINT3 INPUT
SPI SLAVE INPUT
14.3.2 Alternate Functions of Port C
The Port C pins with alternate functions are shown in Table 14-6.
Table 14-6. Port C Pins Alternate Functions
Port Pin Alternate Function
PB2/SS/
OC1B/PCINT2
OC1B ENABLE OC1A ENABLE 0
OC1B OC1A 0
PCINT2 INPUT
SPI SS
PB1/OC1A/
PCINT1
PCINT1 INPUT
PB0/ICP1/
PCINT0
PCINT0 INPUT
ICP1 INPUT
PC6
PC5
PC4
PC3
PC2
PC1
PC0
RESET (Reset pin)
PCINT14 (Pin Change Interrupt 14)
ADC5 (ADC Input Channel 5)
SCL (2-wire Serial Bus Clock Line)
PCINT13 (Pin Change Interrupt 13)
ADC4 (ADC Input Channel 4)
SDA (2-wire Serial Bus Data Input/Output Line)
PCINT12 (Pin Change Interrupt 12)
ADC3 (ADC Input Channel 3)
PCINT11 (Pin Change Interrupt 11)
ADC2 (ADC Input Channel 2)
PCINT10 (Pin Change Interrupt 10)
ADC1 (ADC Input Channel 1)
PCINT9 (Pin Change Interrupt 9)
ADC0 (ADC Input Channel 0)
PCINT8 (Pin Change Interrupt 8)
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 94
ATmega48A/PA/88A/PA/168A/PA/328/P
The alternate pin configuration is as follows:
• RESET
RESET
part will have to rely on Power-on Reset and Brown-out Reset as its reset sources. When the RSTDISBL Fuse
is unprogrammed, the reset circuitry is connected to the pin, and the pin can not be used as an I/O pin.
If PC6 is used as a reset pin, DDC6, PORTC6 and PINC6 will all read 0.
PCINT14: Pin Change Interrupt source 14. The PC6 pin can serve as an external interrupt source.
• SCL/ADC5/PCINT13 – Port C, Bit 5
SCL, 2-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to enable the 2-wire Serial
Interface, pin PC5 is disconnected from the port and becomes the Serial Clock I/O pin for the 2-wire Serial
Interface. In this mode, there is a spike filter on the pin to suppress spikes shorter than 50 ns on the input signal,
and the pin is driven by an open drain driver with slew-rate limitation.
PC5 can also be used as ADC input Channel 5. Note that ADC input channel 5 uses digital power.
PCINT13: Pin Change Interrupt source 13. The PC5 pin can serve as an external interrupt source.
• SDA/ADC4/PCINT12 – Port C, Bit 4
SDA, 2-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the 2-wire Serial
Interface, pin PC4 is disconnected from the port and becomes the Serial Data I/O pin for the 2-wire Serial
Interface. In this mode, there is a spike filter on the pin to suppress spikes shorter than 50 ns on the input signal,
and the pin is driven by an open drain driver with slew-rate limitation.
PC4 can also be used as ADC input Channel 4. Note that ADC input channel 4 uses digital power.
PCINT12: Pin Change Interrupt source 12. The PC4 pin can serve as an external interrupt source.
/PCINT14 – Port C, Bit 6
, Reset pin: When the RSTDISBL Fuse is programmed, this pin functions as a normal I/O pin, and the
• ADC3/PCINT11 – Port C, Bit 3
PC3 can also be used as ADC input Channel 3. Note that ADC input channel 3 uses analog power.
PCINT11: Pin Change Interrupt source 11. The PC3 pin can serve as an external interrupt source.
• ADC2/PCINT10 – Port C, Bit 2
PC2 can also be used as ADC input Channel 2. Note that ADC input channel 2 uses analog power.
PCINT10: Pin Change Interrupt source 10. The PC2 pin can serve as an external interrupt source.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 95
ATmega48A/PA/88A/PA/168A/PA/328/P
• ADC1/PCINT9 – Port C, Bit 1
PC1 can also be used as ADC input Channel 1. Note that ADC input channel 1 uses analog power.
PCINT9: Pin Change Interrupt source 9. The PC1 pin can serve as an external interrupt source.
• ADC0/PCINT8 – Port C, Bit 0
PC0 can also be used as ADC input Channel 0. Note that ADC input channel 0 uses analog power.
PCINT8: Pin Change Interrupt source 8. The PC0 pin can serve as an external interrupt source.
Table 14-7 and Table 14-8 relate the alternate functions of Port C to the overriding signals shown in Figure 14-5
on page 89.
Table 14-7. Overriding Signals for Alternate Functions in PC6...PC4
Signal
Name PC6/RESET/PCINT14 PC5/SCL/ADC5/PCINT13 PC4/SDA/ADC4/PCINT12
PUOE RSTDISBL TWEN TWEN
PUOV 1 PORTC5 • PUD PORTC4 • PUD
DDOE RSTDISBL TWEN TWEN
DDOV 0 SCL_OUT SDA_OUT
PVOE 0 TWEN TWEN
PVOV 0 0 0
DIEOE
DIEOV RSTDISBL PCINT13 • PCIE1 PCINT12 • PCIE1
DI PCINT14 INPUT PCINT13 INPUT PCINT12 INPUT
AIO RESET INPUT ADC5 INPUT / SCL INPUT ADC4 INPUT / SDA INPUT
Note: 1. When enabled, the 2-wire Serial Interface enables slew-rate controls on the output pins PC4 and PC5. This is
RSTDISBL + PCINT14 •
PCIE1
not shown in the figure. In addition, spike filters are connected between the AIO outputs shown in the port
figure and the digital logic of the TWI module.
PCINT13 • PCIE1 + ADC5D PCINT12 • PCIE1 + ADC4D
(1)
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 96
ATmega48A/PA/88A/PA/168A/PA/328/P
Table 14-8. Overriding Signals for Alternate Functions in PC3...PC0
Signal
Name
PUOE 0 0 0 0
PUOV 0 0 0 0
DDOE 0 0 0 0
DDOV 0 0 0 0
PVOE 0 0 0 0
PVOV 0 0 0 0
DIEOE
DIEOV PCINT11 • PCIE1 PCINT10 • PCIE1 PCINT9 • PCIE1 PCINT8 • PCIE1
DI PCINT11 INPUT PCINT10 INPUT PCINT9 INPUT PCINT8 INPUT
AIO ADC3 INPUT ADC2 INPUT ADC1 INPUT ADC0 INPUT
PC3/ADC3/
PCINT11
PCINT11 • PCIE1 +
ADC3D
14.3.3 Alternate Functions of Port D
The Port D pins with alternate functions are shown in Table 14-9.
Table 14-9. Port D Pins Alternate Functions
PC2/ADC2/
PCINT10
PCINT10 • PCIE1 +
ADC2D
PC1/ADC1/
PCINT9
PCINT9 • PCIE1 +
ADC1D
PC0/ADC0/
PCINT8
PCINT8 • PCIE1 +
ADC0D
Port Pin Alternate Function
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
AIN1 (Analog Comparator Negative Input)
PCINT23 (Pin Change Interrupt 23)
AIN0 (Analog Comparator Positive Input)
OC0A (Timer/Counter0 Output Compare Match A Output)
PCINT22 (Pin Change Interrupt 22)
T1 (Timer/Counter 1 External Counter Input)
OC0B (Timer/Counter0 Output Compare Match B Output)
PCINT21 (Pin Change Interrupt 21)
XCK (USART External Clock Input/Output)
T0 (Timer/Counter 0 External Counter Input)
PCINT20 (Pin Change Interrupt 20)
INT1 (External Interrupt 1 Input)
OC2B (Timer/Counter2 Output Compare Match B Output)
PCINT19 (Pin Change Interrupt 19)
INT0 (External Interrupt 0 Input)
PCINT18 (Pin Change Interrupt 18)
TXD (USART Output Pin)
PCINT17 (Pin Change Interrupt 17)
RXD (USART Input Pin)
PCINT16 (Pin Change Interrupt 16)
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 97
ATmega48A/PA/88A/PA/168A/PA/328/P
The alternate pin configuration is as follows:
• AIN1/OC2B/PCINT23 – Port D, Bit 7
AIN1, Analog Comparator Negative Input. Configure the port pin as input with the internal pull-up switched off to
avoid the digital port function from interfering with the function of the Analog Comparator.
PCINT23: Pin Change Interrupt source 23. The PD7 pin can serve as an external interrupt source.
• AIN0/OC0A/PCINT22 – Port D, Bit 6
AIN0, Analog Comparator Positive Input. Configure the port pin as input with the internal pull-up switched off to
avoid the digital port function from interfering with the function of the Analog Comparator.
OC0A, Output Compare Match output: The PD6 pin can serve as an external output for the Timer/Counter0
Compare Match A. The PD6 pin has to be configured as an output (DDD6 set (one)) to serve this function. The
OC0A pin is also the output pin for the PWM mode timer function.
PCINT22: Pin Change Interrupt source 22. The PD6 pin can serve as an external interrupt source.
• T1/OC0B/PCINT21 – Port D, Bit 5
T1, Timer/Counter1 counter source.
OC0B, Output Compare Match output: The PD5 pin can serve as an external output for the Timer/Counter0
Compare Match B. The PD5 pin has to be configured as an output (DDD5 set (one)) to serve this function. The
OC0B pin is also the output pin for the PWM mode timer function.
PCINT21: Pin Change Interrupt source 21. The PD5 pin can serve as an external interrupt source.
• XCK/T0/PCINT20 – Port D, Bit 4
XCK, USART external clock.
T0, Timer/Counter0 counter source.
PCINT20: Pin Change Interrupt source 20. The PD4 pin can serve as an external interrupt source.
• INT1/OC2B/PCINT19 – Port D, Bit 3
INT1, External Interrupt source 1: The PD3 pin can serve as an external interrupt source.
OC2B, Output Compare Match output: The PD3 pin can serve as an external output for the Timer/Counter0
Compare Match B. The PD3 pin has to be configured as an output (DDD3 set (one)) to serve this function. The
OC2B pin is also the output pin for the PWM mode timer function.
PCINT19: Pin Change Interrupt source 19. The PD3 pin can serve as an external interrupt source.
• INT0/PCINT18 – Port D, Bit 2
INT0, External Interrupt source 0: The PD2 pin can serve as an external interrupt source.
PCINT18: Pin Change Interrupt source 18. The PD2 pin can serve as an external interrupt source.
• TXD/PCINT17 – Port D, Bit 1
TXD, Transmit Data (Data output pin for the USART). When the USART Transmitter is enabled, this pin is
configured as an output regardless of the value of DDD1.
PCINT17: Pin Change Interrupt source 17. The PD1 pin can serve as an external interrupt source.
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 98
ATmega48A/PA/88A/PA/168A/PA/328/P
• RXD/PCINT16 – Port D, Bit 0
RXD, Receive Data (Data input pin for the USART). When the USART Receiver is enabled this pin is configured
as an input regardless of the value of DDD0. When the USART forces this pin to be an input, the pull-up can still
be controlled by the PORTD0 bit.
PCINT16: Pin Change Interrupt source 16. The PD0 pin can serve as an external interrupt source.
Table 14-10 and Table 14-11 relate the alternate functions of Port D to the overriding signals shown in Figure
14-5 on page 89.
Table 14-10. Overriding Signals for Alternate Functions PD7...PD4
Signal
Name
PUOE 0 0 0 0
PUO 0 0 0 0
DDOE 0 0 0 0
DDOV 0 0 0 0
PVOE 0 OC0A ENABLE OC0B ENABLE UMSEL
PVOV 0 OC0A OC0B XCK OUTPUT
DIEOE PCINT23 • PCIE2 PCINT22 • PCIE2 PCINT21 • PCIE2 PCINT20 • PCIE2
PD7/AIN1
/PCINT23
PD6/AIN0/
OC0A/PCINT22
PD5/T1/OC0B/
PCINT21
PD4/XCK/
T0/PCINT20
DIEOV 1 1 1 1
DI PCINT23 INPUT PCINT22 INPUT
AIO AIN1 INPUT AIN0 INPUT – –
Table 14-11. Overriding Signals for Alternate Functions in PD3...PD0
Signal
Name
PUOE 0 0 TXEN RXEN
PUO 0 0 0 PORTD0 • PUD
DDOE 0 0 TXEN RXEN
DDOV 0 0 1 0
PVOE OC2B ENABLE 0 TXEN 0
PVOV OC2B 0 TXD 0
DIEOE
DIEOV 1 1 1 1
DI
AIO – – – –
PD3/OC2B/INT1/
PCINT19
INT1 ENABLE +
PCINT19 • PCIE2
PCINT19 INPUT
INT1 INPUT
PD2/INT0/
PCINT18
INT0 ENABLE +
PCINT18 • PCIE1
PCINT18 INPUT
INT0 INPUT
PCINT21 INPUT
T1 INPUT
PD1/TXD/
PCINT17
PCINT17 • PCIE2 PCINT16 • PCIE2
PCINT17 INPUT
PCINT20 INPUT
XCK INPUT
T0 INPUT
PD0/RXD/
PCINT16
PCINT16 INPUT
RXD
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 99
14.4 Register Description
14.4.1 MCUCR – MCU Control Register
ATmega48A/PA/88A/PA/168A/PA/328/P
Bit 7 6 5 4 3 2 1 0
0x35 (0x55)
Read/Write R R/W R/W R/W R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0
–
BODS
(1)
BODSE
(1)
PUD – – IVSEL IVCE MCUCR
Notes: 1. BODS and BODSE only available for picoPower devices ATmega48PA/88PA/168PA/328P
• Bit 4 – PUD: Pull-up Disable
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers
are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See ”Configuring the Pin” on page 85 for more
details about this feature.
14.4.2 PORTB – The Port B Data Register
Bit 76543210
0x05 (0x25)
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 PORTB
14.4.3 DDRB – The Port B Data Direction Register
Bit 76543210
0x04 (0x24)
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB
14.4.4 PINB – The Port B Input Pins Address
Bit 76543210
0x03 (0x23)
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value N/A N/A N/A N/A N/A N/A N/A N/A
PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 PINB
(1)
14.4.5 PORTC – The Port C Data Register
Bit 76543210
0x08 (0x28)
Read/Write R R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
– PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 PORTC
14.4.6 DDRC – The Port C Data Direction Register
Bit 76543210
0x07 (0x27)
Read/Write R R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
– DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 DDRC
2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 100
Loading...