Microchip Technology megaAVR 0, ATmega4808, ATmega4809, ATmega3208, ATmega3209 Series Manual
Introduction
megaAVR® 0-Series
Manual
The ATmega3208/3209/4808/4809 microcontrollers of the megaAVR® 0-series are using the AVR
processor with hardware multiplier, running at up to 20 MHz, with a wide range of Flash sizes up to 48
KB, up to 6 KB of SRAM, and 256 bytes of EEPROM in 28-, 32-, or 48-pin package. The series uses the
latest technologies from Microchip with a flexible and low-power architecture including Event System and
SleepWalking, accurate analog features and advanced peripherals.
This Manual contains the general descriptions of the peripherals. While the available peripherals have
identical features and show the same behavior across the series, packages with fewer pins support a
subset of signals. Refer to the Data Sheet of the individual device for available pins and signals.
®
Features
• AVR® CPU
– Single-cycle I/O access
– Two-level interrupt controller
– Two-cycle hardware multiplier
• Memories
– Up to 48 KB In-system self-programmable Flash memory
– 256B EEPROM
– Up to 6 KB SRAM
– Write/Erase endurance:
• Flash 10,000 cycles
• EEPROM 100,000 cycles
– Data retention: 20 Years at 85°C
• System
– Power-on Reset (POR) circuit
– Brown-out Detection (BOD)
– Clock options:
• Lockable 20 MHz low power internal oscillator
• 32.768 kHz Ultra Low-Power (ULP) internal oscillator
• 32.768 kHz external crystal oscillator
• External clock input
– Single-pin Unified Program Debug Interface (UPDI)
– Three sleep modes:
• Idle with all peripherals running and mode for immediate wake-up time
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• Standby
– Configurable operation of selected peripherals
– SleepWalking peripherals
• Power Down with limited wake-up functionality
• Peripherals
– One 16-bit Timer/Counter type A with dedicated period register, three compare channels (TCA)
– Up to four 16-bit Timer/Counter type B with input capture (TCB)
– One 16-bit Real Time Counter (RTC) running from external crystal or internal RC oscillator
– Up to four USART with fractional baud rate generator, autobaud, and start-of-frame detection
– Master/slave Serial Peripheral Interface (SPI)
– Master/Slave TWI with dual address match
• Can operate simultaneously as master and slave
• Standard mode (Sm, 100 kHz)
• Fast mode (Fm, 400 kHz)
• Fast mode plus (Fm+, 1 MHz)
– Event System for CPU independent and predictable inter-peripheral signaling
– Configurable Custom Logic (CCL) with up to four programmable Lookup Tables (LUT)
– One Analog Comparator (AC) with scalable reference input
– One 10-bit 150 ksps Analog to Digital Converter (ADC)
– Five selectable internal voltage references: 0.55V, 1.1V, 1.5V, 2.5V, and 4.3V
– CRC code memory scan hardware
• Optional automatic scan after reset
– Watchdog Timer (WDT) with Window Mode, with separate on-chip oscillator
– External interrupt on all general purpose pins
• I/O and Packages:
– Up to 41 programmable I/O lines
– 28-pin SSOP
– 32-pin VQFN 5x5 and TQFP 7x7
– 48-pin UQFN 6x6 and TQFP 7x7
• Temperature Range: -40°C to 125°C
• Speed Grades:
– 0-5 MHz @ 1.8V – 5.5V
– 0-10 MHz @ 2.7V – 5.5V
– 0-20 MHz @ 4.5V – 5.5V, -40°C to 105°C
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Table of Contents
Introduction......................................................................................................................1
Features.......................................................................................................................... 1
1. Block Diagram........................................................................................................... 8
2. megaAVR® 0-series Overview................................................................................... 9
2.1. Memory Overview........................................................................................................................ 9
2.2. Peripheral Overview...................................................................................................................10
3. Conventions.............................................................................................................11
3.1. Numerical Notation.....................................................................................................................11
3.2. Memory Size and Type...............................................................................................................11
3.3. Frequency and Time...................................................................................................................11
3.4. Registers and Bits...................................................................................................................... 12
4. Acronyms and Abbreviations...................................................................................14
5. Memories.................................................................................................................17
5.1. Overview.................................................................................................................................... 17
5.2. Memory Map.............................................................................................................................. 17
5.3. In-System Reprogrammable Flash Program Memory................................................................18
5.4. SRAM Data Memory.................................................................................................................. 19
5.5. EEPROM Data Memory............................................................................................................. 19
5.6. User Row (USERROW)............................................................................................................. 19
5.7. Signature Row (SIGROW)......................................................................................................... 20
5.8. Fuses (FUSE).............................................................................................................................28
5.9. Memory Section Access from CPU and UPDI on Locked Device..............................................38
5.10. I/O Memory.................................................................................................................................39
6. Peripherals and Architecture................................................................................... 43
6.1. Peripheral Module Address Map................................................................................................43
6.2. Interrupt Vector Mapping............................................................................................................45
6.3. System Configuration (SYSCFG)...............................................................................................47
7. AVR CPU.................................................................................................................50
7.1. Features..................................................................................................................................... 50
7.2. Overview.................................................................................................................................... 50
7.3. Architecture................................................................................................................................ 50
7.4. Arithmetic Logic Unit (ALU)........................................................................................................52
7.5. Functional Description................................................................................................................52
7.6. Register Summary - CPU...........................................................................................................57
7.7. Register Description...................................................................................................................57
8. Nonvolatile Memory Controller (NVMCTRL)........................................................... 62
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8.1. Features..................................................................................................................................... 62
8.2. Overview.................................................................................................................................... 62
8.3. Functional Description................................................................................................................63
8.4. Register Summary - NVMCTRL.................................................................................................69
8.5. Register Description...................................................................................................................69
9. Clock Controller (CLKCTRL)................................................................................... 77
9.1. Features..................................................................................................................................... 77
9.2. Overview.................................................................................................................................... 77
9.3. Functional Description................................................................................................................79
9.4. Register Summary - CLKCTRL..................................................................................................83
9.5. Register Description...................................................................................................................83
10. Sleep Controller (SLPCTRL)................................................................................... 93
10.1. Features..................................................................................................................................... 93
10.2. Overview.................................................................................................................................... 93
10.3. Functional Description................................................................................................................94
10.4. Register Summary - SLPCTRL.................................................................................................. 97
10.5. Register Description................................................................................................................... 97
11. Reset Controller (RSTCTRL)...................................................................................99
11.1. Features..................................................................................................................................... 99
11.2. Overview.................................................................................................................................... 99
11.3. Functional Description..............................................................................................................100
11.4. Register Summary - RSTCTRL................................................................................................102
11.5. Register Description................................................................................................................. 102
12. CPU Interrupt Controller (CPUINT)....................................................................... 105
12.1. Features................................................................................................................................... 105
12.2. Overview.................................................................................................................................. 105
12.3. Functional Description..............................................................................................................106
12.4. Register Summary - CPUINT................................................................................................... 112
12.5. Register Description................................................................................................................. 112
13. Event System (EVSYS)......................................................................................... 117
13.1. Features................................................................................................................................... 117
13.2. Overview...................................................................................................................................117
13.3. Functional Description.............................................................................................................. 119
13.4. Register Summary - EVSYS.................................................................................................... 123
13.5. Register Description................................................................................................................. 123
14. Port Multiplexer (PORTMUX)................................................................................ 129
14.1. Overview.................................................................................................................................. 129
14.2. Register Summary - PORTMUX.............................................................................................. 130
14.3. Register Description................................................................................................................. 130
15. I/O Pin Configuration (PORT)................................................................................137
15.1. Features................................................................................................................................... 137
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15.2. Overview.................................................................................................................................. 137
15.3. Functional Description..............................................................................................................138
15.4. Register Summary - PORTx.....................................................................................................142
15.5. Register Description - Ports..................................................................................................... 142
15.6. Register Summary - VPORTx.................................................................................................. 155
15.7. Register Description - Virtual Ports.......................................................................................... 155
16. Brown-Out Detector (BOD)....................................................................................160
16.1. Features................................................................................................................................... 160
16.2. Overview.................................................................................................................................. 160
16.3. Functional Description..............................................................................................................161
16.4. Register Summary - BOD.........................................................................................................163
16.5. Register Description................................................................................................................. 163
17. Voltage Reference (VREF)....................................................................................170
17.1. Features................................................................................................................................... 170
17.2. Overview.................................................................................................................................. 170
17.3. Functional Description..............................................................................................................170
17.4. Register Summary - VREF.......................................................................................................172
17.5. Register Description................................................................................................................. 172
18. Watchdog Timer (WDT).........................................................................................175
18.1. Features................................................................................................................................... 175
18.2. Overview.................................................................................................................................. 175
18.3. Functional Description..............................................................................................................176
18.4. Register Summary - WDT........................................................................................................ 180
18.5. Register Description................................................................................................................. 180
19. 16-bit Timer/Counter Type A (TCA)....................................................................... 184
19.1. Features................................................................................................................................... 184
19.2. Overview.................................................................................................................................. 184
19.3. Functional Description..............................................................................................................187
19.4. Sleep Mode Operation............................................................................................................. 196
19.5. Register Summary - TCAn in Normal Mode (SPLITM in TCAn.CTRLD=0)............................. 197
19.6. Register Description - Normal Mode........................................................................................ 198
19.7. Register Summary - TCAn in Split Mode (SPLITM in TCAn.CTRLD=1)..................................218
19.8. Register Description - Split Mode.............................................................................................218
20. 16-bit Timer/Counter Type B (TCB)....................................................................... 234
20.1. Features................................................................................................................................... 234
20.2. Overview.................................................................................................................................. 234
20.3. Functional Description..............................................................................................................235
20.4. Register Summary - TCB......................................................................................................... 243
20.5. Register Description................................................................................................................. 243
21. Real-Time Counter (RTC)......................................................................................255
21.1. Features................................................................................................................................... 255
21.2. Overview.................................................................................................................................. 255
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21.3. Clocks.......................................................................................................................................256
21.4. RTC Functional Description..................................................................................................... 256
21.5. PIT Functional Description....................................................................................................... 257
21.6. Crystal Error Correction............................................................................................................259
21.7. Events...................................................................................................................................... 260
21.8. Interrupts.................................................................................................................................. 260
21.9. Sleep Mode Operation............................................................................................................. 261
21.10. Synchronization........................................................................................................................261
21.11. Register Summary - RTC.........................................................................................................262
21.12. Register Description.................................................................................................................262
22. Universal Synchronous and Asynchronous Receiver and Transmitter (USART).. 280
22.1. Features................................................................................................................................... 280
22.2. Overview.................................................................................................................................. 280
22.3. Functional Description..............................................................................................................283
22.4. Register Summary - USARTn.................................................................................................. 298
22.5. Register Description................................................................................................................. 298
23. Serial Peripheral Interface (SPI)............................................................................317
23.1. Features................................................................................................................................... 317
23.2. Overview.................................................................................................................................. 317
23.3. Functional Description..............................................................................................................319
23.4. Register Summary - SPIn.........................................................................................................327
23.5. Register Description................................................................................................................. 327
24. Two-Wire Interface (TWI)...................................................................................... 334
24.1. Features................................................................................................................................... 334
24.2. Overview.................................................................................................................................. 334
24.3. Functional Description..............................................................................................................335
24.4. Register Summary - TWIn........................................................................................................349
24.5. Register Description................................................................................................................. 349
25. Cyclic Redundancy Check Memory Scan (CRCSCAN)........................................ 370
25.1. Features................................................................................................................................... 370
25.2. Overview.................................................................................................................................. 370
25.3. Functional Description..............................................................................................................371
25.4. Register Summary - CRCSCAN...............................................................................................374
25.5. Register Description................................................................................................................. 374
26. CCL – Configurable Custom Logic........................................................................378
26.1. Features................................................................................................................................... 378
26.2. Overview.................................................................................................................................. 378
26.3. Functional Description..............................................................................................................380
26.4. Register Summary - CCL......................................................................................................... 388
26.5. Register Description................................................................................................................. 388
27. Analog Comparator (AC).......................................................................................399
27.1. Features................................................................................................................................... 399
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27.2. Overview.................................................................................................................................. 399
27.3. Functional Description..............................................................................................................400
27.4. Register Summary - AC........................................................................................................... 403
27.5. Register Description................................................................................................................. 403
28. Analog-to-Digital Converter (ADC)........................................................................ 410
28.1. Features................................................................................................................................... 410
28.2. Overview.................................................................................................................................. 410
28.3. Functional Description..............................................................................................................413
28.4. Register Summary - ADCn.......................................................................................................421
28.5. Register Description................................................................................................................. 421
29. Unified Program and Debug Interface (UPDI).......................................................439
29.1. Features................................................................................................................................... 439
29.2. Overview.................................................................................................................................. 439
29.3. Functional Description..............................................................................................................441
29.4. Register Summary - UPDI........................................................................................................461
29.5. Register Description................................................................................................................. 461
30. Instruction Set Summary....................................................................................... 472
31. Data Sheet Revision History..................................................................................479
The Microchip Web Site.............................................................................................. 480
Customer Change Notification Service........................................................................480
Customer Support....................................................................................................... 480
Product Identification System......................................................................................481
Microchip Devices Code Protection Feature............................................................... 481
Legal Notice.................................................................................................................481
Trademarks................................................................................................................. 482
Quality Management System Certified by DNV...........................................................482
Worldwide Sales and Service......................................................................................483
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1. Block Diagram
I
N
/
O
U
T
D
A
T
A
B
U
S
Clock generation
BUS Matrix
CPU
USARTn
SPIn
TWIn
CCL
ACn
ADCn
TCAn
TCBn
WOn
RXD
TXD
XCK
XDIR
MISO
MOSI
SCK
SS
SDA (master)
SCL (master)
PORTS
EVSYS
System
Management
SLPCTRL
RSTCTRL
CLKCTRL
E
V
E
N
T
R
O
U
T
I
N
G
N
E
T
W
O
R
K
D
A
T
A
B
U
S
UPDI
CRC
SRAM
NVMCTRL
Flash
EEPROM
OSC20M
OSC32K
XOSC32K
Detectors/
references
BOD/
VLM
POR
Bandgap
WDT
RTC
CPUINT
M M
S
M
S
S
OCD
UPDI
RST
TOSC2
TOSC1
S
EXTCLK
LUTn-OUT
WO
CLKOUT
PAn
PBn
PCn
PDn
PEn
PFn
RESET
SDA (slave)
SCL (slave)
GPIOR
AINPn
AINNn
OUT
AINn
EVOUTx
VREFA
LUTn-INn
megaAVR® 0-Series
Block Diagram
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2. megaAVR® 0-series Overview
48KB
32KB
28/32 48
Pins
Flash
ATmega3208
ATmega4808
ATmega3209
ATmega4809
Carrier Type
AT mega 4809 - MFR
Flash size in KB
Series name
Pin count
9=48 pins
8=32 pins (SSOP: 28 pins)
Package Type
A=TQFP
M=QFN
X=SSOP
Temperature Range
F=-40°C to +125°C
R=Tape & Reel
The figure below shows the megaAVR® 0-series devices, laying out pin count variants and memory sizes:
• Vertical migration is possible without code modification, as these devices are fully pin and feature
compatible.
• Horizontal migration to the left reduces the pin count and therefore the available features.
Figure 2-1. megaAVR® 0-series Overview
megaAVR® 0-Series
megaAVR® 0-series Overview
Devices with different Flash memory size typically also have different SRAM and EEPROM.
The name of a device in the megaAVR® 0-series is decoded as follows:
Figure 2-2. megaAVR® Device Designations
2.1 Memory Overview
Table 2-1. Memory Overview
Memory Type ATmega320x ATmega480x
Flash 32 KB 48 KB
SRAM 4 KB 6 KB
© 2018 Microchip Technology Inc.
EEPROM 256B 256B
User row 64B 64B
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2.2 Peripheral Overview
Table 2-2. Peripheral Overview
Property/Peripheral ATmega 08-X ATmega 08-A/M ATmega 09
Pins 28 32 48
Package SSOP VQFN,TQFP UQFN,TQFP
Max. Frequency (MHz) 20 20 20
16-bit Timer/Counter type A (TCA) 1 1 1
16-bit Timer/Counter type B (TCB) 3 3 4
12-bit Timer/Counter type D (TCD) - - -
Real Time Counter (RTC) 1 1 1
USART 3 3 4
SPI 1 1 1
TWI (I2C) 1
(1)
megaAVR® 0-Series
megaAVR® 0-series Overview
(1)
1
(1)
1
ADC (channels) 1 (8) 1 (12) 1 (16)
DAC (outputs) - - -
AC (inputs) 1 (12) 1 (12) 1 (16)
Peripheral Touch Controller (PTC) (self-cap/mutual cap
channels)
Custom Logic (LUTs) 1 (4) 1 (4) 1 (4)
Window Watchdog 1 1 1
Event System channels 6 6 8
General purpose I/O 23 27 41
External interrupts 23 27 41
CRCSCAN 1 1 1
1. TWI can operate as master and slave at the same time on different pins.
- - -
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3. Conventions
3.1 Numerical Notation
Table 3-1. Numerical Notation
Symbol Description
165 Decimal number
0b0101 Binary number (example 0b0101 = 5 decimal)
'0101' Binary numbers are given without prefix if
0x3B24 Hexadecimal number
X Represents an unknown or don't care value
Z Represents a high-impedance (floating) state for
megaAVR® 0-Series
Conventions
unambiguous
either a signal or a bus
3.2 Memory Size and Type
Table 3-2. Memory Size and Bit Rate
Symbol Description
KB kilobyte (210 = 1024)
MB megabyte (220 = 1024*1024)
GB gigabyte (230 = 1024*1024*1024)
b bit (binary '0' or '1')
B byte (8 bits)
1 kbit/s 1,000 bit/s rate (not 1,024 bit/s)
1 Mbit/s 1,000,000 bit/s rate
1 Gbit/s 1,000,000,000 bit/s rate
word 16-bit
3.3 Frequency and Time
Table 3-3. Frequency and Time
Symbol Description
kHz 1 kHz = 103 Hz = 1,000 Hz
KHz 1 KHz = 1,024 Hz, 32 KHz = 32,768 Hz
MHz 1 MHz = 106 Hz = 1,000,000 Hz
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Symbol Description
GHz 1 GHz = 109 Hz = 1,000,000,000 Hz
s second
ms millisecond
µs microsecond
ns nanosecond
3.4 Registers and Bits
Table 3-4. Register and Bit Mnemonics
Symbol Description
R/W Read/Write accessible register bit. The user can read from and write to this bit.
R Read-only accessible register bit. The user can only read this bit. Writes will be
ignored.
megaAVR® 0-Series
Conventions
W Write-only accessible register bit. The user can only write this bit. Reading this bit will
return an undefined value.
BITFIELD Bitfield names are shown in uppercase. Example: INTMODE.
BITFIELD[n:m] A set of bits from bit n down to m. Example: PINA[3:0] = {PINA3, PINA2, PINA1,
PINA0}.
Reserved Reserved bits are unused and reserved for future use. Bitfields in the Register
Summary or Register Description chapters that have gray background are Reserved
bits.
For compatibility with future devices, always write reserved bits to zero when the
register is written. Reserved bits will always return zero when read.
Reserved bit field values must not be written to a bit field. A reserved value won't be
read from a read-only bit field.
PERIPHERALnIf several instances of the peripheral exist, the peripheral name is followed by a single
number to identify one instance. Example: USARTn is the collection of all instances of
the USART module, while USART3 is one specific instance of the USART module.
PERIPHERALx If several instances of the peripheral exist, the peripheral name is followed by a single
capital letter (A-Z) to identify one instance. Example: PORTx is the collection of all
instances of the PORT module, while PORTB is one specific instance of the PORT
module.
Reset Value of a register after a power Reset. This is also the value of registers in a
peripheral after performing a software Reset of the peripheral, except for the Debug
Control registers.
SET/CLR Registers with SET/CLR suffix allows the user to clear and set bits in a register without
doing a read-modify-write operation. These registers always come in pairs. Writing a ‘1’
to a bit in the CLR register will clear the corresponding bit in both registers, while
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Symbol Description
writing a ‘1’ to a bit in the SET register will set the corresponding bit in both registers.
Both registers will return the same value when read. If both registers are written
simultaneously, the write to the CLR register will take precedence.
3.4.1 Addressing Registers from Header Files
In order to address registers in the supplied C header files, the following rules apply:
1. A register is identified by <peripheral_instance_name>.<register_name>, e.g. CPU.SREG,
USART2.CTRLA, or PORTB.DIR.
2. The peripheral name is written in the peripheral's register summary heading, e.g. "Register
Summary - ACn", where "ACn" is the peripheral name.
3. <peripheral_instance_name> is obtained by substituting any n or x in the peripheral name with the
correct instance identifier.
megaAVR® 0-Series
Conventions
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4. Acronyms and Abbreviations
The table below contains acronyms and abbreviations used in this document.
Table 4-1. Acronyms and Abbreviations
Abbreviation Description
AC Analog Comparator
ACK Acknowledge
ADC Analog-to-Digital Converter
ADDR Address
AES Advanced Encryption Standard
ALU Arithmetic Logic Unit
AREF Analog reference voltage, also VREFA
BLB Boot Lock Bit
megaAVR® 0-Series
Acronyms and Abbreviations
BOD Brown-out Detector
CAL Calibration
CCMP Compare/Capture
CCL Configurable Custom Logic
CCP Configuration Change Protection
CLK Clock
CLKCTRL Clock Controller
CRC Cyclic Redundancy Check
CTRL Control
DAC Digital-to-Analog Converter
DFLL Digital Frequency Locked Loop
DMAC DMA (Direct Memory Access) Controller
DNL Differential Nonlinearity (ADC characteristics)
EEPROM Electrically Erasable Programmable Read-Only Memory
EVSYS Event System
GND Ground
GPIO General Purpose Input/Output
I2C Inter-Integrated Circuit
IF Interrupt flag
INL Integral Nonlinearity (ADC characteristics)
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Abbreviation Description
INT Interrupt
IrDA Infrared Data Association
IVEC Interrupt Vector
LSB Least Significant Byte
LSb Least Significant bit
LUT Look Up Table
MBIST Memory Built-in Self-test
MSB Most Significant Byte
MSb Most Significant bit
NACK Not Acknowledge
NMI Non-maskable interrupt
NVM Nonvolatile Memory
megaAVR® 0-Series
Acronyms and Abbreviations
NVMCTRL Nonvolatile Memory Controller
OPAMP Operation Amplifier
OSC Oscillator
PC Program Counter
PER Period
POR Power-on Reset
PORT I/O Pin Configuration
PTC Peripheral Touch Controller
PWM Pulse-width Modulation
RAM Random Access Memory
REF Reference
REQ Request
RISC Reduced Instruction Set Computer
RSTCTRL Reset Controller
RTC Real-time Counter
RX Receiver/Receive
SERCOM Serial Communication Interface
SLPCTRL Sleep Controller
SMBus System Management Bus
SP Stack Pointer
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megaAVR® 0-Series
Acronyms and Abbreviations
Abbreviation Description
SPI Serial Peripheral Interface
SRAM Static Random Access Memory
SYSCFG System Configuration
TC Timer/Counter (Optionally superseded by a letter indicating type of TC)
TRNG True Random Number Generator
TWI Two-wire Interface
TX Transmitter/Transmit
ULP Ultra Low Power
UPDI Unified Program and Debug Interface
USART Universal Synchronous and Asynchronous Serial Receiver and Transmitter
USB Universal Serial Bus
V
DD
Voltage to be applied to V
VREF Voltage Reference
V
CM
Voltage Common mode
WDT Watchdog Timer
XOSC Crystal Oscillator
DD
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5. Memories
5.1 Overview
The main memories are SRAM data memory, EEPROM data memory, and Flash program memory. In
addition, the peripheral registers are located in the I/O memory space.
5.2 Memory Map
The figure below shows the memory map for the biggest memory derivative in the series. Refer to the
subsequent subsections for details on memory sizes and start addresses for devices with smaller
memory sizes.
megaAVR® 0-Series
Memories
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megaAVR® 0-Series
Figure 5-1. Memory Map: Flash 48 KB, Internal SRAM 6 KB, EEPROM 256B
Memories
0x0000
Code space
Flash code
48KB
Data space
64 I/O Registers
960 Ext I/O Registers
NVM I/O Registers and
data
EEPROM 256B
(Reserved)
Internal SRAM
6KB
0x0000 – 0x003F
0x0040 – 0x0FFF
0x1000 – 0x13FF
0x1400
0x1500
0x2800
0x3FFF
0x4000
Flash code
48KB
5.3 In-System Reprogrammable Flash Program Memory
The ATmega3208/3209/4808/4809 contains up to 48 KB On-Chip In-System Reprogrammable Flash
memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized
with 16-bit data width. For write protection, the Flash Program memory space can be divided into three
sections: Boot Loader section, Application code section, and Application data section. Code placed in one
section may be restricted from writing to addresses in other sections, see the NVMCTRL documentation
for more details.
0xFFFF
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megaAVR® 0-Series
Memories
The program counter is able to address the whole program memory. The procedure for writing Flash
memory is described in detail in the documentation of the Non-Volatile Memory Controller (NVMCTRL)
peripheral.
The Flash memory is mapped into the data space and is accessible with normal LD/ST instructions. For
LD/ST instructions, the Flash is mapped from address 0x4000. The Flash memory can be read with the
LPM instruction. For the LPM instruction, the Flash start address is 0x0000.
The ATmega3208/3209/4808/4809 has a CRC module that is a master on the bus.
Table 5-1. Physical Properties of Flash Memory
Property ATmega320x ATmega480x
Size 32 KB 48 KB
Page size 128 B 128 B
Number of pages 256 384
Start address in Data Space 0x4000 0x4000
Start address in Code Space 0x0 0x0
5.4 SRAM Data Memory
The primary task of the SRAM memory is to store application data. It is not possible to execute code from
SRAM.
Table 5-2. Physical Properties of SRAM
Property ATmega320x ATmega480x
Size 4 KB 6 KB
Start address 0x3000 0x2800
5.5 EEPROM Data Memory
The primary task of the EEPROM memory is to store nonvolatile application data. The EEPROM memory
supports single byte read and write. The EEPROM is controlled by the Non-Volatile Memory Controller
(NVMCTRL).
Table 5-3. Physical Properties of EEPROM
Property ATmega320x ATmega480x
Size 256B 256B
Page size 64B 64B
Number of pages 4 4
Start address 0x1400 0x1400
5.6 User Row (USERROW)
In addition to the EEPROM, the ATmega3208/3209/4808/4809 has one extra page of EEPROM memory
that can be used for firmware settings, the User Row (USERROW). This memory supports single byte
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Datasheet Preliminary
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read and write as the normal EEPROM. The CPU can write and read this memory as normal EEPROM
and the UPDI can write and read it as a normal EEPROM memory if the part is unlocked. The User Row
can also be written by the UPDI when the part is locked. USERROW is not affected by a chip erase. The
USERROW can be used for final configuration without having programming or debugging capabilities
enabled.
5.7 Signature Row (SIGROW)
The content of the Signature Row fuses (SIGROW) is pre-programmed and cannot be altered. SIGROW
holds information such as device ID, serial number, and calibration values.
All AVR microcontrollers have a three-byte device ID which identifies the device. This device ID can be
read in both serial and parallel mode, also when the device is locked. The three bytes reside in the
Signature Row. The signature bytes are given in the following table.
Table 5-4. Device ID
Device Name Signature Bytes Address
ATmega4809 0x1E 0x96 0x51
megaAVR® 0-Series
Memories
0x00 0x01 0x02
ATmega4808 0x1E 0x96 0x50
ATmega3209 0x1E 0x95 0x31
ATmega3208 0x1E 0x95 0x30
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Datasheet Preliminary
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megaAVR® 0-Series
Memories
5.7.1 Signature Row Summary - SIGROW
Offset Name Bit Pos.
0x00 DEVICEID0 7:0 DEVICEID[7:0]
0x01 DEVICEID1 7:0 DEVICEID[7:0]
0x02 DEVICEID2 7:0 DEVICEID[7:0]
0x03 SERNUM0 7:0 SERNUM[7:0]
0x04 SERNUM1 7:0 SERNUM[7:0]
0x05 SERNUM2 7:0 SERNUM[7:0]
0x06 SERNUM3 7:0 SERNUM[7:0]
0x07 SERNUM4 7:0 SERNUM[7:0]
0x08 SERNUM5 7:0 SERNUM[7:0]
0x09 SERNUM6 7:0 SERNUM[7:0]
0x0A SERNUM7 7:0 SERNUM[7:0]
0x0B SERNUM8 7:0 SERNUM[7:0]
0x0C SERNUM9 7:0 SERNUM[7:0]
0x0D
...
0x1F
0x20 TEMPSENSE0 7:0 TEMPSENSE[7:0]
0x21 TEMPSENSE1 7:0 TEMPSENSE[7:0]
0x22 OSC16ERR3V 7:0 OSC16ERR3V[7:0]
0x23 OSC16ERR5V 7:0 OSC16ERR5V[7:0]
0x24 OSC20ERR3V 7:0 OSC20ERR3V[7:0]
0x25 OSC20ERR5V 7:0 OSC20ERR5V[7:0]
Reserved
5.7.2 Signature Row Description
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Datasheet Preliminary
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megaAVR® 0-Series
Memories
5.7.2.1 Device ID n
Name: DEVICEIDn
Offset: 0x00 + n*0x01 [n=0..2]
Reset: [Device ID]
Property: -
Each device has a device ID identifying the device and its properties; such as memory sizes, pin count,
and die revision. This can be used to identify a device and hence, the available features by software. The
Device ID consists of three bytes: SIGROW.DEVICEID[2:0].
Bit 7 6 5 4 3 2 1 0
Access
Reset x x x x x x x x
R R R R R R R R
Bits 7:0 – DEVICEID[7:0] Byte n of the Device ID
DEVICEID[7:0]
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Datasheet Preliminary
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megaAVR® 0-Series
Memories
5.7.2.2 Serial Number Byte n
Name: SERNUMn
Offset: 0x03 + n*0x01 [n=0..9]
Reset: [device serial number]
Property: -
Each device has an individual serial number, representing a unique ID. This can be used to identify a
specific device in the field. The serial number consists of ten bytes: SIGROW.SERNUM[9:0].
Bit 7 6 5 4 3 2 1 0
Access
Reset x x x x x x x x
R R R R R R R R
Bits 7:0 – SERNUM[7:0] Serial Number Byte n
SERNUM[7:0]
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Datasheet Preliminary
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megaAVR® 0-Series
Memories
5.7.2.3 Temperature Sensor Calibration n
Name: TEMPSENSEn
Offset: 0x20 + n*0x01 [n=0..1]
Reset: [Temperature sensor calibration value]
Property: -
These registers contain correction factors for temperature measurements by the ADC.
SIGROW.TEMPSENSE0 is a correction factor for the gain/slope (unsigned), SIGROW.TEMPSENSE1 is
a correction factor for the offset (signed).
Bit 7 6 5 4 3 2 1 0
Access
Reset x x x x x x x x
R R R R R R R R
Bits 7:0 – TEMPSENSE[7:0] Temperature Sensor Calibration Byte n
Refer to the ADC chapter for a description on how to use this register.
TEMPSENSE[7:0]
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Datasheet Preliminary
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megaAVR® 0-Series
Memories
5.7.2.4 OSC16 Error at 3V
Name: OSC16ERR3V
Offset: 0x22
Reset: [Oscillator frequency error value]
Property: -
Bit 7 6 5 4 3 2 1 0
Access
Reset x x x x x x x x
R R R R R R R R
Bits 7:0 – OSC16ERR3V[7:0] OSC16 Error at 3V
These registers contain the signed oscillator frequency error value when running at internal 16 MHz at 3V,
as measured during production.
OSC16ERR3V[7:0]
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Datasheet Preliminary
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megaAVR® 0-Series
Memories
5.7.2.5 OSC16 Error at 5V
Name: OSC16ERR5V
Offset: 0x23
Reset: [Oscillator frequency error value]
Property: -
Bit 7 6 5 4 3 2 1 0
Access
Reset x x x x x x x x
R R R R R R R R
Bits 7:0 – OSC16ERR5V[7:0] OSC16 Error at 5V
These registers contain the signed oscillator frequency error value when running at internal 16 MHz at 5V,
as measured during production.
OSC16ERR5V[7:0]
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Datasheet Preliminary
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megaAVR® 0-Series
Memories
5.7.2.6 OSC20 Error at 3V
Name: OSC20ERR3V
Offset: 0x24
Reset: [Oscillator frequency error value]
Property: -
Bit 7 6 5 4 3 2 1 0
Access
Reset x x x x x x x x
R R R R R R R R
Bits 7:0 – OSC20ERR3V[7:0] OSC20 Error at 3V
These registers contain the signed oscillator frequency error value when running at internal 20 MHz at 3V,
as measured during production.
OSC20ERR3V[7:0]
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Datasheet Preliminary
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megaAVR® 0-Series
Memories
5.7.2.7 OSC20 Error at 5V
Name: OSC20ERR5V
Offset: 0x25
Reset: [Oscillator frequency error value]
Property: -
Bit 7 6 5 4 3 2 1 0
Access
Reset x x x x x x x x
R R R R R R R R
Bits 7:0 – OSC20ERR5V[7:0] OSC20 Error at 5V
These registers contain the signed oscillator frequency error value when running at internal 20 MHz at 5V,
as measured during production.
5.8 Fuses (FUSE)
Fuses are part of the nonvolatile memory and hold factory calibration data and device configuration. The
fuses are available from device power-up. The fuses can be read by the CPU or the UPDI, but can only
be programmed or cleared by the UPDI. The configuration and calibration values stored in the fuses are
written to their respective target registers at the end of the start-up sequence.
OSC20ERR5V[7:0]
The fuses are pre-programmed but can be altered by the user. Altered values in the configuration fuse
will be effective only after a Reset.
Note: When writing the fuses write all reserved bits to ‘1’.
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Datasheet Preliminary
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megaAVR® 0-Series
Memories
5.8.1 Fuse Summary - FUSE
Offset Name Bit Pos.
0x00 WDTCFG 7:0 WINDOW[3:0] PERIOD[3:0]
0x01 BODCFG 7:0 LVL[2:0] SAMPFREQ ACTIVE[1:0] SLEEP[1:0]
0x02 OSCCFG 7:0 OSCLOCK FREQSEL[1:0]
0x03
...
0x04
0x05 SYSCFG0 7:0 CRCSRC[1:0] RSTPINCFG EESAVE
0x06 SYSCFG1 7:0 SUT[2:0]
0x07 APPEND 7:0 APPEND[7:0]
0x08 BOOTEND 7:0 BOOTEND[7:0]
0x09 Reserved
0x0A LOCKBIT 7:0 LOCKBIT[7:0]
5.8.2 Fuse Description
Reserved
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Datasheet Preliminary
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megaAVR® 0-Series
Memories
5.8.2.1 Watchdog Configuration
Name: WDTCFG
Offset: 0x00
Reset: Property: -
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0 0 0 0 0 0 0
R R R R R R R R
Bits 7:4 – WINDOW[3:0] Watchdog Window Time-out Period
This value is loaded into the WINDOW bit field of the Watchdog Control A register (WDT.CTRLA) during
Reset.
Bits 3:0 – PERIOD[3:0] Watchdog Time-out Period
This value is loaded into the PERIOD bit field of the Watchdog Control A register (WDT.CTRLA) during
Reset.
WINDOW[3:0] PERIOD[3:0]
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Datasheet Preliminary
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