Microchip USB7252 User Manual
USB7252
4-Port USB 3.2 Gen 2 Type-C® Controller Hub
Highlights
• 4-Port USB Smart Hub with:
- USB Gen 2 Type-B® on upstream port
- Native USB Gen 2 Type-C with Power Delivery PD
support on downstream ports 1 and 2
- One Standard USB 3.2 Gen 2 downstream port
- One Standard USB 2.0 downstream port
®
- Internal Hub Feature Controller enables:
- USB to I2C/SPI/UART/I2S/GPIO bridge endpointsupport
- USB to internal hub register write and read
• USB Link Power Management (LPM) support
• Programming of firmware image to external SPI
memory device from USB host
• USB-IF Battery Charger revision 1.2 support on
downstream ports (DCP, CDP, SDP)
• Enhanced OEM configuration options available
through either OTP or external SPI memory
• Available in 100-pin (12mm x 12mm) VQFN
RoHS compliant package
• Commercial and industrial grade temperature
support
Target Applications
• Standalone USB Hubs
• Laptop Docks
• PC Motherboards
• PC Monitor Docks
• Multi-function USB 3.2 Gen 2 Peripherals
Key Benefits
• USB 3.2 Gen 2 compliant 10 Gbps, 5 Gbps,
480 Mbps, 12 Mbps, and 1.5Mbps operation
- 5V tolerant USB 2.0 pins
- 1.21V tolerant USB 3.2 Gen 2 pins
- Integrated termination and pull-up/down resistors
• Native USB Type-C Support
- Type-C CC Pin with integrated Rp and Rd resistors
- Integrated multiplexer on USB Type-C enabled
ports. USB 3.2 Gen 2 PHYs are disabled until a
valid Type-C attach is detected, saving idle power.
Control for external VCONN supply
* USB Type-C® and USB-C® are registered trademarks of USB Implementers Forum
• Supports battery charging of most popular battery
powered devices on all ports
- USB-IF Battery Charging rev. 1.2 support
(DCP, CDP, SDP)
®
- Apple
- Chinese YD/T 1591-2006/2009 charger emulation
- European Union universal mobile charger support
- Supports additional portable devices
portable product charger emulation
• On-chip Microcontroller
- manages I/Os, VBUS, and other signals
• 96kB RAM, 256kB ROM
• 8kB One-Time-Programmable (OTP) ROM
- Includes on-chip charge pump
• Configuration programming via OTP Memory, SPI
external memory, or SMBus
• FlexConnect
- The roles of the upstream and all downstream
ports are reversible on command
• Multi-Host Endpoint Reflector
- Integrated host-controller endpoint reflector via
CDC/NCM device class for automotive applications
• USB Bridging
- USB to I2C, SPI, UART, I2S, and GPIO
• PortSwap
- Configurable USB 2.0 differential pair signal swap
• PHYBoost
- Programmable USB transceiver drive strength for
recovering signal integrity
• VariSense
- Programmable USB receive sensitivity
• PortSplit
- USB 2.0 and USB 3.2 Gen 2 port operation can be
split for custom applications using embedded USB
3.x devices in parallel with USB 2.0 devices
• Compatible with Microsoft Windows 10, 8, 7, XP,
Apple OS X 10.4+, and Linux hub drivers
• Optimized for low-power operation and low thermal dissipation
• 100-pin VQFN package (12mm x 12mm)
2018 - 2020 Microchip Technology Inc. DS00002736D-page 1
USB7252
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of
your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications
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Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner
of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using.
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DS00002736D-page 2 2018 - 2020 Microchip Technology Inc.
USB7252
1.0 PREFACE
1.1 General Terms
TABLE 1-1: GENERAL TERMS
Term Description
ADC Analog-to-Digital Converter
Byte 8 bits
CDC Communication Device Class
CSR Control and Status Registers
DFP Downstream Facing Port
DWORD 32 bits
EOP End of Packet
EP Endpoint
FIFO First In First Out buffer
FS Full-Speed
FSM Finite State Machine
GPIO General Purpose I/O
HS Hi-Speed
HSOS High Speed Over Sampling
Hub Feature Controller The Hub Feature Controller, sometimes called a Hub Controller for short is the internal
processor used to enable the unique features of the USB Controller Hub. This is not to
be confused with the USB Hub Controller that is used to communicate the hub status
back to the Host during a USB session.
2
C Inter-Integrated Circuit
I
LS Low-Speed
lsb Least Significant Bit
LSB Least Significant Byte
msb Most Significant Bit
MSB Most Significant Byte
N/A Not Applicable
NC No Connect
OTP One Time Programmable
PCB Printed Circuit Board
PCS Physical Coding Sublayer
PHY Physical Layer
PLL Phase Lock Loop
RESERVED Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must
always be zero for write operations. Unless otherwise noted, values are not guaranteed when reading reserved bits. Unless otherwise noted, do not read or write to
reserved addresses.
SDK Software Development Kit
SMBus System Management Bus
UFP Upstream Facing Port
UUID Universally Unique IDentifier
WORD 16 bits
2018 - 2020 Microchip Technology Inc. DS00002736D-page 3
USB7252
1.2 Buffer Types
TABLE 1-2: BUFFER TYPES
Buffer Type Description
I Input.
IS Input with Schmitt trigger.
O12 Output buffer with 12 mA sink and 12 mA source.
OD12 Open-drain output with 12 mA sink
PU 50 μA (typical) internal pull-up. Unless otherwise noted in the pin description, internal pull-
PD 50 μA (typical) internal pull-down. Unless otherwise noted in the pin description, internal
ICLK Crystal oscillator input pin
OCLK Crystal oscillator output pin
I/O-U Analog input/output defined in USB specification.
I-R RBIAS.
A Analog.
AIO Analog bidirectional.
P Power pin.
ups are always enabled.
Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on internal
resistors to drive signals external to the device. When connected to a load that must be
pulled high, an external resistor must be added.
pull-downs are always enabled.
Internal pull-down resistors prevent unconnected inputs from floating. Do not rely on
internal resistors to drive signals external to the device. When connected to a load that
must be pulled low, an external resistor must be added.
DS00002736D-page 4 2018 - 2020 Microchip Technology Inc.
USB7252
1.3 Pin Reset States
The pin reset state definitions are detailed in Table 1-3. Refer to Section 3.1, Pin Assignments for details on individual
pin reset states.
TABLE 1-3: PIN RESET STATE LEGEND
Symbol Description
AI Analog input
AIO Analog input/output
AO Analog output
PD Hardware enables pull-down
PU Hardware enables pull-up
Y Hardware enables function
Z Hardware disables output driver (high impedance)
PU Hardware enables internal pull-up
PD Hardware enables internal pull-down
1.4 Reference Documents
1. Universal Serial Bus Revision 3.2 Specification, http://www.usb.org
2. Battery Charging Specification, Revision 1.2, Dec. 07, 2010, http://www.usb.org
2
3. I
C-Bus Specification, Version 1.1, http://www.nxp.com/documents/user_manual/UM10204.pdf
2
4. I
S-Bus Specification, http://www.sparkfun.com/datasheets/BreakoutBoards/I2SBUS.pdf
5. System Management Bus Specification, Version 1.0, http://smbus.org/specs
Note: Additional USB7252 resources can be found on the Microchip USB7252 product page at www.micro-
chip.com/USB7252.
2018 - 2020 Microchip Technology Inc. DS00002736D-page 5
USB7252
2.0 INTRODUCTION
2.1 General Description
The Microchip USB7252 hub is a low-power, OEM configurable, USB 3.2 Gen 2 hub controller with 4 downstream ports
and advanced features for embedded USB applications. The USB7252 is fully compliant with the Universal Serial Bus
Revision 3.2 Specification and USB 2.0 Link Power Management Addendum. The USB7252 supports 10 Gbps SuperSpeed+ (SS+), 5 Gbps SuperSpeed (SS), 480 Mbps Hi-Speed (HS), 12 Mbps Full-Speed (FS), and 1.5 Mbps LowSpeed (LS) USB downstream devices on three standard USB 3.2 Gen 2 downstream ports and only legacy speeds (HS/
FS/LS) on one standard USB 2.0 downstream port.
The USB7252 is a standard USB 3.2 Gen 2 hub that supports native basic Type-C with integrated CC logic on two downstream ports. The downstream Type-C ports include internal USB 3.2 Gen 2 multiplexers; no external multiplexer is
required for Type-C support.
The USB7252 supports the legacy USB speeds (HS/FS/LS) through a dedicated USB 2.0 hub controller that is the culmination of seven generations of Microchip hub feature controller design and experience with proven reliability, interoperability, and device compatibility. The SuperSpeed hub controller operates in parallel with the USB 2.0 controller,
decoupling the 10/5 Gbps SS+/SS data transfers from bottlenecks due to the slower USB 2.0 traffic.
The USB7252 enables OEMs to configure their system using “Configuration Straps.” These straps simplify the configuration process assigning default values to USB 3.2 Gen 2 ports and GPIOs. OEMs can disable ports, enable battery
charging and define GPIO functions as default assignments on power up removing the need for OTP or external SPI
ROM.
The USB7252 supports downstream battery charging. The USB7252 integrated battery charger detection circuitry supports the USB-IF Battery Charging (BC1.2) detection method and most Apple devices. The USB7252 provides the battery charging handshake and supports the following USB-IF BC1.2 charging profiles:
• DCP: Dedicated Charging Port (Power brick with no data)
• CDP: Charging Downstream Port (1.5A with data)
• SDP: Standard Downstream Port (0.5A[USB 2.0]/0.9A[USB 3.2] with data)
Additionally, the USB7252 includes many powerful and unique features such as:
The Hub Feature Controller, an internal USB device dedicated for use as a USB to I
allows external circuits or devices to be monitored, controlled, or configured via the USB interface.
Multi-Host Endpoint Reflector, which provides unique USB functionality whereby USB data can be “mirrored” between
two USB hosts (Multi-Host) in order to perform a single USB transaction.This capability is fully covered by Microchip
intellectual property (U.S. Pat. Nos. 7,523,243 and 7,627,708) and is instrumental in enabling Apple CarPlay
the Apple iPhone
FlexConnect, which provides flexible connectivity options. One of the USB7252’s downstream ports can be reconfigured to become the upstream port, allowing master capable devices to control other devices on the hub.
PortSwap, which adds per-port programmability to USB differential-pair pin locations. PortSwap allows direct alignment
of USB signals (D+/D-) to connectors to avoid uneven trace length or crossing of the USB differential signals on the
PCB.
PHYBoost, which provides programmable levels of Hi-Speed USB signal drive strength
in the downstream port transceivers. PHYBoost attempts to restore USB signal integrity
in a compromised system environment. The graphic on the right shows an example of
Hi-Speed USB eye diagrams before and after PHYBoost signal integrity restoration. in
a compromised system environment.
VariSense, which controls the Hi-Speed USB receiver sensitivity enabling programmable levels of USB signal receive
sensitivity. This capability allows operation in a sub-optimal system environment, such as when a captive USB cable is
used.
Port Split, which allows for the USB 3.2 Gen 2 and USB 2.0 portions of downstream port 3 to operate independently
and enumerate two separate devices in parallel in special applications.
®
becomes a USB Host.
2
C/UART/SPI/GPIO interface that
™
, where
DS00002736D-page 6 2018 - 2020 Microchip Technology Inc.
USB7252
Hub Controller Logic
I2C/SPI
25 Mhz
USB3 USB2
P4
A
PHY0
+3.3 V
VCORE
P3
A
PHY5 PHY2PHY5PHY1
PHY2
B
PHY1
A
PHY3
PHY4
B
PHY3
A
PHY0
P2
C
P1
C
CC
CC
Hub Feature Controller
GPIO SMB
OTP
SPI I2S
UART
Mux
HFC
PHY
I2C from Master
P0
B
The USB7252 can be configured for operation through internal default settings. Custom OEM configurations are supported through external SPI ROM or OTP ROM. All port control signal pins are under firmware control in order to allow
for maximum operational flexibility and are available as GPIOs for customer specific use.
The USB7252 is available in commercial (0°C to +70°C) and industrial (-40°C to +85°C) temperature ranges. An internal block diagram of the USB7252 in an upstream Type-C application is shown in Figure 2-1.
FIGURE 2-1: USB7252 INTERNAL BLOCK DIAGRAM - UPSTREAM TYPE-B APPLICATION
Note: All port numbering in this document is LOGICAL port numbering with the device in the default configuration.
LOGICAL port numbering is the numbering as communicated to the USB host. It is the end result after any
port number remapping or port disabling. The PHYSICAL port number is the port number with respect to
the physical PHY on the chip. PHYSICAL port numbering is fixed and the settings are not impacted by
LOGICAL port renumbering/remapping. Certain port settings are made with respect to LOGICAL port numbering, and other port settings are made with respect to PHYSICAL port numbering. Refer to the “Configuration of USB7202/USB7206/USB725x” application note for details on the LOGICAL vs. PHYSICAL
mapping and additional configuration details.
2018 - 2020 Microchip Technology Inc. DS00002736D-page 7
USB7252
Thermal slug connects to VSS
1009998979695949392
9089888786
85
91
16
15
14
13
12
11
10
9
8
6
5
4
3
2
1
7
41
40
39
37
36
35
34
33
32
31
30
29
28
27
26
75
74
73
72
71
70
68
67
66
65
69
64
63
62
61
60
38
25
24
23
22
21
20
19
18
17
50
49
48
46
45
44
43
42
47
59
58
57
56
55
54
53
52
51
84
83
8180797877
76
82
Microchip
USB7252
(Top Vi ew 100-VQFN)
RESET_N
DP1_VBUS_MON
PF31
DP1_CC1
USB3DN_RXDM1A
USB3DN_RXDP1A
VCORE
USB3DN_TXDM1A
USB3DN_TXDP1A
USB2DN_DM1/PRT_DIS_M1
PF30
USB3DN_RXDM1B
USB2DN_DP1/PRT_DIS_P1
USB3DN_RXDP1B
VCORE
USB3DN_TXDM1B
USB3DN_TXDP1B
USB2DN_DM4/PRT_DIS_M4
USB2DN_DP4/PRT_DIS_P4
DP1_CC2
CFG_STRAP1
CFG_STRAP2
CFG_STRAP3
TESTEN
VCORE
DP2_CC1
DP2_VBUS_MON
USB3DN_RXDM2A
USB3DN_TXDM2B
USB3DN_TXDP2B
DP2_CC2
USB3DN_RXDP2A
VCORE
USB3DN_TXDP2A
USB2DN_DM2/PRT_D IS_M2
USB2DN_DP2/PRT_DIS_P2
VDD33
USB3DN_TXDM2A
PF9
VCORE
USB3DN_RXDM2B
USB3DN_RXDP2B
PF3
PF2
PF5
PF4
PF6
PF8
PF7
VDD33
PF17
SPI_D3/PF25
SPI_D0/CFG_BC_EN/PF22
SPI_ CLK/ PF21
VDD33
SPI_D1/PF23
PF19
PF26
TEST3
SPI_CE_N/CFG_NON_REM/PF20
TEST1
PF10
PF13
VDD33
TEST2
SPI_D2/PF24
PF18
PF15
PF16
VDD33
VCORE
PF12
PF29
PF11
PF14
PF27
PF28
VCORE
VCORE
USB3DN_TXDM3
USB3DN_TXDP3
USB2DN_DM3/PRT_D IS_M3
USB2DN_DP3/PRT_DIS_P3
VBUS_MON_UP
VDD33
USB3UP_TXDM
USB3UP_TXDP
USB2UP_DM
USB2UP_DP
VDD33
USB3DN_RXDM3
USB3DN_RXDP3
RBIAS
VDD33
XTALI/C LK_IN
XTALO
ATEST
USB3UP_RXDM
USB3UP_RXDP
VCORE
3.0 PIN DESCRIPTIONS
3.1 Pin Assignments
FIGURE 3-1: USB7252 100-VQFN PIN ASSIGNMENTS
Note: Configuration straps are identified by an underlined symbol name. Signals that function as configuration
straps must be augmented with an external resistor when connected to a load.
DS00002736D-page 8 2018 - 2020 Microchip Technology Inc.
USB7252
Pin Num Pin Name Reset Pin Num Pin Name Reset
1 RESET_N Z 51 PF10 PD
2 PF30 Z 52 PF11 PD
3 PF31 Z 53 VDD33 Z
4 DP1_VBUS_MON AI 54 PF12 PD
5 USB2DN_DP1/PRT_DIS_P1 AIO PD 55 VCORE Z
6 USB2DN_DM1/PRT_DIS_M1 AIO PD 56 PF13 PD
7 USB3DN_TXDP1A AO PD 57 PF14 PD
8 USB3DN_TXDM1A AO PD 58 PF15 PD
9 VCORE Z 59 PF16 PD
10 USB3DN_RXDP1A AI PD 60 PF17 PD
11 USB3DN_RXDM1A AI PD 61 PF18 Z
12 DP1_CC1 AI 62 VDD33 Z
13 DP1_CC2 AI 63 TEST1 Z
14 USB2DN_DP4/PRT_DIS_P4 AIO PD 64 TEST2 Z
15 USB2DN_DM4/PRT_DIS_M4 AIO PD 65 TEST3 Z
16 USB3DN_TXDP1B AO PD 66 PF19 Z
17 USB3DN_TXDM1B AO PD 67 VDD33 Z
18 VCORE Z 68 SPI_CLK/PF21 Z
19 USB3DN_RXDP1B AI PD 69 SPI_CE_N/CFG_NON_REM/PF20 PU
20 USB3DN_RXDM1B AI PD 70 SPI_D0/CFG_BC_EN/PF22 Z
21 CFG_STRAP1 Z 71 SPI_D1/PF23 Z
22 CFG_STRAP2 Z 72 SPI_D2/PF24 Z
23 CFG_STRAP3 Z 73 SPI_D3/PF25 Z
24 TESTEN Z 74 PF29 Z
25 VCORE Z 75 PF26 Z
26 VDD33 Z 76 PF27 Z
27 DP2_CC1 AI 77 PF28 Z
28 DP2_CC2 AI 78 VCORE Z
29 USB2DN_DP2/PRT_DIS_P2 AIO PD 79 VDD33 Z
30 USB2DN_DM2/PRT_DIS_M2 AIO PD 80 VBUS_MON_UP AI
31 USB3DN_TXDP2A AO PD 81 USB2DN_DP3/PRT_DIS_P3 AIO PD
32 USB3DN_TXDM2A AO PD 82 USB2DN_DM3/PRT_DIS_M3 AIO PD
33 VCORE Z 83 USB3DN_TXDP3 AO PD
34 USB3DN_RXDP2A AI PD 84 USB3DN_TXDM3 AO PD
35 USB3DN_RXDM2A AI PD 85 VCORE Z
36 DP2_VBUS_MON AI 86 USB3DN_RXDP3 AI PD
37 USB3DN_TXDP2B AO PD 87 USB3DN_RXDM3 AI PD
38 USB3DN_TXDM2B AO PD 88 VDD33 Z
39 VCORE Z 89 USB2UP_DP AIO Z
40 USB3DN_RXDP2B AI PD 90 USB2UP_DM AIO Z
41 USB3DN_RXDM2B AI PD 91 USB3UP_TXDP AO PD
42 VDD33 Z 92 USB3UP_TXDM AO PD
43 PF2 Z 93 VCORE Z
44 PF3 Z 94 USB3UP_RXDP AI PD
45 PF4 Z 95 USB3UP_RXDM AI PD
46 PF5 Z 96 ATEST AO
47 PF6 Z 97 XTALO AO
48 PF7 Z 98 XTALI/CLK_IN AI
49 PF8 Z 99 VDD33 Z
50 PF9 Z 100 RBIAS AI
Exposed Pad (VSS) must be connected to ground.
2018 - 2020 Microchip Technology Inc. DS00002736D-page 9
USB7252
3.2 Pin Descriptions
This section contains descriptions of the various USB7252 pins. The “_N” symbol in the signal name indicates that the
active, or asserted, state occurs when the signal is at a low voltage level. For example, RESET_N indicates that the
reset signal is active low. When “_N” is not present after the signal name, the signal is asserted when at the high voltage
level.
The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of
“active low” and “active high” signal. The term assert, or assertion, indicates that a signal is active, independent of
whether that level is represented by a high or low voltage. The term negate, or negation, indicates that a signal is inactive.
The “If Unused” column provides information on how to terminate pins if they are unused in a customer design.
Buffer type definitions are detailed in Section 1.2, Buffer Types.
TABLE 3-1: PIN DESCRIPTIONS
Name Symbol
Upstream USB
3.2 Gen 2 TX D+
Upstream USB
3.2 Gen 2 TX D-
Upstream USB
3.2 Gen 2 RX D+
Upstream USB
3.2 Gen 2 RX D-
Downstream
Port 1 USB 3.2
Gen 2 TX D+
Orientation A
Downstream
Port 1 USB 3.2
Gen 2 TX D- Ori-
entation A
USB3DN_TXDP1A I/O-U Downstream USB Type-C
USB3DN_TXDM1A I/O-U Downstream USB Type-C “Orientation A”
Buffer
Type
USB 3.2 Gen 2 Interfaces
USB3UP_TXDP I/O-U Upstream USB 3.2 Gen 2 Transmit Data
Plus.
USB3UP_TXDM I/O-U Upstream USB 3.2 Gen 2 Transmit Data
Minus.
USB3UP_RXDP I/O-U Upstream USB 3.2 Gen 2 Receive Data
Plus.
USB3UP_RXDM I/O-U Upstream USB 3.2 Gen 2 Receive Data
Minus.
SuperSpeed+ Transmit Data Plus, port 1.
SuperSpeed+ Transmit Data Minus, port 1.
Description If Unused
®
“Orientation A”
Float
Float
Weak pulldown to
GND
Weak pulldown to
GND
Float
Float
Downstream
Port 1 USB 3.2
Gen 2 RX D+
Orientation A
Downstream
Port 1 USB 3.2
Gen 2 RX DOrientation A
Downstream
Port 1 USB 3.2
Gen 2 TX D+
Orientation B
DS00002736D-page 10 2018 - 2020 Microchip Technology Inc.
USB3DN_RXDP1A I/O-U Downstream USB Type-C “Orientation A”
SuperSpeed+ Receive Data Plus, port 1.
USB3DN_RXDM1A I/O-U Downstream USB Type-C “Orientation A”
SuperSpeed+ Receive Data Minus, port 1.
USB3DN_TXDP1B I/O-U Downstream USB Type-C “Orientation B”
SuperSpeed+ Transmit Data Plus, port 1.
Weak pulldown to
GND
Weak pulldown to
GND
Float
TABLE 3-1: PIN DESCRIPTIONS (CONTINUED)
USB7252
Name Symbol
Downstream
Port 1 USB 3.2
Gen 2 TX D-
Orientation B
Downstream
Port 1 USB 3.2
Gen 2 RX D+
Orientation B
Downstream
Port 1 USB 3.2
Gen 2 RX DOrientation B
Downstream
Port 2 USB 3.2
Gen 2 TX D+
Orientation A
Downstream
Port 2 USB 3.2
Gen 2 TX D-
Orientation A
USB3DN_TXDM1B I/O-U Downstream USB Type-C “Orientation B”
USB3DN_RXDP1B I/O-U Downstream USB Type-C “Orientation B”
USB3DN_RXDM1B I/O-U Downstream USB Type-C “Orientation B”
USB3DN_TXDP2A I/O-U Downstream USB Type-C “Orientation A”
USB3DN_TXDM2A I/O-U Downstream USB Type-C “Orientation A”
Buffer
Type
Description If Unused
SuperSpeed+ Transmit Data Minus, port 1.
SuperSpeed+ Receive Data Plus, port 1.
SuperSpeed+ Receive Data Minus, port 1.
SuperSpeed+ Transmit Data Plus, port 2.
SuperSpeed+ Transmit Data Minus, port 2.
Float
Weak pulldown to
GND
Weak pulldown to
GND
Float
Float
Downstream
Port 2 USB 3.2
Gen 2 RX D+
Orientation A
Downstream
Port 2 USB 3.2
Gen 2 RX DOrientation A
Downstream
Port 2 USB 3.2
Gen 2 TX D+
Orientation B
Downstream
Port 2 USB 3.2
Gen 2 TX D-
Orientation B
Downstream
Port 2 USB 3.2
Gen 2 RX D+
Orientation B
Downstream
Port 2 USB 3.2
Gen 2 RX DOrientation B
USB3DN_RXDP2A I/O-U Downstream USB Type-C “Orientation A”
SuperSpeed+ Receive Data Plus, port 2.
USB3DN_RXDM2A I/O-U Downstream USB Type-C “Orientation A”
SuperSpeed+ Receive Data Minus, port 2.
USB3DN_TXDP2B I/O-U Downstream USB Type-C “Orientation B”
SuperSpeed+ Transmit Data Plus, port 2.
USB3DN_TXDM2B I/O-U Downstream USB Type-C “Orientation B”
SuperSpeed+ Transmit Data Minus, port 2.
USB3DN_RXDP2B I/O-U Downstream USB Type-C “Orientation B”
SuperSpeed+ Receive Data Plus, port 2.
USB3DN_RXDM2B I/O-U Downstream USB Type-C “Orientation B”
SuperSpeed+ Receive Data Minus, port 2.
Weak pulldown to
GND
Weak pulldown to
GND
Float
Float
Weak pulldown to
GND
Weak pulldown to
GND
2018 - 2020 Microchip Technology Inc. DS00002736D-page 11
USB7252
TABLE 3-1: PIN DESCRIPTIONS (CONTINUED)
Name Symbol
Downstream
Port 3 USB 3.2
Gen 2 TX D+
Downstream
Port 3 USB 3.2
Gen 2 TX D-
Downstream
Port 3 USB 3.2
Gen 2 RX D+
Downstream
Port 3 USB 3.2
Gen 2 RX D-
Upstream USB
2.0 D+
Upstream USB
2.0 D-
Downstream
Ports 1-4 USB
2.0 D+
USB3DN_TXDP3 I/O-U Downstream SuperSpeed+ Transmit Data
USB3DN_TXDM3 I/O-U Downstream SuperSpeed+ Transmit Data
USB3DN_RXDP3 I/O-U Downstream SuperSpeed+ Receive Data
USB3DN_RXDM3 I/O-U Downstream SuperSpeed+ Receive Data
USB2DN_DP[1:4] I/O-U Downstream USB 2.0 Ports 1-4 Data Plus
Buffer
Type
Plus, port 3.
Minus, port 3.
Plus, port 3.
Minus, port 3.
USB 2.0 Interfaces
USB2UP_DP I/O-U Upstream USB 2.0 Data Plus (D+). Mandatory
USB2UP_DM I/O-U Upstream USB 2.0 Data Minus (D-). Mandatory
(D+).
Description If Unused
Float
Float
Weak pulldown to
GND
Weak pulldown to
GND
Note 3-12
Note 3-12
Connect
directly to
3.3V
Downstream
Ports 1-4 USB
2.0 D-
SPI Clock SPI_CLK I/O-U SPI clock. If the SPI interface is enabled,
SPI Data 3-0 SPI_D[3:0] I/O-U SPI Data 3-0. If the SPI interface is enabled,
USB2DN_DM[1:4] I/O-U Downstream USB 2.0 Ports 1-4 Data Minus
(D-)
SPI Interface
this pin must be driven low during reset.
these signals function as Data 3 through 0.
Note 3-1 SPI_D0 operates as the
CF G _ BC _E N
external SPI memory is not
used. It must be terminated
wit h t h e sel e c t ed st r a p
resistor to 3.3V or GND.
SP I _ D[ 1 : 3 ] sh o u l d b e
connected to GND through
a weak pull-down.
s t r a p if
Connect
directly to
3.3V
Weak pulldown to
GND
Note 3-1
DS00002736D-page 12 2018 - 2020 Microchip Technology Inc.
TABLE 3-1: PIN DESCRIPTIONS (CONTINUED)
VBUS_P1
43K
49.9K
DP1_VBUS_MON
USB7252
Name Symbol
SPI Chip
Enable
Downstream
Port 1 Type-C
Voltage Monitor
DP1_VBUS_MON AIO Used to detect Type-C VBUS vSafe5V and
Buffer
Type
SPI_CE_N I/O12 Active low SPI chip enable input. If the SPI
interface is enabled, this pin must be driven
high in powerdown states.
Note 3-2 Operates as the
USB Type-C Connector Control
vSafe0V states on Port 1. A nominal voltage
of 2.7V (2.4V min -3.0V max) is required to
detect the presence of vSafe5V.
Externally, VBUS can be as high as 5.25 V,
which can be damaging to this pin. The
amplitude of VBUS must be reduced by a
voltage divider. The recommended voltage
divider is shown below. 1% tolerance resistors are recommended.
Description If Unused
CFG_NO N _REM
external SPI memory is not
used. It must be terminated
wit h t h e sel e c t ed st r ap
resistor to 3.3V or GND.
str ap if
Note 3-2
Note 3-3
Downstream
Port 1 Type-C
CC1
For proper Type-C port operation, it is critical that this pin actually be connected to
VBUS of the port through the recommended
resistor divider. This pin should not be tied
permanently to a fixed voltage power rail.
Note 3-3 If unused: Weak pull-down
to GND. This pin may be
le ft unu s e d if Port 1 is
disabled or reconfigured to
ope rate in legacy Type-A
m o d e th r o ug h hu b
configuration.
DP1_CC1 I/O12 Used for Type-C attach and orientation
detection on Port 1. Includes configurable
Rp/Ra selection. Connect this pin directly to
the CC1 pin of the respective Type-C connector.
Note 3-4 If unused: Weak pull-down
to GND. This pin may only
be left unused if Port 1 is
disabled or reconfigured to
ope rate in legacy Type-A
m o d e th r o ug h hu b
configuration.
Note 3-4
2018 - 2020 Microchip Technology Inc. DS00002736D-page 13
USB7252
VBUS_P2
43K
49.9K
DP2_VBUS_MON
TABLE 3-1: PIN DESCRIPTIONS (CONTINUED)
Name Symbol
Downstream
Port 1 Type-C
CC2
Downstream
Port 2 Type-C
Voltage Monitor
DP2_VBUS_MON AIO Used for detect Type-C VBUS vSafe5V and
Buffer
Type
DP1_CC2 I/O12 Used for Type-C attach and orientation
detection on Port 1. Includes configurable
Rp/Ra selection. Connect this pin directly to
the CC2 pin of the respective Type-C connector.
Note 3-5 If unused: Weak pull-down
vSafe0V states on Port 2. A nominal voltage of 2.7V (2.4V min -3.0V max) is
required to detect the presence of vSafe5V.
Externally, VBUS can be as high as 5.25 V,
which can be damaging to this pin. The
amplitude of VBUS must be reduced by a
voltage divider. The recommended voltage
divider is shown below. 1% tolerance resistors are recommended.
Description If Unused
to GND. This pin may only
be left unused if Port 1 is
disabled or reconfigured to
ope rate in legacy Type-A
m o d e th r o ug h hu b
configuration.
Note 3-5
Note 3-6
Downstream
Port 2 Type-C
CC1
For proper Type-C port operation, it is critical that this pin actually be connected to
VBUS of the port through the recommended
resistor divider. This pin should not be tied
permanently to a fixed voltage power rail.
Note 3-6 If unused: Weak pull-down
to GND. This pin may be
le ft unu s e d if Port 2 is
disabled or reconfigured to
ope rate in legacy Type-A
m o d e th r o ug h hu b
configuration.
DP2_CC1 I/O12 Used for Type-C attach and orientation
detection on Port 2. Includes configurable
Rp/Ra selection. Connect this pin directly to
the CC1 pin of the respective Type-C connector.
Note 3-7 If unused: Weak pull-down
to GND. This pin may only
be left unused if Port 2 is
disabled or reconfigured to
ope rate in legacy Type-A
m o d e th r o ug h hu b
configuration.
Note 3-7
DS00002736D-page 14 2018 - 2020 Microchip Technology Inc.
TABLE 3-1: PIN DESCRIPTIONS (CONTINUED)
VBUS_UP
43K
49.9K
VBUS_MON_UP
USB7252
Name Symbol
Downstream
Port 2 Type-C
CC2
Upstream
Voltage Monitor
VBUS_MON_UP I/O12 Used to detect VBUS on the upstream port.
Buffer
Type
DP2_CC2 I/O12 Used for Type-C attach and orientation
detection on Port 2. Includes configurable
Rp/Ra selection. Connect this pin directly to
the CC2 pin of the respective Type-C connector.
Note 3-8 If unused: Weak pull-down
Externally, VBUS can be as high as 5.25 V,
which can be damaging to this pin. A nominal voltage of 2.7V (2.4V min -3.0V max) is
required to detect the presence of vSafe5V.
The amplitude of VBUS must be reduced by
a voltage divider. The recommended voltage
divider is shown below. 1% tolerance resistors are recommended.
Description If Unused
to GND. This pin may only
be left unused if Port 2 is
disabled or reconfigured to
ope rate in legacy Type-A
m o d e th r o ug h hu b
configuration.
Note 3-8
Mandatory
Note 3-12
Programmable
Function Pins
Note: For embedded host applications,
this pin should be controlled by
an I/O on the host processor to a
2.68V logic level.
Miscellaneous
PF[31:2] I/O12 Programmable function pins.
Note 3-9 If unused: depends on the
co n fi g ure d pin functi on.
Ref e r to S e c t io n 3. 3 .4 ,
PF [ 3 1 : 2 ] C o n f i g ur a ti on
(CFG_STRAP[2:1])
Note 3-9
2018 - 2020 Microchip Technology Inc. DS00002736D-page 15
USB7252
TABLE 3-1: PIN DESCRIPTIONS (CONTINUED)
Name Symbol
Test 1 TEST1 A Test 1 pin.
Test 2 TEST2 A Test 2 pin.
Test 3 TEST3 A Test 3 pin.
Reset Input RESET_N IS This active low signal is used by the system
Bias Resistor RBIAS I-R A 12.0 k
Buffer
Type
Description If Unused
This signal is used for test purposes and
must always be pulled-up to 3.3V via a 10
k
resistor.
This signal is used for test purposes and
must always be pulled-up to 3.3V via a 10
k
resistor.
This signal is used for test purposes and
must always be pulled-up to 3.3V via a 10
k
resistor.
to reset the device.
1.0% resistor is attached from
ground to this pin to set the transceiver’s
internal bias settings. Place the resistor as
close the device as possible with a dedicated, low impedance connection to the
ground plane.
Pull to 3.3V
through a
10 k
resistor
Pull to 3.3V
through a
10 k
resistor
Pull to 3.3V
through a
10 k
resistor
Mandatory
Note 3-12
Mandatory
Note 3-12
Test TESTEN I/O12 Test pin.
This signal is used for test purposes and
must always be connected to ground.
Analog Test ATEST A Analog test pin.
This signal is used for test purposes and
must always be left unconnected.
External 25 MHz
Crystal Input
External 25 MHz
Reference Clock
Input
XTALI ICLK External 25 MHz crystal input Mandatory
CLK_IN ICLK External reference clock input.
The device may alternatively be driven by a
single-ended clock oscillator. When this
method is used, XTALO should be left
unconnected.
Connect to
GND
Float
Note 3-12
Mandatory
Note 3-12
DS00002736D-page 16 2018 - 2020 Microchip Technology Inc.
TABLE 3-1: PIN DESCRIPTIONS (CONTINUED)
USB7252
Name Symbol
External 25 MHz
Crystal Output
Port 4-1 D+
Disable
Configuration
Strap
Buffer
Type
XTALO OCLK External 25 MHz crystal output Float
Configuration Straps
PRT_DIS_P[
4:1] I Port 4-1 D+ Disable Configuration Strap.
These configuration straps are used in conjunction with the corresponding
PRT_DIS_M[
related port (4-1). See Note 3-13.
Both USB data pins for the corresponding
port must be tied to 3.3V to disable the
associated downstream port.
Description If Unused
4:1] straps to disable the
(only if single-ended
clock is
connected
to
CLK_IN)
N/A
Port 4-1 D-
Disable
Configuration
Strap
Non-Removable
Ports
Configuration
Strap
PRT_DIS_M[
CFG_NON_REM
4:1] I Port 4-1 D- Disable Configuration Strap.
These configuration straps are used in conjunction with the corresponding
PRT_DIS_P[
related port (4-1). See Note 3-13.
Both USB data pins for the corresponding
port must be tied to 3.3V to disable the
associated downstream port.
I Non-Removable Ports Configuration Strap.
This configuration strap controls the number
of reported non-removable ports. See
Note 3-13 .
Note 3-10 Mandatory if external SPI
4:1] straps to disable the
me mor y is not us e d for
f i r m w a r e e x e c u t i o n . I f
ext e r na l S P I memory is
us e d f o r f i rm w a re
ex e c u t i o n, t he n
configuration strap resistor
should be omitted.
Mandatory
Note 3-12
Note 3-10
2018 - 2020 Microchip Technology Inc. DS00002736D-page 17
USB7252
TABLE 3-1: PIN DESCRIPTIONS (CONTINUED)
Name Symbol
Battery Charging
Configuration
Strap
Device Mode
Configuration
Straps 3-1
+3.3V I/O Power
Supply Input
CFG_STRAP[3:1]
Buffer
Type
CFG_BC_EN
VDD33 P +3.3 V power and internal regulator input. Mandatory
I/O12 Battery Charging Configuration Strap.
This configuration strap controls the number
of BC 1.2 enabled downstream ports. See
Note 3-13.
Note 3-11 Mandatory if external SPI
I Device Mode Configuration Straps 3-1.
These configuration straps are used to
select the device’s mode of operation. See
Note 3-13.
Power/Ground
Description If Unused
Mandatory
Note 3-12
me mor y is not us e d for
f i r m w a r e e x e c u t i o n . I f
ex t e r na l S P I memory is
us e d f o r f i rm w a re
ex e c u t i o n, t he n
configuration strap resistor
should be omitted.
Mandatory
Note 3-12
Note 3-12
Digital Core
Power Supply
Input
Ground VSS P Common ground.
Note 3-12 Configuration strap values are latched on Power-On Reset (POR) and the rising edge of RESET_N
(external chip reset). Configuration straps are identified by an underlined symbol name. Signals that
function as configuration straps must be augmented with an external resistor when connected to a
load. For additional information, refer to Section 3.3, Configuration Straps and Programmable
Functions.
Note 3-13 Pin use is mandatory. Cannot be left unused.
VCORE P Digital core power supply input. Mandatory
Note 3-12
Mandatory
Note 3-12
This exposed pad must be connected to the
ground plane with a via array.
3.3 Configuration Straps and Programmable Functions
Configuration straps are multi-function pins that are used during Power-On Reset (POR) or external chip reset
(RESET_N) to determine the default configuration of a particular feature. The state of the signal is latched following
deassertion of the reset. Configuration straps are identified by an underlined symbol name. This section details the various device configuration straps and associated programmable pin functions.
Note: The system designer must guarantee that configuration straps meet the timing requirements specified in
Section 9.6.2, Power-On and Configuration Strap Timing and Section 9.6.3, Reset and Configuration Strap
Timing. If configuration straps are not at the correct voltage level prior to being latched, the device may
capture incorrect strap values.
DS00002736D-page 18 2018 - 2020 Microchip Technology Inc.
USB7252
3.3.1 PORT DISABLE CONFIGURATION (PRT_DIS_P[4:1] / PRT_DIS_M[4:1])
The PRT_DIS_P[4:1] / PRT_DIS_M[4:1] configuration straps are used in conjunction to disable the related port (4-1)
For PRT_DIS_P
0 = Port x D+ Enabled
1 = Port x D+ Disabled
For PRT_DIS_M
0 = Port x D- Enabled
1 = Port x D- Disabled
x (where x is the corresponding port 4-1):
x (where x is the corresponding port 4-1):
Note: Both PRT_DIS_P
the associated downstream port. Disabling the USB 2.0 port will also disable the corresponding USB 3.0
port.
x and PRT_DIS_Mx (where x is the corresponding port) must be tied to 3.3 V to disable
3.3.2 NON-REMOVABLE PORT CONFIGURATION (CFG_NON_REM)
The CFG_NON_REM configuration strap is used to configure the non-removable port settings of the device to one of
five settings. These modes are selected by the configuration of an external resistor on the CFG_NON_REM
resistor options are a 200 kΩ pull-down, 200 kΩ pull-up, 10 kΩ pull-down, 10 kΩ pull-up, and 10 Ω pull-down, as shown
in Table 3-2.
pin. The
3.3.3 BATTERY CHARGING CONFIGURATION (CFG_BC_EN)
TABLE 3-2: CFG_NON_REM RESISTOR ENCODING
CFG_NON_REM Resistor Value Setting
200 kΩ Pull-Down All ports removable
200 kΩ Pull-Up Port 1 non-removable
10 kΩ Pull-Down Ports 1, 2 non-removable
10 kΩ Pull-Up Ports 1, 2, 3 non-removable
10 Ω Pull-Down Ports 1, 2, 3, 4 non-removable
The CFG_BC_EN configuration strap is used to configure the battery charging port settings of the device to one of five
settings. These modes are selected by the configuration of an external resistor on the CFG_BC_EN
options are a 200 kΩ pull-down, 200 kΩ pull-up, 10 kΩ pull-down, 10 kΩ pull-up, and 10 Ω pull-down, as shown in
Table 3-3.
pin. The resistor
TABLE 3-3: CFG_BC_EN RESISTOR ENCODING
CFG_BC_EN Resistor Value Setting
200 kΩ Pull-Down Battery charging not enable on any port
200 kΩ Pull-Up BC1.2 DCP and CDP battery charging enabled on Port 1
10 kΩ Pull-Down BC1.2 DCP and CDP battery charging enabled on Ports 1, 2
10 kΩ Pull-Up BC1.2 DCP and CDP battery charging enabled on Ports 1, 2, 3
10 Ω Pull-Down BC1.2 DCP and CDP battery charging enabled on Ports 1, 2, 3, 4
3.3.4 PF[31:2] CONFIGURATION (CFG_STRAP[2:1])
The USB7252 provides 30 programmable function pins (PF[31:2]). These pins can be configured to 4 predefined configurations via the CFG_STRAP[2:1]
CFG_STRAP[2:1]
and should not be used.
2018 - 2020 Microchip Technology Inc. DS00002736D-page 19
pins, as detailed in Table 3-4. Resistor values and combinations not detailed in Table 3-4 are reserved
pins. These configurations are selected via external resistors on the
USB7252
Note: CFG_STRAP3
is not used and must be pulled-down to ground via a 200 k resistor.
TABLE 3-4: CFG_STRAP[2:1] RESISTOR ENCODING
Mode
CFG_STRAP2
Resistor Value
Configuration 1 200 kΩ Pull-Down 200 kΩ Pull-Down
Configuration 2 200 kΩ Pull-Down 200 kΩ Pull-Up
Configuration 3 200 kΩ Pull-Down 10 kΩ Pull-Down
Configuration 4 200 kΩ Pull-Down 10 kΩ Pull-Up
A summary of the configuration pin assignments for each of the 4 configurations is provided in Table 3-5. For details on
behavior of each programmable function, refer to Table 3-6.
CFG_STRAP1
Resistor Value
TABLE 3-5: PF[31:2] FUNCTION ASSIGNMENT
Pin
Configuration 1
(SMBus/I
2
C)
PF2 DP1_VCONN1 DP1_VCONN1 DP1_VCONN1 DP1_VCONN1
PF3 DP1_VCONN2 DP1_VCONN2 DP1_VCONN2 DP1_VCONN2
PF4 DP2_DISCHARGE DP2_DISCHARGE DP2_DISCHARGE DP2_DISCHARGE
PF5 DP1_DISCHARGE DP1_DISCHARGE DP1_DISCHARGE DP1_DISCHARGE
PF6 GPIO70 GPIO70 UART_RX GPIO70
PF7 GPIO71 MIC_DET UART_TX GPIO71
(
) (
PF8
PF9
Note 3-1
(
) (
Note 3-1
PF10 DP2_VCONN1 DP2_VCONN1 DP2_VCONN1 DP2_VCONN1
PF11 DP2_VCONN2 DP2_VCONN2 DP2_VCONN2 DP2_VCONN2
PF12 PRT_CTL3_U3 PRT_CTL3_U3 PRT_CTL3_U3 PRT_CTL3_U3
PF13 PRT_CTL3 PRT_CTL3 PRT_CTL3 PRT_CTL3
PF14 GPIO78 I2S_SDI UART_nCTS GPIO78
PF15 PRT_CTL2 PRT_CTL2 PRT_CTL2 PRT_CTL2
PF16 PRT_CTL4 PRT_CTL4 PRT_CTL4 PRT_CTL4
PF17 PRT_CTL1 PRT_CTL1 PRT_CTL1 PRT_CTL1
(
) (
PF18
Note 3-1
PF19 SLV_I2C_DATA I2S_SDO UART_nRTS GPIO83
PF20 SPI_CE_N SPI_CE_N SPI_CE_N SPI_CE_N
PF21 SPI_CLK SPI_CLK SPI_CLK SPI_CLK
PF22 SPI_D0 SPI_D0 SPI_D0 SPI_D0
PF23 SPI_D1 SPI_D1 SPI_D1 SPI_D1
PF24 SPI_D2 SPI_D2 SPI_D2 SPI_D2
PF25 SPI_D3 SPI_D3 SPI_D3 SPI_D3
PF26 SLV_I2C_CLK I2S_SCK UART_nDSR GPIO90
PF27 GPIO91 I2S_MCLK UART_nDTR GPIO91
PF28 GPIO92 I2S_LRCK UART_nDCD GPIO92
(
) (
PF29
Note 3-1
PF30 MSTR_I2C_CLK MSTR_I2C_CLK MSTR_I2C_CLK MSTR_I2C_CLK
PF31 MSTR_I2C_DATA MSTR_I2C_DATA MSTR_I2C_DATA MSTR_I2C_DATA
Configuration 2
(I2S)
) (
Note 3-1
) (
Note 3-1
) (
Note 3-1
) (
Note 3-1
Configuration 3
(UART)
) (
Note 3-1
) (
Note 3-1
) (
Note 3-1
) (
Note 3-1
Configuration 4
(GPIO & FlexConnect)
)
Note 3-1
)
Note 3-1
)
Note 3-1
)
Note 3-1
DS00002736D-page 20 2018 - 2020 Microchip Technology Inc.
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