Microchip USB7252 User Manual

USB7252

4-Port USB 3.2 Gen 2 Type-C® Controller Hub

Highlights

•4-Port USB Smart Hub with:

-USB Gen 2 Type-B® on upstream port

-Native USB Gen 2 Type-C with Power Delivery PD support on downstream ports 1 and 2®

-One Standard USB 3.2 Gen 2 downstream port

-One Standard USB 2.0 downstream port

-Internal Hub Feature Controller enables:

-USB to I2C/SPI/UART/I2S/GPIO bridge endpointsupport

-USB to internal hub register write and read

•USB Link Power Management (LPM) support

•Programming of firmware image to external SPI memory device from USB host

•USB-IF Battery Charger revision 1.2 support on downstream ports (DCP, CDP, SDP)

•Enhanced OEM configuration options available through either OTP or external SPI memory

•Available in 100-pin (12mm x 12mm) VQFN RoHS compliant package

•Commercial and industrial grade temperature support

Target Applications

•Standalone USB Hubs

•Laptop Docks

•PC Motherboards

•PC Monitor Docks

•Multi-function USB 3.2 Gen 2 Peripherals

Key Benefits

•USB 3.2 Gen 2 compliant 10 Gbps, 5 Gbps, 480 Mbps, 12 Mbps, and 1.5Mbps operation

-5V tolerant USB 2.0 pins

-1.21V tolerant USB 3.2 Gen 2 pins

-Integrated termination and pull-up/down resistors

•Native USB Type-C Support

-Type-C CC Pin with integrated Rp and Rd resistors

-Integrated multiplexer on USB Type-C enabled ports. USB 3.2 Gen 2 PHYs are disabled until a

valid Type-C attach is detected, saving idle power. Control for external VCONN supply

* USB Type-C® and USB-C® are registered trademarks of USB Implementers Forum

•Supports battery charging of most popular battery powered devices on all ports

-USB-IF Battery Charging rev. 1.2 support (DCP, CDP, SDP)

-Apple® portable product charger emulation

-Chinese YD/T 1591-2006/2009 charger emulation

-European Union universal mobile charger support

-Supports additional portable devices

•On-chip Microcontroller

-manages I/Os, VBUS, and other signals

•96kB RAM, 256kB ROM

•8kB One-Time-Programmable (OTP) ROM

-Includes on-chip charge pump

•Configuration programming via OTP Memory, SPI external memory, or SMBus

•FlexConnect

-The roles of the upstream and all downstream ports are reversible on command

•Multi-Host Endpoint Reflector

-Integrated host-controller endpoint reflector via CDC/NCM device class for automotive applications

•USB Bridging

-USB to I2C, SPI, UART, I2S, and GPIO

•PortSwap

-Configurable USB 2.0 differential pair signal swap

•PHYBoost

-Programmable USB transceiver drive strength for recovering signal integrity

•VariSense

-Programmable USB receive sensitivity

•PortSplit

-USB 2.0 and USB 3.2 Gen 2 port operation can be split for custom applications using embedded USB 3.x devices in parallel with USB 2.0 devices

•Compatible with Microsoft Windows 10, 8, 7, XP, Apple OS X 10.4+, and Linux hub drivers

•Optimized for low-power operation and low thermal dissipation

•100-pin VQFN package (12mm x 12mm)

2018 - 2020 Microchip Technology Inc.

DS00002736D-page 1

USB7252

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at [e-mail] or fax the Reader Response Form in the back of this data sheet to [phone]. We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices.As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

•Microchip’s Worldwide Web site; http://www.microchip.com

•Your local Microchip sales office (see last page)

When contactinga salesoffice,please specify whichdevice,revision ofsilicon and data sheet(include literature number) you are using.

Customer Notification System

Register on our web site at www.microchip.com to receive the most current information on all of our products.

DS00002736D-page 2

2018 - 2020 Microchip Technology Inc.

USB7252

1.0PREFACE

1.1General Terms

TABLE 1-1:	GENERAL TERMS
Term		Description
ADC		Analog-to-Digital Converter
Byte		8 bits
CDC		Communication Device Class
CSR		Control and Status Registers
DFP		Downstream Facing Port
DWORD		32 bits
EOP		End of Packet
EP		Endpoint
FIFO		First In First Out buffer
FS		Full-Speed
FSM		Finite State Machine
GPIO		General Purpose I/O
HS		Hi-Speed
HSOS		High Speed Over Sampling
Hub Feature Controller		The Hub Feature Controller, sometimes called a Hub Controller for short is the internal
		processor used to enable the unique features of the USB Controller Hub. This is not to
		be confused with the USB Hub Controller that is used to communicate the hub status
I2C		back to the Host during a USB session.
		Inter-Integrated Circuit
LS		Low-Speed
lsb		Least Significant Bit
LSB		Least Significant Byte
msb		Most Significant Bit
MSB		Most Significant Byte
N/A		Not Applicable
NC		No Connect
OTP		One Time Programmable
PCB		Printed Circuit Board
PCS		Physical Coding Sublayer
PHY		Physical Layer
PLL		Phase Lock Loop
RESERVED		Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must
		always be zero for write operations. Unless otherwise noted, values are not guaran-
		teed when reading reserved bits. Unless otherwise noted, do not read or write to
		reserved addresses.
SDK		Software Development Kit
SMBus		System Management Bus
UFP		Upstream Facing Port
UUID		Universally Unique IDentifier
WORD		16 bits

2018 - 2020 Microchip Technology Inc.

DS00002736D-page 3

USB7252

1.2Buffer Types

TABLE 1-2: BUFFER TYPES

Buffer Type

Description

IInput.

IS	Input with Schmitt trigger.
O12	Output buffer with 12 mA sink and 12 mA source.
OD12	Open-drain output with 12 mA sink
PU	50 μA (typical) internal pull-up. Unless otherwise noted in the pin description, internal pull-
	ups are always enabled.
	Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on internal
	resistors to drive signals external to the device. When connected to a load that must be
	pulled high, an external resistor must be added.
PD	50 μA (typical) internal pull-down. Unless otherwise noted in the pin description, internal
	pull-downs are always enabled.
	Internal pull-down resistors prevent unconnected inputs from floating. Do not rely on
	internal resistors to drive signals external to the device. When connected to a load that
	must be pulled low, an external resistor must be added.
ICLK	Crystal oscillator input pin
OCLK	Crystal oscillator output pin
I/O-U	Analog input/output defined in USB specification.
I-R	RBIAS.

AAnalog.

AIO	Analog bidirectional.

PPower pin.

DS00002736D-page 4

2018 - 2020 Microchip Technology Inc.

USB7252

1.3Pin Reset States

The pin reset state definitions are detailed in Table 1-3. Refer to Section 3.1, Pin Assignments for details on individual pin reset states.

TABLE 1-3: PIN RESET STATE LEGEND

Symbol	Description
AI	Analog input
AIO	Analog input/output
AO	Analog output
PD	Hardware enables pull-down
PU	Hardware enables pull-up

YHardware enables function

ZHardware disables output driver (high impedance)

PU	Hardware enables internal pull-up
PD	Hardware enables internal pull-down

1.4Reference Documents

1.Universal Serial Bus Revision 3.2 Specification, http://www.usb.org

2.Battery Charging Specification, Revision 1.2, Dec. 07, 2010, http://www.usb.org

3.I2C-Bus Specification, Version 1.1, http://www.nxp.com/documents/user_manual/UM10204.pdf

4.I2S-Bus Specification, http://www.sparkfun.com/datasheets/BreakoutBoards/I2SBUS.pdf

5.System Management Bus Specification, Version 1.0, http://smbus.org/specs

Note: Additional USB7252 resources can be found on the Microchip USB7252 product page at www.microchip.com/USB7252.

2018 - 2020 Microchip Technology Inc.

DS00002736D-page 5

USB7252

2.0INTRODUCTION

2.1General Description

The Microchip USB7252 hub is a low-power, OEM configurable, USB 3.2 Gen 2 hub controller with 4 downstream ports and advanced features for embedded USB applications. The USB7252 is fully compliant with the Universal Serial Bus Revision 3.2 Specification and USB 2.0 Link Power Management Addendum. The USB7252 supports 10 Gbps SuperSpeed+ (SS+), 5 Gbps SuperSpeed (SS), 480 Mbps Hi-Speed (HS), 12 Mbps Full-Speed (FS), and 1.5 Mbps LowSpeed (LS) USB downstream devices on three standard USB 3.2 Gen 2 downstream ports and only legacy speeds(HS/ FS/LS) on one standard USB 2.0 downstream port.

The USB7252 is a standard USB 3.2 Gen 2 hub that supportsnative basicType-C with integrated CC logicon two downstream ports. The downstream Type-C ports include internal USB 3.2 Gen 2 multiplexers; no external multiplexer is required for Type-C support.

The USB7252 supports the legacy USB speeds (HS/FS/LS) through a dedicated USB 2.0 hub controller that is the culmination of seven generations of Microchip hub feature controller design and experience with proven reliability, interoperability, and device compatibility. The SuperSpeed hub controller operates in parallel with the USB 2.0 controller, decoupling the 10/5 Gbps SS+/SS data transfers from bottlenecks due to the slower USB 2.0 traffic.

The USB7252 enables OEMs to configure their system using “Configuration Straps.” These straps simplify the configuration process assigning default values to USB 3.2 Gen 2 ports and GPIOs. OEMs can disable ports, enable battery charging and define GPIO functions as default assignments on power up removing the need for OTP or external SPI ROM.

The USB7252 supports downstream battery charging. The USB7252 integrated battery charger detection circuitry supports the USB-IF Battery Charging (BC1.2) detection method and most Apple devices. The USB7252 provides the battery charging handshake and supports the following USB-IF BC1.2 charging profiles:

•DCP: Dedicated Charging Port (Power brick with no data)

•CDP: Charging Downstream Port (1.5A with data)

•SDP: Standard Downstream Port (0.5A[USB 2.0]/0.9A[USB 3.2] with data) Additionally, the USB7252 includes many powerful and unique features such as:

The Hub Feature Controller, an internal USB device dedicated for use as a USB to I2C/UART/SPI/GPIO interface that allows external circuits or devices to be monitored, controlled, or configured via the USB interface.

Multi-Host Endpoint Reflector, which providesuniqueUSB functionality whereby USB datacanbe “mirrored”between two USB hosts (Multi-Host) in order to perform a single USB transaction.This capability is fully covered by Microchip intellectual property (U.S. Pat. Nos. 7,523,243 and 7,627,708) and is instrumental in enabling Apple CarPlay™, where the Apple iPhone® becomes a USB Host.

FlexConnect, which provides flexible connectivity options. One of the USB7252’s downstream ports can be reconfigured to become the upstream port, allowing master capable devices to control other devices on the hub.

PortSwap, which adds per-port programmability to USB differential-pair pin locations. PortSwap allows direct alignment of USB signals (D+/D-) to connectors to avoid uneven trace length or crossing of the USB differential signals on the PCB.

PHYBoost, which provides programmable levels of Hi-Speed USB signal drive strength in the downstream port transceivers. PHYBoost attempts to restore USB signal integrity in a compromised system environment. The graphic on the right shows an example of Hi-Speed USB eye diagrams before and after PHYBoost signal integrity restoration. in a compromised system environment.

VariSense, which controls the Hi-Speed USB receiver sensitivity enabling programmable levels of USB signal receive sensitivity. This capability allows operation in a sub-optimal system environment, such as when a captive USB cable is used.

Port Split, which allows for the USB 3.2 Gen 2 and USB 2.0 portions of downstream port 3 to operate independently and enumerate two separate devices in parallel in special applications.

DS00002736D-page 6

2018 - 2020 Microchip Technology Inc.

USB7252

The USB7252 can be configured for operation through internal default settings. Custom OEM configurations are supported through external SPI ROM or OTP ROM.All port control signal pins are under firmware control in order to allow for maximum operational flexibility and are available as GPIOs for customer specific use.

The USB7252 is available in commercial (0°C to +70°C) and industrial (-40°C to +85°C) temperature ranges.An internal block diagram of the USB7252 in an upstream Type-C application is shown in Figure 2-1.

FIGURE 2-1: USB7252 INTERNAL BLOCK DIAGRAM - UPSTREAM TYPE-B APPLICATION

P0

B

	I2C from Master
+3.3 V
PHY0 PHY0	I2C/SPI
VCORE	USB3 USB2

Hub Controller Logic

	25 Mhz	PHY1 PHY2		PHY1	CC
		A	B

PHY3

PHY4

HFC

A

B

PHY3

CC

PHY5

PHY5

PHY2

PHY

Hub Feature Controller OTP

GPIO SMB SPI I2S UART

Mux

P1	P2	P3	P4
C	C	A	A

Note: All port numberingin this documentis LOGICALportnumbering with the device in thedefault configuration. LOGICALport numbering is the numbering as communicated to the USB host. It is the end result after any port number remapping or port disabling. The PHYSICAL port number is the port number with respect to the physical PHY on the chip. PHYSICAL port numbering is fixed and the settings are not impacted by LOGICALport renumbering/remapping. Certain port settings are made with respect to LOGICALport numbering, and other port settings are made with respect to PHYSICAL port numbering. Refer to the “Configuration of USB7202/USB7206/USB725x” application note for details on the LOGICAL vs. PHYSICAL mapping and additional configuration details.

2018 - 2020 Microchip Technology Inc.

DS00002736D-page 7

USB7252

3.0PIN DESCRIPTIONS

3.1Pin Assignments

FIGURE 3-1: USB7252 100-VQFN PIN ASSIGNMENTS

RESET_N 1

PF30 2

PF31 3

DP1_VBUS_MON 4

USB2DN_DP1/PRT_DIS_P1 5

USB2DN_DM1/PRT_DIS_M1 6

USB3DN_TXDP1A 7

USB3DN_TXDM1A 8

VCORE 9

USB3DN_RXDP1A 10

USB3DN_RXDM1A 11

DP1_CC1 12

DP1_CC2 13

USB2DN_DP4/PRT_DIS_P4 14

USB2DN_DM4/PRT_DIS_M4 15

USB3DN_TXDP1B 16

USB3DN_TXDM1B 17

VCORE 18

USB3DN_RXDP1B 19

USB3DN_RXDM1B 20

CFG_STRAP1 21

CFG_STRAP2 22

CFG_STRAP3 23

TESTEN 24

VCORE 25

<![if ! IE]> <![endif]>RBIAS

<![if ! IE]> <![endif]>VDD33

<![if ! IE]> <![endif]>XTALI/CLK IN

<![if ! IE]> <![endif]>XTALO

<![if ! IE]> <![endif]>ATEST

<![if ! IE]> <![endif]>USB3UP RXDM

<![if ! IE]> <![endif]>USB3UP RXDP

<![if ! IE]> <![endif]>VCORE

<![if ! IE]> <![endif]>USB3UP TXDM

<![if ! IE]> <![endif]>USB3UP TXDP

<![if ! IE]> <![endif]>USB2UP DM

<![if ! IE]> <![endif]>USB2UP DP

<![if ! IE]> <![endif]>VDD33

<![if ! IE]> <![endif]>USB3DN RXDM3

<![if ! IE]> <![endif]>USB3DN RXDP3

<![if ! IE]> <![endif]>VCORE

<![if ! IE]> <![endif]>USB3DN TXDM3

<![if ! IE]> <![endif]>USB3DN TXDP3

<![if ! IE]> <![endif]>USB2DN DM3/PRT DIS M3

<![if ! IE]> <![endif]>USB2DN DP3/PRT DIS P3

<![if ! IE]> <![endif]>VBUS MON UP

<![if ! IE]> <![endif]>VDD33

<![if ! IE]> <![endif]>VCORE

<![if ! IE]> <![endif]>PF28

<![if ! IE]> <![endif]>PF27

<![if ! IE]> <![endif]>100

<![if ! IE]> <![endif]>99

<![if ! IE]> <![endif]>98

<![if ! IE]> <![endif]>97

<![if ! IE]> <![endif]>96

<![if ! IE]> <![endif]>95

<![if ! IE]> <![endif]>94

<![if ! IE]> <![endif]>93

<![if ! IE]> <![endif]>92

<![if ! IE]> <![endif]>91

<![if ! IE]> <![endif]>90

<![if ! IE]> <![endif]>89

<![if ! IE]> <![endif]>88

<![if ! IE]> <![endif]>87

<![if ! IE]> <![endif]>86

<![if ! IE]> <![endif]>85

<![if ! IE]> <![endif]>84

<![if ! IE]> <![endif]>83

<![if ! IE]> <![endif]>82

<![if ! IE]> <![endif]>81

<![if ! IE]> <![endif]>80

<![if ! IE]> <![endif]>79

<![if ! IE]> <![endif]>78

<![if ! IE]> <![endif]>77

<![if ! IE]> <![endif]>76

Microchip

USB7252

(Top View 100-VQFN)

Thermal slug connects to VSS

<![if ! IE]> <![endif]>26

<![if ! IE]> <![endif]>27

<![if ! IE]> <![endif]>28

<![if ! IE]> <![endif]>29

<![if ! IE]> <![endif]>30

<![if ! IE]> <![endif]>31

<![if ! IE]> <![endif]>32

<![if ! IE]> <![endif]>33

<![if ! IE]> <![endif]>34

<![if ! IE]> <![endif]>35

<![if ! IE]> <![endif]>36

<![if ! IE]> <![endif]>37

<![if ! IE]> <![endif]>38

<![if ! IE]> <![endif]>39

<![if ! IE]> <![endif]>40

<![if ! IE]> <![endif]>41

<![if ! IE]> <![endif]>42

<![if ! IE]> <![endif]>43

<![if ! IE]> <![endif]>44

<![if ! IE]> <![endif]>45

<![if ! IE]> <![endif]>46

<![if ! IE]> <![endif]>47

<![if ! IE]> <![endif]>48

<![if ! IE]> <![endif]>49

<![if ! IE]> <![endif]>50

<![if ! IE]> <![endif]>VDD33

<![if ! IE]> <![endif]>DP2 CC1

<![if ! IE]> <![endif]>DP2 CC2

<![if ! IE]> <![endif]>USB2DN DP2/PRT DIS P2

<![if ! IE]> <![endif]>USB2DN DM2/PRT DIS M2

<![if ! IE]> <![endif]>USB3DN TXDP2A

<![if ! IE]> <![endif]>USB3DN TXDM2A

<![if ! IE]> <![endif]>VCORE

<![if ! IE]> <![endif]>USB3DN RXDP2A

<![if ! IE]> <![endif]>USB3DN RXDM2A

<![if ! IE]> <![endif]>DP2 VBUS MON

<![if ! IE]> <![endif]>USB3DN TXDP2B

<![if ! IE]> <![endif]>USB3DN TXDM2B

<![if ! IE]> <![endif]>VCORE

<![if ! IE]> <![endif]>USB3DN RXDP2B

<![if ! IE]> <![endif]>USB3DN RXDM2B

<![if ! IE]> <![endif]>VDD33

<![if ! IE]> <![endif]>PF2

<![if ! IE]> <![endif]>PF3

<![if ! IE]> <![endif]>PF4

<![if ! IE]> <![endif]>PF5

<![if ! IE]> <![endif]>PF6

<![if ! IE]> <![endif]>PF7

<![if ! IE]> <![endif]>PF8

<![if ! IE]> <![endif]>PF9

75 PF26

74 PF29

73 SPI_D3/PF25

72 SPI_D2/PF24

71 SPI_D1/PF23

70 SPI_D0/CFG_BC_EN/PF22

69 SPI_CE_N/CFG_NON_REM/PF20

68 SPI_CLK/PF21

67 VDD33

66 PF19

65 TEST3

64 TEST2

63 TEST1

62 VDD33

61 PF18

60 PF17

59 PF16

58 PF15

57 PF14

56 PF13

55 VCORE

54 PF12

53 VDD33

52 PF11

51 PF10

Note: Configuration straps are identified by an underlined symbol name. Signals that function as configuration straps must be augmented with an external resistor when connected to a load.

DS00002736D-page 8

2018 - 2020 Microchip Technology Inc.

				USB7252
Pin Num	Pin Name	Reset	Pin Num	Pin Name	Reset
1	RESET_N	Z	51	PF10	PD
2	PF30	Z	52	PF11	PD
3	PF31	Z	53	VDD33	Z
4	DP1_VBUS_MON	AI	54	PF12	PD
5	USB2DN_DP1/PRT_DIS_P1	AIO PD	55	VCORE	Z
6	USB2DN_DM1/PRT_DIS_M1	AIO PD	56	PF13	PD
7	USB3DN_TXDP1A	AO PD	57	PF14	PD
8	USB3DN_TXDM1A	AO PD	58	PF15	PD
9	VCORE	Z	59	PF16	PD
10	USB3DN_RXDP1A	AI PD	60	PF17	PD
11	USB3DN_RXDM1A	AI PD	61	PF18	Z
12	DP1_CC1	AI	62	VDD33	Z
13	DP1_CC2	AI	63	TEST1	Z
14	USB2DN_DP4/PRT_DIS_P4	AIO PD	64	TEST2	Z
15	USB2DN_DM4/PRT_DIS_M4	AIO PD	65	TEST3	Z
16	USB3DN_TXDP1B	AO PD	66	PF19	Z
17	USB3DN_TXDM1B	AO PD	67	VDD33	Z
18	VCORE	Z	68	SPI_CLK/PF21	Z
19	USB3DN_RXDP1B	AI PD	69	SPI_CE_N/CFG_NON_REM/PF20	PU
20	USB3DN_RXDM1B	AI PD	70	SPI_D0/CFG_BC_EN/PF22	Z
21	CFG_STRAP1	Z	71	SPI_D1/PF23	Z
22	CFG_STRAP2	Z	72	SPI_D2/PF24	Z
23	CFG_STRAP3	Z	73	SPI_D3/PF25	Z
24	TESTEN	Z	74	PF29	Z
25	VCORE	Z	75	PF26	Z
26	VDD33	Z	76	PF27	Z
27	DP2_CC1	AI	77	PF28	Z
28	DP2_CC2	AI	78	VCORE	Z
29	USB2DN_DP2/PRT_DIS_P2	AIO PD	79	VDD33	Z
30	USB2DN_DM2/PRT_DIS_M2	AIO PD	80	VBUS_MON_UP	AI
31	USB3DN_TXDP2A	AO PD	81	USB2DN_DP3/PRT_DIS_P3	AIO PD
32	USB3DN_TXDM2A	AO PD	82	USB2DN_DM3/PRT_DIS_M3	AIO PD
33	VCORE	Z	83	USB3DN_TXDP3	AO PD
34	USB3DN_RXDP2A	AI PD	84	USB3DN_TXDM3	AO PD
35	USB3DN_RXDM2A	AI PD	85	VCORE	Z
36	DP2_VBUS_MON	AI	86	USB3DN_RXDP3	AI PD
37	USB3DN_TXDP2B	AO PD	87	USB3DN_RXDM3	AI PD
38	USB3DN_TXDM2B	AO PD	88	VDD33	Z
39	VCORE	Z	89	USB2UP_DP	AIO Z
40	USB3DN_RXDP2B	AI PD	90	USB2UP_DM	AIO Z
41	USB3DN_RXDM2B	AI PD	91	USB3UP_TXDP	AO PD
42	VDD33	Z	92	USB3UP_TXDM	AO PD
43	PF2	Z	93	VCORE	Z
44	PF3	Z	94	USB3UP_RXDP	AI PD
45	PF4	Z	95	USB3UP_RXDM	AI PD
46	PF5	Z	96	ATEST	AO
47	PF6	Z	97	XTALO	AO
48	PF7	Z	98	XTALI/CLK_IN	AI
49	PF8	Z	99	VDD33	Z
50	PF9	Z	100	RBIAS	AI

Exposed Pad (VSS) must be connected to ground.

2018 - 2020 Microchip Technology Inc.

DS00002736D-page 9

USB7252

3.2Pin Descriptions

This section contains descriptions of the various USB7252 pins. The “_N” symbol in the signal name indicates that the active, or asserted, state occurs when the signal is at a low voltage level. For example, RESET_N indicates that the reset signal is active low. When “_N” is not present after the signal name, the signal is asserted when at the high voltage level.

The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of “active low” and “active high” signal. The term assert, or assertion, indicates that a signal is active, independent of whether that level is represented by a high or low voltage. The term negate, or negation, indicates that a signal is inactive.

The “If Unused” column provides information on how to terminate pins if they are unused in a customer design. Buffer type definitions are detailed in Section 1.2, Buffer Types.

	TABLE 3-1:	PIN DESCRIPTIONS
	Name	Symbol	Buffer	Description	If Unused
			Type
			USB 3.2 Gen 2 Interfaces
	Upstream USB	USB3UP_TXDP	I/O-U Upstream USB 3.2 Gen 2 Transmit Data		Float
	3.2 Gen 2 TX D+			Plus.
	Upstream USB	USB3UP_TXDM	I/O-U Upstream USB 3.2 Gen 2 Transmit Data		Float
	3.2 Gen 2 TX D-			Minus.
	Upstream USB	USB3UP_RXDP	I/O-U Upstream USB 3.2 Gen 2 Receive Data		Weak pull-
	3.2 Gen 2 RX D+			Plus.	down to
					GND
	Upstream USB	USB3UP_RXDM	I/O-U Upstream USB 3.2 Gen 2 Receive Data		Weak pull-
	3.2 Gen 2 RX D-			Minus.	down to
					GND
	Downstream	USB3DN_TXDP1A	I/O-U Downstream USB Type-C® “Orientation A”		Float
	Port 1 USB 3.2			SuperSpeed+ Transmit Data Plus, port 1.
	Gen 2 TX D+
	Orientation A
	Downstream	USB3DN_TXDM1A	I/O-U Downstream USB Type-C “Orientation A”		Float
	Port 1 USB 3.2			SuperSpeed+ Transmit Data Minus, port 1.
	Gen 2 TX D- Ori-
	entation A
	Downstream	USB3DN_RXDP1A	I/O-U Downstream USB Type-C “Orientation A”		Weak pull-
	Port 1 USB 3.2			SuperSpeed+ Receive Data Plus, port 1.	down to
	Gen 2 RX D+				GND
	Orientation A
	Downstream	USB3DN_RXDM1A	I/O-U Downstream USB Type-C “Orientation A”		Weak pull-
	Port 1 USB 3.2			SuperSpeed+ Receive Data Minus, port 1.	down to
	Gen 2 RX D-				GND
	Orientation A
	Downstream	USB3DN_TXDP1B	I/O-U Downstream USB Type-C “Orientation B”		Float
	Port 1 USB 3.2			SuperSpeed+ Transmit Data Plus, port 1.
	Gen 2 TX D+
	Orientation B

DS00002736D-page 10

2018 - 2020 Microchip Technology Inc.

USB7252

TABLE 3-1: PIN DESCRIPTIONS (CONTINUED)

	Name	Symbol	Buffer
			Type
	Downstream	USB3DN_TXDM1B	I/O-U
	Port 1 USB 3.2
	Gen 2 TX D-
	Orientation B

Description	If Unused
Downstream USB Type-C “Orientation B”	Float
SuperSpeed+ Transmit Data Minus, port 1.

Downstream	USB3DN_RXDP1B	I/O-U Downstream USB Type-C “Orientation B”	Weak pull-
Port 1 USB 3.2		SuperSpeed+ Receive Data Plus, port 1.	down to
Gen 2 RX D+			GND
Orientation B
Downstream	USB3DN_RXDM1B	I/O-U Downstream USB Type-C “Orientation B”	Weak pull-
Port 1 USB 3.2		SuperSpeed+ Receive Data Minus, port 1.	down to
Gen 2 RX D-			GND
Orientation B
Downstream	USB3DN_TXDP2A	I/O-U Downstream USB Type-C “Orientation A”	Float
Port 2 USB 3.2		SuperSpeed+ Transmit Data Plus, port 2.
Gen 2 TX D+
Orientation A
Downstream	USB3DN_TXDM2A	I/O-U Downstream USB Type-C “Orientation A”	Float
Port 2 USB 3.2		SuperSpeed+ Transmit Data Minus, port 2.
Gen 2 TX D-
Orientation A
Downstream	USB3DN_RXDP2A	I/O-U Downstream USB Type-C “Orientation A”	Weak pull-
Port 2 USB 3.2		SuperSpeed+ Receive Data Plus, port 2.	down to
Gen 2 RX D+			GND
Orientation A
Downstream	USB3DN_RXDM2A	I/O-U Downstream USB Type-C “Orientation A”	Weak pull-
Port 2 USB 3.2		SuperSpeed+ Receive Data Minus, port 2.	down to
Gen 2 RX D-			GND
Orientation A
Downstream	USB3DN_TXDP2B	I/O-U Downstream USB Type-C “Orientation B”	Float
Port 2 USB 3.2		SuperSpeed+ Transmit Data Plus, port 2.
Gen 2 TX D+
Orientation B
Downstream	USB3DN_TXDM2B	I/O-U Downstream USB Type-C “Orientation B”	Float
Port 2 USB 3.2		SuperSpeed+ Transmit Data Minus, port 2.
Gen 2 TX D-
Orientation B
Downstream	USB3DN_RXDP2B	I/O-U Downstream USB Type-C “Orientation B”	Weak pull-
Port 2 USB 3.2		SuperSpeed+ Receive Data Plus, port 2.	down to
Gen 2 RX D+			GND
Orientation B
Downstream	USB3DN_RXDM2B	I/O-U Downstream USB Type-C “Orientation B”	Weak pull-
Port 2 USB 3.2		SuperSpeed+ Receive Data Minus, port 2.	down to
Gen 2 RX D-			GND
Orientation B

2018 - 2020 Microchip Technology Inc.

DS00002736D-page 11

USB7252

	TABLE 3-1:	PIN DESCRIPTIONS (CONTINUED)
	Name	Symbol	Buffer	Description	If Unused
			Type
	Downstream	USB3DN_TXDP3	I/O-U	Downstream SuperSpeed+ Transmit Data	Float
	Port 3 USB 3.2			Plus, port 3.
	Gen 2 TX D+
	Downstream	USB3DN_TXDM3	I/O-U	Downstream SuperSpeed+ Transmit Data	Float
	Port 3 USB 3.2			Minus, port 3.
	Gen 2 TX D-
	Downstream	USB3DN_RXDP3	I/O-U Downstream SuperSpeed+ Receive Data		Weak pull-
	Port 3 USB 3.2			Plus, port 3.	down to
	Gen 2 RX D+				GND
	Downstream	USB3DN_RXDM3	I/O-U Downstream SuperSpeed+ Receive Data		Weak pull-
	Port 3 USB 3.2			Minus, port 3.	down to
	Gen 2 RX D-				GND
			USB 2.0 Interfaces
	Upstream USB	USB2UP_DP	I/O-U Upstream USB 2.0 Data Plus (D+).		Mandatory
	2.0 D+				Note 3-12
	Upstream USB	USB2UP_DM	I/O-U Upstream USB 2.0 Data Minus (D-).		Mandatory
	2.0 D-				Note 3-12
	Downstream	USB2DN_DP[1:4]	I/O-U Downstream USB 2.0 Ports 1-4 Data Plus		Connect
	Ports 1-4 USB			(D+).	directly to
	2.0 D+				3.3V
	Downstream	USB2DN_DM[1:4]	I/O-U Downstream USB 2.0 Ports 1-4 Data Minus		Connect
	Ports 1-4 USB			(D-)	directly to
	2.0 D-				3.3V
			SPI Interface
	SPI Clock	SPI_CLK	I/O-U SPI clock. If the SPI interface is enabled,		Weak pull-
				this pin must be driven low during reset.	down to
					GND

SPI Data 3-0	SPI_D[3:0]	I/O-U SPI Data 3-0. If the SPI interface is enabled, Note 3-1
		these signals function as Data 3 through 0.
		Note 3-1	SPI_D0 operates as the
			CFG_BC_EN strap if
			external SPI memory is not
			used. It must be terminated
			with the selected strap

resistor to 3.3V or GND.

SPI_D[1:3] should be connected to GND through a weak pull-down.

DS00002736D-page 12

2018 - 2020 Microchip Technology Inc.

USB7252

TABLE 3-1: PIN DESCRIPTIONS (CONTINUED)

	Name	Symbol	Buffer
			Type
	SPI Chip	SPI_CE_N	I/O12
	Enable

Description

Active low SPI chip enable input. If the SPI interface is enabled, this pin must be driven high in powerdown states.

Note 3-2	Operates	as	the
	CFG_NON_REM strap if
	external SPI memory is not
	used. It must be terminated
	with the	selected	strap

resistor to 3.3V or GND.

USB Type-C Connector Control

Downstream

DP1_VBUS_MON

AIO

Used to detect Type-C VBUS vSafe5V and

Port 1 Type-C

vSafe0V states on Port 1.Anominal voltage

Voltage Monitor

of 2.7V (2.4V min -3.0V max) is required to

detect the presence of vSafe5V.

Externally, VBUS can be as high as 5.25 V,

which can be damaging to this pin. The

amplitude of VBUS must be reduced by a

voltage divider. The recommended voltage

divider is shown below. 1% tolerance resis-

tors are recommended.

VBUS_P1

DP1_VBUS_MON

43K

<![if ! IE]> <![endif]>49.9K

For proper Type-C port operation, it is criti-

cal that this pin actually be connected to

VBUS of the port through the recommended

resistor divider. This pin should not be tied

permanently to a fixed voltage power rail.

Note 3-3

If unused: Weak pull-down

to GND. This pin may be

left unused if Port 1 is

disabled or reconfigured to

operate in legacy Type-A

mode

through

hub

configuration.

Downstream

DP1_CC1

I/O12

Used for Type-C attach and orientation

Port 1 Type-C

detection on Port 1. Includes configurable

CC1

Rp/Ra selection. Connect this pin directly to

the CC1 pin of the respective Type-C con-

nector.

Note 3-4

If unused: Weak pull-down

to GND. This pin may only

be left unused if Port 1 is

disabled or reconfigured to

operate in legacy Type-A

mode

through

hub

configuration.

If Unused

Note 3-2

Note 3-3

Note 3-4

2018 - 2020 Microchip Technology Inc.

DS00002736D-page 13

USB7252

TABLE 3-1: PIN DESCRIPTIONS (CONTINUED)

	Name	Symbol	Buffer
			Type
	Downstream	DP1_CC2	I/O12
	Port 1 Type-C
	CC2

Downstream	DP2_VBUS_MON	AIO
Port 2 Type-C
Voltage Monitor

Downstream	DP2_CC1	I/O12
Port 2 Type-C
CC1

	Description	If Unused
Used for Type-C attach and orientation		Note 3-5
detection on Port 1. Includes configurable
Rp/Ra selection. Connect this pin directly to
the CC2 pin of the respective Type-C con-
nector.
Note 3-5	If unused: Weak pull-down
	to GND. This pin may only
	be left unused if Port 1 is
	disabled or reconfigured to
	operate in legacy Type-A
	mode through	hub
	configuration.

Used for detect Type-C VBUS vSafe5V and Note 3-6 vSafe0V states on Port 2. A nominal volt-

age of 2.7V (2.4V min -3.0V max) is required to detect the presence of vSafe5V. Externally, VBUS can be as high as 5.25 V, which can be damaging to this pin. The amplitude of VBUS must be reduced by a voltage divider. The recommended voltage divider is shown below. 1% tolerance resistors are recommended.

VBUS_P2

	43K	DP2_VBUS_MON
		<![if ! IE]> <![endif]>49.9K

For proper Type-C port operation, it is critical that this pin actually be connected to VBUS of the port through the recommended resistor divider. This pin should not be tied permanently to a fixed voltage power rail.

Note 3-6 If unused: Weak pull-down to GND. This pin may be left unused if Port 2 is disabled or reconfigured to operate in legacy Type-A mode through hub configuration.

Used for Type-C attach and orientation		Note 3-7
detection on Port 2. Includes configurable
Rp/Ra selection. Connect this pin directly to
the CC1 pin of the respective Type-C con-
nector.
Note 3-7	If unused: Weak pull-down
	to GND. This pin may only
	be left unused if Port 2 is
	disabled or reconfigured to
	operate in legacy Type-A
	mode through	hub
	configuration.

DS00002736D-page 14

2018 - 2020 Microchip Technology Inc.

USB7252

TABLE 3-1: PIN DESCRIPTIONS (CONTINUED)

	Name	Symbol	Buffer
			Type
	Downstream	DP2_CC2	I/O12
	Port 2 Type-C
	CC2

Description

Used for Type-C attach and orientation detection on Port 2. Includes configurable Rp/Ra selection. Connect this pin directly to the CC2 pin of the respective Type-C connector.

Note 3-8 If unused: Weak pull-down to GND. This pin may only be left unused if Port 2 is disabled or reconfigured to operate in legacy Type-A mode through hub configuration.

Upstream

VBUS_MON_UP

I/O12 Used to detect VBUS on the upstream port.

Voltage Monitor

Externally, VBUS can be as high as 5.25 V,

which can be damaging to this pin. A nomi-

nal voltage of 2.7V (2.4V min -3.0V max) is

required to detect the presence of vSafe5V.

The amplitude of VBUS must be reduced by

avoltage divider.The recommendedvoltage

divider is shown below. 1% tolerance resis-

tors are recommended.

VBUS_UP

VBUS_MON_UP

43K

<![if ! IE]> <![endif]>49.9K

Note: For embedded hostapplications, this pin should be controlled by an I/O on the host processor to a 2.68V logic level.

		Miscellaneous
Programmable	PF[31:2]	I/O12 Programmable function pins.
Function Pins		Note 3-9	If unused: depends on the
			configured pin function.
			Refer to	Section 3.3.4,
			PF[31:2]	Configuration
			(CFG_STRAP[2:1])

If Unused

Note 3-8

Mandatory

Note 3-12

Note 3-9

2018 - 2020 Microchip Technology Inc.

DS00002736D-page 15

USB7252

TABLE 3-1: PIN DESCRIPTIONS (CONTINUED)

	Name	Symbol	Buffer
			Type
	Test 1	TEST1	A

Test 2

TEST2

A

Test 3

TEST3

A

Reset Input	RESET_N	IS
Bias Resistor	RBIAS	I-R

Description	If Unused
Test 1 pin.	Pullto3.3V
	through a
This signal is used for test purposes and	10 k
must always be pulled-up to 3.3V via a 10	resistor
k resistor.
Test 2 pin.	Pullto3.3V
	through a
This signal is used for test purposes and	10 k
must always be pulled-up to 3.3V via a 10	resistor
k resistor.
Test 3 pin.	Pullto3.3V
	through a
This signal is used for test purposes and	10 k
must always be pulled-up to 3.3V via a 10	resistor
k resistor.
This active low signal is used by the system	Mandatory
to reset the device.	Note 3-12
A 12.0 k 1.0% resistor is attached from	Mandatory
ground to this pin to set the transceiver’s	Note 3-12
internal bias settings. Place the resistor as
close the device as possible with a dedi-
cated, low impedance connection to the
ground plane.

Test	TESTEN	I/O12	Test pin.	Connect to
			This signal is used for test purposes and	GND
			must always be connected to ground.
Analog Test	ATEST	A	Analog test pin.	Float
			This signal is used for test purposes and
			must always be left unconnected.
External 25 MHz	XTALI	ICLK	External 25 MHz crystal input	Mandatory
Crystal Input				Note 3-12
External 25 MHz	CLK_IN	ICLK	External reference clock input.	Mandatory
ReferenceClock				Note 3-12
Input			The device may alternatively be driven by a
			single-ended clock oscillator. When this
			method is used, XTALO should be left
			unconnected.

DS00002736D-page 16

2018 - 2020 Microchip Technology Inc.

USB7252

TABLE 3-1: PIN DESCRIPTIONS (CONTINUED)

	Name	Symbol	Buffer	Description
			Type
	External 25 MHz	XTALO	OCLK External 25 MHz crystal output
	Crystal Output

		Configuration Straps
Port 4-1 D+	PRT_DIS_P[4:1]	I	Port 4-1 D+ Disable Configuration Strap.
Disable			These configuration straps are used in con-
Configuration
Strap			junction with the corresponding
			PRT_DIS_M[4:1] straps to disable the
			related port (4-1). See Note 3-13.
			Both USB data pins for the corresponding
			port must be tied to 3.3V to disable the
			associated downstream port.
Port 4-1 D-	PRT_DIS_M[4:1]	I	Port 4-1 D- Disable Configuration Strap.
Disable
Configuration			These configuration straps are used in con-
Strap			junction with the corresponding
			PRT_DIS_P[4:1] straps to disable the
			related port (4-1). See Note 3-13.
			Both USB data pins for the corresponding
			port must be tied to 3.3V to disable the
			associated downstream port.
Non-Removable	CFG_NON_REM	I	Non-Removable Ports Configuration Strap.
Ports
Configuration			This configuration strap controls the number
Strap			of reported non-removable ports. See
			Note 3-13 .
			Note 3-10 Mandatory if		external SPI
			memory is not used for
			firmware execution. If
			external SPI memory is
			used	for	firmware
			execution,		then
			configuration strap resistor
			should be omitted.

If Unused

Float (only if sin- gle-ended clock is connected to CLK_IN)

N/A

Mandatory

Note 3-12

Note 3-10

2018 - 2020 Microchip Technology Inc.

DS00002736D-page 17

USB7252

TABLE 3-1: PIN DESCRIPTIONS (CONTINUED)

	Name	Symbol	Buffer
			Type
	BatteryCharging	CFG_BC_EN	I/O12
	Configuration
	Strap

Device Mode	CFG_STRAP[3:1]	I
Configuration
Straps 3-1

Description			If Unused
Battery Charging Configuration Strap.			Mandatory
			Note 3-12
This configuration strap controls the number
of BC 1.2 enabled downstream ports. See
Note 3-13.
Note 3-11 Mandatory if		external SPI
memory is not used for
firmware execution. If
external SPI memory			is
used	for	firmware
execution,		then
configuration strap resistor
should be omitted.
Device Mode Configuration Straps 3-1.			Mandatory
			Note 3-12

These configuration straps are used to select the device’s mode of operation. See Note 3-13.

		Power/Ground
+3.3V I/O Power	VDD33	P	+3.3 V power and internal regulator input.	Mandatory
Supply Input				Note 3-12
Digital Core	VCORE	P	Digital core power supply input.	Mandatory
Power Supply				Note 3-12
Input
Ground	VSS	P	Common ground.	Mandatory
				Note 3-12

This exposed pad must be connected to the ground plane with a via array.

Note 3-12 Configuration strap values are latched on Power-On Reset (POR) and the rising edge of RESET_N (external chip reset). Configuration straps are identified by an underlined symbol name. Signals that function as configuration straps must be augmented with an external resistor when connected to a load. For additional information, refer to Section 3.3, Configuration Straps and Programmable Functions.

Note 3-13 Pin use is mandatory. Cannot be left unused.

3.3Configuration Straps and Programmable Functions

Configuration straps are multi-function pins that are used during Power-On Reset (POR) or external chip reset (RESET_N) to determine the default configuration of a particular feature. The state of the signal is latched following deassertion of the reset. Configuration straps are identified by an underlined symbol name. This section details the various device configuration straps and associated programmable pin functions.

Note: The system designer must guarantee that configuration straps meet the timing requirements specified in Section 9.6.2, Power-On and Configuration Strap Timing and Section 9.6.3, Resetand Configuration Strap Timing. If configuration straps are not at the correct voltage level prior to being latched, the device may capture incorrect strap values.

DS00002736D-page 18

2018 - 2020 Microchip Technology Inc.

USB7252

3.3.1PORT DISABLE CONFIGURATION (PRT_DIS_P[4:1] / PRT_DIS_M[4:1])

The PRT_DIS_P[4:1] / PRT_DIS_M[4:1] configuration straps are used in conjunction to disable the related port (4-1) For PRT_DIS_Px (where x is the corresponding port 4-1):

0 = Port x D+ Enabled

1 = Port x D+ Disabled

For PRT_DIS_Mx (where x is the corresponding port 4-1): 0 = Port x D- Enabled

1 = Port x D- Disabled

Note: Both PRT_DIS_Px and PRT_DIS_Mx (where x is the corresponding port) must be tied to 3.3 V to disable the associated downstream port. Disabling the USB 2.0 port will also disable the corresponding USB 3.0 port.

3.3.2NON-REMOVABLE PORT CONFIGURATION (CFG_NON_REM)

The CFG_NON_REM configuration strap is used to configure the non-removable port settings of the device to one of five settings. These modes are selected by the configuration of an external resistor on the CFG_NON_REM pin. The resistor options are a 200 kΩ pull-down, 200 kΩ pull-up, 10 kΩ pull-down, 10 kΩ pull-up, and 10 Ω pull-down, as shown in Table 3-2.

3.3.3 BATTERY CHARGING CONFIGURATION (CFG_BC_EN)

TABLE 3-2: CFG_NON_REM RESISTOR ENCODING

CFG_NON_REM Resistor Value	Setting
200 kΩ Pull-Down	All ports removable
200 kΩ Pull-Up	Port 1 non-removable
10 kΩ Pull-Down	Ports 1, 2 non-removable
10 kΩ Pull-Up	Ports 1, 2, 3 non-removable
10 Ω Pull-Down	Ports 1, 2, 3, 4 non-removable

The CFG_BC_EN configuration strap is used to configure the battery charging port settings of the device to one of five settings. These modes are selected by the configuration of an external resistor on the CFG_BC_EN pin. The resistor options are a 200 kΩ pull-down, 200 kΩ pull-up, 10 kΩ pull-down, 10 kΩ pull-up, and 10 Ω pull-down, as shown in Table 3-3.

TABLE 3-3: CFG_BC_EN RESISTOR ENCODING

CFG_BC_EN Resistor Value	Setting
200 kΩ Pull-Down	Battery charging not enable on any port
200 kΩ Pull-Up	BC1.2 DCP and CDP battery charging enabled on Port 1
10 kΩ Pull-Down	BC1.2 DCP and CDP battery charging enabled on Ports 1, 2
10 kΩ Pull-Up	BC1.2 DCP and CDP battery charging enabled on Ports 1, 2, 3
10 Ω Pull-Down	BC1.2 DCP and CDP battery charging enabled on Ports 1, 2, 3, 4

3.3.4PF[31:2] CONFIGURATION (CFG_STRAP[2:1])

The USB7252 provides 30 programmable function pins (PF[31:2]). These pins can be configured to 4 predefined configurations via the CFG_STRAP[2:1] pins. These configurations are selected via external resistors on the CFG_STRAP[2:1] pins,as detailed in Table 3-4. Resistor values and combinationsnotdetailed in Table 3-4 are reserved and should not be used.

2018 - 2020 Microchip Technology Inc.

DS00002736D-page 19

USB7252

Note: CFG_STRAP3 is not used and must be pulled-down to ground via a 200 k resistor.

TABLE 3-4: CFG_STRAP[2:1] RESISTOR ENCODING

	Mode	CFG_STRAP2	CFG_STRAP1
		Resistor Value	Resistor Value
	Configuration 1	200 kΩ Pull-Down	200 kΩ Pull-Down
	Configuration 2	200 kΩ Pull-Down	200 kΩ Pull-Up
	Configuration 3	200 kΩ Pull-Down	10 kΩ Pull-Down
	Configuration 4	200 kΩ Pull-Down	10 kΩ Pull-Up

A summary of the configuration pin assignments for each of the 4 configurations is provided in Table 3-5. For details on behavior of each programmable function, refer to Table 3-6.

	TABLE 3-5:	PF[31:2] FUNCTION ASSIGNMENT
	Pin	Configuration 1	Configuration 2	Configuration 3	Configuration 4
		(SMBus/I2C)	(I2S)	(UART)	(GPIO & FlexConnect)
	PF2	DP1_VCONN1	DP1_VCONN1	DP1_VCONN1	DP1_VCONN1
	PF3	DP1_VCONN2	DP1_VCONN2	DP1_VCONN2	DP1_VCONN2
	PF4	DP2_DISCHARGE	DP2_DISCHARGE	DP2_DISCHARGE	DP2_DISCHARGE
	PF5	DP1_DISCHARGE	DP1_DISCHARGE	DP1_DISCHARGE	DP1_DISCHARGE
	PF6	GPIO70	GPIO70	UART_RX	GPIO70
	PF7	GPIO71	MIC_DET	UART_TX	GPIO71
	PF8	(Note 3-1)	(Note 3-1)	(Note 3-1)	(Note 3-1)
	PF9	(Note 3-1)	(Note 3-1)	(Note 3-1)	(Note 3-1)
	PF10	DP2_VCONN1	DP2_VCONN1	DP2_VCONN1	DP2_VCONN1
	PF11	DP2_VCONN2	DP2_VCONN2	DP2_VCONN2	DP2_VCONN2
	PF12	PRT_CTL3_U3	PRT_CTL3_U3	PRT_CTL3_U3	PRT_CTL3_U3
	PF13	PRT_CTL3	PRT_CTL3	PRT_CTL3	PRT_CTL3
	PF14	GPIO78	I2S_SDI	UART_nCTS	GPIO78
	PF15	PRT_CTL2	PRT_CTL2	PRT_CTL2	PRT_CTL2
	PF16	PRT_CTL4	PRT_CTL4	PRT_CTL4	PRT_CTL4
	PF17	PRT_CTL1	PRT_CTL1	PRT_CTL1	PRT_CTL1
	PF18	(Note 3-1)	(Note 3-1)	(Note 3-1)	(Note 3-1)
	PF19	SLV_I2C_DATA	I2S_SDO	UART_nRTS	GPIO83
	PF20	SPI_CE_N	SPI_CE_N	SPI_CE_N	SPI_CE_N
	PF21	SPI_CLK	SPI_CLK	SPI_CLK	SPI_CLK
	PF22	SPI_D0	SPI_D0	SPI_D0	SPI_D0
	PF23	SPI_D1	SPI_D1	SPI_D1	SPI_D1
	PF24	SPI_D2	SPI_D2	SPI_D2	SPI_D2
	PF25	SPI_D3	SPI_D3	SPI_D3	SPI_D3
	PF26	SLV_I2C_CLK	I2S_SCK	UART_nDSR	GPIO90
	PF27	GPIO91	I2S_MCLK	UART_nDTR	GPIO91
	PF28	GPIO92	I2S_LRCK	UART_nDCD	GPIO92
	PF29	(Note 3-1)	(Note 3-1)	(Note 3-1)	(Note 3-1)
	PF30	MSTR_I2C_CLK	MSTR_I2C_CLK	MSTR_I2C_CLK	MSTR_I2C_CLK
	PF31	MSTR_I2C_DATA	MSTR_I2C_DATA	MSTR_I2C_DATA	MSTR_I2C_DATA

DS00002736D-page 20

2018 - 2020 Microchip Technology Inc.