Microchip USB7216 User Manual

USB7216

6-Port USB 3.2 Gen 2 Type-C® Controller Hub

Highlights

•6-Port USB Smart Hub with:

-Native USB Gen 2 Type-C® support on downstream port 1

-Three Standard USB 3.2 Gen 2 downstream ports

-Two Standard USB 2.0 downstream ports

-Internal Hub Feature Controller enables:

-USB to I2C/SPI/I2S/GPIO bridge endpoint support -USB to internal hub register write and read

•USB Link Power Management (LPM) support

•Programming of firmware image to external SPI memory device from USB host

•USB-IF Battery Charger revision 1.2 support on downstream ports (DCP, CDP, SDP)

•Enhanced OEM configuration options available through either OTP or external SPI memory

•Available in 100-pin (12mm x 12mm) VQFN RoHS compliant package

•Commercial and industrial grade temperature support

Target Applications

•Standalone USB Hubs

•Laptop Docks

•PC Motherboards

•PC Monitor Docks

•Multi-function USB 3.2 Gen 2 Peripherals

Key Benefits

•USB 3.2 Gen 2 compliant 10 Gbps, 5 Gbps, 480 Mbps, 12 Mbps, and 1.5Mbps operation

-5V tolerant USB 2.0 pins

-1.21V tolerant USB 3.2 Gen 2 pins

-Integrated termination and pull-up/down resistors

•Native USB Type-C Support

-Type-C CC Pin with integrated Rp and Rd resistors

-Integrated multiplexer on USB Type-C enabled ports. USB 3.2 Gen 2 PHYs are disabled until a valid Type-C attach is detected, saving idle power.

-Control for external VCONN supply

* USB Type-C® and USB-C® are registered trademarks of USB Implementers Forum.

•Supports battery charging of most popular battery powered devices on all ports

-USB-IF Battery Charging rev. 1.2 support (DCP, CDP, SDP)

-Apple® portable product charger emulation

-Chinese YD/T 1591-2006/2009 charger emulation

-European Union universal mobile charger support

-Supports additional portable devices

•On-chip Microcontroller

-manages I/Os, VBUS, and other signals

•96kB RAM, 256kB ROM

•8kB One-Time-Programmable (OTP) ROM

-Includes on-chip charge pump

•Configuration programming via OTP Memory, SPI external memory, or SMBus

•FlexConnect

-The roles of the upstream and all downstream ports are reversible on command

•Multi-Host Endpoint Reflector

-Integrated host-controller endpoint reflector via CDC/NCM device class for automotive applications

•USB Bridging

-USB to I2C, SPI, I2S, and GPIO

•PortSwap

-Configurable USB 2.0 differential pair signal swap

•PHYBoost

-Programmable USB transceiver drive strength for recovering signal integrity

•VariSense

-Programmable USB receive sensitivity

•USB Power Delivery Billboard Device Support

-Internal port can enumerate as a Power Delivery Billboard device to communicate Power Delivery Alternate Mode negotiation failure cases to host

•Compatible with Microsoft Windows 10, 8, 7, XP, Apple OS X 10.4+, and Linux hub drivers

•Optimized for low-power operation and low thermal dissipation

•100-pin VQFN package (12mm x 12mm)

2018 - 2020 Microchip Technology Inc.

DS00003143B-page 1

USB7216

TO OUR VALUED CUSTOMERS

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2018 - 2020 Microchip Technology Inc.

USB7216

1.0PREFACE

1.1General Terms

TABLE 1-1:	GENERAL TERMS
Term		Description
ADC		Analog-to-Digital Converter
Byte		8 bits
CDC		Communication Device Class
CSR		Control and Status Registers
DFP		Downstream Facing Port
DWORD		32 bits
EOP		End of Packet
EP		Endpoint
FIFO		First In First Out buffer
FS		Full-Speed
FSM		Finite State Machine
GPIO		General Purpose I/O
HS		Hi-Speed
HSOS		High Speed Over Sampling
Hub Feature Controller		The Hub Feature Controller, sometimes called a Hub Controller for short is the internal
		processor used to enable the unique features of the USB Controller Hub. This is not to
		be confused with the USB Hub Controller that is used to communicate the hub status
I2C		back to the Host during a USB session.
		Inter-Integrated Circuit
LS		Low-Speed
lsb		Least Significant Bit
LSB		Least Significant Byte
msb		Most Significant Bit
MSB		Most Significant Byte
N/A		Not Applicable
NC		No Connect
OTP		One Time Programmable
PCB		Printed Circuit Board
PCS		Physical Coding Sublayer
PHY		Physical Layer
PLL		Phase Lock Loop
RESERVED		Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must
		always be zero for write operations. Unless otherwise noted, values are not guaran-
		teed when reading reserved bits. Unless otherwise noted, do not read or write to
		reserved addresses.
SDK		Software Development Kit
SMBus		System Management Bus
UFP		Upstream Facing Port
UUID		Universally Unique IDentifier
WORD		16 bits

2018 - 2020 Microchip Technology Inc.

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USB7216

1.2Buffer Types

TABLE 1-2: BUFFER TYPES

Buffer Type

Description

IInput.

IS	Input with Schmitt trigger.
O12	Output buffer with 12 mA sink and 12 mA source.
OD12	Open-drain output with 12 mA sink
PU	50 μA (typical) internal pull-up. Unless otherwise noted in the pin description, internal pull-
	ups are always enabled.
	Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on internal
	resistors to drive signals external to the device. When connected to a load that must be
	pulled high, an external resistor must be added.
PD	50 μA (typical) internal pull-down. Unless otherwise noted in the pin description, internal
	pull-downs are always enabled.
	Internal pull-down resistors prevent unconnected inputs from floating. Do not rely on
	internal resistors to drive signals external to the device. When connected to a load that
	must be pulled low, an external resistor must be added.
ICLK	Crystal oscillator input pin
OCLK	Crystal oscillator output pin
I/O-U	Analog input/output defined in USB specification.
I-R	RBIAS.

AAnalog.

AIO	Analog bidirectional.

PPower pin.

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USB7216

1.3Pin Reset States

The pin reset state definitions are detailed in Table 1-3. Refer to Section 3.1, Pin Assignments for details on individual pin reset states.

TABLE 1-3: PIN RESET STATE LEGEND

Symbol	Description
AI	Analog input
AIO	Analog input/output
AO	Analog output
PD	Hardware enables pull-down
PU	Hardware enables pull-up

YHardware enables function

ZHardware disables output driver (high impedance)

PU	Hardware enables internal pull-up
PD	Hardware enables internal pull-down

1.4Reference Documents

1.Universal Serial Bus Revision 3.2 Specification, http://www.usb.org

2.Battery Charging Specification, Revision 1.2, Dec. 07, 2010, http://www.usb.org

3.I2C-Bus Specification, Version 1.1, http://www.nxp.com/documents/user_manual/UM10204.pdf

4.I2S-Bus Specification, http://www.sparkfun.com/datasheets/BreakoutBoards/I2SBUS.pdf

5.System Management Bus Specification, Version 1.0, http://smbus.org/specs

Note: Additional USB7216 resources can be found on the Microchip USB7216 product page at www.microchip.com/USB7216.

2018 - 2020 Microchip Technology Inc.

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USB7216

2.0INTRODUCTION

2.1General Description

The Microchip USB7216 hub is a low-power, OEM configurable, USB 3.2 Gen 2 hub controller with 6 downstream ports and advanced features for embedded USB applications. The USB7216 is fully compliant with the Universal Serial Bus Revision 3.2 Specification and USB 2.0 Link Power Management Addendum. The USB7216 supports 10 Gbps SuperSpeed+ (SS+), 5 Gbps SuperSpeed (SS), 480 Mbps Hi-Speed (HS), 12 Mbps Full-Speed (FS), and 1.5 Mbps LowSpeed (LS) USB downstream devices on four standard USB 3.2 Gen 2 downstream ports and only legacy speeds (HS/ FS/LS) on two standard USB 2.0 downstream ports.

The USB7216 is a standard USB 3.2 Gen 2 hub that supports native basic Type-C with integrated CC logic on downstream port 1. The downstream Type-C port includes an internal USB 3.2 Gen 2 multiplexer; no external multiplexer is required for Type-C support.

The USB7216 supports the legacy USB speeds (HS/FS/LS) through a dedicated USB 2.0 hub controller that is the culmination of seven generations of Microchip hub feature controller design and experience with proven reliability, interoperability, and device compatibility. The SuperSpeed hub controller operates in parallel with the USB 2.0 controller, decoupling the 10/5 Gbps SS+/SS data transfers from bottlenecks due to the slower USB 2.0 traffic.

The USB7216 enables OEMs to configure their system using “Configuration Straps.” These straps simplify the configuration process assigning default values to USB 3.2 Gen 2 ports and GPIOs. OEMs can disable ports, enable battery charging and define GPIO functions as default assignments on power up removing the need for OTP or external SPI ROM.

The USB7216 supports downstream battery charging. The USB7216 integrated battery charger detection circuitry supports the USB-IF Battery Charging (BC1.2) detection method and most Apple devices. The USB7216 provides the battery charging handshake and supports the following USB-IF BC1.2 charging profiles:

•DCP: Dedicated Charging Port (Power brick with no data)

•CDP: Charging Downstream Port (1.5A with data)

•SDP: Standard Downstream Port (0.5A[USB 2.0]/0.9A[USB 3.2] with data) Additionally, the USB7216 includes many powerful and unique features such as:

The Hub Feature Controller, an internal USB device dedicated for use as a USB to I2C/SPI/GPIO interface that allows external circuits or devices to be monitored, controlled, or configured via the USB interface.

Multi-Host Endpoint Reflector, which providesuniqueUSB functionality whereby USB datacanbe “mirrored”between two USB hosts (Multi-Host) in order to perform a single USB transaction.This capability is fully covered by Microchip intellectual property (U.S. Pat. Nos. 7,523,243 and 7,627,708) and is instrumental in enabling Apple CarPlay™, where the Apple iPhone® becomes a USB Host.

FlexConnect, which provides flexible connectivity options. One of the USB7216’s downstream ports can be reconfigured to become the upstream port, allowing master capable devices to control other devices on the hub.

PortSwap, which adds per-port programmability to USB differential-pair pin locations. PortSwap allows direct alignment of USB signals (D+/D-) to connectors to avoid uneven trace length or crossing of the USB differential signals on the PCB.

PHYBoost, which provides programmable levels of Hi-Speed USB signal drive strength in the downstream port transceivers. PHYBoost attempts to restore USB signal integrity in a compromised system environment. The graphic on the right shows an example of Hi-Speed USB eye diagrams before and after PHYBoost signal integrity restoration. in a compromised system environment.

VariSense, which controls the Hi-Speed USB receiver sensitivity enabling programmable levels of USB signal receive sensitivity. This capability allows operation in a sub-optimal system environment, such as when a captive USB cable is used.

Port Split, which allows for the USB 3.2 Gen 2 and USB 2.0 portions of downstream ports 2, 3, and 4 in Configuration 1 and downstream port 4 (only) in Configuration 2 to operate independently and enumerate two separate devices in parallel in special applications.

USB Power Delivery Billboard Device, which allows an internal device to enumerate as a Billboard class device when a Power DeliveryAlternate Mode negotiation has failed. The Billboard device will enumerate temporarily to the host PC when a failure occurs, as indicated by a digital signal from an external Power Delivery controller.

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USB7216

The USB7216 can be configured for operation through internal default settings. Custom OEM configurations are supported through external SPI ROM or OTP ROM.All port control signal pins are under firmware control in order to allow for maximum operational flexibility and are available as GPIOs for customer specific use.

The USB7216 is available in commercial (0°C to +70°C) and industrial (-40°C to +85°C) temperature range.An internal block diagram of the USB7216 in an upstream Type-B application is shown in Figure 2-1.

FIGURE 2-1: USB7216 INTERNAL BLOCK DIAGRAM - UPSTREAM TYPE-B APPLICATION

P0

‘B’

+3.3 V

USB7216

PHY0

PHY0

I2C/SPI

VCORE

Hub Controller Logic

USB3

USB2

25 Mhz

PHY1

PHY2

HFC

PHY1

CC

PHY3

PHY3

PHY4

PHY4

PHY5

PHY5

PHY2

PHY6

‘A’

‘B’

PHY

Hub Feature Controller OTP

GPIO SMB SPI I2S

Mux

P1	P2		P3		P4		P5		P6
‘C’	‘A’		‘A’		‘A’		‘A’		‘A’

Note: All port numberingin this documentis LOGICALportnumbering with the device in thedefault configuration. LOGICALport numbering is the numbering as communicated to the USB host. It is the end result after any port number remapping or port disabling. The PHYSICAL port number is the port number with respect to the physical PHY on the chip. PHYSICAL port numbering is fixed and the settings are not impacted by LOGICALport renumbering/remapping. Certain port settings are made with respect to LOGICALport numbering, and other port settings are made with respect to PHYSICAL port numbering. Refer to the “Configuration of USB7202/USB7206/USB725x” application note for details on the LOGICAL vs. PHYSICAL mapping and additional configuration details.

2018 - 2020 Microchip Technology Inc.

DS00003143B-page 7

USB7216

3.0PIN DESCRIPTIONS

3.1Pin Assignments

FIGURE 3-1: USB7216 100-VQFN PIN ASSIGNMENTS

RESET_N 1

PF30 2

PF31 3

DP1_VBUS_MON 4

USB2DN_DP1/PRT_DIS_P1 5

USB2DN_DM1/PRT_DIS_M1 6

USB3DN_TXDP1A 7

USB3DN_TXDM1A 8

VCORE 9

USB3DN_RXDP1A 10

USB3DN_RXDM1A 11

DP1_CC1 12

DP1_CC2 13

USB2DN_DP5/PRT_DIS_P5 14

USB2DN_DM5/PRT_DIS_M5 15

USB3DN_TXDP1B 16

USB3DN_TXDM1B 17

VCORE 18

USB3DN_RXDP1B 19

USB3DN_RXDM1B 20

CFG_STRAP1 21

CFG_STRAP2 22

CFG_STRAP3 23

TESTEN 24

VCORE 25

<![if ! IE]> <![endif]>RBIAS

<![if ! IE]> <![endif]>VDD33

<![if ! IE]> <![endif]>XTALI/CLK IN

<![if ! IE]> <![endif]>XTALO

<![if ! IE]> <![endif]>ATEST

<![if ! IE]> <![endif]>USB3UP RXDM

<![if ! IE]> <![endif]>USB3UP RXDP

<![if ! IE]> <![endif]>VCORE

<![if ! IE]> <![endif]>USB3UP TXDM

<![if ! IE]> <![endif]>USB3UP TXDP

<![if ! IE]> <![endif]>USB2UP DM

<![if ! IE]> <![endif]>USB2UP DP

<![if ! IE]> <![endif]>VDD33

<![if ! IE]> <![endif]>USB3DN RXDM4

<![if ! IE]> <![endif]>USB3DN RXDP4

<![if ! IE]> <![endif]>VCORE

<![if ! IE]> <![endif]>USB3DN TXDM4

<![if ! IE]> <![endif]>USB3DN TXDP4

<![if ! IE]> <![endif]>USB2DN DM4/PRT DIS M4

<![if ! IE]> <![endif]>USB2DN DP4/PRT DIS P4

<![if ! IE]> <![endif]>VBUS MON UP

<![if ! IE]> <![endif]>VDD33

<![if ! IE]> <![endif]>VCORE

<![if ! IE]> <![endif]>PF28

<![if ! IE]> <![endif]>PF27

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Microchip

USB7216

(Top View 100-VQFN)

Thermal slug connects to VSS

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<![if ! IE]> <![endif]>49

<![if ! IE]> <![endif]>50

<![if ! IE]> <![endif]>VDD33

<![if ! IE]> <![endif]>USB2DN DP2/PRT DIS P2

<![if ! IE]> <![endif]>USB2DN DM2/PRT DIS M2

<![if ! IE]> <![endif]>USB3DN TXDP2

<![if ! IE]> <![endif]>USB3DN TXDM2

<![if ! IE]> <![endif]>VCORE

<![if ! IE]> <![endif]>USB3DN RXDP2

<![if ! IE]> <![endif]>USB3DN RXDM2

<![if ! IE]> <![endif]>USB2DN DP3/PRT DIS P3

<![if ! IE]> <![endif]>USB2DN DM3/PRT DIS M3

<![if ! IE]> <![endif]>USB3DN TXDP3

<![if ! IE]> <![endif]>USB3DN TXDM3

<![if ! IE]> <![endif]>VCORE

<![if ! IE]> <![endif]>USB3DN RXDP3

<![if ! IE]> <![endif]>USB3DN RXDM3

<![if ! IE]> <![endif]>USB2DN DM6/PRT DIS M6

<![if ! IE]> <![endif]>USB2DN DP6/PRT DIS P6

<![if ! IE]> <![endif]>VDD33

<![if ! IE]> <![endif]>PF3

<![if ! IE]> <![endif]>PF4

<![if ! IE]> <![endif]>PF5

<![if ! IE]> <![endif]>PF6

<![if ! IE]> <![endif]>PF7

<![if ! IE]> <![endif]>PF8

<![if ! IE]> <![endif]>PF9

75 PF26

74 PF29

73 SPI_D3/PF25

72 SPI_D2/PF24

71 SPI_D1/PF23

70 SPI_D0/CFG_BC_EN/PF22

69 SPI_CE_N/CFG_NON_REM/PF20

68 SPI_CLK/PF21

67 VDD33

66 PF19

65 TEST3

64 TEST2

63 TEST1

62 VDD33

61 PF18

60 PF17

59 PF16

58 PF15

57 PF14

56 PF13

55 VCORE

54 PF12

53 VDD33

52 PF11

51 PF10

Note: Configuration straps are identified by an underlined symbol name. Signals that function as configuration straps must be augmented with an external resistor when connected to a load.

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				USB7216
Pin Num	Pin Name	Reset	Pin Num	Pin Name	Reset
1	RESET_N	Z	51	PF10	PD
2	PF30	Z	52	PF11	PD
3	PF31	Z	53	VDD33	Z
4	DP1_VBUS_MON	AI	54	PF12	PD
5	USB2DN_DP1/PRT_DIS_P1	AIO PD	55	VCORE	Z
6	USB2DN_DM1/PRT_DIS_M1	AIO PD	56	PF13	PD
7	USB3DN_TXDP1A	AO PD	57	PF14	PD
8	USB3DN_TXDM1A	AO PD	58	PF15	PD
9	VCORE	Z	59	PF16	PD
10	USB3DN_RXDP1A	AI PD	60	PF17	PD
11	USB3DN_RXDM1A	AI PD	61	PF18	Z
12	DP1_CC1	AI	62	VDD33	Z
13	DP1_CC2	AI	63	TEST1	Z
14	USB2DN_DP5/PRT_DIS_P5	AIO PD	64	TEST2	Z
15	USB2DN_DM5/PRT_DIS_M5	AIO PD	65	TEST3	Z
16	USB3DN_TXDP1B	AO PD	66	PF19	Z
17	USB3DN_TXDM1B	AO PD	67	VDD33	Z
18	VCORE	Z	68	SPI_CLK/PF21	Z
19	USB3DN_RXDP1B	AI PD	69	SPI_CE_N/CFG_NON_REM/PF20	PU
20	USB3DN_RXDM1B	AI PD	70	SPI_D0/CFG_BC_EN/PF22	Z
21	CFG_STRAP1	Z	71	SPI_D1/PF23	Z
22	CFG_STRAP2	Z	72	SPI_D2/PF24	Z
23	CFG_STRAP3	Z	73	SPI_D3/PF25	Z
24	TESTEN	Z	74	PF29	Z
25	VCORE	Z	75	PF26	Z
26	VDD33	Z	76	PF27	Z
27	USB2DN_DP2/PRT_DIS_P2	AIO PD	77	PF28	Z
28	USB2DN_DM2/PRT_DIS_M2	AIO PD	78	VCORE	Z
29	USB3DN_TXDP2	AO PD	79	VDD33	Z
30	USB3DN_TXDM2	AO PD	80	VBUS_MON_UP	AI
31	VCORE	Z	81	USB2DN_DP4/PRT_DIS_P4	AIO PD
32	USB3DN_RXDP2	AI PD	82	USB2DN_DM4/PRT_DIS_M4	AIO PD
33	USB3DN_RXDM2	AI PD	83	USB3DN_TXDP4	AO PD
34	USB2DN_DP3/PRT_DIS_P3	AIO PD	84	USB3DN_TXDM4	AO PD
35	USB2DN_DM3/PRT_DIS_M3	AIO PD	85	VCORE	Z
36	USB3DN_TXDP3	AO PD	86	USB3DN_RXDP4	AI PD
37	USB3DN_TXDM3	AO PD	87	USB3DN_RXDM4	AI PD
38	VCORE	Z	88	VDD33	Z
39	USB3DN_RXDP3	AI PD	89	USB2UP_DP	AIO Z
40	USB3DN_RXDM3	AI PD	90	USB2UP_DM	AIO Z
41	USB2DN_DM6/PRT_DIS_M6	AIO PD	91	USB3UP_TXDP	AO PD
42	USB2DN_DP6/PRT_DIS_P6	AIO PD	92	USB3UP_TXDM	AO PD
43	VDD33	Z	93	VCORE	Z
44	PF3	Z	94	USB3UP_RXDP	AI PD
45	PF4	Z	95	USB3UP_RXDM	AI PD
46	PF5	Z	96	ATEST	AO
47	PF6	Z	97	XTALO	AO
48	PF7	Z	98	XTALI/CLK_IN	AI
49	PF8	Z	99	VDD33	Z
50	PF9	Z	100	RBIAS	AI

Exposed Pad (VSS) must be connected to ground.

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DS00003143B-page 9

USB7216

3.2Pin Descriptions

This section contains descriptions of the various USB7216 pins. The “_N” symbol in the signal name indicates that the active, or asserted, state occurs when the signal is at a low voltage level. For example, RESET_N indicates that the reset signal is active low. When “_N” is not present after the signal name, the signal is asserted when at the high voltage level.

The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of “active low” and “active high” signal. The term assert, or assertion, indicates that a signal is active, independent of whether that level is represented by a high or low voltage. The term negate, or negation, indicates that a signal is inactive.

The “If Unused” column provides information on how to terminate pins if they are unused in a customer design. Buffer type definitions are detailed in Section 1.2, Buffer Types.

	TABLE 3-1:	PIN DESCRIPTIONS
	Name	Symbol	Buffer	Description	If Unused
			Type
			USB 3.2 Gen 2 Interfaces
	Upstream USB	USB3UP_TXDP	I/O-U Upstream USB 3.2 Gen 2 Transmit Data		Float
	3.2 Gen 2 TX D+			Plus.
	Upstream USB	USB3UP_TXDM	I/O-U Upstream USB 3.2 Gen 2 Transmit Data		Float
	3.2 Gen 2 TX D-			Minus.
	Upstream USB	USB3UP_RXDP	I/O-U Upstream USB 3.2 Gen 2 Receive Data		Weak pull-
	3.2 Gen 2 RX D+			Plus.	down to
					GND
	Upstream USB	USB3UP_RXDM	I/O-U Upstream USB 3.2 Gen 2 Receive Data		Weak pull-
	3.2 Gen 2 RX D-			Minus.	down to
					GND
	Downstream	USB3DN_TXDP1A	I/O-U Downstream USB Type-C® “Orientation A”		Float
	Port 1 USB 3.2			SuperSpeed+ Transmit Data Plus, port 1.
	Gen 2 TX D+
	Orientation A
	Downstream	USB3DN_TXDM1A	I/O-U Downstream USB Type-C “Orientation A”		Float
	Port 1 USB 3.2			SuperSpeed+ Transmit Data Minus, port 1.
	Gen 2 TX D- Ori-
	entation A
	Downstream	USB3DN_RXDP1A	I/O-U Downstream USB Type-C “Orientation A”		Weak pull-
	Port 1 USB 3.2			SuperSpeed+ Receive Data Plus, port 1.	down to
	Gen 2 RX D+				GND
	Orientation A
	Downstream	USB3DN_RXDM1A	I/O-U Downstream USB Type-C “Orientation A”		Weak pull-
	Port 1 USB 3.2			SuperSpeed+ Receive Data Minus, port 1.	down to
	Gen 2 RX D-				GND
	Orientation A
	Downstream	USB3DN_TXDP1B	I/O-U Downstream USB Type-C “Orientation B”		Float
	Port 1 USB 3.2			SuperSpeed+ Transmit Data Plus, port 1.
	Gen 2 TX D+
	Orientation B

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USB7216

TABLE 3-1: PIN DESCRIPTIONS (CONTINUED)

Name	Symbol
Downstream	USB3DN_TXDM1B
Port 1 USB 3.2
Gen 2 TX D-
Orientation B
Downstream	USB3DN_RXDP1B
Port 1 USB 3.2
Gen 2 RX D+
Orientation B
Downstream	USB3DN_RXDM1B
Port 1 USB 3.2
Gen 2 RX D-
Orientation B
Downstream	USB3DN_TXDP[2:4]
Ports 2-4 USB
3.2 Gen 2 TX D+

	Buffer	Description	If Unused
	Type
	I/O-U Downstream USB Type-C “Orientation B”		Float
		SuperSpeed+ Transmit Data Minus, port 1.
	I/O-U Downstream USB Type-C “Orientation B”		Weak pull-
		SuperSpeed+ Receive Data Plus, port 1.	down to
			GND
	I/O-U Downstream USB Type-C “Orientation B”		Weak pull-
		SuperSpeed+ Receive Data Minus, port 1.	down to
			GND
	I/O-U Downstream SuperSpeed+ Transmit Data		Float
		Plus, ports 2 through 4.

Downstream	USB3DN_TXDM[2:4]	I/O-U Downstream SuperSpeed+ Transmit Data	Float
Ports 2-4 USB		Minus, ports 2 through 4.
3.2 Gen 2 TX D-
Downstream	USB3DN_RXDP[2:4]	I/O-U Downstream SuperSpeed+ Receive Data	Weak pull-
Ports 2-4 USB		Plus, ports 2 through 4.	down to
3.2 Gen 2 RX D+			GND
Downstream	USB3DN_RXDM[2:4]	I/O-U Downstream SuperSpeed+ Receive Data	Weak pull-
Ports 2-4 USB		Minus, ports 2 through 4.	down to
3.2 Gen 2 RX D-			GND
		USB 2.0 Interfaces
Upstream USB	USB2UP_DP	I/O-U Upstream USB 2.0 Data Plus (D+).	Mandatory
2.0 D+			Note 3-9
Upstream USB	USB2UP_DM	I/O-U Upstream USB 2.0 Data Minus (D-).	Mandatory
2.0 D-			Note 3-9
Downstream	USB2DN_DP[1:6]	I/O-U Downstream USB 2.0 Ports 1-6 Data Plus	Connect
Ports 1-6 USB		(D+).	directly to
2.0 D+			3.3V
Downstream	USB2DN_DM[1:6]	I/O-U Downstream USB 2.0 Ports 1-6 Data Minus	Connect
Ports 1-6 USB		(D-)	directly to
2.0 D-			3.3V
		SPI Interface
SPI Clock	SPI_CLK	I/O-U SPI clock. If the SPI interface is enabled,	Weak pull-
		this pin must be driven low during reset.	down to
			GND

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USB7216

TABLE 3-1: PIN DESCRIPTIONS (CONTINUED)

	Name	Symbol	Buffer
			Type
	SPI Data 3-0	SPI_D[3:0]	I/O-U

	Description	If Unused
SPI Data 3-0. If the SPI interface is enabled,		Note 3-1
these signals function as Data 3 through 0.
Note 3-1	SPI_D0 operates as the
	CFG_BC_EN strap if
	external SPI memory is not
	used. It must be terminated
	with the selected strap

resistor to 3.3V or GND.

SPI_D[1:3] should be connected to GND through a weak pull-down.

SPI Chip	SPI_CE_N	I/O12 Active low SPI chip enable input. If the SPI				Note 3-2
Enable		interface is enabled, this pin must be driven
		high in powerdown states.
		Note 3-2	Operates	as	the
			CFG_NON_REM strap if
			external SPI memory is not
			used. It must be terminated
			with the	selected	strap

resistor to 3.3V or GND.

USB Type-C Connector Control

Downstream

DP1_VBUS_MON

AIO

Used to detect Type-C VBUS vSafe5V and

Note 3-3

Port 1 Type-C

vSafe0V states on Port 1.Anominal voltage

Voltage Monitor

of 2.7V (2.4V min -3.0V max) is required to

detect the presence of vSafe5V.

Externally, VBUS can be as high as 5.25 V,

which can be damaging to this pin. The

amplitude of VBUS must be reduced by a

voltage divider. The recommended voltage

divider is shown below. 1% tolerance resis-

tors are recommended.

VBUS_P1

DP1_VBUS_MON

43K

<![if ! IE]> <![endif]>49.9K

For proper Type-C port operation, it is criti-

cal that this pin actually be connected to

VBUS of the port through the recommended

resistor divider. This pin should not be tied

permanently to a fixed voltage power rail.

Note 3-3

If unused: Weak pull-down

to GND. This pin may be

left unused if Port 1 is

disabled or reconfigured to

operate in legacy Type-A

mode through hub

configuration.

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USB7216

TABLE 3-1: PIN DESCRIPTIONS (CONTINUED)

	Name	Symbol	Buffer
			Type
	Downstream	DP1_CC1	I/O12
	Port 1 Type-C
	CC1

Downstream	DP1_CC2	I/O12
Port 1 Type-C
CC2

Description	If Unused
Used for Type-C attach and orientation	Note 3-4

detection on Port 1. Includes configurable Rp/Ra selection. Connect this pin directly to the CC1 pin of the respective Type-C connector.

Note 3-4 If unused: Weak pull-down to GND. This pin may only be left unused if Port 1 is disabled or reconfigured to operate in legacy Type-A mode through hub

configuration.
Used for Type-C attach and orientation	Note 3-5
detection on Port 1. Includes configurable

Rp/Ra selection. Connect this pin directly to the CC2 pin of the respective Type-C connector.

Note 3-5 If unused: Weak pull-down to GND. This pin may only be left unused if Port 1 is disabled or reconfigured to operate in legacy Type-A mode through hub configuration.

Upstream

VBUS_MON_UP

I/O12 Used to detect VBUS on the upstream port.

Mandatory

Voltage Monitor

Externally, VBUS can be as high as 5.25 V,

Note 3-9

which can be damaging to this pin. A nomi-

nal voltage of 2.7V (2.4V min -3.0V max) is

required to detect the presence of vSafe5V.

The amplitude of VBUS must be reduced by

avoltage divider.The recommendedvoltage

divider is shown below. 1% tolerance resis-

tors are recommended.

VBUS_UP

VBUS_MON_UP

43K

<![if ! IE]> <![endif]>49.9K

Note: For embedded hostapplications, this pin should be controlled by an I/O on the host processor to a 2.68V logic level.

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USB7216

TABLE 3-1:	PIN DESCRIPTIONS (CONTINUED)
Name		Symbol	Buffer		Description		If Unused
			Type
			Miscellaneous
Programmable		PF[31:3]	I/O12	Programmable function pins.			Note 3-6
Function Pins				Note 3-6	If unused: depends on the
					configured pin function.
					Refer to	Section 3.3.4,
					PF[31:3]	Configuration
					(CFG_STRAP[2:1])
Test 1		TEST1	A	Test 1 pin.			Pullto3.3V
							through a
				This signal is used for test purposes and			10 k
				must always be pulled-up to 3.3V via a 10			resistor
				k resistor.
Test 2		TEST2	A	Test 2 pin.			Pullto3.3V
							through a
				This signal is used for test purposes and			10 k
				must always be pulled-up to 3.3V via a 10			resistor
				k resistor.
Test 3		TEST3	A	Test 3 pin.			Pullto3.3V
							through a
				This signal is used for test purposes and			10 k
				must always be pulled-up to 3.3V via a 10			resistor
				k resistor.
Reset Input		RESET_N	IS	This active low signal is used by the system			Mandatory
				to reset the device.			Note 3-9
Bias Resistor		RBIAS	I-R	A 12.0 k 1.0% resistor is attached from			Mandatory
				ground to this pin to set the transceiver’s			Note 3-9
				internal bias settings. Place the resistor as
				close the device as possible with a dedi-
				cated, low impedance connection to the
				ground plane.
Test		TESTEN	I/O12	Test pin.			Connect to
				This signal is used for test purposes and			GND
				must always be connected to ground.
Analog Test		ATEST	A	Analog test pin.			Float
				This signal is used for test purposes and
				must always be left unconnected.
External 25 MHz		XTALI	ICLK	External 25 MHz crystal input			Mandatory
Crystal Input							Note 3-9
External 25 MHz		CLK_IN	ICLK	External reference clock input.			Mandatory
ReferenceClock							Note 3-9
Input				The device may alternatively be driven by a
				single-ended clock oscillator. When this
				method is used, XTALO should be left
				unconnected.

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USB7216

TABLE 3-1: PIN DESCRIPTIONS (CONTINUED)

	Name	Symbol	Buffer	Description
			Type
	External 25 MHz	XTALO	OCLK External 25 MHz crystal output
	Crystal Output

		Configuration Straps
Port 6-1 D+	PRT_DIS_P[6:1]	I	Port 6-1 D+ Disable Configuration Strap.
Disable			These configuration straps are used in con-
Configuration
Strap			junction with the corresponding
			PRT_DIS_M[6:1] straps to disable the
			related port (6-1). See Note 3-10.
			Both USB data pins for the corresponding
			port must be tied to 3.3V to disable the
			associated downstream port.
Port 6-1 D-	PRT_DIS_M[6:1]	I	Port 6-1 D- Disable Configuration Strap.
Disable
Configuration			These configuration straps are used in con-
Strap			junction with the corresponding
			PRT_DIS_P[6:1] straps to disable the
			related port (6-1). See Note 3-10.
			Both USB data pins for the corresponding
			port must be tied to 3.3V to disable the
			associated downstream port.
Non-Removable	CFG_NON_REM	I	Non-Removable Ports Configuration Strap.
Ports
Configuration			This configuration strap controls the number
Strap			of reported non-removable ports. See
			Note 3-10 .
			Note 3-7	Mandatory if		external SPI
				memory is not used for
				firmware execution. If
				external SPI memory is
				used	for	firmware
				execution,		then
				configuration strap resistor
				should be omitted.

If Unused

Float (only if sin- gle-ended clock is connected to CLK_IN)

N/A

Mandatory

Note 3-9

Note 3-7

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USB7216

TABLE 3-1: PIN DESCRIPTIONS (CONTINUED)

	Name	Symbol	Buffer
			Type
	BatteryCharging	CFG_BC_EN	I/O12
	Configuration
	Strap

Device Mode	CFG_STRAP[3:1]	I
Configuration
Straps 3-1

	Description			If Unused
Battery Charging Configuration Strap.				Mandatory
				Note 3-9
This configuration strap controls the number
of BC 1.2 enabled downstream ports. See
Note 3-10.
Note 3-8	Mandatory if		external SPI
	memory is not used for
	firmware execution. If
	external SPI memory			is
	used	for	firmware
	execution,		then
	configuration strap resistor
	should be omitted.
Device Mode Configuration Straps 3-1.				Mandatory
				Note 3-9

These configuration straps are used to select the device’s mode of operation. See Note 3-10.

		Power/Ground
+3.3V I/O Power	VDD33	P	+3.3 V power and internal regulator input.	Mandatory
Supply Input				Note 3-9
Digital Core	VCORE	P	Digital core power supply input.	Mandatory
Power Supply				Note 3-9
Input
Ground	VSS	P	Common ground.	Mandatory
				Note 3-9

This exposed pad must be connected to the ground plane with a via array.

Note 3-9 Configuration strap values are latched on Power-On Reset (POR) and the rising edge of RESET_N (external chip reset). Configuration straps are identified by an underlined symbol name. Signals that function as configuration straps must be augmented with an external resistor when connected to a load. For additional information, refer to Section 3.3, Configuration Straps and Programmable Functions.

Note 3-10 Pin use is mandatory. Cannot be left unused.

3.3Configuration Straps and Programmable Functions

Configuration straps are multi-function pins that are used during Power-On Reset (POR) or external chip reset (RESET_N) to determine the default configuration of a particular feature. The state of the signal is latched following deassertion of the reset. Configuration straps are identified by an underlined symbol name. This section details the various device configuration straps and associated programmable pin functions.

Note: The system designer must guarantee that configuration straps meet the timing requirements specified in Section 9.6.2, Power-On and Configuration Strap Timing and Section 9.6.3, Resetand Configuration Strap Timing. If configuration straps are not at the correct voltage level prior to being latched, the device may capture incorrect strap values.

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USB7216

3.3.1PORT DISABLE CONFIGURATION (PRT_DIS_P[6:1] / PRT_DIS_M[6:1])

The PRT_DIS_P[6:1] / PRT_DIS_M[6:1] configuration straps are used in conjunction to disable the related port (6-1) For PRT_DIS_Px (where x is the corresponding port 6-1):

0 = Port x D+ Enabled

1 = Port x D+ Disabled

For PRT_DIS_Mx (where x is the corresponding port 6-1): 0 = Port x D- Enabled

1 = Port x D- Disabled

Note: Both PRT_DIS_Px and PRT_DIS_Mx (where x is the corresponding port) must be tied to 3.3 V to disable the associated downstream port. Disabling the USB 2.0 port will also disable the corresponding USB 3.0 port.

3.3.2NON-REMOVABLE PORT CONFIGURATION (CFG_NON_REM)

The CFG_NON_REM configuration strap is used to configure the non-removable port settings of the device to one of six settings. These modes are selected by the configuration of an external resistor on the CFG_NON_REM pin. The resistor options are a 200 kΩ pull-down, 200 kΩ pull-up, 10 kΩ pull-down, 10 kΩ pull-up, 10 Ω pull-down, and 10 Ω pullup, as shown in Table 3-2.

TABLE 3-2: CFG_NON_REM RESISTOR ENCODING

CFG_NON_REM Resistor Value		Setting
200 kΩ Pull-Down		All ports removable
200 kΩ Pull-Up		Port 1 non-removable
10 kΩ Pull-Down		Ports 1, 2 non-removable
10 kΩ Pull-Up		Ports 1, 2, 3 non-removable
10	Ω Pull-Down	Ports 1, 2, 3, 4 non-removable
10	Ω Pull-Up	Ports 1, 2, 3, 4, 5, 6 non-removable

3.3.3BATTERY CHARGING CONFIGURATION (CFG_BC_EN)

The CFG_BC_EN configuration strap is used to configure the battery charging port settings of the device to one of six settings. These modes are selected by the configuration of an external resistor on the CFG_BC_EN pin. The resistor options are a 200 kΩ pull-down, 200 kΩ pull-up, 10 kΩ pull-down, 10 kΩ pull-up, 10 Ω pull-down, and 10 Ω pull-up, as shown in Table 3-3.

TABLE 3-3: CFG_BC_EN RESISTOR ENCODING

	CFG_BC_EN Resistor Value	Setting
200 kΩ Pull-Down		Battery charging not enable on any port
200 kΩ Pull-Up		BC1.2 DCP and CDP battery charging enabled on Port 1
10 kΩ Pull-Down		BC1.2 DCP and CDP battery charging enabled on Ports 1, 2
10 kΩ Pull-Up		BC1.2 DCP and CDP battery charging enabled on Ports 1, 2, 3
10	Ω Pull-Down	BC1.2 DCP and CDP battery charging enabled on Ports 1, 2, 3, 4
10	Ω Pull-Up	BC1.2 DCP and CDP battery charging enabled on Ports 1, 2, 3, 4, 5, 6

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USB7216

3.3.4PF[31:3] CONFIGURATION (CFG_STRAP[2:1])

The USB7216 provides 29 programmable function pins (PF[31:3]). These pins can be configured to 2 predefined configuration via the CFG_STRAP[2:1] pins. These configurations are selected via external resistors on the CFG_STRAP[2:1] pins,as detailed in Table 3-4. Resistor values and combinationsnotdetailed in Table 3-4 are reserved and should not be used.

Note: CFG_STRAP3 is not used and must be pulled-down to ground via a 200 k resistor.

TABLE 3-4: CFG_STRAP[2:1] RESISTOR ENCODING

	Mode	CFG_STRAP2	CFG_STRAP1
		Resistor Value	Resistor Value
	Configuration 1	200 kΩ Pull-Down	200 kΩ Pull-Down
	Configuration 2	200 kΩ Pull-Down	200 kΩ Pull-Up

A summary of the configuration pin assignments for each of the 2 configurations is provided in Table 3-5. For details on behavior of each programmable function, refer to Table 3-6.

TABLE 3-5: PF[31:3] FUNCTION ASSIGNMENT

	Pin	Configuration 1	Configuration 2
		(SMBus/I2C)	(I2S)
PF3		DP1_VCONN2	DP1_VCONN2
PF4		DP1_VCONN1	DP1_VCONN1
PF5		DP1_DISCHARGE	DP1_DISCHARGE
PF6		GPIO70	GPIO70
PF7		GPIO71	MIC_DET
PF8		GPIO72	GPIO72
PF9		GPIO73	GPIO73
PF10		PRT_CTL2_U3	I2S_SDI
PF11		PRT_CTL3_U3	I2S_MCLK
PF12		PRT_CTL4_U3	PRT_CTL4_U3
PF13		PRT_CTL4	PRT_CTL4
PF14		PRT_CTL3	PRT_CTL3
PF15		PRT_CTL2	PRT_CTL2
PF16		PRT_CTL5	PRT_CTL5
PF17		PRT_CTL1	PRT_CTL1
PF18		ALERT0	ALERT0
PF19		-	I2S_SDO
PF20		SPI_CE_N	SPI_CE_N
PF21		SPI_CLK	SPI_CLK
PF22		SPI_D0	SPI_D0
PF23		SPI_D1	SPI_D1
PF24		SPI_D2	SPI_D2
PF25		SPI_D3	SPI_D3
PF26		SLV_I2C_CLK	I2S_SCK
PF27		SLV_I2C_DATA	PRT_CTL6
PF28		PRT_CTL6	I2S_LRCK
PF29		(Note 3-1)	(Note 3-1)

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USB7216

TABLE 3-5: PF[31:3] FUNCTION ASSIGNMENT (CONTINUED)

	Pin	Configuration 1	Configuration 2
		(SMBus/I2C)	(I2S)
PF30		MSTR_I2C_CLK	MSTR_I2C_CLK
PF31		MSTR_I2C_DATA	MSTR_I2C_DATA

Note 3-1 The default function is not used in the USB7216.

Note: The default PFx pin functions can be overridden with additional configuration by modification of the pin mux registers. These changes can be made during the SMBus configuration stage, by programming to OTP memory, or during runtime (after hub has attached and enumerated) by register writes via the SMBus slave interface or USB commands to the internal Hub Feature Controller Device.

2018 - 2020 Microchip Technology Inc.

DS00003143B-page 19