MICROCHIP TC7109, TC7109A Technical data

TC7109/A

12-Bit µA-Compatible Analog-to-Digital Converters

Features

• Zero Integrator Cycle forFast Recovery from Input Overloads

• Eliminates Cross-Talk in Multiplexed Systems

• 12-Bit Plus Sign Integrating A/D Converter with Over Range Indication

• Sign Magnitude Coding Format

• True DifferentialSignal Input and Differential Reference Input

• Low Noise: 15µV

• Input Current: 1pA Typ.

• No Zero Adjustment needed

• TTL Compatible, Byte Organized Tri-State Outputs

• UART Handshake Mode for simple Serial Data Transmissions

P-P

Typ.

Device Selection Table

PartNumber

(TC7109X)*

TC7109CKW 44-Pin PQFP 0°C to +70°C

TC7109CLW 44-Pin PLCC 0°Cto +70°C

TC7109CPL 40-PinPDIP 0°C to +70°C

TC7109IJL 40-PinCERDIP -25°Cto +85°C

*The “A” version has a higher I

Package

OUT

Temperature

Range

on the digital lines.

General Description

The TC7109A is a 12-bit plus sign, CMOS low power analog-to-digital converter (ADC). Only eight passive components and a crystal are required to form a complete dual slope integrating ADC.

TheimprovedV featuresmakeitan attractiveper-channelalternativeto analog multiplexing for many data acquisition applications. These features include typical input bias current of 1pA, drift of less than 1µV/°C, input noise t ypically 15µV erence allow measurement of bridge typetransducers, such as load cells, strain gauges, and temperature transducers.

The TC7109A provides a versatile digital interface. In the Direct mode, chip select and HIGH enable control parallel bus interface.In the Handshake mode, the TC7109Awill operate with industry standard UART sin controlling serial data transmission – ideal for remote data logging. Controland monitoring of conversion timing is provided by the RUN/HOLD STATUS output.

For applications requiring more resolution, see the TC500, 15-bit plus sign ADC datasheet.The TC7109A has improved over range recovery performance and higher output drive capability than the original TC7109. All new (or existing) designs should specify the TC7109A wherever possible.

, and auto-zero. True differential input and ref-

P-P

source current and other TC7109A

/LOW byte

input and

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2002 Microchip TechnologyInc. DS21456B-page 1

TC7109/A

Package Type

44 43 42 41 39 3840

12 13 14 15 17 18

TEST

44-Pin PQFP

STATUS

POL

GND

TC7109ACKW

TC7109CKW

LBEN

HBEN

CE/LOAD

REF CAP-

REF IN-

V+

37 36 35 34

19 20 21 22

MODE

OSC IN

OSC OUT

REF IN+

REF CAP+

268

259

2410

2311

BUFF

OSC SEL

OSC OUT

IN HI

IN LO

COMMON

INT

BUFF

REF OUT

V-

SEND

RUN/HOLD

40-Pin PDIP/CERDIP

44-Pin PLCC

6543 1442

18 19 20 21 23 24

TEST

POL

LBEN

STATUS

TC7109ACLW

TC7109CLW

HBEN

GND

CE/LOAD

V+

43 42 41 40

25 26 27 28

MODE

REF CAP-

REF IN-

OSC IN

OSC OUT

REF IN+

REF CAP+

3214

3115

3016

2917

BUFF

OSC SEL

OSC OUT

IN HI

IN LO

COMMON

INT

BUFF

REF OUT

V-

SEND

RUN/HOLD

GND

STATUS

CE/LOAD

POL

TEST

LBEN

HBEN

TC7109A

NC = No internal connection

TC7109

V+

REF IN-

REF CAP-

REF CAP+

REF IN+

IN HI

IN LO

COMMON

INT

BUFF

REF OUT

V-

SEND

RUN/HOLD

BUFF OSC OUT

OSC SEL

OSC OUT

OSC IN

MODE

DS21456B-page 2

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2002 Microchip TechnologyInc.

Typical Application

REF

IN+

CAP+

37 36

AZZIAZ

INT

Input High

Common

Input Low

INT

DE (±)

(–)DE(+)

(+)

DE (–)

TC7109/A

POL

TEST

Conversion

Control Logic

High Order Byte Inputs

B9B8B7B6B5B4B3B2B

B12B11B

16 Three-State Outputs

14 Latches

12-Bit Counter

Oscillator and

Clock Circuitry

Latch

Clock

Low Order

Byte Inputs

15 16

Handshake

Logic

LBEN

HBEN

CE/LOAD

TC7109A

REF

IN-

INT

REF CAP-

3839

Buffer

–

10µA

–

6.2V

BUFF

3130

Integrator

–

To Analog

Section

INT

Comparator

Comp Out

INT

DE (±)

17 3 4 5 6 7 8 9 10 11 12 13 14

Comp Out

28 40

REF

V-

OUT

226222324

OSC

RUN/

V+

Status

HOLD

OSC

OUT

OSC

SEL

BUFF

OSC OUT

Mode

Send

GND

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2002 Microchip TechnologyInc. DS21456B-page 3

TC7109/A

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings*

Positive Supply Voltage (GND to V+)..................+6.2V

*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affectdevice reliability.

Negative Supply Voltage ( GND to V-).....................-9V

Analog Input Voltage (Low to High)

(Note 1)

....V+ to V-

Reference Input Voltage:

(Low to High) (Note 1) ............................. V+ to V-

Digital Input Voltage:

(Pins 2-27) (Note 2) ...........................GND – 0.3V

Power Dissipation, T

< 70°C (Note 3)

CerDIP ........................................................2.29W

Plastic DIP ..................................................1.23W

PLCC ..........................................................1.23W

PQFP ..........................................................1.00W

Operating Temperature Range

Plastic Package (C) .........................0°C to +70°C

Ceramic Package (I) .....................-25°C to +85°C

StorageTemperature Range..............-65°C to +150°C

TC7109/TC7109A ELECTRICA L SPECIFICATIONS

Electrical Characteristics: All parameters with V+ = +5V, V-= -5V, GND = 0V, TA= +25°C, unless otherwise indicated. Symbol Parameter Min Typ Max Unit Test Conditions

Analog

Overload Recovery Time (TC7109A) — 0 1 Measurement

Cycle Zero InputReading -0000 Ratio Metric Reading 3777

NL Non-Linearity (Max Deviation

from Best Straight Line Fit)

Rollover Error (Differencein Readingfor Equal Positive and Inputs near (Full Scale)

CMRR Input Common Mode

Rejection Ratio

CMR

TC TC

Note 1: Input voltages may exceed supply voltages if input current is limited to ±100µA.

CommonMode Voltage Range V-+1.5 — V+ -1.5 V Input High, InputLow and

Noise (P-P Value Not Exceeded 95% of Time)

Leakage Current at Input — 1 10 pA VIN, All Packages: +25°C

Zero Reading Drift — 0.2 1 µV/°C VIN=0V

Scale Factor Temperature Coefficient — 1 5 µV/°C VIN= 408.9mV = >7770

2: Connecting any digital inputs or outputsto voltages greater than V+ or less than GND may cause destructive device

latchup. Therefore, it is recommended that inputsfrom sources other than the same power supply shouldnotbe applied to the TC7109A beforeitspowersupply is established. In multiple supply systems, the supply to the device should be activated first.

3: Thislimit refers to that of thepackage and will not occur during normal operation.

±00008+00008Octal Reading VIN= 0V; Full Scale = 409.6mV

3777

4000

-1 ±0.2 +1 Count Full Scale = 409.6mV to 2.048V

-1 ±0.02 +1 Count Full Scale = 409.6mV to

—50 — µV/V V

—15 — µVVIN= 0V,Full Scale = 409.6mV

— 20 100 pA C Device:0°C≤ T — 100 250 pA I Device: -25°C ≤ T

40008Octal Reading VIN=V

8 8

REF

=204.8mV

REF

Over Full Operating T emperature Range

2.048VOver Full Operating T emperature Range

±1V, VIN=0V

Full Scale = 409.6mV

Common Pins

≤ +70°C

Reading,ExtRef = 0ppm/°C

≤ +85°C

DS21456B-page 4

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2002 Microchip TechnologyInc.

TC7109/A

TC7109/TC7109A ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: All parameters with V+ = +5V, V-= -5V, GND = 0V, TA= +25°C, unless otherwise indicated. Symbol Parameter Min Typ Max Unit Test Conditions

REF

Digital

Note 1: Input voltages may exceed supply voltages if input current is limited to ±100µA.

Supply Current (V+ to GND) — 700 1500 µAVIN= 0V, Crystal Oscillator

3.58MHzTestCircuit

Supply Current (V+ to V-) — 700 1500 µA Pins 2-21, 25, 26, 27, 29 Open Reference Out Voltage -2.4 -2.8 -3.2 V Referenced to V+, 25kΩ

Between V+ and Ref Out

Ref Out Temperature Coefficient — 80 — ppm/°C 25kΩ Between V+ and Ref Out

REF

OutputHighVoltage I

=700µA

OUT

3.5 4.3 — V TC7109: I

OutputLowVoltage — 0.2 0.4 µAI

0°C ≤ T

Pins 3 -16, 18, 19,20 TC7109A: I

OUT

≤ +70°C

OUT

=1.6mA

=100µA

=700µA

OutputLeakage Current — ±0.01 ±1 µA P ins 3 -16 High Impedance Control I /O Pull-up Current — 5 — µF Pins 18, 19, 20 V

Mode Input at GND

Control I/O Loading — — 50 pF HBEN

,Pin19;LBEN,Pin18

InputHighVoltage 2.5 — — V Pins 18 -21, 26, 27

Referenced to GND

Input Low Voltage — — 1 V Pins 18-21, 26, 27

Referenced to GND

Input Pull-up Current —

— Input Pull-down Current — 1 — µAPins21,V Oscillator OutputCurrent, High — 1 — mA V Oscillator OutputCurrent, Low — 1.5 — mA V Buffered Oscillator Output Current High — 2 — mA V

Buffered Oscillator Output Current Low — 5 — mA V

— —

µA µA

Pins 26, 27; V Pins 17, 24; V

OUT

–2.5V

OUT

–2.5V

OUT

–2.5V

OUT

–2.5V

OUT

OUT OUT

=GND=+3V

Mode Input Pulse Width 60 — — nsec

2: Connecting any digital inputs or outputsto voltages greater than V+ or less than GND may cause destructive device

3: Thislimit refers to that of thepackage and will not occur during normal operation.

=V+–3V

OUT

=V+–3V =V+– 3V

HANDLING PRECAUTIONS: Thesedevices are CMOS andmust be handledcorrectlyto prevent damage. Package

and store only in conductive foam, antistatic tubes, or other conductingmaterial. Use proper antistatic handling procedures. Do not connectin circuits under "power-on" conditions, as high transients may cause permanent damage.

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2002 Microchip TechnologyInc. DS21456B-page 5

TC7109/A

2.0 PIN DESCRIPTIONS

ThedescriptionsofthepinsarelistedinTable2-1.

TABLE 2-1: PIN FUNCTION TABLE

Pin Number

(40-Pin PDIP)

1 GND Digital ground, 0V, ground return for all digital logic. 2 STATUS Output HIGH during integrate and de-integrate until datais latched. Output LOW when

3 POL Polarity - High for positive input. 4 OR Over Range - High if over ranged (Three-State Data bit). 5B 6B 7B 8B

9B 10 B 11 B 12 B 13 B 14 B 15 B 16 B 17 TEST Input High - Normal operation. Input LOW - Forces all bit outputs HIGH.

18 LBEN

19 HBEN

20 CE

21 MODE Input LOW - DirectOutputmodewhereCE

Symbol Description

analogsection is in auto-zero or zero integrator configuration.

12 11 10

9 8 7 6 5 4 3 2 1

Bit 12 (Most Significant bit) (Three-State Data bit). Bit 11 (Three-State Data bit). Bit10(Three-StateDatabit). Bit 9 (Three-State Data bit). Bit 8 (Three-State Data bit). Bit 7 (Three-State Data bit). Bit 6 (Three-State Data bit). Bit 5 (Three-State Data bit). Bit 4 (Three-State Data bit). Bit 3 (Three-State Data bit). Bit 2 (Three-State Data bit). Bit 1 (Least Significant bit) (Three-State Data bit).

Note: This input is used for test purposes only. Low Byte Enable - with MODE (Pin 21) LOW, and CE/LOAD (Pin 20) LOW, taking this pin

LOW activates low order byte outputs,B low byte flag outputused in Handshakemode. (SeeFigure 3-7, Figure 3-8, and Figure 3-9.)

. With MODE (Pin 21) HIGH, this pin serves as

1–B8

High Byte Enable - with MODE (Pin 2 1) LOW, and CE/LOAD (Pin 20) LOW, taking this pin LOW activates high order byte outputs, B pin serves as high byte flag output used in Handshakemode.See Figures3-7,3-8,and3-9.

, POL, OR. With MODE (Pin 21) HIGH, this

9–B12

/LOAD Chip Enable/Load - with MO DE (Pin 21) LOW, CE/LOAD servesas a master output enable.

When HIGH,B strobeis used in handshakemode. (See Figure 3-7, Figure 3-8, and Figure 3-9.)

, POL, OR outputs are disabled. When MODE (Pin 21) is HIGH, a load

1–B12

/LOAD(Pin 20), HBEN (Pin 19), and LBEN (Pin

18) act as inputs directlycontrolling byte outputs. InputP ulsed H IGH - Causes immediate entryintoHandshake mode and output of data as in Figure3-9.

Input HIGH- enablesCE

/LOAD (Pin 20), HBEN (Pin 19), and LBEN (Pin 18) as outputs, Handshake mode will be entered and data output as in Figure 3-7 and Figure 3-9 at conversions completion.

22 OSC IN Oscillator Input. 23 OSC OUT Oscillator Output. 24 OSC SEL Oscillator Select - Input HIGH configures OSC IN, OSC OUT ,BUFF OSC OUT as RC

oscillator - clock will be same phase and duty cycle as BUFF OSC OUT. Input LOW configures OSC IN, OSC OUT for crystal oscillator - clock frequency will be 1/58 of frequency at BUFF OSC OUT.

25 BUFFOSC OUT BufferedOscillator Output. 26 RUN/HOLD

Input HIGH - Conversionscontinuously performed every 8192clockpulses. InputLOW-Conversionin progress completed; converterwill stop in auto-zero seven counts beforeintegrate.

27 SEND Input- Used in Handshake mode to indicateability of an external device to accept data.

Connect to V+ if not used.

28 V- Analog Negative Supply - Nominally -5V with respect to GND (Pin 1). 29 REF OUT Reference Voltage Output - Nominally 2.8V down from V+ (Pin 40).

DS21456B-page 6

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2002 Microchip TechnologyInc.

TABLE 2-1: PIN FUNCTION TABLE (CONTINUED)

Pin Number

(40-Pin PDIP)

30 BUFF Buffer Amplifier Output. 31 AZ Auto-Zero Node - Inside foil of C 32 INT Integrator Output - Outside foil of C 33 COMMON Analog Common - System is auto-zeroedto COMMON. 34 IN LO Differential Input Low Side. 35 IN HI Differential Input High Side. 36 REF IN+ Differential Reference Input Positive. 37 REF CAP+ Reference Capacitor Positive. 38 REF CAP- Reference Capacitor Negative. 39 REF IN- Differential Reference Input Negative. 40 V+ Positive Supply Voltage - Nominally +5V with respectto GND (Pin 1).

Note: All Digital levels are positive true.

Symbol Description

INT

TC7109/A

3.0 DETAILED DESCRIPTION

(All Pin Designations Refer to 40-Pin DIP.)

3.1 Analog Section

The Typical Application diagram on page 3 shows a block diagram of the analog section of the TC7109A. The circuit will perform conversions at a rate determined by the clock frequency (8192 clock periods per cycle), when the RUN/HOLD nected to V+. Each measurement cycle is divided into four phases, as shown in Figure 3- 1. They are: (1) Auto-Zero (AZ), (2) Signal Integrate (INT), (3) Reference De-integrate (DE), and (4) Zero Integrator (ZI).

3.1.1 AUTO-ZERO PHASE

The buffer and the integrator inputs are disconnected from input high and input low and connected to analog common.The reference capacitorischargedto the reference voltage. A feedback loop is closed around the system to charge the auto-zero capacitor, C pensate for offset voltage in the buffer amplifier, i ntegrator, and comparator. Since the comparator is included in the l oop, the AZ accuracy is limited only by the noise of the system. The offset referred to the input is less than 10µV.

input is left open or con-

,tocom-

3.1.2 SIGNAL INTEGRATE PHASE

The bufferandintegrator inputsareremovedfrom common and connected to input high and input low. The auto-zero loop is opened. The auto-zero capacitor is placed in series in the loop to provide an equal and opposite compensating offset voltage. The differential voltage between input high and input low is integrated for a fixedtime of 2048 clock periods. At the end of this phase, the polarity of the integrated signal is determined. If the input signal has no return to the converter's power supply, input low can be tied to analog common to establish the correct Common mode voltage.

3.1.3 DE-INTEGRATE P HA SE

Input high i s connected across the previously charged reference capacitor and input low is internally connected to analog common. Circuitry within the chip ensuresthecapacitor will be connectedwiththecorrect polarity to cause the integrator output to return to the zero crossing (established by auto-zero), with a fixed slope. The time, represented by the number of clock periods counted for the output to return to zero, is proportionalto the input signal.

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2002 Microchip TechnologyInc. DS21456B-page 7

TC7109/A

3.1.4 Z ERO INTEGRATOR PHASE

The ZI phase only occurs when an input over range condition exists. The function of the ZI phase is to eliminateresidualchargeon the integratorcapacitorafteran overrangemeasurement.Unless removed,the residual chargewillbe transferredto the auto-zerocapacitorand cause an errorin the succeeding conversion.

The ZI phase virtually eliminates hysteresis, or "crosstalk" in multiplexed systems. An over range input on one channel will not cause an erroron the next channel measured. This feature is especially useful in thermocouple measurements, where unused (or broken t hermocouple) inputs are pulled to the positive supply rail.

During ZI, the referencecapacitorischargedto the reference voltage. The signal inputs are disconnected fromthebufferandintegrator.Thecomparatoroutputis connected to the buffer input, causing the integrator output to be driven rapidly to 0V (Figure 3-1). The ZI phase only occurs following an overrange and lasts for a maximum of 1024 clock periods.

3.1.5 DIFFERENTIAL INPUT

The TC7109A has been optimized for operation with analog common near digital ground. With +5V and -5V power supplies, a full ±4V full scale integrator swing maximizes the analog section's performance.

A typical CMRR of 86dB is achieved for input differential voltages anywhere within the typical Comm on mode range of 1V below the positive supply, to 1.5V above the negative supply. However, for optimum performance, the IN HI and IN LO inputs should not come within 2V of either supply rail. Since the integrator also swings with the Common mode voltage, care must be exercised to ensure the integrator output does not saturate. A worst case condition is near a full scale negative differential input voltage with a large positive Common mode voltage. The negative input signal drives the integrator positive when most of its swing has been used up by the positive Common mode voltage. In such cases, the integrator swing can be reduced to less than the recommended ±4V full scale value, with some loss of accuracy. The integrator output can swing to within 0.3V of either supply without loss of linearity.

3.1.6 DIFFERENTIAL REFERENCE

The reference voltage can be generated anywhere within the power supply voltage of the converter. Rollover voltage is the main source of Common mode error, caused by the referencecapacitorlosingor gaining charge, due to stray capacity on its nodes. With a large Common mode voltage, the reference capacitor can gain charge (increasevoltage) when called upon to de-integrate a positive signal and lose charge (decrease voltage) when called upon to de-integrate a negative input signal. This difference in reference for (+) or (–) i nput voltages will causea rollovererror. This error can be held to less than 0.5 count, worst case, by using a large r eference capacitor in comparison to the stray capacitance. To minimize rollover error from these sources, keep the reference Common mode voltage near or at analog common.

3.2 Digital Section

The di gital section is shown in Figure 3-2 and includes the clock oscillator and scaling circuit, a 12-bit binary counter with output latches and TTL compatible threestate output drivers, UART handshake logic, polarity, over range, and control logic. Logic levels are referred to as LOW or HIGH.

Inputs driven from TTL gates should have 3kΩ to 5kΩ pull-up resistors added for maximum noise immunity. For minimum power consumption, all inputs should swing from GND (LOW) to V+ (HIGH).

3.2.1 STATUS OUTPUT

During a conversion cycle, the STATUS output goes high at the beginning of signal integrate and goes low one-half clock period after new data from the conversion has been stored in the output latches (see Figure 3-1). The signal may be used as a "data valid" flag to drive interrupts, or for monitoring the status of theconverter.(Datawillnotchange while statusislow.)

3.2.2 MODE INPUT

The Output mode of the converter is controlled by the MODE input. The converter is in its "Direct" Output mode, when the MODE input i s LOW or left open. The output data is directly accessible under the control of the chip and byte enable inputs (this input is provided with a pull-down resistor to ensure a LOW level when the pin is left open). When the MODE input is pulsed high, the converter enters the UART Handshake mode and outputs the data in 2 bytes, then returnsto "Direct" mode. When the MODE input is kept HIGH, the converter will output data in the Handshake mode at the end of every conversion cycle. With MODE = 0 (direct bus transfer), the send input should be tied toV+. (See "Handshake Mode".)

DS21456B-page 8

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2002 Microchip TechnologyInc.

TC7109/A

3.2.3 RUN/HO LD INPUT

With the RUN/HOLD input high, or open, the circuit operates normally as a dual slope ADC, as shown in Figure 3-1. Conversion cycles operate continuously with the output latches updated after zero crossing in the De-integrate mode. An internal pull-up resistor is provided to ensure a HIGH level with an open i nput.

The RUN/HOLD sion time. If RUN/HOLD crossing in the De-integrate mode, the circuit will jump to auto-zero and eliminate that portion of time normally spent in de-integrate.

If RUN/HOLD complete with minimum time in de-integrate. It will stay in auto-zero for the minimum time and waitin auto-zero for a HIGH at the RUN/HOLD Figure 3-3, the STATUS output will go HIGH, 7 clock

input may be used to shorten conver-

goes LOW any timeafter zero

stays or goes LOW, t he conversion will

input. As shown in

periods after RUN/HOLD converter will begin the integrate phase of the next conversion.

The RUN/HOLD interface. The converter may be held at IDLE in autozero with RUN/HOLD when RUN/HOLD valid when the STATUS output goes LOW (or is transferred to the UART; see "Handshake Mode"). RUN/ HOLD

may now go LOW, terminating de-integrate and ensuring a minimum auto-zero time before stopping to wait for the next conversion. Conversion time can be minimized by ensuring RUN/HOLD de-integrate, after zero crossing, and goes HIGH after the hold point is reached.

The required activity on the RUN/HOLD provided by connecting it to the buffered oscillator output.In this mode, the inputvaluemeasureddetermines the conversion time.

FIGURE 3-1: CONVERSION TIMING (RUN/HOLD PIN HIGH

Integrator Saturates

Integrator Output

for Over Range Input

Integrator Output

for Normal Input

Internal Clock

Phase I

INT

Phase II

No Zero Crossing

Zero Crossing Occurs

Zero Crossing Detected

Phase III

is changed to HIGH, and t he

input allows controlled conversion

LOW.Theconversionisstarted

goes HIGH, and the new data is

goes LOW during

input can be

Zero Integrator Phase forces Integrator Outpu to 0V

Internal Latch

Status Output

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2002 Microchip TechnologyInc. DS21456B-page 9

2048

Counts

Min.

Number of Counts to Zero Crossing

Fixed 2048

Counts

Proportional to V

4096

Counts

Max

After Zero Crossing, Analog section will

be in Auto-Zero Configuration

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