MICROCHIP TC1232 Technical data
M
TC1232
Microprocessor Monitor
Features
• Precision Voltage Monitor
- Adjustable +4.5V or +4.75V
• Reset Pulse Width – 250 msec minimum
• No External Components
• Adjustable Watchdog Timer
- 150 msec, 600 msec or 1.2 sec
• Debounced Manual Reset Input for External
Override
Applications
• Computers
• Controllers
• Intelligent Instruments
• Automotive Systems
• Critical µP Power Monitoring
General Description
The TC1232 is a fully-integrated processor supervisor
that provides three important functions to safeguard
processor sanity: precision power on/off reset control,
watchdog timer and external reset override.
On power-up, the TC1232 holds the processor in the
reset state for a minimum of 250 msec after V
within tolerance to ensure a stable system start-up.
Microprocessor sanity is monitored by the on-board
watchdog circuit. The microprocessor must provide a
periodic low-going signal on the ST
processor fail to supply this signal within the selected
time-out period (150 msec, 600 msec or 1200 msec),
an out-of-control processor is indicated and the
TC1232 issues a processor reset as a result.
The outputs of the TC1232 are immediately driven
active when the PB input is brought low by an external
push-button switch or other electronic signal. When
connected to a push-button switch, the TC1232
provides contact debounce.
The TC1232 is packaged in a space-saving 8-Pin PDIP
or SOIC package and a 16-Pin SOIC (Wide) package
and requires no external components.
input. Should the
CC
is
Package Types
16-Pin SOIC Wide8-Pin PDIP 8-Pin SOIC
1
V
PB RST
2003 Microchip Technology Inc. DS21370B-page 1
18
TD
TOL
GND
2
3
4
TC1232
7
6
5
CC
ST
RST
RST
PB RST
TOL
18
18
TD
27
TC1232
TC1232
36
36
45
45
V
CC
ST
RST
RSTGND
NC
PB RST
NC
TD
NC
TOL
NC
GND
2
3
4
5
6
7
8
TC1232
16
NC
V
15
CC
NC
14
13
ST
NC
12
RST
11
NC
10
RST
9
TC1232
Functional Block Diagram
V
CC
TOL
PB RST
TD
5%/10%
Tol er an ce
Select
Debounce
Watchdog
Time ba se
Select
+
–
+
+
V
REF
–
Reset
Generator
RST
RST
TC1232
Watchdog
Time r
GND
ST
DS21370B-page 2 2003 Microchip Technology Inc.
TC1232
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings†
Voltage on Any Pin (With Respect to GND)
...................................................... -0.3V to +5.8V
† Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at
these or any other conditions above those indicated in the
operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended
periods may affect device reliability.
Operating Temperature Range
C-Version ........................................ 0°C to +70°C
E-Version ..................................... -40°C to +85°C
Storage Temperature Range ............. -65°C to +150°C
DC CHARACTERISTICS
= T
Electrical Specifications: Unless otherwise noted, T
A
Parameters Sym Min Typ Max Units Conditions
Supply Voltage V
and PB RST Input High Level V
ST
ST
and PB RST Input Low Level V
Input Leakage ST
, TOL I
Output Current RST I
Current RST, RST
Operating Current I
V
5% Trip Point V
CC
V
10% Trip Point V
CC
CC
IH
IL
L
OH
I
OL
CC
CCTP
CCTP
4.5 5.0 5.5 V
2.0 — VCC +0.3 V Note 1
-0.3 — +0.8 V
-1.0 — +1.0 µA
-1.0 -12 — mA VOH = 2.4V
2.0 10 — mA VOL = 0.4V
— 50 200 µA Note 2
4.50 4.62 4.74 V TOL = GND (Note 3)
4.25 4.37 4.49 V TOL = VCC (Note 3)
Capacitance Electrical Characteristics: Unless otherwise noted, T
Input Capacitance ST
Output Capacitance RST, RST
, TOL C
C
IN
OUT
—— 5 pF
—— 7 pF
AC Electrical Characteristics: Unless otherwise noted, T
PB RST
PB RST
Delay t
Reset Active Time t
Pulse Width t
ST
ST
Time-out Period t
t
PB
PBD
RST
ST
TD
20 — — msec Figure 3-3 (Note 5)
1 4 20 msec Figure 3-3
250 610 1000 msec
20 — — nsec Figure 3-4
62.5 150 250 msec TD Pin = 0V, Figure 3-4
250 600 1000 msec TD Pin = Open, Figure 3-4
500 1200 2000 msec TD Pin = V
VCC Fall Time t
V
Rise Time t
CC
V
Detect to RST High and
CC
Low
RST
V
Detect to RST High and
CC
Open
RST
Note 1: PB RST
is internally pulled up to Vcc with an internal impedance of typically 40 kΩ.
t
RPD
t
RPU
F
R
10 — — µsec Figure 3-5, (Note 4)
0— —µsecFigure 3-6, (Note 4)
— — 100 nsec Figure 3-7, VCC Falling
250 610 1000 msec Figure 3-8, VCC Rising, (Note 6)
2: Measured with outputs open.
3: All voltages referenced to GND.
4: Ensured by design.
= 5 µsec.
R
must be held low for a minimum of 20 msec to ensure a reset.
5: PB RST
6: t
MIN
A
= T
to T
MIN
; VCC = +4.5V to 5.5V.
MAX
= +25°C
A
to T
. (Note 4)
; VCC = +5V to ±10%.
MAX
Figure 3-4
CC,
2003 Microchip Technology Inc. DS21370B-page 3
TC1232
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
Pin No.
(8-pin PDIP, SOIC)
1 2 PB RST
2 4 TD Time Delay Set. The watchdog time-out select input (t
3 6 TOL Tolerance Input. Connect to GND for 5% tolerance or to V
4 8 GND Ground.
5 9 RST Reset Output (Active-High) – goes active:
611
713
815V
— 1,3,5,7,10,12,16 NC No internal connection.
Pin No.
(16-pin SOIC)
Symbol Function
Push-button Reset Input. A debounced active-low input that ignores pulses
less than 1 msec in duration and is ensured to recognize inputs of 20 msec or
greater.
0V,
t
= 600 msec for TD = open, tTD = 1.2 sec for TD = VCC).
TD
1. If V
2. If PB RST
3. If ST
4. During power-up
RST Reset output (active-low, open-drain) – see RST.
ST Strobe input. Input for watchdog timer.
The +5V power-supply input.
CC
TD
falls below the selected reset voltage threshold.
CC
is forced low.
is not strobed within the minimum time-out period.
= 150 msec for TD =
for 10% tolerance.
CC
DS21370B-page 4 2003 Microchip Technology Inc.
TC1232
3.0 DETAILED DESCRIPTION
3.1 Power Monitor
The TC1232 provides the function of warning the processor of a power failure. When V
being below the voltage levels defined by the TOL pin,
the TC1232’s comparator outputs the RST and RST
signals to a logic level that warns the system of an outof-tolerance power supply. The RST and RST
switch at a threshold value of 4.5V if TOL is tied to V
and at a value of 4.75 volts if TOL is grounded. The
RST and RST
signals are held active for a minimum of
250 msec to ensure that the power supply voltage has
been stabilized.
3.2 Push-Button Reset Input
The debounced manual reset input (PB RST) manually
forces the reset outputs into their active states. Once
PB RST
delay time) the reset outputs go active. The reset
outputs remain in their active states for a minimum of
250 msec after PB RST
A mechanical push-button or active logic signal can
drive the PB RST
input pulses less than 1 msec and ecognizes pulses of
20 msec or greater. No external pull-up resistor is
required
pull-up to
has been low for a time t
rises above VIH (Figure 3-3).
input. The debounced input ignores
because the PB RST input has an internal
of approximately 100 µA.
VCC
is detected as
CC
(the push-button
PBD
signals
CC
3.4 Supply Monitor Noise Sensitivity
The TC1232 is optimized for fast response to negativegoing changes in V
amount of electrical noise on V
using relays) may require a 0.01 µF or 0.1 µF bypass
capacitor to reduce detection sensitivity. This capacitor
should be installed as close to the TC1232 as possible
to keep the capacitor lead length short.
+5V
V
PB RST
FIGURE 3-1: Push-Button Reset.
. Systems with an inordinate
DD
CC
TC1232
GND
TD
ST
RST
TOL
(such as systems
DD
I/O
processor
Reset
Micro-
3.3 Watchdog Timer
When the ST input is not stimulated for a preset time
period, the watchdog timer function forces RST and
RST
signals to the active state. The preset time period
is determined by the TD
connected to ground, 600 msec with TD floating, or
1200 msec with TD connected to V
watchdog timer starts timing-out from the set time
period as soon as RST and RST
to-low transition occurs on the ST input pin prior to
time-out, the watchdog timer is reset and begins to
time-out again. If the watchdog timer is allowed to timeout, then the RST and RST
active state for 250 msec minimum (Figure 3-2).
The software routine that strobes ST
code must be in a section of software that is executed
frequently enough so the time between toggles is less
than the watchdog time-out period. One common
technique controls the µP I/O line from two sections of
the program. The software might set the I/O line high
while operating in the foreground mode and set it low
while in the background or interrupt mode. If both
modes do not execute correctly, the watchdog timer
issues reset pulses.
inputs to be 150 msec with TD
(typical). The
CC
are inactive. If a high-
signals are driven to the
is critical. The
+5V
10 kΩ
0.1
µF
+5V
V
CC
TC1232
TOL GND
TD
RST
ST
RESET
processor
I/O
3-Terminal
Regulator
FIGURE 3-2: Watchdog Timer.
Micro-
2003 Microchip Technology Inc. DS21370B-page 5
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