microchip smps User Manual

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Page 1

SMPS AC/DC Reference Design

User’s Guide

Page 2

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and t he lik e is provided only for your convenience and may be su perseded by upda t es . It is y our responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life supp ort and/or safety ap plications is entir ely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless M icrochip from any and all dama ges, claims, suits, or expenses re sulting from such use. No licens es are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Tec hnology Incorporated in the U.S.A. and other countries.

FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programmin g , IC SP, ICE P I C , M in d i , MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC

logo, PowerCal, PowerInfo, PowerMate, PowerT ool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology In corporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

MCUs and dsPIC® DSCs, KEELOQ

code hopping

Page 3

SMPS AC/DC REFERENCE

DESIGN USER’S GUIDE

Table of Contents

Preface ........................................................................................................................... 1

Chapter 1. Introduction

1.1 System Spe c if ic a tio n s ......... .................................................................... ....... 7

1.2 Block Diagram ............ .................................................................................... 8

1.3 Multi-Phase Synchronous Buck Converter ...................................................19

1.4 Listing of I/O Signals for Each Block, Type of Signal and

Expected Signal Levels ................... ................................................... ....21

Chapter 2. Hardware Design

2.1 PFC Boost Co n ve r te r ................................ ................................................... 25

2.2 Full-Bridge ZVT Converter .................................................................. ......... 30

2.3 Single-Phase Synchronous Buck Converter ................ ................................41

2.4 Three-Phase Synchronous Buck Converter .................................................43

2.5 Auxiliary Power Supply .................................................................................45

Chapter 3. Software Design

3.1 Overview ............. ......................................................................................... 51

3.2 Structure of the Control Software .................................................................52

3.3 Primary Side Control Software (PFC_ZVT) .................................................. 54

3.4 Secondary Side Control Software (DC_DC) ................................................61

3.5 Auxiliary So ftware Routine s ............. .. .......................................................... 6 4

Chapter 4. System Operation

4.1 System Set u p ............................................................................................... 67

4.2 System Operation ......................................................................................... 72

Appendix A. Board Layouts and Schematics

A.1 Introduction ................................................................... ...............................75

A.2 SMPS AC/DC R e fe r e n ce De sign Layout ..................................................... 75

A.3 SMPS AC/DC R e fe r e n ce De sign Schemati cs ....... .. .................................... 77

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SMPS AC/DC Reference Design User’s Guide

Appendix B. Test Results

B.1 Soft-Start and Overshoot .............................................................................93

B.2 Dynamic Load Response ............................... .................... .......................... 95

B.3 Output Volt a g e Rip p le .................................................................................. 99

B.4 Input Current .............................................................................................. 101

B.5 Efficienc y . ............................................................................................... .... 103

B.6 Input Current Total Harmonic Distortion (ITHD) ......................................... 103

B.7 Power Fact o r .. ..................................................................... ....................... 10 3

B.8 Test Results Table ..................................................................................... 104

Appendix C. References

Index ...........................................................................................................................111

Worldwide Sales and Service ...................................................................................114

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SMPS AC/DC REFERENCE

DESIGN USER’S GUIDE

Preface

NOTICE TO CUSTOMERS

All documentation becomes dated, and this manual is no exception. Microchip tools and documentation are constantly evolving to meet customer needs, so some actual dialogs and/or tool descriptions may differ from those in this document. Please refer to our web site (www.microchip.com) to obtain the latest documentation available.

Documents are identified with a “DS” number. This number is located on the bottom of each page, in front of the p age number. The numbering convention for the DS number is “DSXXXXXA”, where “XXXXX” is the document number and “A” is the revision level of the document.

For the most up-to-date information on development tools, see the MPLAB Select the Help menu, and then Topics to open a list of available on-line help files.

INTRODUCTION

IDE on-line help.

This chapter contains general information that will be useful to know before using the SMPS AC/DC Reference Design. Items discussed in this chapter include:

• Document Layout

• Conventions Used in this Guide

• Warranty Registration

• Recommended Reading

• The Microchip Web Site

• Development Systems Customer Change Notification Service

• Customer Support

• Document Revision History

DOCUMENT LAYOUT

This document describes how to use the SMPS AC/DC Reference Design as a development tool to emulate and debug firmware on a target board. The manual layout is as follows:

• Chapter 1. “Introduction” – This chapter introduces the SMPS AC/DC Reference Design and provides an overview of its features and background information.

• Chapter 2. “Hardwa re Desi gn” – This chapter provides a functional overview of the SMPS AC/DC Reference Design and identifies the major hardware components.

• Chapter 3. “Software Design” – This chapter provides a functional overview of the software used in the hardware design and identifies the major software components.

• Chapter 4. “System Operat ion” – This chapter provides information on the system operation and setup for the SMPS AC/DC Reference Design.

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SMPS AC/DC Reference Design User’s Guide

• Appendix A. “Board Layouts and Schematics” – This appendix provides detailed technical drawings and schematic diagrams of the SMPS AC/DC Reference Design.

• Appendix B. “Test Results” – This appendix provides information on obtaining the source code referenced in this document.

• Appendix C. “References” – This appendix provides detailed information on all external references used throughout this document.

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CONVENTIONS USED IN THIS GUIDE

This manual uses the following docum entat io n conven tion s:

DOCUMENTATION CONVENTIONS

Description Represents Examples

Arial font:

Italic chara c ters Referenced books MPLAB

Initial caps A window the Output window

Quotes A field name in a window or

Underlined, italic text with right angle bracket

Bold characters A dialog button Click OK

N‘Rnnnn A number in verilog format,

Text in angle brackets < > A key on the keyboard Press <Enter>, <F1>

Courier New font:

Plain Courier New Sample source code #define START

Italic Courier New A variable argument file.o, where file can be

Square brackets [ ] Optional arguments mcc18 [options] file

Curly brackets and pipe character: { | }

Ellipses... Replaces r epeated text var_name [,

Preface

IDE User’s Guide

Emphasized text ...is the only compiler...

A dialog the Settings dialog A menu selection select Enable Programmer

“Save project before build”

dialog A menu path File>Save

A tab Click the Power tab

4‘b0010, 2‘hF1 where N is the tota l number of digits, R is th e radi x and n is a digit.

Filenames autoexec.bat File paths c:\mcc18\h Keywords _asm, _endasm, static Command-line options -Opa+, -Opa- Bit values 0, 1 Constants 0xFF, ‘A’

any valid filename

[options]

Choice of mut ually exclus ive arguments; an OR selection

Represents code supplied by user

errorlevel {0|1}

var_name...]

void main (void)

{ ...

}

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SMPS AC/DC Reference Design User’s Guide

WARRANTY REGISTRATION

Please complete the enclosed Warranty Registration Card and mail it promptly. Sending in the Warranty Registration Card entitles users to receive new product updates. Interim software releases are available at the Microchip web site.

Chapter 1. Introduction

This chapter provides an introduction to the SMPS AC/DC Reference Design and includes the following major topics:

• System Specifications

•Block Diagram

• Multi-Phase Synchronous Buck Converter

• Listing of I/O Signals for Each Block, Type of Signal and Expected Signal Levels

1.1 SYSTEM SPECIFICATIONS

SMPS AC/DC REFERENCE

DESIGN USER’S GUIDE

This reference design describes the design of an off-line Switch Mode Power Supply (SMPS) design using an SMPS dsPIC

The SMPS AC/DC Reference Design works with universal input voltage range and produces three output voltages (12V, 3.3V and 5V). The continuous output rating of the reference design is 300 Watts. This reference design is based on a modular structure having three major block sets as shown in Figure 1-1. Figure 1-2 shows a more detailed block diagram with all functional blocks as implemented on the SMPS AC/DC Reference Design.

The Power Factor Circuit (PFC) converts the universal AC input voltage to constant high-voltage DC, and maintains the sinusoidal input current at high power factor. The Phase-Shift Zero Voltage Transition circuit converts high-voltage DC to intermediate low-voltage DC with isolation from the input AC mains, at high efficiency. The Multi-Phase Synchronous and Single-Phase Synchronous Buck circuit converts intermediate low-voltage DC to very low-voltage DC at high current at high efficiency. The input and output specifications are as follows:

• Input:

- Input voltage: 85 V

- Input frequency: 45 Hz-65 Hz

• Outputs (individually loaded):

- Output voltage 1 (Vo 1) = 12 V

- Output load 1 (Io1) = 0A-30A

- Output voltage 2 (Vo 2) = 3. 3V

- Output load 2 (Io2) = 0A-69A

- Output voltage 3 (Vo 3) = 5V

- Output load 3 (Io3) = 0A-23A

• Outputs (simultaneously loaded):

- Output voltage 2 (Vo 2) = 3. 3V

- Output load 2 (Io2) = 0A-56A

- Output voltage 3 (Vo 3) = 5V

- Output load 3 (Io3) = 0A-23A

AC-265 VAC

DSC (dsPIC33FJ16GS504).

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SMPS AC/DC Reference Design User’s Guide

Input Stage

AC-DC Converter

Intermediate Stage

DC-DC Converter

Point of Load

DC-DC Converter

AC Input

Voltage 85-265V 45-65 Hz

Multiple

DC Outputs

85-265 VAC 45-65 Hz

EMI Filter

and Bridge

Rectifier

PFC

Boost

Converter

ZVT

Full-Bridge

Converter

Synchronous

Rectifier

Optocoupler

3.3 VDC 69A

5 V

23A

Isolation

Barrier

420 V

Rectified

Sinusoidal

Voltage

Multi-Phase

Buck Converter

Single-Phase

Buck Converter

Phase-Shift ZVT Converter

dsPIC33FJ16GS504

12 VDC 30A

1.2 BLOCK DIAGRAM

A conventional SMPS must implement PFC if it draws more than 75 watts from the AC Mains. The PFC circuitry draws input current in phase with the input voltage, and the T otal Harmonic Distortion (THD) of the input current should be less than 5% at full load. The PFC provides a fixed DC high-output voltage, which needs to be converted to a lower Direct Current (DC) output voltage and isolated with an input mains supply. Figure 1-2 shows a high-level block diagram of the SMPS AC/DC Reference Design. Figure 1-2 shows a detailed block diagram.

The SMPS AC/DC Reference Design operates on universal input voltage and produces multiple DC output voltages. The front-end PFC Boost circuit converts universal AC input voltage to 420 VDC bus voltage. The Phase-Shift Zero Voltage Transition (ZVT) circuit produces 12 VDC output voltage from a 420 VDC bus. The Phase-Shift ZVT converter also provides output voltage isolation from the input AC mains. The Multi-Phase Synchronous Buck converter produces 3.3 VDC @ 69 Amps from the 12 VDC bus. The Single-Phase Buck converter produces 5 VDC @ 23 Amps from the 12 VDC bus.

The following sections in this chapter provide an overview and background of the main power conversion blocks implemented in the SMPS AC/DC Reference Design.

FIGURE 1-1: HIGH-LEVEL SMPS AC/DC REFERENCE DESIGN BLOCK DIAGRAM

FIGURE 1-2: DETAILED SMPS AC/DC REFERENCE DESIGN BLOCK DIAGRAM

Page 13

Introduction

1.2.1 Power Factor Correction (PFC)

Most power conversion applications consist of an AC-to-DC conversion stage immediately following the AC source. The DC output obtained after rectification is subsequently used for further stages. Current pulses with high peak amplitude are drawn from a rectified voltage source with sine wave input and capacitive filtering. Regardless of the load connected to the system, the current drawn is discontinuous and of short duration. Because many applications demand a DC voltage source, a rectifier with a capacitive filter is necessary. However, this results in discontinuous, short duration current spikes.

1.2.1.1 OVERVIEW AND BACKGROUND INFORMATION Two factors that provide a quantitative measure of the power quality in an electrical

system are Power Factor (PF) and Total Harmonic Distortion (THD). The amount of useful power being consumed by an electrical system is predominantly decided by the PF of the system.

To understand PF, it is important to know that power has two components:

• Working (or Active Power) Working Power is the power that is actually consumed and registered on the

electric meter at the consumer's location. Working power is expressed in kilowatts (kW), which register as kilowatt hour (kWh) on an electric meter.

• Reactive Power Reactive Power is required to maintain and sustain the electromagnetic field asso-

ciated with the industrial inductive loads such as induction motors driving pumps or fans, welding machines and many more. Reactive Power is measured in kilovolt ampere reactive (kVAR) units. The total required power capacity, including Working Power and Reactive Power, is known as Apparent Power, expressed in kilovolt ampere (kVA) units.

Power Factor is a parameter that gives the amount of working power used by any system in terms of the total apparent power. Power Factor becomes an important measurable quantity because it often results in significant economic savings. Typical waveforms of current with and without PFC are shown in Figure 1-3.

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SMPS AC/DC Reference Design User’s Guide

Input Voltage

DC Bus Output Voltage

Input Current

DC Bus Output Voltage

Input Current

Without

PFC

With PFC

FIGURE 1-3: INPUT CURRENT WAVEFORM WITH AND WITHOUT PFC

These waveforms illustrate that PFC can improve the input current drawn from the mains supply and reduce the DC bus voltage ripple. The objective of PFC is to make the input to a power supply look like a simple resistor. The PFC circuitry provides a power factor that is nearly equal to unity with very low current THD (< 5%).

Figure 1-4 shows a block diagram of the AC-to-DC converter stage, which converts the AC input voltage to a DC voltage and maintains sinusoidal input current at a high input Power Factor.

The input rectifier converts the alternating voltage at power frequency into unidirectional voltage. This rectified voltage is fed to the chopper circuit to produce a smooth and constant DC output voltage to the load. The chopper circuit is controlled by the PWM switching pulses generated by the dsPIC DSC device, based on three measured feedback signals:

• Rectified input voltage

• DC bus current

• DC bus voltage

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Introduction

Rectifier Chopper

Rectified Voltage

Bus Current

DC Voltage

dsPIC

Digital Signal Controller (DSC)

Load

AC Input

Switching pulses

FIGURE 1-4: BLOCK DIAGRAM OF THE COMPONENTS FOR POWER FACTOR CORRECTION

1.2.1.2 PFC TOPOLOGIES

The Power Factor can be achieved with various basic topologies such as Buck, Boost and Buck/Boost.

1.2.1.2.1 Buck PFC Circuit

In a Buck PFC circuit, the output DC voltage is less than the input rectified voltage. Large filters are needed to suppress switching ripples and this circuit produces considerable Power Factor improvement. The switch (MOSFET) is rated to V case. Figure 1-5 shows the circuit for the Buck PFC stage. Figure 1-6 shows the Buck PFC input current shape.

FIGURE 1-5: BUCK PFC

IN in this

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SMPS AC/DC Reference Design User’s Guide

Input Current

Input Voltage

Input Current

Input Voltage

FIGURE 1-6: BUCK PFC INPUT CURRENT SHAPE

1.2.1.2.2 Boost PFC C ircuit The Boost converter produces a voltage higher than the input rectified voltage;

therefore, the switch (MOSFET) rating should be rated higher than V shows the circuit for the Boost PFC stage. Figure 1-8 shows the Boost PFC input current shape.

FIGURE 1-7: BOOST PFC

OUT. Figure 1-7

FIGURE 1-8: BOOST PFC INPUT CURRENT SHAPE

1.2.1.2.3 Buck/Boost PFC Circuit In the Buck/Boost PFC circuit, the output DC voltage may be either less or greater than

the input r ectifi ed vol ta ge. Hig h Power Fact or can b e achi eved i n this case. Th e swit ch (MOSFET) is rated to (V

IN + VOUT). Figure 1-9 shows the circuit for the Buck/Boost

PFC stage. Figure 1-10 shows the Boost PFC input current shape.

Page 17

Introduction

Input Current

Input Voltage

FIGURE 1-9: BUCK/BOOST PFC

FIGURE 1-10: BUCK/BOOST PFC INPUT CURRENT SHAPE

Regardless of the input line voltage and output load variations, input current drawn by the Buck converter and the Buck/Boost converter is always discontinuous. However, when the Boost converter operates in Continuous Conduction mode, the current drawn from the input voltage source is always continuous and smooth as shown in Figure 1-8. This feature makes the Boost converter an ideal choice for the Power Factor Correction (PFC) application. In PFC, the input current drawn by the converter should be continuous and smooth enough to meet T otal Harmonic Distortion (THD) specifications for the input current (ITHD) such that it is close to unity. In addition, input current should follow the input sinusoidal voltage waveform to meet displacement factor such that it is close to unity.

1.2.2 Phase-Shift ZVT Converter

A Full-Bridge converter is a transformer isolated Buck converter. The basic schematic and switching waveform is shown in Figure 1-11. The transformer primary is connected between the two legs formed by switches Q1,Q2 and Q4,Q3. Switches Q1,Q2 and Q4, Q3 create a pulsating AC voltage at the transformer primary. The transformer is used to step down the pulsating primary voltage, as well as to provide isolation between the input voltage source and the output voltage V retains the voltage properties of the Half-Bridge topology , and the current properties of push-pull topology. The diagonal switch pairs, Q1,Q3 and Q4,Q2, are switched alternately at the selected switching period. Since the maximum voltage stress across any switch is V

IN, and with the complete utilization of magnetic core and copper, this

combination makes the Full-Bridge converter an ideal choice for high input voltage, high-power range SMPS applications.

OUT. A Full-Bridge converter configuration

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SMPS AC/DC Reference Design User’s Guide

1PWM

3PWM

4PWM

2PWM

OSS1

OSS2

OSS3

OSS4

LKG

(A) = Full-Bridge/Half-Bridge Phase-Shift ZVT converter (B) = PWM gate pulse waveform for Full-Bridge switches (C) = Voltage across the transformer primary (D) = Output inductor and rectifier diode current

(A)

(B)

(C)

(D)

OUT

OFF

FIGURE 1-11: FULL-BRIDGE CONVERTER

In the Full-Bridge converter, four switches are used, thereby increasing the amount of switching device loss. The conduction loss of a MOSFET can be reduced by using a MOSFET with a low R Voltage Transition (ZVT), Zero Current Switching (ZCS), or both techniques. At high power output and high input voltage, the ZVT technique is preferred for the MOSFET. In a Phase-Shift ZVT converter, the output is controlled by varying the phase of switch

DS(ON) rating. Switching losses can be reduced by using Zero

Q4 with respect to Q1. In this topology, the parasitic output capacitor of the MOSFETs, and the leakage

inductance of the switching transformer, are used as a resonant tank circuit to achieve zero voltage across the MOSFET at the turn-on transition. There are two major differences in the operation of a Phase-Shift ZVT and simple Full-Bridge topology. In a Phase-Shift ZVT converter, the gate drive of both diagonal switches is phase shifted. In addition, both halves of the bridge switch network are driven through the complementary gate pulse with a fixed 50% duty cycle. The phase difference between the two half-bridge switching network gate drives control the power flow from primary to secondary, which results in the effective duty cycle.

Page 19

Introduction

1PWM

2PWM

3PWM

4PWM

Vprimary

t0 t1 t2 t3 t4

(A) = Gate pulse for all switches for Phase-Shift ZVT converter (B) = Voltage across primary (C) = Current across primary

(A)

(B)

(C)

Power is transferred to the secondary only when the diagonal switches are ON. If the top or bottom switches of both legs are ON simultaneously, zero voltage is applied across the transformer primary. Therefore, no power is transferred to the secondary during this period. When the appropriate diagonal switch is turned OFF , primary current flows through the output capacitor of the respective MOSFETs causing switch drain voltage to move toward to the opposite input voltage rail. This creates zero voltage across the MOSFET to be turned ON next, which creates zero voltage switching when it turns ON. This is possible when enough circulating current is provided by the inductive storage energy to charge and discharge the output capacitor of the respective MOSFETs. Figure 1-12 shows the gate pulse required, and the voltage and current waveform across the switch and transformer.

The operation of the Phase-Shift ZVT can be divided into different time intervals. Assuming that the transformer was delivering the power to the load, the current flowing through pr imary i s I is turned OFF as shown in Figure 1-12.

FIGURE 1-12: REQUIRED GATE PULSES AND VOLTAGE AND CURRENT ACROSS

PRIMARY

PK, and the diagonal switch Q1,Q3 was ON, at t = t0, the switch Q3

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SMPS AC/DC Reference Design User’s Guide

1.2.2.1 TIME INTERVALS

• Interval1: t0 < t < t1

Switch Q3 is turned OFF, beginning the resonant transition of the right leg. Primary current is maintained constant by the resonant inductor L current charges the output capacitor of switch Q3 (C V

IN, which results in the output capacitance of Q4 (COSS4) being discharged to

zero potential. This creates zero potential across switch Q4 prior to turn-on, resulting in zero voltage switching. During this transition period, the transformer primary voltage decreases from V

IN to zero, and the primary no longer supplies power to

the output. Inductive energy stored in the output inductor, and zero voltage across the primary, cause both output MOSFETs to share the load current equally.

• Interval2: t1 < t < t2

After charging C

OSS3 to VIN, the primary current starts flowing through the body

diode of Q4. Q4 can then be turned on any time after t1 and have a zero voltage turn-on transition.

• Interval3: t2 < t < t3

At t = t2, Q1 was turned OFF and the primary was maintained by the resonant inductor L I

PK because of finite losses. The primary resonant current charges the output

capacitor of switch Q1 (C capacitor of Q2 (C

LK. In addition, at t = t2, IP is slightly less than the primary peak current

OSS1) to input voltage VIN, which discharges the output

OSS2) to zero potential, thus preparing for zero voltage turn-on

for switch Q2. During this transition, the primary current decays to zero. ZVS of the left leg switches depending on the energy stored in the resonant inductor, conduction losses in the primary switches and the losses in the transformer winding. Since the left leg transition depends on leakage energy stored in the transformer, it may require an external series inductor if the stored leakage energy is not enough for ZVS. When Q2 is then turned ON in the next interval, voltage V is applied across the primary in the reverse direction.

• Interval: t3 < t < t4

The two diagonal switches Q4, Q2 are ON, applying full input voltage across the primary. During this period, the magnetizing current, plus the reflected secondary current into the primary, flows through the switch. The exact diagonal switch-on time depends on the input voltage, the transformer turns ratio and the output voltage. After the switch-on time period of the diagonal switch, Q4 is turned OFF.

One switching cycle is completed when the switch Q4 is turned OFF. The primary current charges C

OSS4 to a potential of input voltage VIN, and discharges COSS3

to zero potential, thereby enabling ZVS for switch Q3. The identical analysis is required for the next half cycle.

In the Phase-Shift ZVT converter shown in Figure 1-11, the maximum transition time occurs for the left leg at minimum load current and maximum input voltage, and minimum transition time occurs for the right leg at maximum load current and minimum input voltage. Therefore, to achieve ZVT for all switches, enough inductive energy must be stored to charge and discharge the output capacitance of the MOSFET in the specified allocated time. Energy stored in the inductor must be greater than the capacitive energy required for the transition. The MOSFET output capacitance varies as applied drain-to-source voltage varies. Thus, the output capacitance of the MOSFET should be multiplied by a factor of 4/3 to calculate the equivalent output capacitance.

OSS3) to the input voltage

LK. The primary

Page 21

Introduction

OUT

1GATE

- V

OUT

-V

OUT

-V

OUT

(VIN - V

OUT

)/L

1.2.3 Buck Converter Description and Background

A Buck converter, as its name implies, can only produce lower average output voltage than the input voltage. The basic schematic of a Buck converter is shown in Figure 1-13. The switching waveforms for a Buck converter are shown in Figure 1-14.

FIGURE 1-13: BUCK CONVERTER

In a Buck converter, a switch (Q1) is placed in series with the input voltage source V Input source V

IN feeds the output through the switch and a low-pass filter, implemented

IN.

with an inductor and a capacitor. In a steady state of operation, when the switch is ON for a period of T

provides energy to the output as well as to the inductor (L). During the T inductor current flows through the switch and the difference of voltages between V and V

OUT is applied to the inductor in the forward direction, as shown in Figure 1-13.

Therefore, the inductor current I During th e T

OFF period, when the switch is OFF, the inductor current continues to flow

L rises linearly from its present value IL1 to IL2.

ON, the input

ON period, the

in the same direction as the stored energy within the inductor, which continues to supply the load current. Diode D1 completes the inductor current path during the Q1 OFF period (T output voltage V Figure 1-14. Therefore, the inductor current decreases from its present value I

OFF); thus, it is called a freewheeling diode. During the TOFF period, the

OUT is applied across the inductor in the reverse direction, as shown in

L2 to IL1.

FIGURE 1-14: BUCK CONVERTER SWITCHING WAVEFORM

Page 22

SMPS AC/DC Reference Design User’s Guide

OUT

DVIN⋅=

where

D is the duty cycle

------

where ton is the ON time and TS is the switching time period

The inductor current is continuous and never reaches zero during one switching period (T

S); therefore, this mode of operation is known as Continuous Conduction mode. In

Continuous Conduction mode, the relation between the output and input voltage is given by Equation 1-1. The duty cycle is given by Equation 1-2.

EQUATION 1-1:

EQUATION 1-2:

When the output current requirement is high, the excessive power loss inside freewheeling diode D1 limits the minimum output voltage that can be achieved. To reduce the loss at high current, and to achieve lower output voltage, the freewheeling diode is replaced by a MOSFET with a very low ON state resistance (R MOSFET is turned on and off synchronously with the Buck MOSFET. Therefore, this topology is known as a Synchronous Buck converter. A gate drive signal, which is the complement of the Buck switch gate drive signal, is required for this synchronous MOSFET.

A MOSFET can conduct in either direction; which means the synchronous MOSFET should be turned off immediately if the current in the inductor reaches zero because of a light load. Otherwise, the direction of the inductor current will reverse (after reaching zero) because of the output LC resonance. In such a scenario, the synchronous MOSFET acts as a load to the output capacitor, and dissipates energy in the R of the MOSFET, resulting in an increase in power loss during the discontinuous mode of operation (inductor current reaches zero in one switching cycle). This may happen if the Buck converter inductor is designed for a medium load, but needs to operate at no load and/or a light load. In this case, the output voltage may fall below the regulation limit if the synchronous MOSFET is not switched off immediately after the inductor reaches zero.

DS(ON)). This

DS(ON)

Page 23

1.3 MULTI-PHASE SYNCHRONOUS BUCK CONVERTER

OUT

1PWM

IQ5+IQ

3PWM

5PWM

IQ1+IQ

IQ3+IQ

IQ5+IQ

If the load current requirement is more than 35-40 amps, more than one converter is connected in parallel to deliver the load. T o optimize the input and output capacitors, all the parallel converters operate on the same time base and each converter starts switching after a fixed time/phase from the previous one. This type of converter is called a Multi-Phase Synchronous Buck converter, which is shown in Figure 1-15. Figure 1-16 shows gate pulse timing relation of each leg and the input current drawn by the converter. The fixed time/phase is given by Time period/n (or 360/n), where “n” is the number of the converters connected in parallel.

The design of input and output capacitors is based on the switching frequency of each converter multiplied by the number of parallel converters. The ripple current seen by the output capacitor reduces by “n” times. As shown in Figure 1-16, the input current drawn by a Multi-Phase Synchronous Buck converter is continuous, with less ripple current as compared to a single converter. Therefore, a smaller input capacitor meets the design requirement in the case of a Multi-Phase Synchronous Buck converter.

FIGURE 1-15: MULTI-PHASE SYNCHRONOUS BUCK CONVERTER

Introduction

FIGURE 1-16: SWITCHING WAVEFORM OF SYNCHRONOUS BUCK

CONVERTER

Page 24

SMPS AC/DC Reference Design User’s Guide

HV Bias Supply

TNY277

-H

V_BUS

+HV_BUS

F/B

Live Drive

Supply

LIVE_GND

Live Digital

Supply

+13V

+7V

Drive Supply

GND

Digital Supply

+17V

+7V

High-Voltage

Bus (400V)

Energy Efficient

Bias Supplies

Switching Converter

1.3.1 Auxiliary Supply Description

The auxiliary power supply is based on the flyback topology, where it generates a voltage source for the control circuitry and MOSFET drivers on both sides of the isolation boundary. The multiple output flyback converter is controlled by a TNY277G switch; the block diagram is shown in Figure 1-17. The auxiliary power supply generates four isolated outputs, where on each side of the isolation barrier, the auxiliary transformer will generate a voltage source for the MOSFET drivers and a voltage source for the control circuitry.

A flyback converter is a transformer-isolated converter based on the basic Buck topology. In a flyback converter, a switch is connected in series with the transformer primary. The transformer is used to store energy during the ON period of the switch, and provides isolation between the input voltage source V V

OUT. During the TOFF period, the energy stored in the primary of the flyback

transformer transfers to secondary through the flyback action. This stored energy provides energy to the load, and charges the output capacitor. Since the magnetizing current in the transformer cannot change instantaneously when the switch is turned OFF, the primary current transfers to the secondary, and the amplitude of the secondary current will be the product of the primary current and the transformer turns ratio.

FIGURE 1-17: AUXILIARY POWER SUPPLY BLOCK DIAGRAM

IN and the output voltage

At the end of the ON period, when the switch is turned OFF, there is no current path to dissipate the stored leakage energy in the magnetic core of the flyback transformer. There are many ways to dissipate this leakage energy . One such method is shown in Figure 1-17 as a snubber circuit consisting of D, R, and C. In this method, the leakage flux stored inside the magnetic core induces positive voltage at the non-dot end primary winding, which forward-biases diode D and provides the path to the leakage energy stored in the core, and clamps the primary winding voltage to a safe value. Because of the presence of the secondary reflected voltage on the primary winding and the leakage stored energy in the transformer core, the maximum voltage stress VDS of the switch is approximately 1.6 times the input voltage (i.e., 400•1.6 = 660V).

Page 25

Introduction

VAC

IPFC

VHV_BUS

ADC Channel

PWM Output

AC|

FET Driver

dsPIC33FJ16GS504

(1)

Note 1: K1, K2 and K3 are feedback gain circuits. See A.3 “SMPS AC/DC Reference Design Schematics” for detailed

schematics.

1.4 LISTING OF I/O SIGNALS FOR EACH BLOCK, TYPE OF SIGNAL AND EXPECTED SIGNAL LEVELS

1.4.1 PFC Boost Converter

As indicated in the block diagram in Figure 1-18, three input signals are required to implement the control algorithm. The only output from the dsPIC DSC device is firing pulses to the Boost converter switch to control the nominal voltage on the DC bus in addition to presenting a resistive load to the AC line. Table 1-1 shows the dsPIC DSC resources used by the PFC application.

FIGURE 1-18: RESOURCES REQUIRED FOR DIGITAL PFC

TABLE 1-1: RESOURCES REQUIRED FOR DIGITAL PFC

Description Type of Signal

Output V oltage (V PFC Current (I

PFC) Analog AN4 2.5V (maximum)

AC Input Voltage (V

dsPIC

HV_BUS) Analog AN5 3.01V (nominal)

AC) Analog AN3 1.9V (maximum)

DSC Resources

Used

Expected Signal Level

PFC Gate Drive PFC Drive Output, Digital PWM4L —

Page 26

SMPS AC/DC Reference Design User’s Guide

dsPIC33FJ16GS504

ADC

Channel

ADC

Channel

UART

PWM

UART

PWM

IZVT

VHV_BUS

VOUT

Isolation

Barrier

ADC

Channel

PWM

FET

Driver

FET

Driver

FET

Driver

dsPIC33FJ16GS504

Note 1: K4 and K5 are feedback gain circuits. See A.3 “SMPS AC/DC Reference Design Schematics” for detailed

schematics.

(1)

1.4.2 Phase-Shift ZVT Converter

As indicated in the block diagram in Figure 1-19, three input signals are required to implement the control algorithm. The only outputs from the dsPIC DSC device are firing pulses to the Full-Bridge Phase-Shift ZVT and synchronous MOSFETs to control the nominal voltage on V

FIGURE 1-19: RESOURCES REQUIRED FOR DIGITAL PHASE-SHIFT ZVT CONVERTER

OUT.

TABLE 1-2: RESOURCES REQUIRED FOR DIGITAL PHASE-SHIFT ZVT

ZVT C ZVT CURRENT 2 (IZVT2) Analog AN2 1.5V (maximum) Volt age Sense (VOUT) Analog AN5 (secondary side) 2.79V (maximum) ZVT Gate Drive Full-Bridge Drive Outputs,

Synchronous Rectifier Gate Drive

Table 1-2 shows the dsPIC DSC resources used by Phase-Shift ZVT application.

Description Type of Signal

URRENT 1 (IZVT1) Analog AN0 1.5V (maximum)

dsPIC

Resources Used

PWM1H, PWM1L,

Digital

PWM2H, PWM2L

Sync FET Drive Outputs, Digital PWM3H, PWM3L —

DSC

Expected Signal Level

—

Page 27

Table 1-3 shows the common resources used on the Primary side.

Analog

Comp.

UART

PWM

ADC

Channel

Analog Comparator

ADC Channel

Analog Comparator

ADC

Channel

PWM

3.3V Output

5V Output

12V Input

FET

Driver

FET

Driver

FET

Driver

FET

Driver

3.3V_3

3.3V_2

3.3V_1

dsPIC33FJ16GS504

Note 1: K5 through K11 are feedback gain circuits. See A.3 “SMPS AC/DC Reference Design Schematics” for

detailed schematics.

(1)

TABLE 1-3: PRIMARY COMMON RESOURCES

Signal Name Type of Signal

dsPIC® DSC Resources

Used

Introduction

Expected Signal Level

Live_MCLR Digital MCLR

— Live_PGC Digital PGC — Live_PGD Digital PGD — Live_Fault Digital RC6 — Live_RS232_TX Digital UART1 T rans mi t — Live_RS232_RX Digital UART1 Receive — Live_Temp_Sense Analog AN10 1.4V

1.4.3 Secondary Side Synchronous Buck Converters

Figure 1-20 shows the input signals required to implement the control algorithms for the synchronous Buck converters. The output from the dsPIC DSC device is firing pulses to the Multi-Phase as well as Single-Phase Synchronous Buck converters.

FIGURE 1-20: RESOURCES REQUIRED FOR DIGITAL SYNCHRONOUS BUCK CONVERTERS

Page 28

SMPS AC/DC Reference Design User’s Guide

Table 1-4 shows the dsPIC DSC resources used by Multi-Phase as well as Single-Phase Synchronous Buck converters.

TABLE 1-4: RESOURCES REQUIRED FOR SECONDARY SIDE SYNCHRONOUS BUCK

CONVERTERS

Description/Signal Name Type of Signal

5V Buck Current Analog AN0, CMP1A 1.25V (maximum) 5V Buck Output Analog AN1 2.7V (nominal)

3.3V Buck Current 1 Analog AN2, CMP2A 1V (maximum)

3.3V Buck Current 2 Analog AN4, CMP3A 1V (maximum)

3.3V Buck Current 3 Analog AN6, CMP4A 1V (maximum)

3.3V Buck Output Analog AN3 1.65V (nominal) 5V Buck Gate Drive Single-Phase Synchronous

Buck Drive

3.3V Buck Gate Drive Multi-Phase Synchronous Buck Drive

12V Bus Sense Analog AN5 2.79V 12V Digital Feedback Digital UART1 Transmit — RS232_RX Digital UART1 Receive — Temperature Sense Analog AN8 1.4V MCLR PGC Digital PGC — PGD Digital PGD — Fault_Reset Digital RC6 —

Digital MCLR —

dsPIC® DSC Resources

Used

PWM4H, PWM4L —

PWM1H, PWM1L, PWM2H, PWM2L, PWM3H, PWM3L,

Expected Signal Level

—

Page 29

Chapter 2. Hardware Design

VDC

VAC

()

(

)

DtV=−

100

THD

−

This chapter provides a functional overview of the SMPS AC/DC Reference Design and identifies the major hardware components. Topics covered include:

• PFC Boost Converter

• Full-Bridge ZVT Conver ter

• Single-Phase Synchronous Buck Converter

• Three-Phase Synchronous Buck Converter

• Auxiliary Power Supply

2.1 PFC BOOST CONVERTER

The conventional single-phase power factor correction circuit is a standard Boost converter topology operating from the full wave rectified mains input, as shown in Figure 2-1.

The converter controller has an inner current control loop and outer voltage control loop. The current reference waveform is the input rectified mains voltage, so that the resultant current drawn from the mains is essentially sinusoidal and in-phase with the mains voltage. The amplitude of the current is controlled by the duty cycle of the fixed frequency PWM of the MOSFET , and is controlled by the PWM reference, which is the product of the current reference and the output of the DC link voltage error amplifier. Refer to Chapter 1. “Introduction” for details on the operation of this converter.

SMPS AC/DC REFERENCE

DESIGN USER’S GUIDE

FIGURE 2-1: PFC POWER CONVERTER

EQUATION 2-1:

EQUATION 2-2:

Page 30

SMPS AC/DC Reference Design User’s Guide

oac

mos

=−

diode

iV=

2.1.1 Power-Train Design

The target specification for the PFC converter is as follows:

• Input voltage, V

• Input frequency, f

• Switching frequency, f

• Maximum Output voltage, V

• Maximum Output power, POUT = 450 W

• Current THD < 5% EMC standards for conducted, radiated and line current harmonics:

• FCC Class B

• EN55022 (CISPR 22) Class B

• EN61000-3-2 A14 Class A

• EN61000-3-3

• IEEE519

2.1.1.1 MOSFETS AND GATE DRIVE MOSFET s are the preferred technology for the Boost converter power switch because

of the high operating frequency. The rms current in the MOSFET switch can be approximated using Equati on 2-3.

IN = 85-265 Vrms

= 45-65 Hz

= 125 kHz

OUT = 420 VDC

EQUATION 2-3:

16 2

CVf

wossdcsw

The maximum rms current occurs at minimum mains voltage, so the maximum normal operating MOSFET current is 4.6 Arms. Therefore, two TO-220 Infineon CoolMOS SPP11N60CFD 500V, 0.44Ω MOSFETs are connected in parallel, with each dissipating 2.3W of conduction loss. The MOSFET output capacitance is 390 pF so the switching loss is estimated at about 0.4W each. The actual loss in practice will be layout dependent and will probably be a factor of 2 higher, but still low enough to achieve high system efficiency.

The gate drive circuitry is a low-side Microchip TC1412N gate-drive IC, which drives the MOSFET gates directly. A single dsPIC DSC PWM module pin interfaces with the gate-drive IC via an inverting open-collector transistor stage which provides immunity against noise voltage differences between the Boost converter common and dsPIC DSC signal common (ground bounce).

2.1.1.2 OUTPUT DIODE The output diode must be rated for the mean output current, which is given by

Equation 2-4.

™

EQUATION 2-4:

Page 31

Hardware Design

rms

−

ripple

)

ripple

In this design, the diode must be rated for 1.2A, so a STMicroelectronics STTH5R06D 600V , 5A TO-220 ultra-fast high-voltage rectifier has been selected. The typical forward voltage drop at high junction temperature is 1.4V, which means that the device will run cool since the dissipation is only 1.7 Watts. There will be additional switching losses due to the high switching frequency and dio de reco ver y charac teri sti c s. For a lower cost solution, a smaller axial diode may be used. Alternatively, if switching losses are an issue, then the recently introduced SiC Schottky diode would be an attractive option.

2.1.1.3 PFC CHOKE The target THD of the input current is 5%, which means the non-fundamental (50 Hz

nominal) rms current component must be only 1% of input rms current. This component is the high-frequency ripple current in the Boost inductor, and is dependent on the inductance. If it is assumed that, on average, the duty cycle is 0.5, the ripple current rms of a triangular waveform is given by Equation 2-5.

EQUATION 2-5:

pk pk

Therefore, for a 5.3 Arms input current, we can only allow a maximum of 0.2A peak-to-peak, which will entail a large inductor size. However, the high frequency capacitor placed across the output terminals of the bridge rectifier will shunt-off most of the high frequency current so that a larger component of ripple can be tolerated in a smaller inductor. Note that too large a capacitance will cause distortion in the current waveform, so a design compromise must be reached. The inductor current peak-to-peak ripple in a PFC Boost converter varies over the whole mains cycle and depends on the input voltage, as shown in Equation 2-6.

EQUATION 2-6:

However, the absolute maximum value is independent of input voltage and is calculated from Equation 2-7.

EQUATION 2-7:

In this design, the ripple current is chosen to be 25% of the minimum voltage peak mains current; therefore, inductance of about 400 μH is required. The Boost choke uses a Kool Mu 77548 core, which has an outside diameter of 33 mm. The A this core is 127. A single layer of 58 turns of 0.9 mm (19 AWG) enameled copper fits on the core giving an unsaturated inductance of 427 μH. From the Magnetics Inc. published wire-core tables, this results in a predicted winding resistance of 77 mΩ at 100ºC. The variation of ripple current for a selection of input voltages is shown in Figure 2-2 and Figure 2-3.

The core loss can be roughly estimated from the mean flux density over a complete mains cycle. The worst case condition occurs at roughly 180 Vrms, where the mean flux density is 180 mT.

L value for

Page 32

SMPS AC/DC Reference Design User’s Guide

FIGURE 2-2: INPUT VOLTAGE RIPPLE CURRENT VARIATION

FIGURE 2-3: CORE LOSSES FOR PFC CHOKE

2.1.1.4 PFC OUTPUT CAPACITOR The PFC output capacitor provides bulk capacitance on the output of the PFC Boost

converter and smooths the DC voltage input to the ZVT Full-Bridge converter. The size of the capacitor is dictated by the hold-up requirements of the SMPS, its AC ripple current and thermal lifetime under normal operating conditions.

Page 33

Hardware Design

()

hold o

dc dc

−

Mains

The capacitance must be high enough to maintain the PFC output voltage within acceptable bounds under normal peak power operating conditions and when a mains brown-out occurs. The required hold-up time, t 22 ms, therefore the conditions of Equation 2-8 must be met.

EQUATION 2-8:

For a minimum DC link voltage of 300V, a 330 μF is required. The actual capacitor selected is a Panasonic EET-ED2W331EA 35 x 40 mm electrolytic capacitor rated to 450 V

DC and 105ºC. The ESR at 20 kHz is 0.181Ω, and the maximum ripple current

rating at 105ºC is 2.64 Arms.

2.1.1.5 EMI FILTER The SMPS AC/DC Reference Design has been designed to meet international

standards for conducted EMC. The EMI filter between the mains input terminals and the PFC is a two-stage design because of the high switching frequency of the different stages in the SMPS. The circuit is shown in Figure 2-4. The two common-mode chokes are rated to 6 Arms, and the 2.2 mH inductance forms a filter with the capacitors to Earth Ground for common-mode noise. The leakage inductance of the chokes together with the capacitors across the live and neutral terminals, filter the differential-mode noise.

The six capacitors connected to Earth Ground are 2.2 nF Y2-class capacitors meeting the CATII overvoltage category . The two X2-class capacitors are 220 nF. A transient spike voltage protection MOV is also fitted across the mains input, and a 470 kΩ discharging resistor is fitted across the input to the SMPS to ensure that the filter capacitors discharge with in one seco nd.

, at the minimum mains frequency is

hold

(min)

Note: The EMI/EMC filter value has been chosen based on switching frequencies

and expected noise levels in the system. This value may be changed based on the final test results of EMI/EMC.

FIGURE 2-4: EMI FILTER

Page 34

SMPS AC/DC Reference Design User’s Guide

≥

tVΔ=

max

=−

2.2 FULL-BRIDGE ZVT CONVERTER

The main power circuit for a ZVT Full-Bridge converter is shown in Figure 2-5. It is a standard Full-Bridge converter, but with additional series resonant inductance, which limits the rise rate of current at switching transitions and can eliminate turn-off switching power dissipation in the MOSFETs. The stray leakage inductance of the transformer forms part of the series resonant inductor and, in this particular design, is large enough to ensure quasi-resonant operation over 80% of the operating power range without the need for an additional inductor. The secondary-side high-frequency rectification is normally done by using ultrafast recovery rectifiers or Schottky diodes. Alternatively, lower loss rectification can be achieved by using MOSFETs operating as synchronous rectifiers with primary-side commutation control, and this is the preferred solution in this reference design.

ZVT operation occurs when the stored energy in the inductor is transferred to the capacitor in parallel with the MOSFET. In this design, the stray output capacitance of the MOSFET is large enough to not require additional capacitors in parallel. From Reference 3 (see Appendix C. “References”), the equation relating energy in the MOSFET output capacitance and the series inductance for ZVT operation is given by Equation 2-9.

EQUATION 2-9:

ICV

Rpri Rin

This ensures that there is more than enough energy to charge the MOSFET output capacitance and maintain ZVT operation. Note that at low output power, there will be far less energy stored in the resonant inductance so ZVT operation will be lost. The inductor is therefore selected based on the minimum operating output power for ZVT switching.

The modulation control scheme required for ZVT operation of a Full-Bridge converter is phase-shifted PWM. The ideal power stage waveforms for the circuit are shown in Figure 2-6. The ZVT transition in the switch is short in comparison with the primary current transition time. This time, Δt, is dictated by the resonant inductance, L is given by Equation 2-10.

EQUATION 2-10:

Rpri

The control duty cycle is limited in a ZVT due to the time taken for the current to rise/fall during switching transitions. The maximum duty cycle, D ZVT operating conditions given by Equation 2-11.

EQUATION 2-11:

, is achievable under the

max

, which

21t

Page 35

Hardware Design

max

pri

InV=

VIN

IPRI

VPRI

VSEC

VOUT

The transformer turns ratio, n, for the current doubling synchronous rectifier topology can then be selected for the required operating input and output voltages using the following ideal relationship shown in Equation 2-12.

EQUATION 2-12:

The previous equations governing the ZVT operation and resonant circuit component selection are also dependent on the peak primary current. If the output inductor magnetizing current is ignored, the primary peak current is given by Equation 2-13.

EQUATION 2-13:

oin

FIGURE 2-5: ZVT FULL-BRIDGE POWER CONVERTER WITH

SYNCHRONOUS RECTIFICATION

Page 36

SMPS AC/DC Reference Design User’s Guide

PRI

SEC

FIGURE 2-6: ZVT WAVEFORMS

Page 37

Hardware Design

2.2.1 Full-Bridge ZVT Power-Train Design

The target specification for the ZVT Full-Bridge converter is as follows:

• Input voltage, V

• Switching frequency, f

• Maximum output voltage, V

• Maximum output current, I

2.2.1.1 MOSFETS AND GATE DRIVE Care must be taken when selecting the MOSFET switch for the ZVT Full-Bridge since

there are potential failure modes associated with the diode characteristic and timing control at light loads (see Reference 4 in Appendix C. “References”). For this reference design, an Infineon CoolMOS CFD device has been selected because of its optimized diode characteristic. The SPA11N60CFD is a 600V, 0.44Ω MOSFET in a TO-220 package, and is a good compromise between cost and efficiency for this output power rating. The output capacitance, C capacitor for ZVT operation.

Gate driving is typically achieved with either a proprietary high-side and low-side high-voltage driver IC, or using a small transformer. These circuit techniques provide level-shifting of the dsPIC DSC gate firing signals. Adequate voltage creepage and clearance distances are maintained in the layout. Given the high switching frequency in this application, the transformer isolated gate drive approach has been adopted. This is because of thermal concerns in standard gate driver ICs, although there are potential candidates from a number of manufacturers available on the market.

A single drive transformer with two secondary windings manufactured by Sirio Elettronica is used for each half-limb, and the turn-on switching time is controlled by a single resistor in each MOSFET gate. Turn-off is much faster due to the diode across the gate resistor. The drive for each transformer primary is provided by a Microchip TC1404, which is a dual high-speed CMOS driver IC. The dead-time for each MOSFET half-limb is inserted by the dsPIC DSC PWM peripheral module and is selected to avoid any possible shoot-through condition based on the timing delays inherent in the transformer gate drive circuitry.

IN = 390-420V

= 250 kHz

OUT = 12V

OUT = 33A

OSS, is 45 pF and will form the resonant

2.2.1.2 TRANSFORMER The following section describes a basic procedure for designing the ZVT Full-Bridge

transformer. The optimum choice of ferrite core and winding turns/construction is dependent on many factors in the overall converter and may well involve a number of design optimization iterations.

The transformer turns ratio must be selected to ensure that voltage regulation is maintained at the maximum duty limit. As a starting point, D

is assumed to be 0. 85,

max

so for the minimum DC link voltage (390V) and the output voltage (12.5V), which includes the voltage drop across the synchronous rectifiers and output chokes, the required transformer turns ratio is 13.3 or less (see Equation 2-12).

An ungapped ETD29 ferrite core pair is selected for the transformer. Table 2-1 lists the various parameters for ETD29 cores made of N87 material.

TABLE 2-1: TRANSFORMER CORE DATA

(nH/Turn2)

ETD29 2200 76 5350 19.4 4.85 52.8 28

(mm2)

(mm3)

(mm)

(ºC/W)

Page 38

SMPS AC/DC Reference Design User’s Guide

max

min

41.592.74

1.36 10

−

=×

where fsw is in kHz and B is in mT.

T o compute the operating flux density and decide on the number of turns, it is assumed that the maximum allowable transformer temperature rise is 80ºC. The power converter will have forced air cooling from a lid mounted fan so the actual thermal resistance will be about a third less at around 10ºC/W. This means that the total power dissipation can be as much as 8W, with the losses split equally in the copper windings and the ferrite cores. From the core loss curves shown in Figure 2-7, the operating AC peak-to-peak flux density can be as high as 150 mT. The minimum number of turns at the given maximum operating duty is given by Equation 2-14.

EQUATION 2-14:

VD T

max

Therefore, N

is 58, which means that the secondary winding must have either four

min

or five turns to give the required turns ratio computed above. Based on this, a good solution is 64 turns on the primary and five turns on the secondary with a turns ratio, n, of 12.8.

FIGURE 2-7: N87 POWER LOSS CURVES

With the selected turns ratio from Equation 2-12, the actual operating duty, D, is 0.82. Therefore, the operating peak-to-peak flux density is 130 mT at 250 kHz. The core loss in a N87 core can be computed by Equation 2-15.

EQUATION 2-15:

core sw e

fBV

Page 39

Hardware Design

sec

ssw

when

45 10

where lm is the mean turn length and b

is the foil width.

Therefore, the predicted core loss is actually 2.9W. The next stage is now to optimize the winding designs to minimize the losses, especially the high-frequency AC losses due to skin-effect and the proximity effect in multilayer windings (see Reference 5 and Reference 6 in Appendix C. “References”). The available winding width, b reduced to accommodate a 3 mm creepage border on each side of the bobbin, leaving around 13 mm available for the windings. The total height of the two windings must be less than 4.5 mm which takes into account the layers of 0.05 mm inter-winding tape.

The secondary transformer winding rms current for the current-doubler synchronous rectifier, ignoring inductor ripple current, is given by the relationship shown in Equation 2-16.

EQUATION 2-16:

The secondary rms current is therefore 16.5A, but will be slightly higher in practice due to the magnetizing ramp component of current in the output inductors. For high current windings, copper foil is better suited to utilize the available winding area, and minimize AC copper losses. The secondary winding is a 5 turn strip of copper, and the ideal foil height, h

, in mm is given by Equation 2-17.

, must be

EQUATION 2-17:

9.74 10

So h

at 250 kHz is 0.088 mm. The resistance factor, FR, is given by Equation 2-18.

EQUATION 2-18:

⎛⎞

⎜⎟ ⎝⎠

1.4

Therefore, for a practical foil thickness, h, of 0.1 mm, F including AC effects is given by Equation 2-19.

EQUATION 2-19:

= 1.56. The total resistance

The realistic foil width for the ETD29 is 13.0 mm. This means that the secondary resistance is 1.4 mΩ, which leads to a secondary winding copper loss of about 0.5 W. The current density is actually 14A/mm acceptable.

and, although very high, the power loss is

Page 40

SMPS AC/DC Reference Design User’s Guide

17.1

1.01

SNf

where S is the number of strands and N is number of turns in the winding portion.

There is no requirement to reduce leakage inductance in the transformer design so the primary winding can be a single winding block. This may also reduce the inter-winding capacitance between primary and secondary and have an impact on EMC. For the low current primary with the large number of turns, round conductors are preferred. Equation 2-20 can be used to identify the ideal wire diameter at the operating frequency, which takes into account skin and proximity effects, and was derived through experimental work by Dowell in the 1960s (see Reference 7 in Appendix

C. “References”).

EQUATION 2-20:

⎛⎞ ⎜⎟ ⎝⎠

The resistance factor for round conductors can then be computed from Equation 2-21.

EQUATION 2-21:

⎛⎞ ⎜⎟ ⎝⎠

The best fill factor is achieved by using seven-stranded Litz wire, so this is a starting point. Also, assume four layers as an initial starting point with 16 turns per layer. Therefore, the ideal optimum wire diameter is 0.2 mm (32 AWG), giving a resistance factor of 1.5. A commercially available Litz wire has eight strands of 0.2 mm with an OD of 0.75 mm. The DC resistance per meter for single 0.2 mm strand at 100ºC is 0.7074 Ω/m, so the resistance for one mean turn of eight strands is 4.7 mΩ. Therefore, the total adjusted AC resistance of the primary winding is 0.45Ω. The primary current is 1.3 Arms for the estimated secondary current and selected transformer turns ratio, which leads to a primary winding loss of 0.8W. Therefore, the total transformer losses are estimated to be 4.2W in the ETD29 transformer, and will limit the total temperature rise to less than 80ºC with forced air-cooling.

The primary Litz wire has a total OD of around 0.7 mm, so the four-layer primary winding height is about 3 mm. The secondary five-layer foil winding height, including inter-turn insulation, will be around 0.75 mm height, and this design will easily fit in the available 4.85 mm maximum winding window height. The final winding construction is shown in Figure 2-8. The primary winding start and finish are terminated to bobbin pins, while the secondary winding has flying leads which are soldered directly into the PCB.

Page 41

Hardware Design

3 mm

margin

3 mm

margin

3 mm

margin

3 mm

margin

64 turns of 8 x 0.2 mm Litz wire

3 layers 0.05 mm Melinex

5 turns of 0.1 mm x 13 mm foil

3 layers 0.05 mm Melinex

410

−

×+

µH

where c is the space between the primary and secondary. All dimensions are in mm.

FIGURE 2-8: ZVT FULL-BRIDGE TRANSFORMER WINDING

CONSTRUCTION

The last check is to assess whether an additional inductor is needed for ZVT operation. The leakage inductance (see Reference 8 in Appendix C. “References”) for a standard construction transformer is given by Equation 2-22.

EQUATION 2-22:

The ideal computed leakage inductance is 32 µH, which meets the criteria of Equation 2-9 with the MOSFET output capacitance without requiring an additional resonant inductor. Provision has been made on the reference design PCB for an external inductor and parallel capacitors across the MOSFETs if the ZVT operation needs tuning.

2.2.2 Synchronous Rectifier Design

Synchronous rectification is the technique used for reducing the power loss in the output stage of switched mode power supplies (see Reference 9 in Appendix C. “References”). The conventional diode is replaced by a MOSFET and is controlled so that current will flow into the third quadrant in the source-to-drain direction when the equivalent R

DS(ON) voltage drop is lower than the intrinsic diode voltage drop. This

means that with very low R significantly increased. This is especially true in low output voltage power supplies.

lN h h

⎛⎞

mp p s

⎜⎟ ⎝⎠

DS(ON) MOSFETs, the power supply efficiency can be

Page 42

SMPS AC/DC Reference Design User’s Guide

Note: Dotted lines with arrows indicate current polarity.

SEC

OUT

SEC

OUT

SEC

OUT

In push-pull type power converters, there are a number of synchronous rectifier topologies. In this particular reference design, a current-doubler form has been used (see Reference 10 in Appendix C. “References”). Figure 2-9 illustrates the current paths for the four operating modes of the rectifier. The MOSFET commutation is synchronized to the ZVT Full-Bridge switching and gate control signals are generated by the primary-side dsPIC DSC device and fed to the secondary-side via high-speed opto-isolators.

The operating waveforms for the synchronous rectifier are shown in Figure 2-10. As shown in the figure, switch Q6 is gated when the primary current is positive, which coincides with the gating of switch Q2, and Q5 is synchronized with the primary bridge MOSFET Q4 gate signal.

FIGURE 2-9: CURRENT-DOUBLER SYNCHRONOUS RECTIFIER

OPERATING MODES

Page 43

Hardware Design

Q5 (Q4)

(Q2)

SEC

out

FIGURE 2-10: SYNCHRONOUS RECTIFIER WAVEFORMS

2.2.2.1 MOSFET SYNCHRONOUS RECTIFIERS AND GATE DRIVES The MOSFET rectif iers selecte d for the synchron ous rectifier ar e Internatio nal Rectifier

IRF2804SPBF 40V, 2 mΩ devices. They are packaged in a D directly onto the PCB. The minimum blocking voltage required is equal to the peak

PAK and mounted

applied transformer secondary voltage. With the turns ratio of 12:8 and at the maximum input voltage of 410V, this is 32V. There will be very little overshoot voltage due to the compact layout achieved through mounting on the PCB, and the RC snubber across the secondary winding. The junction to ambient thermal resistance is 40ºC/W when mounted on a 25.4 mm C. “References”).

(1 inch2) PCB copper pad (see Reference 11 in Appendix

The MOSFET’s internal diode voltage characteristic is 0.6V at 30A, 175ºC, which is significantly above the voltage drop across the 2 mΩ ON state resistance, and the benefits of synchronous rectification are maintained over the whole operating power region.

The gate-drive circuit employs a Microchip MCP1403 gate driver. The gate control signals are generated by the primary-side dsPIC DSC device so that they are synchronized with the ZVT Full-Bridge commutation. Isolation is achieved by high-speed opto-isolators.

Page 44

SMPS AC/DC Reference Design User’s Guide

VDT

=−

VDT

NA n

⎛⎞

=−

⎜⎟

⎜⎟ ⎝⎠

⎝⎠

W/m

BNA=

2.2.2.2 OUTPUT CHOKE There are two output chokes in the current-doubler synchronous rectifier. Each

inductor's mean current is half the output current, and the fluxing voltage period occurs in only half of the cycle. Therefore the ripple current is given by Equation 2-23.

EQUATION 2-23:

⎛⎞

ripple o

The choke is designed to have a 20% current ripple component, and the inductance is selected to give 3.3A at the nominal input voltage 400V. Therefore, the inductance needs to be 9 μH and the winding rated for a current of around 18A.

The Magnetics Kool Mu core iron loss can be computed from Equation 2-24.

EQUATION 2-24:

⎜⎟ ⎝⎠

cosw

The peak flux density is computed from Equation 2-25.

EQUATION 2-25:

Taking the 20.3 mm OD core No. 77848 with an A required number of turns, N, is 17. Therefore, the peak-to-peak AC flux density is 77 mT and the core loss is 0.5W. According to the single-layer winding data, 1.6 mm OD wire (14 AWG) will fit on the core so that the 13 x 0.315 mm will fit. The copper cross-sectional area is 1.01 mm is estimated to be 7 mΩ (double the 14 AWG resistance) and so the copper loss is

2.2W. With forced air-cooling this is acceptable.

2.2.2.3 OUTPUT CAPACITOR The main output capacitor is a 2200 μF, 25V electrolytic with two 10 μF, 25V multilayer

ceramic capacitors in parallel. The larger bulk capacitance provides the main energy storage while the small ceramic capacitors with very low ESR provide the high-frequency ripple current decoupling capability. The capacitor ripple current is the combined AC components of the two output inductors plus the AC component of the synchronous Buck loads. In the case of the inductor currents, this is lower compared to a conventional output rectifier due to the 50% phase shift in the inductor currents, and is dominated by current supplied to the synchronous Buck regulators. The capacitor must also provide enough energy during a step load transient to maintain the 12V output voltage within the required regulated limits.

, so the current density is 17.7A/mm2. The resistance

1.46

= 32 with Ae = 22.6 mm2, the

Page 45

2.3 SINGLE-PHASE SYNCHRONOUS BUCK CONVERTER

out

bus

DV=

high o

The Single-Phase Synchronous Buck converter uses the same basic topology as the standard step-down Buck converter, but replaces the free-wheel diode with a MOSFET . Figure 2-11 shows the main power circuitry. The two switches are operated as a complementary pair with a dead-time inserted by the PWM controller to avoid shoot-through. The low-side MOSFET is operated in the third quadrant with current flowing from source to drain when the current is required to free-wheel, and, due to the very lower ON state resistance of the MOSFET, higher efficiency is achieved compared with a conventional Schottky diode.

FIGURE 2-11: SINGLE-PHASE SYNCHRONOUS BUCK CONVERTER

Hardware Design

2.3.1 Single-Phase Buck Converter Power-Train Design

The target specification for the Single-Phase Buck converter is as follows:

• Input voltage, V

• Switching frequency, fsw = 500 kHz

• Output voltage, V

• Output current, IOUT = 23A

• Voltage ripple < 2%

• Output slew rate > 5 A/μs

2.3.1.1 MOSFETS AND GATE DRIVE The equation governing the duty cycle of a Buck converter is shown in Equation 2-26.

EQUATION 2-26:

The rms currents in the high-side and low-side MOSFETs, assuming a low inductor ripple current is as follows in Equation 2-27 and Equation 2-28.

EQUATION 2-27:

IN = 12 VDC

OUT = 5 VDC

bus

iID

Page 46

SMPS AC/DC Reference Design User’s Guide

low o

1 6

(

on bus

−

Δ=

EQUATION 2-28:

iI D

The nominal duty cycle is 0.42 ignoring stray voltage drops and inductor current ripple. This equates to a high-side MOSFET on-time, t MOSFET is rated for 14.9 Arms and the low-side MOSFET is rated for 17.5A.

The selected MOSFETs are International Rectifier IRLR7833PBF , 30V , 4.5 mΩ devices in a DPAK package, and are mounted directly on the PCB. The intrinsic reverse diode of the MOSFET is relatively slow in switching, so a fast Schottky diode is placed in parallel across the MOSFET to reduce switching loss. The conduction losses of the high-side and low-side MOSFETs are estimated at 0.85W and 1.2W respectively. It is possible in some designs to optimize the efficiency performance by selecting different devices for the high-side and low-side switches.

The switching loss in the MOSFETs can be estimated by assuming ideal linear switching transitions using Equation 2-29.

EQUATION 2-29:

wbusorsw

The estimated switching transition time is 50 ns, so the switching loss for each device is 2.4W.

The gate drive circuitry is a dual Microchip MCP1404 gate-drive IC, which drives the MOSFET gates directly. The maximum gate threshold of each MOSFET is 4V, so the drive circuit for the high-side MOSFET is provided by the auxiliary SMPS power rail, which is higher than the gate threshold and source voltage combined. The PWM module pin of the dsPIC DSC device interfaces with the gate-drive IC via an inverting open-collector transistor stage, which provides immunity against ground bounce.

−

, of 840 ns. Therefore, the high-side

VItf

2.3.1.2 OUTPUT CHOKES The ripple current is given by the relationship shown in Equation 2-30.

EQUATION 2-30:

tV V

The ripple current needs to be less than 25% of the output current so each output choke is a 1 μH Coilcraft SER1360-102KL surface mount. A smaller inductor would improve the output transient response, but at the expense of higher ripple current and, consequently, higher output voltage ripple. The DC resistance is 2.5 mΩ and the power loss is 1.3W for the maximum 23A output current. The peak-to-peak ripple current is

5.9A.

2.3.1.3 OUTPUT CAPACITOR The output capacitor ripple current is fairly low in a Buck converter due to the

continuous inductor current, and is only dependent on the amplitude of ripple current in the inductor. The relationship for capacitor rms current is given by Equation 2-31.

)

Page 47

EQUATION 2-31:

cap

iΔ=

VBUS

VOUT

Therefore, the total capacitor ripple current is 1.7 Arms. Another important design consideration for the bulk capacitors is the transient load requirements, so low ESR/ESL p art s ar e req uire d to meet t he sp ecif ica tio n (see Refe re nce 1 2 in Appendix C. “References”). Two Rubycon 10ZL1500M10X23 1500 μF, 10V electrolytic capacitors, plus four 10 μF, 16V multi-layer ceramics in parallel were selected. The electrolytic capacitors are each rated to 2.15 Arms at 105ºC, which can easily handle the ripple current on their own.

2.4 THREE-PHASE SYNCHRONOUS BUCK CONVERTER

Multiple synchronous Buck converters can be connected in parallel to increase the power handling of a step-down voltage stage. Performance improvements and a reduction in output capacitor size can be achieved by phase-shifting the PWM modulation in each stage. In this reference design, a Three-Phase Synchronous Buck converter has been designed. The power circuit is shown in Figure 2-12 and illustrates the switching cycle 120 degree PWM phase-shifting in the output choke currents.

Hardware Design

FIGURE 2-12: THREE-PHASE SYNCHRONOUS BUCK CONVERTER

Page 48

SMPS AC/DC Reference Design User’s Guide

DV=

high o

low o

1 6

(

on bus

−

Δ=

2.4.1 Multi-Phase Buck Converter Power-Train Design

The target specification for the Multi-Phase Buck converter is as follows:

• Input voltage, V

• Switching frequency, fsw = 500 kHz

• Output voltage, V

• Output power, IOUT = 69 A

• Voltage ripple < 2%

• Output slew rate > 50A/μs

2.4.1.1 MOSFETS AND GATE DRIVE The output current for each phase Buck stage is 23A and nominal duty cycle is 0.275

ignoring stray voltage drops and inductor current ripple. This equates to a high-side MOSFET on-time, t Arms, and the low-side MOSFET is rated for 19.6A.

The selected MOSFETs are International Rectifier IRLR7833PBF, 30 V, 4.5 mΩ devices in a DPAK package, and are mounted directly on the PCB. The conduction losses of the high and low-side MOSFETs are estimated at 0.55W and 1.5W respectively. The estimated switching transition time is 50 ns, so the switching loss for each device is 1.2W.

IN = 12 VDC

OUT = 3.3 VDC

, of 550 ns. Therefore, the high-side MOSFET is rated for 12

EQUATION 2-32:

bus

iID

iI D

wbusorsw

2.4.1.2 OUTPUT CHOKES The ripple current in each inductor is given by the relationship shown in Equation 2-33.

EQUATION 2-33:

tV V

The ripple current needs to be about 20% of the output current; therefore, each output choke is a 1 μH Coilcraft SER1360-102KL surface mount. The DC resistance is 2.5 mΩ and the power loss is 1.3W. The peak-to-peak ripple current is 4.8A.

−

VItf

)

Page 49

2.4.1.3 OUTPUT CAPACITOR

cap

iΔ=

Snubber/

Clamp

Control

SEC_17V

SEC_7V

SEC_0V

PRI_13V

PRI_7V

The output capacitor ripple current is very low due to the continuous inductor currents with phase shifting. The relationship for capacitor rms current is given by Equation 2-34.

EQUATION 2-34:

Therefore, the total capacitor ripple current is 1.0 Arms. The output capacitor is made up of three Rubycon 6.3ZL1500M10X20 1500 μF, 6.3V electrolytic capacitors plus three 10 μF, 16V multi-layer ceramics in parallel. The electrolytic capacitors are each rated to 1.82 Arms at 105ºC, and can easily handle the ripple current on their own.

2.5 AUXILIARY POWER SUPPLY

The supply voltages for the primary and secondary side dsPIC DSC device and gate drive circuitry are generated by a simple low-power flyback SMPS. Figure 2-13 illustrates the main components in the design. The integrated high-voltage proprietary controlled switch feeds a high-frequency transformer, and multiple secondary windings tapped-off via a diode/capacitor circuit. The SMPS operates in discontinuous flyback mode, so that energy is stored in the magnetizing inductance of the transformer during the switch on-period, and transferred to the secondary circuits during the off-period. A snubber arrangement is required across the transformer primary to dissipate the transformer parasitic leakage energy and ensure that the switch voltage does not exceed its maximum rating. The typical flyback MOSFET waveforms are shown in Figure 2-14.

Hardware Design

312

FIGURE 2-13: AUXILIARY FLYBACK SMPS

Page 50

SMPS AC/DC Reference Design User’s Guide

0 2.5 5 7.5 10 12.5 15

100

200

300

400

500

600

700

MOSFET Voltage (V)

Time ( s)

0 2.5 5 7.5 10 12.5 15

0.1

0.2

0.3

0.4

0.5

0.6

0.7

MOSFET Current (A)

Time ( s)

1 2

FIGURE 2-14: FLYBACK SMPS MOSFET WAVEFORMS

2.5.1 Basic Design Methodology

The target specification for the auxiliary flyback SMPS is as follows:

• Input voltage, V

• Primary Output Rail 1 = 7V @ 0.3A

• Primary Output Rail 2 = 13V @ 0.15A

• Secondary Output Rail 1 = 7V @ 0.3A

• Secondary Output Rail 2 = 17V @ 0.45A

2.5.1.1 HVIC TECHNOLOGY The total output power rating of the auxiliary power supply is 13.8W; therefore, a Power

Integrations TinySwitch (see Reference 13 in Appendix C. “References”) was selected for the main power switch. These devices are intended specifically for low-cost high-efficiency designs and operate with simple ON/OFF control rather than more sophisticated PWM common to higher power SMPS. The TNY277G is a suitably rated part for this wide input voltage application, and can be mounted directly on the PCB without any additional cooling requirements.

2.5.1.2 TRANSFORMER Based on the operating frequency and power throughput requirement, an EF20 ferrite

core pair is selected for the transformer design. The first step in the design is to select the number of primary turns and transformer air-gap. Discontinuous flyback SMPS output power is dictated by the energy stored in the primary magnetizing inductance of the transformer and the switching frequency. The basic equation, ignoring losses, is shown in Equation 2-35.

IN = 120-400 VDC

EQUATION 2-35:

LI f

oppsw

Page 51

Hardware Design

tV=

LP=

41.59

1.36 10

core

sw e

−

where fsw is in kHz and B is in mT.

ppp

The peak current in the primary is fixed for a given output power and the switch on-time varies as a function of the DC input voltage, as shown in Equation 2-36.

EQUATION 2-36:

From the TNY277 data sheet, the maximum switching frequency is 140 kHz, and a sensible maximum on-time is 4.5 μs. The minimum DC voltage is 120V, and the power at the transformer primary is 17W, assuming ~ 80% efficiency. It is worth noting that this is only a transient requirement, since once the dsPIC DSC device rails are established, the PFC will boost the DC input voltage to 400V. Equation 2-35 and Equation 2-36 can be rearranged to find the required primary magnetizing inductance of the transformer, as shown in Equation 2-37.

EQUATION 2-37:

tV f

on DC sw

Therefore, the target primary inductance is 1.2 mH and the peak primary current is

0.45A. The primary turns must be selected to ensure that the ferrite core losses are around 0.5W for thermal reasons. The EF20 core has a cross-sectional area of 32 mm and a volume of 1490 mm

The core loss can be computed from Equation 2-38.

EQUATION 2-38:

0.365

⎛⎞ ⎜⎟ ⎝⎠

Therefore, the peak flux density is about 150 mT . The required number of primary turns can be computed using Equation 2-39.

EQUATION 2-39:

Using the above formula, N EF20 core to give 1.2 mH inductance. To minimize the leakage inductance of the transformer, and hence the loss in the snubber/clamp, the primary winding is split into two layers of 55 turns each. The rms current in the primary is given by Equation 2-40.

is set at 110 turns, which requires a 0.5 mm air-gap in the

EQUATION 2-40:

Page 52

SMPS AC/DC Reference Design User’s Guide

off

It=

off

T t

From Equation 2-36, the on-time for the switch at 400V is 1.35 μs and the duty cycle is

0.19. Therefore, the rms current in the primary is 0.11 Arms. A suitable winding wire diameter is 0.16 mm with 5.5 Amm from the mean turn length of the bobbin (41.2 mm), the predicted primary resistance is 5Ω. Therefore, the primary copper loss is 60 mW.

The secondary turns must be selected to ensure that the referred voltage across the TNY277 does not exceed its maximum blocking voltage rating and for discontinuous current operation given the operating duty cycle. The peak voltage across the TNY277 when energy is transferred to the secondary is given by Equation 2-41.

EQUATION 2-41:

-2

. The 100ºC resistance of this wire is 1.1 Ωm-1, and

VV V

A sensible limit on the maximum switch voltage is 540V, so for the main 17V secondary output, including a 0.8V diode forward voltage drop, the required turns ratio is 7.86. Therefore, the secondary turns on the 17V winding is 14. A separate tapping at six turns on this winding can be used for the 7V secondary. The secondary winding is constructed using TEX-E wire to give the required 2500 Vrms galvanic voltage isolation.

The time taken for the flyback transformer to be de-fluxed is given by Equation 2-42.

EQUATION 2-42:

Therefore, the off period is 3.9 μs, which is lower than the maximum available period to ensure discontinuous operation under normal operating conditions.

The secondary peak and rms currents in the winding are given by the following formula in Equation 2-43 and Equation 2-44.

EQUATION 2-43:

DC o

off

EQUATION 2-44:

Therefore, the secondary current in the main 17V output is 0.7 Arms. The secondary winding resistance is 0.1Ω and the total copper loss in the secondary winding is estimated to be 50 mW. Keeping a similar winding current density as the primary means that a 0.4 mm wire gauge can be chosen for the secondary windings. The two auxiliary supply windings on the primary side follow directly from the chosen transformer turns ratio. The total transformer power dissipation is dominated by the iron loss and is roughly 0.8W. This will lead to a temperature rise of 40ºC, based on the published thermal characteristics of an EF20 transformer. Figure 2-15 illustrates the flyback transformer construction.

Page 53

Hardware Design

3 layers 0.05 mm Melinex

8 turns of 0.4 mm 6 turns of 0.4 mm

6 turns of 0.5 mm5 turns of 0.5 mm

55 turns of 0.16 mm

FIGURE 2-15: FLYBACK TRANSFORMER CONSTRUCTION

2.5.1.3 OUTPUT CAPACITORS The capacitors selected for outputs are 100 μF, 25V and 470 μF, 10V, for gate drive

voltage rails and the dsPIC DSC device voltage rails, respectively. The ripple current rating for United Chemi-Con electrolytic capacitors are 0.34 Arms and 0.64 Arms, respectively.

Page 54

SMPS AC/DC Reference Design User’s Guide

NOTES:

Page 55

3.1 OVERVIEW

85-265 VAC 45-65 Hz

EMI Filter

and Bridge

Rectifier

PFC

Boost

Converter

ZVT

Full-Bridge

Converter

Synchronous

Rectifier

Opto-

Coupler

3.3 V

69A

5 V

23A

Isolation

Barrier

420 V

Rectified

Sinusoidal

Voltage

Multi-Phase

Buck Converter

Single-Phase

Buck Converter

Phase-Shift ZVT Converter

dsPIC33FJ16GS504

12 VDC 30A

The SMPS AC/DC Reference Design is controlled using two dsPIC DSCs as shown in the block diagram in Figure 3-1.

The dsPIC DSC on the primary side (on the left of the isolation barrier in Figure 3-1) controls the PFC Boost Converter and the Phase-Shift ZVT Converter. The dsPIC DSC on the secondary side (on the right of the isolation barrier in Figure 3-1) controls the Multi-Phase Buck Converter and the Single-Phase Buck Converter.

The secondary side dsPIC DSC also performs the function of measuring the output voltage of the Phase-Shift ZVT Converter, and feeding back to the primary side dsPIC DSC as a digital feedback signal.

SMPS AC/DC REFERENCE

DESIGN USER’S GUIDE

Chapter 3. Software Design

Note: Any libraries and source files associated with SMPS AC/DC Reference

Design are available by request from your local Microchip sales office. See the Microchip Web site, or the last page of this document for contact information.

FIGURE 3-1: BLOCK DIAGRAM OF SMPS AC/DC REFERENCE DESIGN

Page 56

SMPS AC/DC Reference Design User’s Guide

Initialization

Start

Idle Loop

(Normal Operation)

Enable Peripherals

Fault Present?

Fault Loop

ADC Interrupt

Yes

Soft-Start

3.2 STRUCTURE OF THE CONTROL SOFTWARE

The control software for the SMPS AC/DC Reference Design essentially follows a single basic structure as shown in Figure 3-2.

FIGURE 3-2: FLOWCHART OF CONTROL SOFTWARE

The control software uses a mixture of C programming and Assembly programming. All time-critical functions are written in Assembly language. The main loop, peripheral setup routines, initialization routines and non-critical functions are all written using the C programming language.

The SMPS AC/DC Reference Design comprises of two separate projects, namely:

• Primary: This project contains the complete code for the primary side of the SMPS AC/DC Reference Design. This includes the control software for the PFC Boost Converter and the Phase-Shift ZVT Converter.

• Secondary: This project contains the complete code for the secondary side of the SMPS AC/DC Reference Design. This includes the control software for the Single-Phase Buck Converter and Multi-Phase Buck Converter, and also includes code for the ZVT output voltage measurement and digital voltage feedback.

All of the functional blocks shown in Figure 3-2 are common to both projects. Brief descriptions of each functional block are provided in subsequent sections.

Page 57

3.2.1 Initialization Routine

Software Design

The initialization routines are called from the main program at the start of execution. All peripherals including PWM, ADC, analog comparator, UART, I configured in this step. It is important that none of the peripherals are enabled before the entire peripheral configuration is completed.

In addition to configuring the peripherals, all required interrupts and interrupt priorities are configured in the initialization step. Memory allocation for control loop variables is also done during the initialization stage.

C™ and Timers are

3.2.2 Peripheral Enable Routine

After configuring all peripheral modules that are used in the project, we enable them in the correct sequence. Since the PWM output directly affects the output of the system, it is important to enable it after all other peripherals have been enabled.

3.2.3 Soft-Start Routine

Each individual stage of the SMPS AC/DC Reference Design employs a controlled soft-start routine. This routine ramps individual output stages to the desired output voltage.

3.2.4 Fault Check Routine

The fault check routine is used to check for faults that have occurred in the system. If a fault has occurred, the system has to be shut down. To do this, the fault loop is called and used to disable all active modules, such as the ADC and PWM, and to visually display the fault on the LEDs.

The PWM module on the dsPIC33FJ16GS504 has built-in fault inputs that ensure a fast PWM shutdown in order to prevent damage to the system and downstream electronics. After the PWM is shutdown, the program execution jumps to the fault loop.

3.2.5 ADC Interrupt Service Routine

The ADC Interrupt Service Routine (ISR) is the heart of the control software. All control loops are executed in the ISR. Since faster control loop execution is desired for the best system performance, functions executed in this routine are written in Assembly language. The ADC ISR has the highest priority of execution.

The ADC module is configured to generate interleaved interrupt requests in order to execute multiple control loops within the same ISR.

The implementation of the control software for each stage of the SMPS AC/DC Reference Design contains all the blocks described above. However, there are subtle differences in the implementation for each stage.

Specific details for each stage of the design are covered in subsequent sections of this user’s guide.

Page 58

SMPS AC/DC Reference Design User’s Guide

Voltage

Reference

VOUT

PFC

Choke

Voltage Feedback

PWM

Current

Feedback

PFC

Current

Sense

OUT

Sense

Voltage Error

Compensator

ADC

1001011011

1011001010

Current Error Compensator

Rectified

AC Mains

Voltage

Current

Reference

|VAC|MEAN

S&H

Calculated

3.3 PRIMARY SIDE CONTROL SOFTWARE (PFC_ZVT)

The PFC Boost Converter and Phase-Shift ZVT Converter follow a similar control scheme. However, there are significant differences in the operation of these two converters. These differences will be explained in the description of the control software for each conver ter.

3.3.1 PFC Boost Converter Control Softwar e

3.3.1.1 PFC CONTROL SCHEME

The control scheme implemented for the PFC Boost Converter is shown in Figure 3-3.

FIGURE 3-3: PFC CONTROL SCHEME

The PFC Boost Converter uses an outer voltage loop and inner current loop control scheme. The output of the voltage error compensator is multiplied by a function of the rectified AC mains voltage to generate a sinusoidal current reference.

An additional feed-forward term is introduced, |V error compensator to make the control loop immune to fluctuations in the AC input

AC|MEAN, at the output of the voltage

voltage. This feed-forward term ensures that the PFC Boost Converter always delivers the correct output power for the entire input voltage range.

The PFC voltage and current error compensators are both implemented as Proportional-Integral (PI) systems with excess error compensation. The compensator functions are math intensive routines and utilize the DSP engine of the dsPIC DSC. The output of the PFC Current compensator modifies the PWM duty cycle to maintain a constant output voltage and also a sinusoidal input current waveform.

Both the current and voltage compensators are executed in the ADC ISR. The current control loop is executed at a much faster rate compared to the voltage control loop.

Page 59

Software Design

VAC

IPFC

VHV_BUS

ADC Channel

ADC

Channel

ADC

Channel

PWM

Output

AC|

FET Driver

dsPIC33FJ16GS504

3.3.1.1.1 Digital PFC Implementation Using the dsPIC DSC Figure 3-4 shows the hardware resources utilized on the primary side dsPIC DSC for

Power Factor Correction.

FIGURE 3-4: dsPIC

DSC RESOURCE ALLOCATION FOR PFC BOOST CONVERTER

T able 3-1 lists the resources used on the dsPIC DSC for implementing the PFC control scheme shown in Figure 3-3.

TABLE 3-1: dsPIC

Description Type of Signal dsPIC® DSC Resource Used

HV_BUS Analog Input AN5

PFC Current (I |VAC| Sense Analog Input AN3 MOSFET Gate Drive Drive Output PWM4L

PFC) Analog Input AN4

DSC RESOURCES FOR PFC BOOST CONVERTER

The control of the PFC Boost Converter is obtained by varying the duty cycle of the PWM signal. Only one pin of the PWM is utilized for the PFC control scheme, and therefore the PWM module is configured for independent output mode. The frequency of the PWM is determined by the hardware design. It is configured to be approximately 125 kHz.

The Analog Inputs AN4 and AN5 are configured to sample simultaneously. A conversion is triggered on both AN4 and AN5 once every 3 PWM cycles, and the current loop is executed on every conversion. The voltage loop is executed only once in 15 curr ent loop executions.

The Analog Input AN3 measures the AC Input voltage, which is used for generating a sinusoidal current reference. In the SMPS AC/DC Reference Design, the current reference value is calculated when the current loop is executed.

Page 60

SMPS AC/DC Reference Design User’s Guide

Voltage

Reference

VOUT

ZVT

Transformer

Voltage

Update

Phase

Overcurrent

Protection

ZVT Current Sense

OUT

Sense

Voltage Error Compensator

ADC

1001011011

1011001010

S&H

Rectifier

Optocoupler

S&H

for overcurrent protection

ADC

1011001010

UART

Feedback

PWM

3.3.2 Phase-Shift ZVT Control Scheme

3.3.2.1 ZVT RESOURCE ALLOCATION

The control scheme for the Phase-Shift ZVT Converter is shown in Figure 3-5. A schematic of the Phase-Shift ZVT Converter is shown in Figure 3-6.

FIGURE 3-5: PHASE-SHIFT ZVT CONVERTER CONT RO L SCHEME

The ZVT converter uses voltage mode control to maintain a constant output voltage. The circuit configuration of the ZVT converter has the output voltage (the parameter to be controlled) on the secondary side of the isolation barrier (refer to Figure 3-8).

The SMPS AC/DC Reference Design implements the ZVT voltage feedback by measuring the output voltage using the secondary side dsPIC DSC. The Most Significant 8 bits of data are transmitted back to the primary side dsPIC DSC through a UART communication channel.

The data received by the primary side dsPIC DSC is right-shifted by two bits (for 10-bit data) and is compared with the voltage reference to produce the voltage error. The voltage error compensator is then executed in the ADC ISR.

The output of the voltage error compensator is feed into the phase-shifted PWM. The Phase-Shift ZVT converter uses the unique phase-shifting capability of the PWM module in the dsPIC33FJ16GS504. The phase of the PWM signal can be modified by simply writing the new value in the appropriate Special Function Register in the PWM module.

Page 61

FIGURE 3-6: ZVT PHASE-SHIFT CONVERTER

VIN

IPRI

VPRI

VSEC

VOUT

Software Design

Current sensing for the Phase-Shift ZVT Converter uses two dedicated analog inputs to measure the primary transformer current in both directions. The two analog inputs are tied to the same current signal, but are sampled at opposite current peaks. The precise triggering instants are in Figure 3-7 along with the expected current waveform. The current in the positive and negative directions must be measured and checked for any imbalance. If the currents in the two directions are not balanced, it may cause a phenomenon called “flux walking” in the ZVT transformer. Flux walking must be prevented since it may lead to transformer saturation and subsequent damage to the system hardware.

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SMPS AC/DC Reference Design User’s Guide

1PWM

2PWM

3PWM

4PWM

ADC Trigger generated

by PWM2 at beginning

of PWM cycle

ADC Trigger generated by PWM1 at duty cycle

(1)

Note 1: The shaded regions represent the times when power is transferred from the primary side to the

secondary side. This region is sometimes referred to as the “effective” ZVT duty cycle.

minus phase shift

FIGURE 3-7: ZVT CURRENT SAMPLING INSTANTS

The voltage compensator is implemented as a Proportional-Integral-Derivative (PID) function. The voltage compensator is executed in the ADC ISR.

Page 63

Software Design

ADC

Channel

ADC

Channel

UART

PWM

UART

PWM

IZVT

VHV_BUS

VOUT

Isolation

Barrier

ADC

Channel

PWM

FET

Driver

FET

Driver

FET

Driver

dsPIC33FJ16GS504

3.3.2.2 PHASE-SHIFT ZVT IMPLEMENTATION USING THE dsPIC DSC

FIGURE 3-8: dsPIC

DSC RESOURCE ALLOCATION FOR PHASE-SHIFT ZVT CONVERTER

Table 3-2 lists the resources used on the primary side dsPIC DSC for the different feedback and control signals required for the Phase-Shift ZVT Converter control scheme. Table 3-3 lists resources used on the secondary side dsPIC DSC, also required for the Phase-Shift ZVT Converter control scheme.

T ABLE 3-2: PRIMARY SIDE dsPIC

DSC RESOURCES FOR PHASE-SHIFT

ZVT CONVERTER

Description Type of Signal

ZVT Current 1 (I ZVT Current 2 (I

OUT Feedback UART Input U1RX

V Full-Bridge Gate Drive Drive Output PWM1H, PWM1L,

ZVT1) Analog Input AN0 ZVT2) Analog Input AN2

dsPIC

DSC Resource

Used

PWM2H, PWM2L

Synchronous Rectifier Gate Drive Drive Output PWM3H, PWM3L

TABLE 3-3: SECONDARY SIDE dsPIC

DSC RESOURCES FOR

PHASE-SHIFT ZVT CONVERTER

Description Type of Signal

Volt a ge Sens e (VOUT) Analog Input AN5 V

OUT Feedback UART Output U1TX

The Phase-Shift ZVT Converter is controlled by modifying the phase of the PWM drive signals of one leg of the Full-Bridge relative to the drive signals of the other leg of the Full-Bridge.

dsPIC

DSC Resource

Used

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SMPS AC/DC Reference Design User’s Guide

PWM1H

PWM1L

PWM2H

PWM2L

PWM4L

ZVT Trigger:

Once every 2 ZVT Cycles

PFC Current Trigger:

Once every 3 PFC Cycles

Sample and Convert

AN0, AN1

Execute

ZVT

Voltage

Loop

Sample and Convert

AN4, AN5

Execute

PFC

Current

Loop

Idle Loop

PFC Current Trigger:

Once every 3 PFC Cycles

Phase

Shift

Execute

ZVT

Voltage

Loop

Execute

ZVT

Voltage

Loop

Execute

PFC

Current

Loop

Sample and

AN4, AN5

ADC Pair 0 has highest priority

Convert

As specified in Table 3-2, PWM1H, PWM1L, PWM2H, and PWM2L are the PWM signals used for switching the Full-Bridge MOSFET s. PWM1H and PWM1L control one leg of the Full-Bridge, while PWM2H and PWM2L control the second leg of the Full-Bridge.

PWM1 and PWM2 are configured to operate in the complementary PWM mode and approximately 250 kHz switching frequency. The duty cycle of these PWM signals is fixed at 50%. Some dead time is also inserted to prevent shoot-through.

PWM3 is used for driving the synchronous rectifier MOSFETs on the secondary side of the ZVT Transformer. PWM3 is also configured as a complementary mode PWM signal with dead time. The PWM3 signal is configured identically to that of PWM1. The output of the control loop directly modifies the phase of PWM2 to accomplish the control of the output.

AN0 and AN2 both measure the ZVT current, but each input is sampled on opposite peaks of the current signal. The conversion result of AN0 is used for the ZVT overcurrent primary side dsPIC DSC.

The voltage loop is executed every two PWM periods, but the measured voltage is only updated when data is received by the UART. This UART data reception is asynchronous to the PWM drive signals.

3.3.3 Primary Side Software Time Management

fault protection. The voltage feedback is received on the U1RX pin of the

Both the PFC and ZVT converters are controlled using a single dsPIC DSC. The execution rates are carefully chosen to effectively utilize the available processing bandwidth of the dsPIC DSC. The flexible PWM-ADC trigger feature of the dsPIC33FJ16GS504 enables precise sampling of analog signals and interleaved control loop execution.

Figure 3-9 shows the interleaved control loop execution as implemented on the primary side control software on the SMPS AC/DC Reference Design.

FIGURE 3-9: INTERLEAVED CONTROL LOOP EXECUTION

Page 65

Software Design

Voltage

Reference

OUT

Buck

Inductor

Voltage Feedback

PWM

Buck

Current

Sense

OUT

Sense

Voltage Error Compensator

ADC

1001011011

S&H

Analog Comparator

REF

Calculated

Current

Reference

Current-Limit

Shutdown

3.4 SECONDARY SIDE CONTROL SOFTWARE (DC_DC)

3.4.1 Single-Phase Buck Converter

3.4.1.1 SINGLE-PHAS E BUCK CONVERTER CONTROL SCHEME The Single-Phase Buck Converter on the SMPS AC/DC Reference Design uses peak

current mode control. The control scheme is shown in Figure 3-10. The control loop is implemented by utilizing the analog comparator module. The Buck

MOSFET current is sensed using a current transformer and fed directly to the analog comparator input.

FIGURE 3-10: SINGLE-PHASE BUCK CONVERTER CONTROL SCHEME

The measured output voltage is compared with the reference to produce the voltage error. The voltage error compensator is then executed and a current reference value is obtained. The current control loop is implemented on the dsPIC DSC using the analog comparator by varying the programmable threshold in software.

The analog comparators on the dsPIC33FJ16GS504 have built-in programmable Digital-to-Analog Converters (DACs) that determine the comparator threshold. The calculated current reference is used to set a new threshold for the analog comparator.

When the inductor current signal exceeds the programmed threshold, the comparator terminates the PWM pulse. This termination of the PWM pulse effectively modifies the ON time for the PWM signal to control the output voltage.

The Voltage Error Compensator is implemented as a PI function in the ADC ISR.

3.4.1.2 SINGLE-PHAS E BUCK CONVERT E R IMPL EM ENTAT I ON USIN G THE dsPIC DSC

The resources used on the secondary side dsPIC DSC for the Single-Phase Buck Converter are summarized in Table 3-4.

TABLE 3-4: dsPIC

Description Type of Signal dsPIC® DSC Resource Used

Buck Current Analog Comparator Input CMP1A, AN0 Buck Voltage (V Single-Phase Synchronous

Buck Gate Drive

OUT) Analog Input AN1

BUCK CONVERTER

DSC RESOURCE ALLOCATION FOR SINGLE-PHASE

Drive Output PWM4H, PWM4L

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SMPS AC/DC Reference Design User’s Guide

Voltage

Reference

OUT

Phase 3

Inductor

Voltage Feedback

PWM

OUT

Sense

Voltage

Compensator

ADC

1001011011

S&H

Phase 2

Inductor

Phase 1

Inductor

Update

PWM Cycle

PWM

Duty

Error

The output voltage is measured using the analog input AN1. The analog comparator input CMP1A is connected to the output of the current transformer. The output voltage is controlled by varying the duty cycle of PWM4.

The PWM4 pair is operated in Complementary mode with dead time. The switching frequency is approximately 500 kHz. The duty cycle is controlled directly by the built-in Cycle-by-Cycle Current-Limit mode and the analog comparator.

When the current-sense signal at the input of the analog comparator exceeds the programmed comparator threshold, the PWM output is immediately terminated for the remainder of the PWM cycle.

The Single-Phase Buck Converter circuitry is designed to operate in continuous conduction mode at load currents greater than approximately 3A. If the Single-Phase Buck Converter is operated in Discontinuous Conduction mode, the freewheeling MOSFET is disabled through software.

At no load and light load current (< 3A), the PWM output may enter a “burst” mode. This is caused by a low demand for load current by the converter in this range load current.

The voltage control loop is executed in the ADC ISR every two PWM cycles.

3.4.2 Multi-Phase Buck Converter

3.4.2.1 MULTI-PHASE BUCK CONVERTER CONTROL SCHEME Voltage mode control is used for controlling the output of the Multi-Phase Buck

Converter on the SMPS AC/DC Reference Design. As shown in Figure 3-11, the control sc heme only implements a single control loop.

FIGURE 3-11: MULTI-PHASE BUCK CONVERTER CONTROL SCHEME

The output voltage is compared with the reference and results in a voltage error, which is fed as an input to the voltage error compensator. The output of the voltage error compensator modifies the duty cycle of all phases of the Multi-Phase Buck Converter.

The voltage error compensator is implemented as a PID function that is implemented in the ADC ISR.

The Multi-Phase converter comprises of three individual phases, but the output is controlled by a single duty cycle that identically drives the three phases. The PWM drive signals for each phase are phase shifted by 120 degrees using the built-in PWM phase-shifting feature available on the dsPIC33FJ16GS504. The PWM drive signals for the Multi-Phase Buck Converter are shown in Figure 3-12.

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Software Design

12V Input

3.3V Output

GND

120º 120º 120º

Drive Signals are

Phase-Shifted by 120º

FIGURE 3-12: MULTI-PHASE BUCK CONVERTER PWM DRIVE SIGNALS

3.4.2.2 MULTI-PHASE BUCK CONVERTER IMPLEMENTATION USING THE dsPIC DSC

Table 3-5 summarizes the resource allocat ion for the Multi-Phase Buck Converter.

TABLE 3-5: dsPIC

DSC RESOURCE ALLOCATION FOR MULTI-PHASE

BUCK CONVERTER

Description Type of Signal dsPIC® DSC Resource Used

Buck 1 Curre nt Analog Comparator Input CMP2A Buck 2 Curre nt Analog Comparator Input CMP3A Buck 3 Curre nt Analog Comparator Input CMP4A Buck Voltage Analog Input AN3 Multi-Phase Synchronous

Gate Drive

Drive Outputs PWM1H, PWM1L,

PWM2H, PWM2L,

PWM3H, PWM3L

The output voltage is measured from the analog input AN3. As this converter uses voltage mode control, there is no need for current measurement. However, overcurrent protection must be provided for each individual phase. Overcurrent protection is implemented using the analog comparators on the dsPIC33FJ16GS504. CMP2A, CMP3A and CMP4A are used for the overcurrent sensing for the Multi-Phase Buck Converter.

Each of the three phases is driven by a pair of complementary PWM signals. The PWM module on the dsPIC33FJ16GS504 provides a built-in mode to generate a pair of complementary PWM outputs with dead time insertion. The PWM module also has a feature to generate a Master Period and Master Duty Cycle for multiple outputs. PWM1, PWM2, and PWM3 are all configured for a PWM switching frequency of approximately 500 kHz, and complementary mode operation with dead time.

PWM2 is phase advanced by 120 degrees from PWM1, and PWM3 is phase advanced by 120 degrees from PWM2 (or 240 degrees from PWM1). The voltage control loop is executed every two PWM cycles. The control loop is called from the ADC ISR.

The output of the voltage control loop is used to directly modify the PWM Master Duty Cycle to control the output voltage.

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SMPS AC/DC Reference Design User’s Guide

PWM1H PWM1L

PWM2H PWM2L

PWM3H PWM3L PWM4H PWM4L

3.3V Buck

Voltage Trigger

Execute

3.3V

Buck

Control

Loop

Sample

and

Convert

AN2, AN3

Idle

Loop

Execute 5V Buck

Control

Loop

Sample

and

Convert

AN0, AN1

Idle

Loop

5V Buck

Voltage Trigger

Execute 5V Buck

Control

Loop

Sample

and

Convert AN0, AN1

Idle

Loop

5V Buck

Voltage Trigger

3.3V Buck

Voltage Trigger

Execute

3.3V

Buck

Control

Loop

Sample

and

Convert

AN2, AN3

Idle

Loop

Execute

5V Buck

Control

Loop

Idle

Loop

5V Buck

Voltage Trigger

3.3V Buck

Voltage Trigger

Execute

3.3V

Buck

Control

Loop

Sample

and

Convert

AN2, AN3

Sample

and Convert AN0, AN1

3.4.3 Secondary Side Software Time Management

The Single-Phase Buck Converter and Multi-Phase Buck Converter are both controlled digitally by the same dsPIC DSC. Both converters operate at the same switching frequency.

The two control loops are executed in an interleaved manner as shown in Figure 3-13. The execution rate for each control loop is once every other PWM cycle. The execution rate is determined by the execution times of each control loop.

The ADC ISR assumes the highest priority of all user software. Other interrupts are assigned lower priority than the ADC interrupt, and all auxiliary software functions are performed in the “Idle loop” (when the ADC interrupt is not being serviced).

FIGURE 3-13: INTERLEAVED CONTROL LOOP EXECUTION FOR SINGLE-PHASE AND

MULTI-PHASE BUCK CONVERTERS

3.5 AUXILIARY SOFTWARE ROUTINES

3.5.1 Output Sequencing

Many applications require specific turn-on and turn-off sequencing of power supplies to ensure correct operation of the downstream electronics. The SMPS AC/DC Reference Design implements power-on sequencing in the following order:

1. Initial start-up delay (allows all circuitry to stabilize after power-up).

2. PFC Converter ramps to around 420V.

3. Phase-Shift ZVT Converter ramps to 12V.

4. Single-Phase Buck Converter ramps to 5V.

5. Multi-Phase Buck Converter ramps to 3.3V.

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Software Design

3.5.2 Soft-Start Routine

Each individual stage of the SMPS AC/DC Reference Design employs a controlled soft-start routine. At power-up, all reference set points are configured to produce 0V output. Once the power-on delay has lapsed, the outputs begin their soft-start where the reference set point is incremented until the desired output voltage is reached.

3.5.3 Overtemperature Protection

Temperature sensors are provided on the SMPS AC/DC Reference Design in two positions. Overtemperature protection must be enabled to prevent damage to the system in the event of:

• Insufficient airflow in the system caused by a failure of the cooling fan

• Operation of the system at a high ambient temperature The implementation detail for each sensor is described in the following sections.

3.5.3.1 PCB OVERTEMPERATURE PROTECTION One of the PCB temperature sensors is located on the secondary side in the middle of

the four Buck phases. The other temperature sensor is located on the primary side just below the Boost inductor (L4). An analog temperature sensor is chosen that outputs an analog voltage proportional to the measured temperature.

The output of the temperature sensor is connected to analog input AN8 on the secondary side dsPIC DSC, and AN10 on the primary side dsPIC DSC. The PCB temperature is measured in the ADC ISR and checked for overtemperature protection in the fault loop. The maximum temperature set point is configured to approximately 90°C. If the measured temperature exceeds the maximum set point, a fault is generated and the PWM outputs are turned OFF.

3.5.4 Input AC Undervoltage/Overvoltage Protection

The PFC Boost Converter is designed to operate normally for input voltages in the range 85V–265V. In the event of an undervoltage condition, the circuit components will undergo excessive stress due to the additional current drawn by the system to deliver maximum output power. Therefore, undervoltage and overvoltage faults must be implemented to prevent damage to the system and load. In the event of an overvoltage condition, the input voltage may exceed the device ratings.

There are instances when the power grid may exhibit momentary voltage fluctuations, which must be ignored by the system.

The input AC voltage protection is implemented in software by calculating the average input voltage in the ADC ISR. The average input voltage is calculated as a part of the PFC control scheme, and is checked in the fault loop to detect a sustained undervoltage/overvoltage condition.

The first time an undervoltage/overvoltage condition is detected, a counter is incremented. If the undervoltage/overvoltage condition remains for an extended period of time, a fault is generated and the outputs are turned OFF.

3.5.5 Fault Source Identification

If a Fault condition is detected, it is often required that the system be turned OFF to prevent damage. The PWM module on the dsPIC33FJ16GS504 has a built-in latched fault mode. Using the latched fault mode, certain faults will immediately disable the PWM outputs with no software overhead.

Each fault is assigned a fault ID to indicate the source of the last fault that occurred. A visual indication is also provided using LEDs on both the primary and secondary side of the SMPS AC/DC Reference Design.

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SMPS AC/DC Reference Design User’s Guide

The LED flashes the same number of times as the fault ID of the source that caused the fault. The source of the fault can be decoded using the values in Table 3-6 and Table 3-7.

TABLE 3-6: FAULT SOURCE INDICATION ON PRIMARY SIDE

Fault ID Source of Fault

1 PCB overtemper ature 2 PFC output overvoltage 3 ZVT overcurrent 4 AC overvoltage 5 AC undervoltage 6 Secondary UART failure 7 System overlo ad

TABLE 3-7: FAULT SOURCE INDICATION ON SECONDARY SIDE

Fault ID Source of Fault

1 12V Buck overvoltage 2 12V Buck undervoltage 3 Multi-phase overcurrent 4 PCB overtemper ature 5 Single-phase overcurrent

Page 71

Chapter 4. System Operation

85-265 VAC 45-65 Hz

EMI Filter

and Bridge

Rectifier

PFC

Boost

Converter

ZVT

Full-Bridge

Converter

Synchronous

Rectifier

Optocoupler

3.3 VDC 69A

5 V

23A

Isolation

Barrier

420 V

Rectified

Sinusoidal

Voltage

Multi-Phase

Buck Converter

Single-Phase

Buck Converter

Phase-Shift ZVT Converter

dsPIC33FJ16GS504

12 VDC 30A

This chapter describes the system setup and operation of the SMPS AC/DC Reference Design.

4.1 SYSTEM SETUP

4.1.1 Recommended Test Equipment

The following list of test equipment is recommended for complete evaluation of the SMPS AC/DC Reference Design and/or development of software.

• Oscilloscope

• High Voltage Probe (100:1 attenuation ratio) or Differential Probe

• 10A AC Current Probe

• Power Quality Meter

• DC Electronic Load (350W or higher, and should have capability to load at least two outputs simultaneously)

• 0V-265V Variac or Programmable AC Source (500W or higher)

• Two Digital Multimeters

SMPS AC/DC REFERENCE

DESIGN USER’S GUIDE

4.1.2 Functional Blocks of the System

Figure 4-1 shows a block diagram of the SMPS AC/DC Reference Design. Table 4-1 describes the inputs and outputs of the system and also displays the location of the isolation barrier. To assist in identifying each functional block on the SMPS AC/DC Reference Design, Figure 4-2 shows a top-view of the system with each block called out with dotted lines.

FIGURE 4-1: SMPS AC/DC REFERENCE DESIGN BLOCK DIAGRAM

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SMPS AC/DC Reference Design User’s Guide

1. EMI Filter

2. Single-Phase Converter

3. Multi-Phase Converter

4. Primary Side Controller

5. Secondary Side Controller

6. Bridge Rectifier

7. PFC Boost Converter

8. ZVT Full-Bridge Converter

9. Synchronous Rectifier

10. 12V Output (Intermediate Bus)

11. 3.3V Output

12. 5V Output

FIGURE 4-2: FUNCTIONAL BLOCKS OF SMPS AC/DC REFERENCE DESIGN

TABLE 4-1: INPUT AND OUTPUT ELECTRICAL SPECIFICATIONS

Functional Block Input Output

EMI Filter 85-265V AC, 45-65 Hz 85-265V AC, 45-65 Hz Bridge Rectifier 85-265V AC, 45-65 Hz 120-374V DC (unregulated) PFC Boost Converter 120-374V DC (unregulated) 420V DC Full-Bridge Converter 420V DC N/A Synchronous Rectifier N/A 12V DC Multi-Phase Buck Converter 12V DC 3.3V DC Single-Phase Buck Converter 12V DC 5V DC

4.1.3 Safety Isolation Information

The SMPS AC/DC Reference Design provides safety isolation to protect users and downstream electronics from the input AC Mains voltage. The location of the isolation boundary on the SMPS AC/DC Reference Design is displayed with a dotted line in Figure 4-3.

Page 73

System Operation

Isolation Boundary

+12V GND

+3.3V

GND

+5V GND

FIGURE 4-3: ISOLATION BOUNDARY ON SMPS AC/DC REFERENCE

DESIGN

NOTICE

During testing and evaluation of the SMPS AC/DC Reference Design, no equipment should be connected across the isolation boundary. This applies to oscilloscope probes, multimeters, and programm ers/debuggers. Under no c ircumstan ces should the Live_GND (on the primary or “live” side) and GND (on the secondary or “isola ted” side) be tied together.

As a general rule, the primary (live) side and the secondary (isolated) side should always be tested independently with no connections across the isolation boundary.

Before connecting oscilloscope probes to the SMPS AC/DC Reference Design, ensure that the oscilloscope is isolated from the SMPS AC/DC Reference Design.

Table 4-2 lists the location where each functional block resides with respect to the isolation barrier.

TABLE 4-2: LOCATION OF FUNCTIONAL BLOCK WITH RESPECT TO

ISOLATION BARRIER

Live or Isolated Side?

Functional Block

EMI Filter Primary (Live) N/A Bridge Rectifier Primary (Live) N/A PFC Boost Converter Primary (Live) Primary (Live) Full-Bridge Converter Prima ry (Live) Primary (Live) Synchronous Rectifier Secondary (Isolated) Primary (Live) Multi-Phase Buck Converter Secondary (Isolated) Secondary (Isolated) Single-Phase Buck Converter Secondary (Isolated) Secondary (Isolated)

Power Circuit Control Circuit

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SMPS AC/DC Reference Design User’s Guide

Live

Earth

(No connection)

Neutral

+12V GND

+3.3V

GND

+5V GND

4.1.4 System Connections

4.1.4.1 INPUT CONNECTIONS The AC input connector (J16) is shown in Figure 4-4. The SMPS AC/DC Reference

Design has a transparent lid (not shown in pictures) with a 12V fan mounted on it. There are three holes provided in the lid to fasten the connection screws on the AC input connector (J16).

Ensure th at the power chor d is not conne cted to the V ari ac or programm able AC sourc e (or AC Mains). Connect the AC cord with terminal lugs to the AC input connector in the configuration shown in Figure 4-4.

FIGURE 4-4: SMPS AC/DC REFERENCE DESIGN INPUT CONNECTIONS

This is the minimum connection required to power up the SMPS AC/DC Reference Design. However, other connections are recommended for detailed testing and evaluation of the system.

4.1.4.2 OUTPUT CONNECTIONS Ensure that the SMPS AC/DC Reference Design is not powered. Connect DC

Electronic Loads (if available) to the 5V and 3.3V output terminals shown in Figure 4-5.

FIGURE 4-5: SMPS AC/DC REFERENCE DESIGN OUTPUT CONNECTIONS

A DC electronic load can be used to adjust the output power delivered by the SMPS AC/DC Reference Design. If a DC electronic load is not available, a rheostat or resistors with sufficient power ratings may also be used for loading the SMPS AC/DC

Reference Design.

Page 75

System Operation

Primary Side

ICSP™ Header

Secondary Side

ICSP™ Header

4.1.4.3 PROGRAMMING CONNECTIONS

The SMPS AC/DC Reference Design comes pre-programmed with the control software and does not require a programmer to be connected to the system. However, ICSP™ headers are provided on the primary and secondary side for software development and testing.

Figure 4-6 shows the location of the primary side programming header (J2 on the control board).

FIGURE 4-6: PRIMARY SIDE PROGRAMMING HEADER

CAUTION

The primary side ICSP header (J2) is not isolated from the AC Mains. An isolated USB hub must be used to connect the prog ramm er to the c ompu ter's USB port. If the power supply of the SMPS AC/DC Reference Design is not isolated before programming the device, ensure that the computer is isolated or removed from the grid.

Figure 4-7 shows the location of the secondary side programming header (J1 on the control board).

FIGURE 4-7: SECONDARY SIDE PROGRAMMING HEADER

The secondary side ICSP header is isolated from the AC Mains, so there are no special precautions necessary when programming the device.

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SMPS AC/DC Reference Design User’s Guide

–

Reference Design

AC Mains

Series Ammeter Power Quality Meter

–

SMPS AC/DC

Reference Design

AC Mains

Clamp-on Ammeter Power Quality Meter

SMPS AC/DC

4.2 SYSTEM OPERATION

4.2.1 System Power-Up

Once the input and output connections as described in Section 4.1.4 “System Connections” are completed, the mains voltage can be applied to the SMPS AC/DC

Reference Design. There are three power-on indicator LEDs on the system. One LED (D38) on the power

board near the AC input terminals, and two more on the control board (one on the primary side (LED1), and one on the secondary side (LED2)).

There will be a short delay before the 12V, 5V , and 3.3V outputs are ON because of the soft-start routines and output sequencing scheme implemented on each stage of the SMPS AC/DC Reference Design. Details of the soft-start routine and output sequencing are provided in Chapter 3. “Software Design”.

As soon as the 12V output is ON, the cooling fan mounted on the lid will start running. LEDs are provided near each output terminal to indicate that the output is ON.

Faults are indicated on the control board with two LEDs (one on the primary side (D34) and one on the secondary side (D33)). Details of faults are provided in Chapter

3. “Software Design”.

4.2.2 System Evaluation and Testing

4.2.2.1 INPUT PERFORMANCE TESTING The input specifications of the SMPS AC/DC Reference Design can be tested by using

a power meter. The voltage is measured directly across the Live and Neutral terminals on the SMPS AC/DC Reference Design. The input current is measured by sensing the current through either the Live or Neutral line. Figure 4-8 shows two separate power meter connections depending on the type of power meter used.

FIGURE 4-8: TYPICAL POWER METER CONNECTIONS

Page 77

System Operation

A power meter is capable of measuring the input Power Factor of the SMPS AC/DC Reference Design and also the Total Harmonic Distortion (THD) on the current drawn by the system.

Using a programmable AC source will enable the user to evaluate the system performance over the entire range of input voltage (85V-265V, 45Hz-65Hz).

4.2.2.2 OUTPUT PERFORMANCE TESTING

The SMPS AC/DC Reference Design can be loaded using DC electronic loads. A number of output parameters can be tested by connecting oscilloscope probes to the output terminals. Some of the parameters that can be tested are:

• Output Ripple Voltage

• Load Regulation

• Transient Response

• Step-Load Response

• Fault Shutdown Delay

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SMPS AC/DC Reference Design User’s Guide

NOTES:

Page 79

SMPS AC/DC REFERENCE

GND

+5V

+3.3V +12V

GND

SMPS Power Rev C.1

FAN

DESIGN USER’S GUIDE

Appendix A. Board Layouts and Schematics

A.1 INTRODUCTION

This appendix contains the schematics and layouts for the SMPS AC/DC Reference Design (Power board and Signal board).

A.2 SMPS AC/DC REFERENCE DESIGN LAYOUT

FIGURE A-1: SMPS AC/DC REFERENCE DESIGN LAYOUT (POWER BOARD)

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SMPS AC/DC Reference Design User’s Guide

FIGURE A-2: SMPS AC/DC REFERENCE DESIGN LAYOUT (SIGNAL BOARD)

Page 81

Board Layouts and Schematics

EARTH EARTH

NEUTRAL

EARTH

LIVE

EMC_NEUTRAL

EMC_LIVE

A.3 SMPS AC/DC REFERENCE DESIGN SCHEMATICS

FIGURE A-3: EMI FILTER SCHEMATIC

Page 82

SMPS AC/DC Reference Design User’s Guide

EMC_NEUTRAL

PFC_SHUNT_NEG

LIVE_DRIVE_SUPPLY

EMC_NEUTRAL

EMC_LIVE

EARTH

D15

BAT54S_SOT23

DNP

EMC_LIVE

-HV_BUS

PFC_FIRE

1N5408D23

|VAC|_SENSE

-HV_BUS

LIVE_GND

+HV_BUS

BAS16

D10

DO-220 Formed

STTH5R06D

+HV_BUS

GBU8

BR1

C31

BAS16

D12

NTC1

D=21mm, P=7.5mm

HV_LINK_SENSE

FIGURE A-4: PFC CIRCUIT SCHEMATIC

Page 83

FIGURE A-5: FULL-BRIDGE ZVT SCHEMATIC

+HV_BUS

DRIVE_B

LIVE_GND

DRIVE_D

DRIVE_B

DRIVE_A

LIVE_GND

BAS16

DRIVE_A

DRIVE_D

DRIVE_C

BRIDGE_B

DRIVE_C

C6C8

ZVT_LEFT_LOW_FIRE

ZVT_LEFT_HIGH_FIRE

-HV_BUS

ZVT_RIGHT_LOW_FIRE

LIVE_DRIVE_SUPPLY

ZVT_RIGHT_HIGH_FIRE

D47

D45

BRIDGE_A

D49

BAS16

LIVE_DRIVE_SUPPLY

Connect Resistor and Transformer Directly to Source

and then connect to -HV_BUS

D48

C5C7

BAS16

Board Layouts and Schematics

Page 84

SMPS AC/DC Reference Design User’s Guide

LIVE_GND

ZVT_CT_|BURDEN|_POS

BRIDGE_B

BRIDGE_A

LIVE_GND

+DIG

SR#1_FIRE

DRIVE_SUPPLY

NEG_OUT

LIVE_GND

12V_BUS_ERROR_F/B

D11

BAT54S_SOT23

+HV_BUS

R13

DNP

NEG_OUT

SR#2_FIRE

BAS16

9uH

C24

1000pF

C25

D13

BAT54S_SOT23

C20

4.7nF

SYNCH_RECT_#2_FIRE

SYNCH_RECT_#1_FIRE

12V_F/B_OPTO_CATHODE

NEG_OUT

SR#1_FIRE

12V_F/B_OPTO_ANODE

12V_OUT

12V_F/B_OPTO_ANODE

2N2 Y2

C43

SR#2_FIRE

12V_F/B_OPTO_CATHODE

12V_OUT

C21

100pF

SFH617-2

Q23

R14

15R 3W AX P=20mm

BAS16

9uH

S4S

P6P

10mm dia, 5mm pitch

FIGURE A-6: SYNCHRONOUS RECTIFIER AND ZVT CURRENT SENSE SCHEMATIC

Page 85

Board Layouts and Schematics

+HV_BUS

LIVE_GND

100nF

1N4007

D22

D30

DRIVE_SUPPLY

C34

5mm Pitch, 10mm Dia Disc

10nF 1KV

R48

100R 0.6W

L10

BL01RN1A1D2B

-HV_BUS

LIVE_DRIVE_SUPPLY

DIG_SUPPLY

R58

1K 0.6W

1N5819

D35

LIVE_DIG_SUPPLY

DRIVE_SUPPLY

BZx84C16

D37

P6KE150A

D19

3.9M .25W MetalGlazed R62

TNY277G

U10

D32

UF4002

BL01RN1A1D2B

L11

D25

UF4002

D29

1N5819

BL01RN1A1D2B

LIVE_DRIVE_SUPPLY

SFH617-2

Q22

FIGURE A-7: AUXILIARY POWER SUPPLY SCHEMATIC

Page 86

SMPS AC/DC Reference Design User’s Guide

NEG_OUT

12V_OUT

5V_OUT

3.3V_OUT

NEG_OUT

3.3V_OUT_J3P5_IN

3.3V_OUT

CT_POS

CT_NEG

3.3V_OUT

12V_OUT

CT_NEG

15MQ040NPBF

D31

NEG_OUT

15MQ040NPBF

D20

NEG_OUT

15MQ040NPBF

D14

15MQ040NPBF

D41

3.3V_OUT

3.3V_BUCK#3_ SHUNT_POS

3.3V_BUCK#1_FW_GATE

3.3V_BUCK#1_ CONTROL_GATE

12V_OUT

3.3V_OUT

NEG_OUT

3.3V_BUCK#3_FW_GATE

NEG_OUT

5V_BUCK_FW _G A T E

3.3V_BUCK#1_SHUNT_POS

NEG_OUT

3.3V_BUCK#3_SHU NT_POS

NEG_OUT

12V_OUT

3.3V_BUCK#2_SHUNT_POS

3.3V_BUCK#2_FW _ GATE

3.3V_BUCK#2_ CONTROL_GATE

3.3V_OUT_J3P7_IN

5V_BUCK_SHUNT_NEG_SENSE

5V_BUCK_SHUNT_POS_SENSE

NEG_OUT

3.3V_BUCK#3_ CONTROL_GATE

3.3V_BUCK#1_ SHUNT_POS

CT_POS

5V_BUCK_CONTROL_GATE

NEG_OUT

Coilcraft SER1360 1uH

NEG_OUT

Coilcraft SER1360 1uH

L14

NEG_OUT

3.3V_OUT_J3P9_ IN

3.3V_BUCK#2_SHUNT_POS

3.3V_OUT

47pF

7 8

3 1

Coilcraft SER1360 1uH

D46

BAT54S_SOT23

3.3V_BUCK#1_SHU NT_POS_HDR

3.3V_BUCK#2_SHUNT_POS_HDR

3.3V_BUCK#3_SHUNT_POS_HDR

FIGURE A-8: BUCK CONVERTER STAGES SCHEMATIC

Page 87

Board Layouts and Schematics

DRIVE_SUPPLY

PULLUP_SUPPLY

DRIVE_SUPPLY

NEG_OUT

3.3V_BUCK#3_FW_GATE

NEG_OUT

5V_BUCK_FW_GATE

3.3V_BUCK#1_FW_FIRE

DRIVE_SUPPLY

3.3V_BUCK#1_FW_GATE

D18

BAT54S_SOT23

PULLUP_SUPPLY

3.3V_BUCK#3_FW_FIRE

3.3V_BUCK#3_CONTROL_FIRE

PULLUP_SUPPLY

3.3V_BUCK#3_CONTROL_GATE

3.3V_BUCK#1_CONTROL_GATE

NEG_OUT

3.3V_BUCK#1_CONTROL_FIRE

DRIVE_SUPPLY

D17

BZX84C5V1

D33

BAT54S_SOT23

D16

BAT54S_SOT23

MCP1404-E/SN_SO8N

D43

BAT54S_SOT23

D44

BAT54S_SOT23

MCP1404-E/SN_SO8N

D24

BAT54S_SOT23

D26

BAT54S_SOT23

MCP1404-E/SN_SO8N

5V_BUCK_FW_FIRE

5V_BUCK_CONTROL_FIRE

PULLUP_SUPPLY

3.3V_BUCK#2_FW_FIRE

3.3V_BUCK#2_CONTROL_FIRE

3.3V_BUCK#2_FW_GATE

PULLUP_SUPPLY

5V_BUCK_CONTROL_GATE

3.3V_BUCK#2_CONTROL_GATE

D36

BAT54S_SOT23

FIGURE A-9: BUCK CONVERTER GATE DRIVE SCHEMATIC

Page 88

SMPS AC/DC Reference Design User’s Guide

5V_OUT

PKSB

5V_REMOTE_NEG

3.3V_REMOTE_POS

TEMP_SENSE

SCL

PKSB

+DIG

5V_BUCK_FW_FIRE

3.3V_OUT

3.3V_REMOTE_NEG

3.3V_OUT_J3P7_IN

3.3V_OUT_J3P9_IN

TEMP_SENSE

5V_OUT

5V_REMOTE_NEG

12V_OUT

DRIVE_SUPPLY

12V_OUT

LIVE_GND

LIVE_DIG_SUPPLY

LIVE_GND

LIVE_SCL

LIVE_SDA

LIVE_GND

|VAC|_SENSE

LIVE_+DIG

PKSA

5V_REMOTE_POS

3.3V_REMOTE_NEG

NEG_OUT

12V_OUT

SDA

PKSA

3.3V_OUT_J3P5_IN

3.3V_REMOTE_POS

5V_REMOTE_POS

DIG_SUPPLY

NEG_OUT

LIVE_+DIG

100nF

LIVE_+DIG

PFC_FIRE

-HV_BUS

HV_LINK_SENSE

LIVE_GND

0.1uF

+DIG

3.3V_BUCK#3_CONTROL_FIRE

3.3V_BUCK#3_FW_FIRE

3.3V_BUCK#2_FW_FIRE

3.3V_BUCK#1_CONTROL_FIRE

5V_BUCK_CONTROL_FIRE

3.3V_BUCK#1_SHUNT_POS_HDR

3.3V_BUCK#2_SHUNT_POS_HDR

5V_OUT

5V_BUCK_SHUNT_POS_SENSE

NEG_OUT

LIVE_SCL3.3V_OUT

NEG_OUT

ZVT_LEFT_LOW_FIRE

ZVT_RIGHT_HIGH_FIRE

SYNCH_RECT_#1_FIRE

SYNCH_RECT_#2_FIRE

+DIG

Remote Analog Inputs

MCP9700_SC-70

U11

3.3V_BUCK#2_CONTROL_FIRE

3.3V_BUCK#1_FW_FIRE

NEG_OUT3.3V_BUCK#3_SHUNT_POS_HDR

LIVE_SDA

NEG_OUT

220R

5V_BUCK_SHUNT_NEG_SENSE

3.3V_OUT

0.1uF

LIVE_GND

12V_OUT

ZVT_LEFT_HIGH_FIRE

ZVT_RIGHT_LOW_FIRE

BAT54S_SOT23

D39

BAT54S_SOT23

D40

MCP9700_SC-70

D34

BZX84C5V1

LIVE_TEMP_SENSE

PFC_SHUNT_NEG

12V_BUS_ERROR_F/B

LIVE_DIG_SUPPLY

LIVE_DRIVE_SUPPLY

ZVT_CT_|BURDEN|_POS

TC74_TO-220_5PUP

FIGURE A-10: CONTROL BOARD I/F AND TEMPERATURE SENSING/MISC. SCHEMATIC

Page 89

Board Layouts and Schematics

R182

470R

4K7

R96

R46

DNP

R77

0.1uF

C74

R544K7

R56

4K7

R35

470R

1uF

C28

1R or Ferrite beads

LIVE_+DIG

IC_24LC128_SO8

LIVE_GND

dsPIC33FJ16GS504

FIGURE A-11: PRIMARY SIDE CONTROLLER SCHEMATIC

Page 90

SMPS AC/DC Reference Design User’s Guide

R74

270R

R120

R109

270R

R24

270R

R75

100pF

C21

100pF

HCPL-2611#300

FIGURE A-12: PRIMARY ↔ SECONDARY COMMUNICATION SCHEMATIC

Page 91

Board Layouts and Schematics

C31

1nF

R47

2.7K

C18

1nF

R78

1.3K

4K7

R147

C16

1nF

100R

R148

FIGURE A-13: PRIMARY SIDE FEEDBACK CIRCUITS SCHEMATIC

Page 92

SMPS AC/DC Reference Design User’s Guide

R92 47K R3 10K

220pF

C39

220pF

C37

R106

R80

R83

4K7

R87

R76

4K7

R18

470R

R16

470R

100pF

C44

R117

100K 100KR129

DNP

R94

47K R7 100K

220pF

C36

220pF

4K7

R82

4K7

R28

R17

470R

R14

470R

R15

470R

R121

4K7

R97

3.3K

R13

220pF

R19

470R

R90

10K

R32

10K

R31

Under-Voltage AC

Over-Voltage AC

4K7

R130 4K7

4K7

R190

R89

100K

R86

10K

R93

47K

R25

10K

R29

4K7

R30

R122

R91

47K

R188 4.7K

R85

10K

R84

10K

R88

10K

R33

10K

R95

10K

R81

10K

R36

10K

FIGURE A-14: PRIMARY SIDE HARDWARE FAULT CIRCUITRY SCHEMATIC

Page 93

0.1uF

C23

+DIG

R514K7 R52

4K7

R12

470R

R181

470R

4K7

R98

1uF

GND

R68

1uF

R53

4K7

C71

1uF

IC_24LC128_SO8

dsPIC33FJ16GS504

Board Layouts and Schematics

FIGURE A-15: SECONDARY SIDE CONTROLLER SCHEMATIC

Page 94

SMPS AC/DC Reference Design User’s Guide

R69

OPA4354AID

D35

BAT54S_SOT23

R140

3.3K

When using the Maxim Part:

Remove R100,R105,R65, R60

Replace 0R at the following locations

R101,R102, R103, R104, R61, R62, R63, R64

FIGURE A-16: SECONDARY SIDE FEEDBACK SCHEMATIC

Page 95

Board Layouts and Schematics

220pF

C13

220pF

C17

R58

220pF

C53

47K

R135

R11

470R

C58

100pF

R189 4.7K

R142

100K

R143

100K

220pF

C19

R48

470R

R22

470R

R10

R155

4k7

R145

47K

R191

R150

4K7

R37

10K

R34

10K

R44

R66 47K

R49

10K

R55

10K

R45

6K8

4K7

10K

R116

R118

4K7

R114

4K7

R126

4K7

R134

10K

R26

R23

47K

R67

10K

R57

47K

R39

47K

R38

100K

10K

R59

R21

R79

4K7

R136

10K

R27

47K

Over_Voltage DC Bus

R123

FIGURE A-17: SECONDARY SIDE HARDWARE FAULT CIRCUITS SCHEMATIC

Page 96

SMPS AC/DC Reference Design User’s Guide

NOTES:

Page 97

Appendix B. Test Results

This appendix provides information on the test procedures and results for the SMPS AC/DC Reference Design.

The following equipment was used to test the SMPS AC/DC Reference Design:

• Programmable DC Load (or resistive load)

• Two- or Four-Channel Oscilloscope (100 MHz or higher)

• Current probe and Differential probe

• Programmable AC Source, or Variac, or AC Power Cord

• Power Meter

• True RMS Multimeter

B.1 SOFT-START AN D OVE RSHOOT

The SMPS AC/DC Reference Design has soft-start routines implemented for the PFC Boost converter, ZVT converter, Single-Phase and Multi-Phase Buck converters. The soft-start routines eliminate in-rush current, eliminates overshoot and provides control of the output voltages during start-up. The soft-start scheme is sequenced as follows:

• The PFC Boost converter ramps to 420V,

• the ZVT converter ramps to 12V,

• the Single-Phase Buck converter ramps to 5V,

• and then the Multi-Phase converter ramps to 3.3V.

SMPS AC/DC REFERENCE

DESIGN USER’S GUIDE

B.1.1 Test Procedure

1. Ensure that the system is off and that all probes are disconnected.

2. Connect the oscilloscope probes across the output terminals (J2, J4, and J17).

3. Set up the oscilloscope for normal trigger mode and on the rising edge of the scope connected to (J2) with a time scale equal to 100 ms or greater. Move the trigger start point to 200 ms.

4. Power on the unit and observe the soft-start.

5. Turn off the system and connect a programmable DC load to any single output or to the 5V and 3.3V outputs simultaneously.

6. Power on the unit and observe the soft-start.

7. Turn off the system and disconnect all probes.

Figure B-1 demonstrates the soft-start sequence for the ZVT converter and the Single-Phase and Multi-Phase converters.

Figure B-2 demonstrates the soft-start sequence with the Single-Phase and Multi-Phase outputs loaded (5V @ 23A, 3.3V @ 35A).

Page 98

SMPS AC/DC Reference Design User’s Guide

FIGURE B-1: SOFT-START WITHOUT LOAD

Note: The PFC soft-start (not shown in Figure B-1 and Figure B-2) should not be

observed simultaneously with the secon dary side outputs.

FIGURE B-2: SOFT-START WITH LOAD

Page 99

B.2 DYNAMIC LOAD RESPONSE

Dynamic load response is measuring the under/overshoot voltage and settling time of the output voltage when performing a load step. The SMPS AC/DC Reference Design has the following load step parameters when the outputs are loaded individually:

• 12V full load step of 30A

• 5V full load step of 23A

• 3.3V full load step of 69A

When the Single-Phase and Multi-Phase converters are loaded simultaneously, the following are the max load steps:

• 5V full load step of 23A

• 3.3V full load step of 56A

The load response of each unit is tested with the following load steps with a maximum slew rate of 1A/us:

• 0-15A and 15-0A (for the 12V output)

• 0-35A and 35-0A (for the 3.3V output)

• 0-12A and 12-0A (for the 5V output)

B.2.1 Test Procedure

Test Results

1. Ensure that the system is off and that all probes are disconnected.

2. Connect a programmable DC load to any one of the three outputs.

3. Connect the oscilloscope probe across the output terminals with the DC load.

4. Connect the current probe to one of the load cables making sure of the direction of current flow.

5. Set up the oscilloscope for a single capture and trigger on the current probe on either edge and set the oscilloscope channel for AC coupling.

6. Perform the load steps and measure the settling time and under/overshoot voltage.

7. Turn off the system and disconnect all probes.

Figure B-3 through Figure B-8 show the dynamic load response and settling time with 50% load steps.

Page 100

SMPS AC/DC Reference Design User’s Guide