Microchip SCH5127-NW Schematic [ru]

SCH5127

Super I/O with Temperature Sensing, Auto Fan Contr ol and

Glue Logic

Product Features

• General Features

- 3.3 Volt Operation (Most I/O Pins are 5 Volt Tolerant)

- LPC Interface

- PC99, PC2001 Compliant

- ACPI 2.0 Compliant

- Multiplexed Command, Address and Data Bus

- Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems

- PME Interface

- ISA Plug-and-Play Compatible Register Set

- Programmable Wake-up Event (PME) Interface

- System Management Interrupt (SMI)

- 30 General Purpose Input/Output Pins

• AC Power Failure Recovery

• Watchdog Timer Capable to Pulse PWRGD Low and Change GPO Polarity

• 2.88MB Super I/O Floppy Disk Controller

- Licensed CMOS 765B Floppy Disk Controller

- Software and Register Compatible with

Microchip's Proprietary 82077AA Compatible Core

- Supports One Floppy Drive

- Configurable Open Drain/Push-Pull

Output Drivers

- Supports Vertical Recording Format

- 16-Byte Data FIFO

- 100% IBM® Compatibility

- Detects All Overrun and Underrun Conditions

- Sophisticated Power Control Circuitry (PCC)

Including Multiple Powerdown Modes for Reduced Power Consumption

- DMA Enable Logic

- Data Rate and Drive Control Registers

- 480 Address, Up to Eight IRQ and Four DMA

Options

- Support 3 Mode FDD

• Enhanced Digital Data Separator

- 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250

Kbps Data Rates

- Programmable Precompensation Modes

• Serial Port

- Two Full Function Serial Ports

- High Speed NS16C550A Compatible UARTs with Send/Receive 16-Byte FIFOs

- Supports 230k and 460k Baud

- Programmable Baud Rate Generator

- Modem Control Circuitry

- 480 Address and 15 IRQ Options

• Multi-Mode Parallel Port with ChiProtect

- Standard Mode IBM PC/XT PS/2™ Compatible Bi-directional Parallel Port

- Enhanced Parallel Port (EPP) Compatible EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant)

- IEEE 1284 Compliant Enhanced Capabilities Port (ECP)

- ChiProtect Circuitry for Protection

- 960 Address, Up to 15 IRQ and Four DMA Options

• Keyboard Controller

- 8042 Software Compatible

- 8 Bit Microcomputer

- 2k Bytes of Program ROM

- 256 Bytes of Data RAM

- Four Open Drain Outputs Dedicated for Keyboard/Mouse Interface

- Asynchronous Access to Two Data Registers and One Status Register

- Supports Interrupt and Polling Access

- 8 Bit Counter Timer

- Port 92 Support

- Fast Gate A20 and KRESET Outputs

- Phoenix Keyboard BIOS ROM

• Motherboard GLUE Logic

- Resume Reset Signal Generation

- IDE Reset Output

- (4) Buffered PCI Reset Outputs with software controlled reset capability

- Two 3VSB Gate signal generation for Suspend to RAM or S3/S5 Wake up dual power plane control

- Front Panel Reset Debouncing and Main

3.3V Power Good Signal Generation

- Power Supply Turn On Circuitry with Support for power button on PS/2 Keyboard

- Switches for SMBus Isolation or Voltage Translation for DDC to VGA Monitor Circuitry

- LED Control (2)

- Speaker Input & Output Control

®,

PC/AT®, and

 2006 - 2016 Microchip Technology Inc. DS00002081A-page 1

SCH5127

• Fan Control

- LPC compliant interface for Hardware Monitoring

- 3 PWM (Pulse width Modulation) Outputs with High Frequency PWM Support

- 3 Fan Tachometer Inputs

- Two Programmable automatic fan control thermal zones based on Selectable Temperature Reading

- Fan Tachometer Event can generate PME, SMI and/or Speaker Warning

• Temperature Monitor

- Monitoring of Two Remote Thermal Diodes with  3C TYP,  5C MAX Accuracy

- Internal Ambient Temperature Measurement

- Beta Compensation for Accurate Temperature Sensing on Intel 65nm CPUs

- Limit Comparison of all Monitored Values

- Thermal Event can generate PME, SMI and/ or Speaker Warning

• Processor Hot and Thermal Trip Support

• Voltage Monitor

- Monitor Power supplies (V1_IN for +12V, V2_IN for +5V, +2.5V, VCCP, VBAT, +3.3VTR, +3.3VCC, +1.5VTRIP)

- Limit Comparison of all Monitored Values

- Voltage Event can generate PME, SMI and/or Speaker Warning

• Intruder Detection Support

• 8 VID (Voltage Identification) Input/Output Pins

• VRD revision 10 or 11 Detection

• 128-Pin QFP (3.9mm footprint) RoHS Compliant Package

DS00002081A-page 2  2006 - 2016 Microchip Technology Inc.

SCH5127

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are

using.

Customer Notification System

 2006 - 2016 Microchip Technology Inc. DS00002081A-page 3

SCH5127

Table of Contents

1.0 General Description ........................................................................................................................................................................ 5

2.0 Pin Layout ....................................................................................................................................................................................... 6

3.0 Block Diagram ............................................................................................................................................................................... 15

4.0 Power Functionality ....................................................................................................................................................................... 16

5.0 SIO Overview ................................................................................................................................................................................ 20

6.0 LPC Interface ................................................................................................................................................................................ 21

7.0 Floppy Disk Controller ................................................................................................................................................................... 23

8.0 Serial Port (UART) ........................................................................................................................................................................ 57

9.0 Parallel Port ................................................................................................................................................................................... 71

10.0 Power Management .................................................................................................................................................................... 87

11.0 Serial IRQ .................................................................................................................................................................................... 88

12.0 8042 Keyboard Controller Description ........................................................................................................................................ 91

13.0 General Purpose I/O (GPIO) ....................................................................................................................................................... 99

14.0 System Management Interrupt (SMI) ........................................................................................................................................ 105

15.0 PME Support ............................................................................................................................................................................. 106

16.0 Watchdog Timer ........................................................................................................................................................................ 111

17.0 Buffered PCI Outputs ................................................................................................................................................................ 112

18.0 Power Control Features ............................................................................................................................................................ 114

19.0 Intruder Detection Support ........................................................................................................................................................ 135

20.0 Low Battery Detection Logic ..................................................................................................................................................... 137

21.0 Speaker Warning Output ........................................................................................................................................................... 139

22.0 VID Pin Operation ..................................................................................................................................................................... 141

23.0 SMBus Isolation Circuitry .......................................................................................................................................................... 142

24.0 Hardware Monitoring and Fan Control ...................................................................................................................................... 145

25.0 Hardware Monitoring Register Set ............................................................................................................................................ 174

26.0 Runtime Registers ..................................................................................................................................................................... 209

27.0 Configuration ............................................................................................................................................................................. 238

28.0 Valid Power Modes ................................................................................................................................................................... 252

29.0 Operational Description ............................................................................................................................................................. 253

30.0 Timing Diagrams ....................................................................................................................................................................... 258

31.0 Package Outline ........................................................................................................................................................................ 278

Appendix A: ADC Voltage Conversion .............................................................................................................................................. 279

Appendix B: Example Fan Circuits .................................................................................................................................................... 280

Appendix C: Test Mode ..................................................................................................................................................................... 283

Appendix D: Data Sheet Revision History ......................................................................................................................................... 285

The Microchip Web Site .................................................................................................................................................................... 286

Customer Change Notification Service ............................................................................................................................................. 286

Customer Support ............................................................................................................................................................................. 286

Product Identification System ............................................................................................................................................................ 287

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SCH5127

1.0 GENERAL DESCRIPTION

The SCH5127 is a 3.3V (Super I/O Block is 5V tolerant) PC99/PC2001 compliant Super I/O controller with an LPC interface. SCH5127 also includes Hardware Monitoring capabilities, enhanced Secu rity features, Power Control lo gic and Motherboard Glue logic.

The SCH5127's hardware monitoring capability includes temperature, voltage and fan speed monitoring. It has the ability to alert the system to out-of-limit conditions and automatically control the speeds of multiple fans. There are five analog inputs for monitoring external voltages of +V1_IN (for scaled +12V), V2_IN (for scaled +5V), VTRIP (1.5V), +2.5V and VCCP (core processor voltage), as well as internal monitoring of the SIO's VC C, VTR, and VBAT power supplies. The SCH5127 includes support for monitoring two external temperatures via thermal diode inputs and an internal sensor for measuring ambient temperature. The hardware monitoring block of the SCH5127 is accessible via the LPC Bus. The out-of -limit temperature, voltage of fan tachometer events can be reported on the PME and/or SMI output pin and speaker alarm annunciation.

The Motherboard Glue logic includes various power management and system logic including generation of nRSMRST, SMBus isolation buffers, and buffered PCI reset outputs.

The SCH5127 incorporates complete legacy Super I/O functionality including an 8042 based keyboard and mouse controller, an IEEE 1284, EPP, and ECP compatible parallel port, one serial port that is 16C550A UART compatible, one IrDA 1.0 infrared ports, and a floppy disk controller with Microchip's true CMOS 765B core and enhanced digital data separator. The true CMOS 765B core provides 100% comp atibility with IBM PC/XT and PC/AT architectures and is software and register compatible with Microchip's proprietary 82077AA core. System related functionality, which offers flexibility to the system designer, is available via General Purpose I/O control functions, control of two LED's, and fan control using fan tachometer inputs and pulse width modulator (PWM) outputs.

The SCH5127 is ACPI 1.0/2.0 compatible and therefore supports multiple low power-down modes. It incorporates sophisticated power control circuitry (PCC), which includes support for keyboard and mouse wake-up events.

The SCH5127 supports the ISA Plug-and-Play Standard register set (Version 1.0a). The I/O Address, DMA Channel and hardware IRQ of each logical device in the SCH5127 may be reprogrammed through the internal configuration registers. There are up to 480 (960 - Parallel Port) I/O address location options, a Serialized IRQ interface, and three DMA channels.

1.1 Reference Documents

1. Intel Low Pin Count Specification, Revision 1.0, September 29, 1997

2. PCI Local Bus Specification, Revision 2.2, December 18, 1998

3. Advanced Configuration and Power Interface Specification, Revision 1.0b, February 2, 1999

4. IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993

5. Hardware Description of the 8042, Intel 8 bit Embedded Controller Handbook

6. System Management Bus (SMBus) Specification, Version 2.0, dated August 3, 2000

C Bus Specification, version 2.0, Philips Semiconductors, Dec. 1998

7. I

8. Application Note (AN 8-8) “Keyboard and Mouse Wakeup Functionality”, dated 03/23/02

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SCH5127

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102 101 100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

39404142434445464748495051525354555657585960616263

MDAT/GP32

MCLK/GP33

GP36/nKBDRST

GP37/A20M

VSS

VTR

nINIT

nSLCTIN

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

VSS

SLCT

BUSY

nACK

nERROR

nALF

nSTROBE

nRI1

nDCD1

V1_IN V2_IN

VTRIP_IN

VTR

nMTR0

nDSKCHG

nDS0

VSS

nDIR

nSTEP nWDATA nWGATE

nHDSEL

nINDEX

nTRK0

nWRTPRT

nRDATA

CLOCKI

LAD0 LAD1 LAD2 LAD3

nLFRAME

nLDRQ

nPCI_RESET

PCI_CLK

SER_IRQ

nIDE_RSTDRV/GP10

VTR

GP20/SPEAKER_OUT

VSS

VBAT

nINTRD_IN

AVSS

VCC

GP2 7 /nIO_S MI/P17

KDAT/GP21 KCLK/GP22

+2.5V_IN

VCCP_IN

REMOTE1+

REMOTE1-

REMOTE2+

REMOTE2-

HVTR

HVSS

VID0

VID1

VID2

VID3

VID4

FANTACH1

FANTACH2

VID5

FANTACH3

PWM1

PWM2

GP17/PWM3

GP16/PWM3/nPROCHOT

SDA (DDCSDA_2.5V)

SCLK (DDCSCL_2.5V)

SCLK1 (DDCSCL_5V)

SDA1 (DDCSDA_5V)

GP15/nTHERM_TRIP/nV_TRIP

VCC

VBAT

VCC

VTR

FCAP VSS nRSMRST nPB_OUT nPB_IN nPCIRST_OUT1/GP11 nPCIRST_OUT2/GP12 nPCIRST_OUT3/GP13 GP60/nLED1/WDT GP61/LED2 nPS_ON VTR GP42/nIO_PME nSLP_S3 nSLP_S5 nPCIRST_OUT4/GP14 n3VSB_GATE2/GP41/DRVDEN0 n3VSB_GATE1 PWRGD_3V PWRGD_CPU/SPEAKER_IN/GP40/DRVDEN0 PWRGD_PS GP43/nFPRST/VRD_DET GP57/nDTR2/SPEAKER_OUT GP56/nCTS2/LED2 GP55/nRTS2/VID6 GP54/nDSR2/PWM2 GP53/TXD2(IRTX)/VID7 GP52/RXD2(IRRX)/SPEAKER_IN VSS GP51/nDCD2/LED1/WDT VTR GP5 0 /nRI2/P WM1 nDTR1 nCTS1 nRTS1 (SYSOPT) nDSR1 TXD1 RXD1

128 PIN QFP

HVTR

2.0 PIN LAYOUT

2.1 Pin Layout

FIGURE 2-1: SCH5127 PIN LAYOUT

DS00002081A-page 6  2006 - 2016 Microchip Technology Inc.

SCH5127

2.2 Pin Configuration

TABLE 2-1: SCH5127 QFP PIN CONFIGURATION

Pin # Name Pin # Name Pin # Name Pin # Name

1 V1_IN (+12V_IN) 33 nINTRD_IN 65 RXD1 97 nPCIRST_OUT1/

2 V2_IN (+5V_IN) 34 AVSS 66 TXD1 (XNOR_OUT) 98 nPB_IN 3 VTRIP_IN 35 VCC 67 nDSR1 99 nPB_OUT 4 VTR 36 GP27/nIO_SMI/P17 68 nRTS1 (SYSOPT) 100 nRSMRST 5 nMTR0 37 KDAT/GP21 69 nCTS1 101 VSS 6 nDSKCHG 38 KCLK/GP22 70 nDTR1 102 FCAP 7 nDS0 39 MDAT/GP32 71 GP50/nRI2/PWM1 103 GP15/nTHERM_

8 VSS 40 MCLK/GP33 72 VTR 104 SDA1

9 nDIR 41 GP36/nKBDRST 73 GP51/nDCD2/LED1/

10 nSTEP 42 GP37/A20M 74 VSS 106 SCLK

1 1 nWDATA 43 VSS 75 GP52/RXD2/

12 nWGATE 44 VTR 76 GP53/TXD2/ VID7 108 GP16/PWM3/

13 nHDSEL 45 nINIT 77 GP54/nDSR2/PWM2 109 GP17/PWM3 14 nINDEX 46 nSLCTIN 78 GP55/nRTS2/VID6 110 PWM2 15 nTRK0 47 PD0 79 GP56/nCTS2/LED2 111 PWM1 16 nWRTPRT 48 PD1 80 GP57/nDTR2/

17 nRDATA 49 PD2 81 GP43/nFPRST/

18 CLOCKI 50 PD3 82 PWRGD_PS 1 14 FANTACH2 19 LAD0 51 PD4 83 PWRGD_CPU/

20 LAD1 52 PD5 84 PWRGD_3V 116 VID4 21 LAD2 53 PD6 85 n3VSB_GATE1 117 VID3 22 LAD3 54 PD7 86 n3VSB_GATE2/

23 nLFRAME 55 VSS 87 nPCIRST_OUT4/GP14 119 VID1 24 nLDRQ 56 SLCT 88 nSLP_S5 120 VID0 25 nPCI_RESET 57 PE 89 nSLP_S3 121 HVSS 26 PCI_CLK 58 BUSY 90 GP42/nIO_PME 122 HVTR 27 SER_IRQ 59 nACK 91 VTR 123 REMOTE228 nIDE_RSTDRV/G

P10 29 VTR 61 nALF 93 GP61/nLED2 125 REMOTE130 GP20/

SPEAKER_OUT 31 VSS 63 nRI1 95 nPCIRST_OUT3/GP13 127 VCCP_IN 32 VBAT 64 nDCD1 96 nPCIRST_OUT2/GP12 128 +2.5V_IN

60 nERROR 92 nPS_ON 124 REMOTE2+

62 nSTROBE 94 GP60/nLED1/WDT 126 REMOTE1+

WDT

SPEAKER_IN

SPEAKER_OUT

VRD_DET

SPEAKER_IN/ GP40/DRVDEN0

GP41/DRVDEN0

105 SCLK1

107 SDA

112 FANTACH3

113 VID5

115 FANTACH1

118 VID2

GP11

TRIP/nV_TRIP

(DDCSDA_5V)

(DDCSCL_5V)

(DDCSCL_2.5V)

(DDCSDA_2.5V)

nPROCHOT

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SCH5127

APPLICATION NOTE: The V1_IN (+12V_IN) pin is a 1.125V input. If it is used to monitor 12V, it must be externally

scaled to 5V max. The V2_IN (+5V_IN) pin is a 1.125V inp ut. If it is used to monitor 5V, it must be externally scaled to 5V max.

2.3 Pin Functions

TABLE 2-2: PIN FUNCTIONS DESCRIPTION

Note Name Description

POWER PINS

2-3, 2-4 VCC +3.3 Volt Supply Voltage 2-3, 2-4 VTR +3.3 Volt Standby Supply Voltage

2-7 VBAT +3.0 Volt Battery Supply

VSS Ground AVSS Analog Ground

2-3 HVTR Analo g Power. +3.3V VTR pin dedicated

2-3 HVSS Analog Ground. Interna lly connected to

FCAP Capacitor for 1.8V regulator

CLOCKI 14.318MHz Clock Input VCC N/A IS

LAD[3:0] Multiplexed Command Address and Data VCC VCC PCI_IO nLFRAME Frame signal. Indicates start of new cycle

nLDRQ Encoded DMA Request VCC VCC PCI_O nPCI_RESET PCI Reset VCC N/A PCI_I PCI_CLK PCI Clock VCC N/A PCI_I SER_IRQ Serial IRQ VCC VCC PCI_IO

See GP40,

GP41

(DRVDEN0) Muxed function

nMTR0 Motor On 0 N/A VCC (O12/OD12) nDSKCHG Disk Change VCC N/A IS nDS0 Drive Select 0 N/A VCC (O12/OD12) nDIR Step Direction N/A VCC (O12/OD12) nSTEP Step Pulse N/A VCC (O12/OD12) nWDATA Write Disk Data N/A VCC (O12/OD12) nWGATE Write Gate N/A VCC (O12/OD12) nHDSEL Head Select N/A VCC (O12/OD12) nINDEX Index Pulse Input VCC N/A IS nTRK0 Track 0 VCC N/A IS nWRTPRT Write Protected VCC N/A IS nRDATA Read Disk Da ta VCC N/A IS

to the Hardware Monitoring block. HVTR must be powered by +3.3V Standby supply (VTR).

all of the Hardware Monitoring Block circuitry.

LPC INTERFACE

and termination of broken cycle

FDD INTERFACE

Drive Density Select 0

)

CLOCK PIN

Input

Power

Plane

VCC N/A PCI_I

Output

Power

Plane

Buffer Modes

(Note 2-1)

DS00002081A-page 8  2006 - 2016 Microchip Technology Inc.

TABLE 2-2: PIN FUNCTIONS DESCRIPTION (CONTINUED)

Note Name Description

SERIAL PORT 1 INTERFACE RXD1 Receive Data 1 VCC N/A IS TXD1

/XNOR_OUT nDSR1 Data Set Ready 1 VCC N/A I

2-6 nRTS1/

2-8, 2-11 nRI1 Ring Indicator 1 VCC,

2-8, 2-11 GP50

2-8, 2-11 GP51

2-8, 2-11 GP52

2-8, 2-10,

2-1 1

2-8, 2-11 GP54

2-8, 2-11 GP55

2-8, 2-11 GP56

2-8, 2-11 GP57

SYSOPT

nCTS1 Clear to Send 1 VCC N/A I nDTR1 Data Terminal Ready 1 N/A VCC O8

nDCD1 Data Carrier Detect 1 VCC N/A I

/nRI2 /PWM1

/nDCD2 /LED1 /WDT

/RXD2 (IRRX) /SPEAKER_IN

GP53 /TXD2 (IRTX) /VID7

/nDSR2 /PWM2

/nRTS2 /VID6

/nCTS2 /LED2

/nDTR2 SPEAKER_OUT

Transmit Data 1 / XNOR-Chain Test Mode Output

Request to Send 1/ SYSOPT (Configuration Port Base Address Control)

SERIAL PORT 2 INTERFACE

General Purpose I/O /Ring Indicator 2 /PWM1 Output

General Purpose I/O /Data Carrier Detect 2 /LED 1 /Watchdog Timer output

General Purpose I/O /Receive Data 2 (IRRX) /Speaker Input

General Purpose I/O /Transmit Data 2 (IRTX) /VID7 I/O

General Purpose I/O /Data Set Ready 2 PWM2 Output

General Purpose I/O /Request to Send 2 /VID6 I/O

General Purpose I/O /Clear to Send 2 /LED2

General Purpose I/O /Data Terminal Ready 2 /Speaker Output

Power

Plane

SCH5127

Input

N/A VCC O12/O12

N/A VCC OP14

VTR

VTR VTR (I/O8/OD8)/I/

VCC,

VTR

VCC,

VTR VTR VTR (I_VID/O16/

VCC,

VTR VTR VTR (I_VID

VCC,

VTR VTR VTR (I/O8/OD8)/I/

Output Power

Plane

N/A IS

VTR (I/O12/OD12)/I(

VTR (IS/O8/OD8)/

VTR (I/O8/OD8)/I/

VTR (I/O12/OD12)/I/

Buffer Modes

(Note 2-1)

(O8/OD8)

O12/OD12)/ (O12/OD12)

IS/IS

OD16) /O16/

(I_VID/O16/

OD16)

(O8/OD8)

/O16/OD16)/ (O16/OD16)/

(I_VID

/O16/OD16)

(O12/OD12)

(O8/OD8)

PARALLEL PORT INTERFACE nINIT Initiate Output N/A VCC (OD14/OP14) nSLCTIN Printer Select Input N/A VCC (OD14/OP14) PD0 Port Data 0 VCC VCC IOP14 PD1 Port Data 1 VCC VCC IOP14 PD2 Port Data 2 VCC VCC IOP14 PD3 Port Data 3 VCC VCC IOP14 PD4 Port Data 4 VCC VCC IOP14

 2006 - 2016 Microchip Technology Inc. DS00002081A-page 9

SCH5127

TABLE 2-2: PIN FUNCTIONS DESCRIPTION (CONTINUED)

Note Name Description

PD5 Port Data 5 VCC VCC IOP14 PD6 Port Data 6 VCC VCC IOP14 PD7 Port Data 7 VCC VCC IOP14 SLCT Printer Selected Status VCC N/A I PE Paper End VCC N/A I BUSY Busy VCC N/A I nACK Acknowledge VCC N/A I nERROR Error VCC N/A I nALF Autofeed Output N/A VCC (OD14/OP14) nSTROBE Strobe Output N/A VCC (OD14/OP14)

KEYBOARD/MOUSE INTERFACE

2-8, 2-11 KDAT/GP21 Keyboard Data I/O

2-1 1 KCLK/GP22 Keyboard Clock I/O

2-8, 2-11 MDAT/GP32 Mouse Data I/O

2-1 1 MCLK/GP33 Mouse Clock I/O

2-5, 2-11 GP36

/nKBDRST

2-5, 2-11 GP37

/A20M

2-1 1 GP42/

nIO_PME

2-7, 2-8, 2-11GP60

/nLED1 /WDT

2-7, 2-8, 2-11GP61

/nLED2

2-8, 2-11 GP27

/nIO_SMI /P17

2-1 1 GP20/

SPEAKER_OUT

2-8 nINTRD_IN Intruder Input. Latches the state of a

General Purpose I/O

/General Purpose I/O

/General Purpose I/O General Purpose I/O. GPIO can be

configured as an Open-Drain Output. Keyboard Reset Open-Drain Output (Note 2-5)

General Purpose I/O. GPIO can be configured as an Open-Drain Output. Gate A20 Open-Drain Output (Note 2-5)

MISCELLANEOUS PINS

General Purpose I/O. Power Management Event Output. This active low Power Management Event signal allows this device to request wakeup in S3 and below.

General Purpose Output /nLED1 Watchdog Timer Output

General Purpose Output /nLED2

General Purpose I/O /System Mgt. Interrupt /8042 P17 I/O

General Purpose Input/Output. /Speaker Output. Provides audio warning of HW Monitor or Intruder events and may be enabled by software.

INTRUDER DETECTION

chassis cover removal switch. A high-tolow or low-to-high will set the INTRUSION bit to indicate an intrusion event.

Input

Power

Plane

VCC,

VTR

VCC,

VTR

VCC,

VTR

VCC,

VTR VTR VCC (I/O8/OD8)

VTR VCC (I/O8/OD8)

VTR VTR (I/O12/OD12)

N/A VTR O12/OD12

VCC,

VTR

VCC,

VTR

VBAT N/A IL

Output

Power

Plane

VCC (I/OD16)/

VTR (I/O12/OD12)

VCC (I/O8/OD8)/

Buffer Modes

(Note 2-1)

(I/O16/OD16)

/OD8

/(O12/OD12)

/(I/O12/OD12)

(O8/OD8)

DS00002081A-page 10  2006 - 2016 Microchip Technology Inc.

SCH5127

TABLE 2-2: PIN FUNCTIONS DESCRIPTION (CONTINUED)

Input

Note Name Description

GLUE LOGIC

2-1 1 nPS_ON Power Supply Control Open Drain Output VTR VTR OD8 2-1 1 nPB_IN Power Button In is used to detect a

nPB_OUT Power Button Output N/A VTR OD12

2-1 1 nSLP_S3 S3 Sleep State Input Pin. VTR N/A I 2-1 1 nSLP_S5 S5 Sleep State Input Pin. VTR N/A I 2-1 1 GP43

/nFPRST

/VRD_DET

2-1 1 PWRGD_PS Power Good Input from Power Suppl y VTR N/A ISPU_400

2-1 1, 2-12 PWRGD_CPU

/SPEAKER_IN

/GP40

/DRVDEN0

PWRGD_3V Power Good Output – Push Pull N/A VTR O8

n3VSB_GATE1 PS Control Output 1 N/A VTR O 8

2-1 1, 2-12 n3VSB_GATE2

/GP41

/DRVDEN0

nPCIRST_OUT1

/GP11

nPCIRST_OUT2

/GP12

nPCIRST_OUT3

/GP13

nPCIRST_OUT4

/GP14

nIDE_RSTDRV

/GP10

nRSMRST Resume Reset Output N/A VTR O8

2-1 1 VID0 Voltage ID 0 Input/Output VTR VTR IO_VID 2-1 1 VID1 Voltage ID 1 Input/Output VTR VTR IO_VID 2-1 1 VID2 Voltage ID 2 Input/Output VTR VTR IO_VID 2-1 1 VID3 Voltage ID 3 Input/Output VTR VTR IO_VID 2-1 1 VID4 Voltage ID 4 Input/Output VTR VTR IO_VID

2-11 VID5 Voltage ID 5 Input/Output VTR VTR IO_VID

See GP55 (VID6)

Muxed function

See GP53 (VID7)

Muxed function

See GP43 (VRD_DET)

Muxed function

2-9, 2-10 +2.5V_IN Analog input for +2.5V HVTR N/A I

2-9 V1_IN Analog input for 1.125V HVTR N/A I 2-9 V2_IN Analog input for 1.125V HVTR N/A I

power button event

GP43/ Front Panel Reset /VRD Detect Input

Power Good Output – Open Drain/ Speaker Input General Purpose I/O Drive Density Select 0

PS Control Output 2 General Purpose I/O Drive Density Select 0

Buffered PCI Reset Output 1 /General Purpose Output.

Buffered PCI Reset Output 2 /General Purpose Output.

Buffered PCI Reset Output 3 /General Purpose Output.

Buffered PCI Reset Output 4 /General Purpose Output.

IDE Reset Output /General Purpose Output.

VOLTAGE ID

Voltage ID 6 Input/Output - -

Voltage ID 7 Input/Output - -

VRD Detect Input - -

HARDWARE MONITORING, FAN CONTROL

Power

Plane

VTR N/A I

VTR VTR (I/O16/OD16)

VCC,

VTR

VTR VTR (O12/OD12)

N/A VTR OP14

N/A VCC I/OD8

Output Power

Plane

VTR OD12/I/

Buffer Modes

(I/O12/OD12)/

(Note 2-1)

/ISPU_400

/I_VID

(O12/OD12)

AN AN AN

 2006 - 2016 Microchip Technology Inc. DS00002081A-page 11

SCH5127

TABLE 2-2: PIN FUNCTIONS DESCRIPTION (CONTINUED)

Input

Note Name Description

Power

Plane

2-9 VCCP_IN Analog input for +2.25V HVTR N/A I 2-9 VTRIP_IN Analog input for +1.5V HVTR N/A I

REMOTE1- This is the negative Analog input (current

HVTR N/A I

sink) from the remote thermal diode 1.

REMOTE1+ This is the positive input (current source)

HVTR N/A I

from the remote thermal diode 1.

REMOTE2- This is the negative Analog input (current

HVTR N/A I

sink) from the remote thermal diode 2.

REMOTE2+ This is the positive input (current source)

HVTR N/A I

from the remote thermal diode 2.

2-1 1 FANTACH1 Tachometer Input 1 for monitoring a fan. VT R N/A I 2-1 1 FANTACH2 Tachometer Input 2 for monitoring a fan. VT R N/A I 2-1 1 FANTACH3 Tachometer Input 3 for monitoring a fan. VTR N/A I

2.4 Buffer Description

Table 2-3 lists the buffers that are used in this device. A complete description of these b uffers can be found in the DC

Electrical Characteristics section.

TABLE 2-3: BUFFER DESCRIPTION

Buffer Description

I Input TTL Compatible - Super I/O Block. IL Input, Low Leakage Current. I

AND-

AND+

IS Input with Schmitt Trigger. I_VID Input, high input level 0.8V min, low input level 0.4V max. IO_VID Input/Output, high input level 0.8V min, low input level 0.4V max,

O8 Output, 8mA sink, 8mA source. OD8 Open Drain Output, 8mA sink. IO8 Input/Output, 8mA sink, 8mA source. IOD8 Input/Open Drain Output, 8mA sink, 8mA source. IS/O8 Input with Schmitt Trigger/Output, 8mA sink, 8mA source. O12 Output, 12mA sink, 12mA source. OD12 Open Drain Output, 12mA sink. IO12 Input/Output, 12mA sink, 12mA source.

Input - Hardware Monitoring Block. Analog Input, Hardware Monitoring Block. Remote Thermal Diode (current sink) Negative Input Remote Thermal Diode (current source) Positive Input

16mA sink/source.

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SCH5127

TABLE 2-3: BUFFER DESCRIPTION (CONTINUED)

Buffer Description

IOD12 Input/Open Drain Output, 12mA sink, 12mA source. OD14 Open Drain Output, 14mA sink. OP14 Output, 14mA sink, 14mA source. IOP14 Input/Output, 14mA sink, 14mA source. Backdrive protected. IO16 Input/Output 16mA sink. IOD16 Input/Output (Open Drain), 16mA sink. PCI_IO Input/Output. These pins must meet the PCI 3.3V AC and DC Char-

acteristics. (Note 2-13)

PCI_O Output. These pins must meet the PCI 3.3V AC and DC Character-

istics. (Note 2-13)

PCI_I Input. These pins must meet the PCI 3.3V AC and DC Characteris-

tics. (Note 2-13)

PCI_ICLK Clock Input. These pins must meet the PCI 3.3V AC and DC Char-

acteristics and timing. (Note 2-14) nSW n Channel Switch (R ISPU_400 Input with 400mV Schmitt Trigger and 30uA Integrated Pull-Up. ISPU Input with Schmitt Trigger and Integrated Pull-Up.

Note 2-13 See the “PCI Local Bus Specification,” Revision 2.2, Section 4.2.2. Note 2-14 See the “PCI Local Bus Specification,” Revision 2.2, Section 4.2.2 and 4.2.3.

~25 Ohms)

DS00002081A-page 14  2006 - 2016 Microchip Technology Inc.

3.0 BLOCK DIAGRAM

LEDs

LED2*

LED1*

Internal Bus

(Data, Address, and Control lines)

Power Mgmt

nIO_SMI*

GP1[0:7]*, GP2[0:2,7]*

GP3[2,3,6,7]*, GP4[0,1,2,3]*

GP5[0:7]*, GP6[0:1]*

Note 1: This diagram does not show all power and

ground connections. Note 2: Signal names followed by an asterisk (*) are located on multifunction p ins. This diagram is designed to show the various functions available on the chip and should not be used as a pin layout.

CLOCK GEN

14MHz

CLOCKI

WDT

nDSR1, nDTR1 nDCD1, nRI1

Power Control

and Recovery

nSLP_S3

nSLP_S5 PWRGD_CPU PWRGD_3V n3VSB_GATE1 n3VSB_GATE2* nRSMRST

nFPRST

PWRGD_PS

VTRIP_IN

VCCP_IN

V1_IN

V2_IN

+2.5V_IN

Remote1-

Remote1+

Remote2-

Remote2+

PWM1

PWM2

PWM3

FANTACH1

FANTACH2

FANTACH3

HVTR

HVSS

Hardware

Monitor/

Fan Control

General

Purpose

I/O

nIO_PME*

VCC

VTR

VBAT

PWRGD

HWM_INT

14MHz

WDT

SER_IRQ

LAD[3:0]

nLFRAME

nLDRQ

nPCI_RESET

PCI_CLK

LPC

Interface

SERIAL

IRQ

SMbus

Isolation

Switch

SDA1

SCLK1

SDA

SCLK

SMSC

Proprietary

82077 Compatible Floppydisk

Controller with

Digital Data

Separator &

Write Precom-

pensation

nRDATA, nWDATA

nDIR, nSTEP

nMTR0, nTRK0, InNDEX

DRVDEN0*, nWRTPRT

nWGATE, nHDSEL

nDSKCHG, nDS0,

High-Speed

16550A

UART

PORT 1

TXD1*, RXD1 nCTS1, nRTS1*

Multi-Mode

Parallel Port

with

ChiProtect

FDC MUX

PD[7,0] BUSY, SLCT, PE,

nERROR, nACK nSTROBE, nINIT,

nSLCTIN, nALF

Intruder

Detection

Keyboard/Mouse

8042

controller

KCLK, KDAT

MCLK, MDAT

A20M nKBDRST

PCI Reset

Outputs

nPCIRST_OUT[1:4]

nIDE_RSTDRV

Speaker

SPEAKER_IN*

High-Speed

16550A

UART

PORT 2

TXD2 (IRTX)*, RXD2 (IRRX)*

DSR2*, DTR2* DCD2*, RI2*

CTS2*, RTS2 *

nPS_ON

nPB_IN

WDT*

nINTRD_IN

SPEAKER_OUT*

1.8V

Regulato

FCAP

VTR

VCC

VCC POR

Circuit

WDT

STRAP

OPTIONS

VBAT

POR Ckt

VID I/O

VID0

VID1

VID2

VID3

VID4

VID5

VID6*, VID7*

VRD_DET*

FIGURE 3-1: SCH5127 BLOCK DIAGRAM

SCH5127

 2006 - 2016 Microchip Technology Inc. DS00002081A-page 15

SCH5127

4.0 POWER FUNCTIONALITY

The SCH5127 has four power planes: VCC, VTR, HVTR and VBAT.

4.1 VCC Power

The SCH5127 is a 3.3 Volt part. The VCC supply is 3.3 Volts (nominal). VCC is the main power supply for the Super I/O Block. See Section 29.2, "DC Electrical Characteristics," on page 253.

4.2 3 Volt Operation / 5 Volt Tolerance

The SCH5127 is a 3.3-Volt part. It is intended solely for 3.3V applications. Non-LPC bus pins are 5V tolerant; that is, the operating input voltage is 5.0V Max, and the I/O buffer output pads are backdrive protected (they do not impose a load on any external VCC powered circuitry). The 5V tolerant pins are applicable to the Super I/O Block only.

The LPC interface pins are 3.3 V only. These signals meet PCI DC specifications for 3.3V signaling. The operating input voltage on these pins is 3.6V Max. These pins are:

• LAD[3:0]

• nLFRAME

• nLDRQ The following pins are also 3.3 V only. The operating input voltage on these pins is 3.6V Max.

•VTR

•VCC

• VBAT

• V1_IN

• V2_IN

•VTRIP_IN

• +2.5V_IN

• VCCP_IN

• VID0-VID4, VID5

•SDA, SCLK

• GP43/nFPRST/VRD_DET

• GP55/nRTS2/VID6

• GP53/TXD2(IRTX)/VID7 The input voltage for all other pins is 5.0V max. These pins include all non-LPC Bus pins and the following pins in the

Super I/O Block:

• nPCI_RESET

• PCI_CLK

• SER_IRQ

•nIO_PME

4.3 HVTR Power

The SCH5127 is a 3.3 Volt part. The HVTR supply is 3.3 Volts (nominal). HVTR is a dedicated power supply for the Hardware Monitoring Block. HVTR is connected to the VTR suspend well. See Section 29.2, "DC Electrical Character-

istics," on page 253.

Note: The hardware monitoring logic is powered by HVTR, but only operational whe n VCC is on. The hardware

monitoring block is connected to the suspend well to retain the programmed configuration through a sleep cycle.

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SCH5127

4.4 VTR Support

The SCH5127 requires a trickle supply (VTR) to provide sleep current for the programmable wake-up events in the PME interface when VCC is removed. The VTR supply is 3.3 Volts (nominal). See Section 29.0, "Operational Description,"

on page 253. The maximum VTR current that is required depends on the functions that are used in the part. See Section

29.0, "Operational Description," on page 253.

If the SCH5127 is not intended to provide wake-up capabilities on standby current, VTR can be connected to VCC. VTR powers the IR interface, the PME configuration registers, and the PME interface. The VTR pin generates a VTR Poweron-Reset signal to initialize these components. If VTR is to be used for programmable wake-up events when VCC is removed, VTR must be at its full minimum potential at least 10 ms before Vcc begins a power-on cycle. Note that under all circumstances, the hardware monitoring HVTR must be driven as the same source as VTR.

4.4.1 TRICKLE POWER FUNCTIONALITY

When the SCH5127 is running under VTR on ly (VCC removed), PME w akeup events are active a nd (if enabled) able to assert the nIO_PME pin active low. (See Table 15-2, “PME Events,” on page 106.)

The following requirements apply to all I/O pins that are specified to be 5 volt tolerant.

• I/O buffers that are wake-up event compatible are powered by VCC. Under VTR power (VCC=0), these pins may only be configured as inputs. These pins have input buffers into the wakeup logic that are powered by VTR.

• I/O buffers that may be configured as either push-pull or open drain under VTR power (VCC=0), are powered by VTR. This means, at a minimum, they will source their specified current from VTR even when VCC is present.

The GPIOs that are used for PME wakeup as input function as follows: (See Table 13-1, “GPIO Functionality,” on

page 99.)

• Buffers are powered by VCC, but in the absence of VCC they are backdrive protected (they do not impose a load on any external VTR powered circuitry). They are wakeup compatible as inputs under VTR power. These pins have input buffers into the wakeup logic that are powered by VTR.

The following list summarizes the blocks, registers and pins that are powered by VTR.

• PME interface block

• PME runtime register block (includes all PME, SMI, GPIO, Fan and other misce llaneous registers)

• Digital logic in the Hardware Monitoring block

• “Wake on Specific Key” logic

• LED control logic

• Watchdog Timer

• Power Control and Recovery Logic

• Intruder Detection Logic

• Pins for PME Wakeup:

- GPIOs and alternate functions as indicated in Table 13-1, “GPIO Functionality,” on page 99.

- nRI1 (input)

• Other pins:

- GPIOs and alternate functions as indicated in Table 13-1, “GPIO Functionality,” on page 99.

-nRSMRST

- nPB_IN

- nPB_OUT

- nPS_ON

-PWRGD_PS

- nSLP_S3#

- nSLP_S5#

- PWRGD_3V, PWRGD_CPU

- n3VSB_GATE1,2

- PWM1, PWM2, PWM3

- VID pins

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SCH5127

4.5 VBAT Support

VBA T is a battery generated power supply that is needed to support the power recovery logic. The power recovery logic is used to restore power to the system in the event of a power failure. Power may be returned to the system by a keyboard power button, the main power button, or by the power recovery logic following an unexpected power failure.

The VBAT supply is 3.0 Volts (nominal). See Sectio n 29.0, "Operational Description," on page 253. The following input pin is powered by VBAT:

• nINTRD_IN The following Runtime Registers are powered by VBAT:

• PME_PBOUT_EN at offset 03h

• PME_PB_EN1, PME_PB_EN3, PME_PB_EN5, PME_PB_EN6 at offset 10h-13h

• GP16 at offset 29h, GP17 at offset 2Ah

• GP41 at offset 3Ch, GP43 at offset 3Eh

• GP50-GP57 at offset 3Fh-46h

• PWR_REC Register at offset 49h

• SLP_S3_Shift Register at offset 4Ah

• INTRD Register at offset 52h

• SLP_S3_Pre_State at offset 53h

• DBLCLICK at offset 5Bh

• Mouse Specific Wake at offset 5Ch

• Keyboard Scan Code – Make Byte 1 at offset 5Fh

• Keyboard Scan Code – Make Byte 2 at offset 60h

• Keyboard Scan Code – Break Byte 1 at offset 61h

• Keyboard Scan Code – Break Byte 2 at offset 62h

• Keyboard Scan Code – Break Byte 3 at offset 63h

• Keyboard PWRBTN/SPEKEY at offset 64h

• SMB_ISO Register at offset 6Ah

• WDT Option at offset 6Bh

• PWM Start/Gate Option at offset 6Ch

• TEST at offset 6Dh. Note: All VBA T powered pins and registers are powered by VTR when VTR power is on and are battery backed-

up when VTR is removed.

APPLICATION NOTE: If the battery features are not required and the VBAT pin is not connected to a battery, the

VBAT pin should be connected to ground. Note that in this case, the following features listed above will not function as intended.

To conserve battery power, the battery logic is switched internally between the VBAT and VTR pins. The switch takes place as follows:

• On rising VTR, switch from VBAT to VTR when VTR > 2.5V (nominal) or VTR > VBAT.

• On falling VTR, switch from VTR to VBAT when VTR < 2.45V (nominal) and VTR < VBAT.

Backdrive protection prevents VBAT from driving the VCC or VTR rails.

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SCH5127

4.6 Super I/O Functions

The maximum VTR current, ITR, is given with all outputs open (not loaded), and all inputs in a fixed state (i.e., 0V or

3.3V). The total maximum current for the part is the unloaded value PLUS the maximum current sourced by the pin that is driven by VTR. The super I/O pins that are powered by VTR are as follows: GPIOs as indicated in Table 13-1, “GPIO

Functionality,” on page 99, PWRGD_3V, n3VSB_GATE1. These pins, if configured as push-pull outputs, will source a

minimum of 6mA at 2.4V when driving. The maximum VCC current, I

3.3V). The maximum Vbat current, I

4.7 Power Management Events (PME/SCI)

The SCH5127 offers support for Power Management Events (PMEs), also referred to as System Control Interrupt (SCI) events. The terms PME and SCI are used synonymously throughout this document to refer to the indication of an event to the chipset via the assertion of the nIO_PME output signal. See Section 15.0, "PME Support," on page 106.

, is given with all outputs open (not loaded) and all inputs in a fixed state (i.e., 0V or

, is given with all outputs open (not loaded) and all inputs in a fixed state (i.e., 0V or 3.3V).

bat

 2006 - 2016 Microchip Technology Inc. DS00002081A-page 19

SCH5127

5.0 SIO OVERVIEW

The SCH5127 is a Super I/O Device with hardware monitoring. The Super I/O features are implemented as logical devices accessible through the LPC interface. The Super I/O blocks are powered by VCC, VTR, or VBAT. The Hardware Monitoring block is powered by VTR and is accessible via the LPC interface. The following chapters define each of the functional blocks implemented in the SCH5127, their corresponding registers, and physical characteristics.

This chapter offers an introduction into the Super I/O functional blo cks, registers and host interfa ce. Details regarding the hardware monitoring block are defined in later chapters. The block diagram in of the device. Note that the Super I/O registers are implemented as typical Plug-and-Play components.

Note: The LPC interface is the main interface used to access the components of this chip. The LPC interface is

used to access the Super I/O registers and the Hardware Monitoring registers.

5.1 Super I/O Registers

The address map, shown below in Table 5-1 shows the addresses of the different blocks of the Super I/O immediately after power up. The base addresses of all the Super I/O Logical Blocks, including the configuration register block, can be moved or relocated via the configuration registers.

Note: Some addresses are used to access more than one register.

5.2 Host Processor Interface (LPC)

Section 3.0 further details the layout

The host processor communicates with the Super I/O features in the SCH5127 through a series of read/write registers via the LPC interface. The port addresses for these registers are shown in T able 5-1, "Super I/O Block Addresses". Register access is accomplished through I/O cycles or DMA transfers. All registers are 8 bits wide.

TABLE 5-1: SUPER I/O BLOCK ADDRESSES

Address Block Name Logical Device Notes

Base+(0-5) and +(7) Floppy Disk 0

na Reserved 1 (Note 5-3) na Reserved 2 (Note 5-3)

Parallel Port Base+(0-3) Base+(0-7)

Base+(0-3), +(400-402) Base+(0-7), +(400-402)

Base+(0-7) Serial Port Com 1 4 Base+(0-7) Serial Port Com 2 5

na Reserved 6

60, 64 KYBD 7

na Reserved

Base + (0-7F) Runtime Registers A (Note 5-2)

na Reserved B (Note 5-3)

Base + (0-1) Configuration (Note 5-1)

SPP EPP ECP

ECP+EPP+SPP

8,9

Note 5-1 Refer to the configuration register descriptions for setting the base address. Note 5-2 Logical Device A is referred to as the Runtime Register block or PME Block and may be used

interchangeably throughout this document.

Note 5-3 na = not applicable

DS00002081A-page 20  2006 - 2016 Microchip Technology Inc.

SCH5127

6.0 LPC INTERFACE

6.1 LPC Interface Signal Definition

The signals implemented for the LPC bus interface are described in the tables below. LPC bus signals use PCI 33MHz electrical signal characteristics.

6.1.1 LPC REQUIRED SIGNALS

Signal Name Type Description

LAD[3:0] I/O LPC address/data bus. Multiplexed command, address and data bus. nLFRAME Input Frame sign al. Indicates start of new cycle and termination of broken cycle nPCI_RESET Input PCI Reset. Used as LPC Interface Reset. Active low. PCI_CLK Input PCI Clock.

6.1.2 LPC OPTIONAL SIGNALS

Signal Name Type Description

nLDRQ Output Encoded DMA/Bus Master request for the LPC inte rface. SER_IRQ I/O Serial IRQ. nIO_PME OD Same as the PME or Power Mgt Event signal. Allows the SCH5127 to request

wakeup in S3 and below.

6.2 Supported LPC Cycles

Table 6-1 summarizes the cycle types are supported by the SCH5127. All other cycle types are ignored.

TABLE 6-1: SUPPORTED LPC CYCLES

Cycle Type Transfer Size

I/O Write 1 Byte

I/O Read 1 Byte DMA Write 1 Byte DMA Read 1 Byte

6.3 Device Specific Information

The LPC interface conforms to the “Low Pin Count (LPC) Interface Specification”. The following section will review any implementation specific information for this device.

6.3.1 SYNC PROTOCOL

The SYNC pattern is used to add wait states. For read cycles, the SCH5127 immediately drives the SYNC pattern upon recognizing the cycle. The host immediately drives the sync pattern for write cycles. If the SCH5127 needs to assert wait states, it does so by driving 0101 or 0110 on LAD[3:0] until it is ready, at which point it will drive 0000 or 1001. The SCH5127 will choose to assert 0101 or 0110, but not switch between the two patterns.

The data (or wait state SYNC) will immediately follow the 0000 or 1001 value. The SYNC value of 0101 is intended to be used for normal wait states, wherein the cycle will complete within a few clocks. The SCH5127 uses a SYNC of 0101 for all wait states in a DMA transfer.

The SYNC value of 01 10 is intended to be used where the number of wait states is large. This is provided for EPP cycles, where the number of wait states could be quite large (>1 microsecond). However, the SCH5127 uses a SYNC of 0110 for all wait states in an I/O transfer.

 2006 - 2016 Microchip Technology Inc. DS00002081A-page 21

SCH5127

The SYNC value is driven within 3 clocks.

6.3.2 RESET POLICY

The following rules govern the reset policy:

• When nPCI_RESET goes inactive (high), the PCI clock is assumed to have been running for 100usec prior to the removal of the reset signal, so that everything is stable. This is the same reset active time after clock is stable that is used for the PCI bus.

• When nPCI_RESET goes active (low):

1. The host drives the nLFRAME signal high, tristates the LAD[3:0] signals, and ignores the nLDRQ signal.

2. The SCH5127 ignores nLFRAME, tristates the LAD[3:0] pins and drives the nLDRQ signal inactive (high).

DS00002081A-page 22  2006 - 2016 Microchip Technology Inc.

SCH5127

7.0 FLOPPY DISK CONTROLLER

The Floppy Disk controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write Precompensation and Data Rate Selection logic for an IBM XT/AT compatible FDC. The true CMOS 765B core provides 100% IBM PC XT/AT compatibility in addition to providing data overflow and underflow protection. SCH5127 supports a single floppy disk drive.

The FDC is compatible to the 82077AA using Microchip’s proprietary floppy disk controller core.

7.1 FDC Internal Registers

The Floppy Disk Controller contains eight internal registers which fa cilitate the interfacing between the host mi croprocessor and the disk drive. Table 7-1 shows the addresses required to access these registers. Registers other than the ones shown are not supported. The rest of the description assumes that the primary addresses have been selected.

(Shown with base addresses of 3F0 and 370.)

TABLE 7-1: STATUS, DATA AND CONTROL REGISTERS

Primary Address

3F0 3F1 3F2 3F3 3F4 3F4 3F5 3F6 3F7 3F7

Secondary

Address

370 371 372 373 374 374 375 376 377 377

R/W Register

R R R/W R/W R W R/W

R W

Status Register A (SRA) Status Register B (SRB) Digital Output Register (DOR) Ta pe Drive Register (TDR) Main Status Register (MSR) Data Rate Select Register (DSR) Data (FIFO) Reserved Digital Input Register (DIR) Configuration Control Register (CCR)

7.1.1 STATUS REGISTER A (SRA)

Address 3F0 READ ONLY

This register is read-only and monitors the state of the internal inte rrupt signal and several disk interfa ce pins in PS/2 and Model 30 modes. The SRA can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 – D7 are held in a high impedance state for a read of address 3F0.

PS/2 Mode

7 6543210 INT

PENDING

RESET COND.

Bit 0 DIRECTION

Active high status indicating the direction of head movement. A logic “1” indicates inward direction; a logic “0” indicates outward direction.

Bit 1 nWRITE PROTECT

Active low status of the WRITE PROTECT disk interface input. A logic “0” indicates that the disk is write protected.

Bit 2 nINDEX

Active low status of the INDEX disk interface input.

Bit 3 HEAD SELECT

Active high status of the HDSEL disk interface input. A logic “1” selects side 1 and a logic “0” selects side 0.

Bit 4 nTRACK 0

Active low status of the TRK0 disk interface input.

0 1 0 N/A 0 N/A N/A 0

nDRV2 STEP nTRK0 HDSEL nINDX nWP DIR

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SCH5127

Bit 5 STEP

Active high status of the STEP output disk interface output pin.

Bit 6 nDRV2

This function is not supported. This bit is always read as “1”.

Bit 7 INTERRUPT PENDING

Active high bit indicating the state of the Floppy Disk Interrupt output.

PS/2 Model 30 Mode

7 6543 210 INT PENDING DRQ STEP

RESET COND.

Bit 0 DIRECTION

Active low status indicating the direction of head movement. A logic “0” indicates inward direction; a logic “1” indicates outward direction.

Bit 1 WRITE PROTECT

Active high status of the WRITE PROTECT disk interface input. A logic “1” indicates that the disk is write protected.

Bit 2 INDEX

Active high status of the INDEX disk interface input.

Bit 3 HEAD SELECT

Active low status of the HDSEL disk interface input. A logic “0” selects side 1 and a logic “1” selects side 0.

Bit 4 TRACK 0

Active high status of the TRK0 disk interface input.

Bit 5 STEP

Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP output going active, and is cleared with a read from the DIR register, or with a hardware or software reset.

Bit 6 DMA REQUEST

Active high status of the DMA request pending.

Bit 7 INTERRUPT PENDING

Active high bit indicating the state of the Floppy Disk Interrupt.

0 0 0 N/A 1 N/A N/A 1

F/F

TRK0 nHDSEL INDX WP nDIR

7.1.2 STATUS REGISTER B (SRB)

Address 3F1 READ ONLY

This register is read-only and monitors the state of several disk interface pin s in PS/2 and Model 30 modes. The SRB can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 – D7 are held in a high impedance state for a read of address 3F1.

PS/2 Mode

7654321 0 Reserved Reserved DRIVE

RESET COND.

Bit 0 MOTOR ENABLE 0

Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset.

DS00002081A-page 24  2006 - 2016 Microchip Technology Inc.

1100000 0

SEL0

WDATA TOGGLE

RDATA TOGGLE

WGATE Reserved MOT EN0

SCH5127

Bit 1 Reserved

Reserved will return a zero (0) when read. This bit is low after a hardware reset and unaffected by a software reset.

Bit 2 WRITE GATE

Active high status of the WGATE disk interface output.

Bit 3 READ DATA TOGGLE

Every inactive edge of the RDATA input causes this bit to change state.

Bit 4 WRITE DATA TOGGLE

Every inactive edge of the WDATA input causes this bit to change state.

Bit 5 DRIVE SELECT 0

Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a hardware reset and it is unaffected by a software reset.

Bit 6 RESERVED

Always read as a logic “1”.

Bit 7 RESERVED

Always read as a logic “1”.

PS/2 Model 30 Mode

76543210

RESET COND.

nDRV2 nDS1 nDS0 WDATA

F/F

N/A1 100011

RDATA F/F WGATE F/F nDS3 nDS2

Bit 0 nDRIVE SELECT 2

The DS2 disk interface is not supported.

Bit 1 nDRIVE SELECT 3

The DS3 disk interface is not supported.

Bit 2 WRITE GATE

Active high status of the latched WGATE output signal. This bit is latched by the active going edge of WGATE and is cleared by the read of the DIR register.

Bit 3 READ DATA

Active high status of the latched RDATA output sig nal. This bit is latched by the inactive going edge of RDATA and is cleared by the read of the DIR register.

Bit 4 WRITE DA TA

Active high status of the latched WDATA output signal. This bit is latched by the inactive goi ng edge of WDATA and is cleared by the read of the DIR register. This bit is not gated with WGATE.

Bit 5 nDRIVE SELECT 0

Active low status of the DS0 disk interface output.

Bit 6 nDRIVE SELECT 1

The DS 1 disk interface is not supported.

Bit 7 nDRV2

Active low status of the DRV2 disk interface input. Note: This function is not supported.

7.1.3 DIGITAL OUTPUT REGISTER (DOR)

Address 3F2 READ/WRITE

The DOR controls the drive select and motor enab les of the disk interface ou tputs. It also contains the enable for the DMA logic and a software reset bit. The contents of the DOR are unaffected by a software reset. The DOR can be written to at any time.

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76543210 MOT EN3 MOT EN2 MOT EN1 MOT EN0 DMAEN nRESET DRIVE

RESET COND.

Bit 0 and 1 DRIVE SELECT

These two bits are binary encoded for the drive selects, thereby allowing only one drive to be selected at one time. For proper device operation, they must be programmed to 0b00.

Bit 2 nRESET

A logic “0” written to this bit resets the Floppy disk controller. This reset will remain active until a logic “1” is written to this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the other bits of the DOR register. The minimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this register is a valid method of issuing a software reset.

Bit 3 DMAEN PC/AT and Model 30 Mode: Writing this bit to logic “1” will enable the DMA and interrupt functions. This bit being a logic “0” will disable the DMA and

interrupt functions. This bit is a logic “0” after a reset and in these modes. PS/2 Mode: In this mode the DMA and interrupt functions are always enabled. During a reset, this bit will be cleared to

a logic “0”.

Bit 4 MOTOR ENABLE 0 This bit controls the MTR0 disk interface output. A logic “1” in this bit wil l cause the output pin to go active.

Bit 5 MOTOR ENABLE 1 The MTR1 disk interface output is not support in the SCH5127. For proper device operation this bit must be programmed

with a zero (0).

00000000

SEL1

DRIVE SEL0

Drive DOR Value

01CH

TABLE 7-2: INTERNAL 2 DRIVE DECODE – NORMAL

Digital Output Register Drive Select Outputs (Active Low) Motor On Outputs (Active Low)

Bit 4 Bit1 Bit 0 nDS0 nMTR0

100 0 nBIT 4 X10 1 nBIT 4 XX1 1 nBIT 4

Bit 6 MOTOR ENABLE 2

The MTR2 disk interface output is not supported in the SCH5127.

Bit 7 MOTOR ENABLE 3

The MTR3 disk interface output is not supported in the SCH5127.

7.1.4 TAPE DRIVE REGISTER (TDR)

Address 3F3 READ/WRITE

The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to assign tape support to a particular drive during initialization. Any future references to that drive automatically invokes tape support. The TDR T ape Select bits TDR.[1:0] determine the tape drive number . Table 7-3 illustrates the T ape Select Bit encoding. Note that drive 0 is the boot device and cannot be assigned tape support. The remaining Tape Drive Register bits TDR.[7:2] are tristated when read. The TDR is unaffected by a software reset.

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TABLE 7-3: TAPE SELECT BITS

Tape SEL1

(TDR.1)

0 0 1 1

APPLICATION NOTE: Note that in this device since only drive 0 is supported, the tape sel0/1 bits must be set to

0b00 for proper operation.

Normal Floppy Mode

Normal mode.Register 3F3 contains only bits 0 and 1. When this register is read, bits 2 – 7 are ‘0’ Note only drive 0 is supported.

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

REG 3F3000000tape sel1tape sel0

Enhanced Floppy Mode 2 (OS2)

Tape SEL0

(TDR.0)

0 1 0 1

Drive Selected

None 1 (not supported) 2 (not supported) 3 (not supported)

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

REG 3F3 Reserved Reserved Drive Type ID Floppy Boot Drive tape sel1 tape sel0

TABLE 7-4: DRIVE TYPE ID

Digital Output Register Register 3F3 – Drive Type ID

Bit 1 Bit 0 Bit 5 Bit 4 0 0 L0-CRF2 – B1 L0-CRF2 – B0 0 1 L0-CRF2 – B3 L0-CRF2 – B2 1 0 L0-CRF2 – B5 L0-CRF2 – B4 1 1 L0-CRF2 – B7 L0-CRF2 – B6

Note: L0-CRF2-Bx = Logical Device 0, Configuration Register F2, Bit x.

7.1.5 DATA RATE SELECT REGISTER (DSR)

Address 3F4 WRITE ONLY

This register is write only. It is used to program the data rate, amount of write precompensation, power down status, and software reset. The data rate is programmed using the Configuration Control Register (CCR) not the DSR, for PC/AT and PS/2 Model 30.

76543210

RESET COND.

S/W RESET

00000010

POWER DOWN

0PRE-

COMP2

PRECOMP1

PRECOMP0

DRATE SEL1

DRATE SEL0

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Other applications can set the data rate in the DSR. The data rate of the floppy controller is the most re cent write of either the DSR or CCR. The DSR is unaffected by a software reset. A hardware reset will set the DSR to 02H, which corresponds to the default precompensation setting and 250 Kbps.

Bit 0 and 1 DATA RATE SELECT

These bits control the data rate of the floppy controller. See Table 7-6 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset.

Bit 2 through 4 PRECOMPENSATION SELECT

These three bits select the value of write precompensation that will be applied to the WDATA output signal. Table 7-5 shows the precompensation values for the combination of these bits settings. Track 0 is the default starting track number to start precompensation. This starting track number can be changed by the configure command.

TABLE 7-5: PRECOMPENSATION DELAYS

PRECOMP

432

111 001 010 011 100 101 110 000

Default: See Table 7-8 on page 29.

0.00

41.67

83.34

125.00

166.67

208.33

250.00 Default

Precompensation Delay (nsec)

<2Mbps 2Mbps

20.8

41.7

62.5

83.3

104.2 125 Default

Bit 5 UNDEFINED

Should be written as a logic “0”.

Bit 6 LOW POWER

A logic “1” written to this bit will put the floppy controller into manual low power mode. The floppy con troller clock and data separator circuits will be turned off. The controller will come out of manual low power mode after a software reset or access to the Data Register or Main Status Register.

Bit 7 SOFTWARE RESET

This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self clearing.

Note: The DSR is Shadowed in the Floppy Data Rate Select Shadow Register, located at the offset 0x1F in the

runtime register block Separator circuits will be turned off. The controller will come out of manual low power.

TABLE 7-6: DATA RATES

Drive Rate Data Rate Data Rate DENSEL DRATE(1)

DRT1 DRT0 SEL1 SEL0 MFM FM 10

0 0 1 1 1Meg --- 1 1 1 0 0 0 0 500 250 1 0 0 0 0 0 1 300 150 0 0 1 0 0 1 0 250 125 0 1 0 0 1 1 1 1Meg --- 1 1 1 0 1 0 0 500 250 1 0 0 0 1 0 1 500 250 0 0 1 0 1 1 0 250 125 0 1 0 1 0 1 1 1Meg --- 1 1 1 1 0 0 0 500 250 1 0 0 1 0 0 1 2Meg --- 0 0 1 1 0 1 0 250 125 0 1 0

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SCH5127

Drive Rate Table (Recommended) 00 = 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format 01 = 3-Mode Drive 10 = 2 Meg Tape

Note: The DRATE and DENSEL values are mapped onto the DRVDEN pins.

TABLE 7-7: DRVDEN MAPPING

DT1 DT0 DRVDEN1 (1) DRVDEN0 (1) Drive Type

0 0 DRATE0 DENSEL 4/2/1 MB 3.5”

1 0 DRATE0 DRATE1 0 1 DRATE0 nDENSEL PS/2 1 1 DRATE1 DRATE0

TABLE 7-8: DEFAULT PRECOMPENSATION DELAYS

Data Rate Precompensation Delays

2 Mbps 1 Mbps 500 Kbps 300 Kbps 250 Kbps

20.8 ns

41.67 ns 125 ns 125 ns 125 ns

2/1 MB 5.25” FDDS 2/1.6/1 MB 3.5” (3-MODE)

7.1.6 MAIN STATUS REGISTER

Address 3F4 READ ONLY

The Main Status Register is a read-only register and indicates the status of the disk controller. The Main Status Register can be read at any time. The MSR indicates when the disk controller is ready to receive data via the Data Register. It should be read before each byte transferring to or from the data register except in DMA mode. No delay is required when reading the MSR after a data transfer.

76543210 RQM DIO NON DMA CMD BUSY Reserved Reserved Reserved DRV0 BUSY

Bit 0 DRV0 BUSY

This bit is set to 1 when a drive is in the seek portio n of a command, including implied an d overlapped seeks and re calibrates.

BIT 1 RESERVED

Reserved - read returns 0

Bit 4 COMMAND BUSY

This bit is set to a 1 when a command is in progress. This bit will go active after the command byte has been accepted and goes inactive at the end of the results phase. If there is no result phase (Seek, Re calibrate commands), this bit is returned to a 0 after the last command byte.

Bit 5 NON-DMA

Reserved, read ‘0’. This part does not support non-DMA mode.

Bit 6 DIO

Indicates the direction of a data transfer once a RQM is set. A 1 indicates a read and a 0 indicates a write is required.

Bit 7 RQM

Indicates that the host can transfer data if set to a 1. No access is permitted if set to a 0.

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7.1.7 DATA REGISTER (FIFO)

Address 3F5 READ/WRITE

All command parameter information, disk data and result status are transferred between the host processor and the floppy disk controller through the Data Register.

Data transfers are governed by the RQM and DIO bits in the Main Status Register. The Data Register defaults to FIFO disabled mode after any form of reset. This maintains PC/AT hardware compatibility .

The default values can be changed through the Configure command (enable full FIFO operation with threshold control). The advantage of the FIFO is that it allows the system a larger DMA latency without causing a disk error. Table 7-9 gives several examples of the delays with a FIFO.

The data is based upon the following formula:

DELAY = Fifo Threshold # x DATA RATE x 8 - 1.5 s

At the start of a command, the FIFO action is always disabled and command parameters must be sent based upon the RQM and DIO bit settings. As the command execution phase is entered, the FIFO is cleared of any data to ensure that invalid data is not transferred.

An overrun or underrun will terminate the current command and the transfer of data. Disk writes will complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to remove the remaining data so that the result phase may be entered.

TABLE 7-9: FIFO SERVICE DELAY

FIFO THRESHOLD EXAMPLES MAXIMUM DELAY TO SERVICING AT 2 MBPS DATA RATE

1 byte 2 bytes 8 bytes 15 bytes

FIFO THRESHOLD EXAMPLES MAXIMUM DELAY TO SERVICING AT 1 MBPS DATA RATE

1 byte 2 bytes 8 bytes 15 bytes

FIFO THRESHOLD EXAMPLES MAXIMUM DELAY TO SERVICING AT 500 KBPS DATA RATE

1 byte 2 bytes 8 bytes 15 bytes

1 x 4 s - 1.5 s = 2.5 s 2 x 4 s - 1.5 s = 6.5 s 8 x 4 s - 1.5 s = 30.5 s 15 x 4 s - 1.5 s = 58.5 s

1 x 8

s - 1.5 s = 6.5 s

2 x 8 s - 1.5 s = 14.5 s 8 x 8 s - 1.5 s = 62.5 s 15 x 8 s - 1.5 s = 118.5 s

1 x 16 s - 1.5 s = 14.5 s 2 x 16 s - 1.5 s = 30.5 s 8 x 16 s - 1.5 s = 126.5 s 15 x 16 s - 1.5 s = 238.5 s

7.1.8 DIGITAL INPUT REGISTER (DIR)

Address 3F7 READ ONLY

This register is read-only in all modes.

PC-AT Mode

76543210 DSK CHG0000000

RESET COND.

Bit 0 – 6 UNDEFINED

The data bus outputs D0 – 6 are read as ‘0’.

Bit 7 DSKCHG

This bit monitors the pin of the same name and reflects the opposi te value seen on the disk cable or the value programmed in the Force Disk Change Register (see the Runtime Register at offset 0x1E).

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+ 260 hidden pages

Microchip SCH5127-NW Schematic [ru]

Specifications and Main Features

Frequently Asked Questions

User Manual

1.0 GENERAL DESCRIPTION

1.1 Reference Documents

2.0 PIN LAYOUT

2.1 Pin Layout

FIGURE 2-1: SCH5127 PIN LAYOUT

2.2 Pin Configuration

TABLE 2-1: SCH5127 QFP PIN CONFIGURATION

2.3 Pin Functions

TABLE 2-2: PIN FUNCTIONS DESCRIPTION

2.4 Buffer Description

TABLE 2-3: BUFFER DESCRIPTION

3.0 BLOCK DIAGRAM

FIGURE 3-1: SCH5127 BLOCK DIAGRAM

4.0 POWER FUNCTIONALITY

4.1 VCC Power

4.2 3 Volt Operation / 5 Volt Tolerance

4.3 HVTR Power

4.4 VTR Support

4.4.1 TRICKLE POWER FUNCTIONALITY

4.5 VBAT Support

4.6 Super I/O Functions

4.7 Power Management Events (PME/SCI)

5.0 SIO OVERVIEW

5.1 Super I/O Registers

5.2 Host Processor Interface (LPC)

TABLE 5-1: SUPER I/O BLOCK ADDRESSES

6.0 LPC INTERFACE

6.1 LPC Interface Signal Definition

6.1.1 LPC REQUIRED SIGNALS

6.1.2 LPC OPTIONAL SIGNALS

6.2 Supported LPC Cycles

TABLE 6-1: SUPPORTED LPC CYCLES

6.3 Device Specific Information

6.3.1 SYNC PROTOCOL

6.3.2 RESET POLICY

7.0 FLOPPY DISK CONTROLLER

7.1 FDC Internal Registers

TABLE 7-1: STATUS, DATA AND CONTROL REGISTERS

7.1.1 STATUS REGISTER A (SRA)

7.1.2 STATUS REGISTER B (SRB)

7.1.3 DIGITAL OUTPUT REGISTER (DOR)

TABLE 7-2: INTERNAL 2 DRIVE DECODE – NORMAL

7.1.4 TAPE DRIVE REGISTER (TDR)

TABLE 7-3: TAPE SELECT BITS

TABLE 7-4: DRIVE TYPE ID

7.1.5 DATA RATE SELECT REGISTER (DSR)

TABLE 7-5: PRECOMPENSATION DELAYS

TABLE 7-6: DATA RATES

TABLE 7-7: DRVDEN MAPPING

TABLE 7-8: DEFAULT PRECOMPENSATION DELAYS

7.1.6 MAIN STATUS REGISTER

7.1.7 DATA REGISTER (FIFO)

TABLE 7-9: FIFO SERVICE DELAY

7.1.8 DIGITAL INPUT REGISTER (DIR)