Microchip SAMA5D2-PTC-EK User Manual

SAMA5D2-PTC-EK

SAMA5D2-PTC-EK User's Guide

Scope

This user's guide describes how to use the SAMA5D2 PTC Evaluation Kit (SAMA5D2-PTC-EK).

The SAMA5D2-PTC-EK is used to evaluate the capabilities of the Peripheral Touch Controller (PTC) designed for the SAMA5D2 series of embedded MPUs. Refer to the Configuration Summary table in the SAMA5D2 Series Datasheet for the list of MPUs featuring PTC.

DS50002709B-page 1

SAMA5D2-PTC-EK

1. Introduction

1.1 Document Layout

The document is organized as follows:

• Chapter 1. "Introduction"

• Chapter 2. "Product Overview" – Important information about the SAMA5D2-PTC-EK board

• Chapter 3. "Board Components" – Specifications of the SAMA5D2-PTC-EK and high-level description of the major components and interfaces

• Chapter 4. "Installation and Operation" – Instructions on how to get started with the SAMA5D2-PTC-EK

• Appendix A. "Schematics and Layouts" – SAMA5D2-PTC-EK schematics and layout diagrams

1.2 Recommended Reading

The following Microchip document is available and recommended as a supplemental reference resource:

• SAMA5D2 Series Datasheet. Lit. Number DS60001476

SAMA5D2-PTC-EK

Introduction

DS50002709B-page 3

2. Product Overview

2.1 SAMA5D2-PTC-EK Features

The SAMA5D2-PTC-EK follows the Microchip MPU strategy for low cost evaluation kits with maximum reuse capability, and is built on the SAMA5D2 Xplained Ultra (XULT) hardware and software ecosystem. This board is mainly dedicated to evaluating the Peripheral Touch Controller capabilities.

Table 2-1. SAMA5D2-PTC-EK Features

Characteristics Specifications Components

SAMA5D2-PTC-EK

Product Overview

Processor

Clock speed

Memory

Display One LCD interface connector RGB, 18 bits

SD/MMC

USB

Ethernet One ETH PHY Micrel KSZ8081RN

Debug port

SAMA5D27-CU (289-ball BGA) 14x14mm body,

0.8mm pitch

MPU: 24 MHz, 32.768 KHz

PHY: Crystal 25 MHz

Two 16-bit, 2-Gbit DDR2

One 4-Gbit Nand Flash

One QSPI Flash

One Serial Data Flash (optional)

One EEPROM

One standard SD card interface

One microSD card interface

One USB host type A

One USB device type Micro-AB

One USB HSIC

One J-Link-OB/J-Link-CDC

One JTAG interface

–

Winbond W972GG6KB-25

Micron MT29F4G08

Microchip SST26VF064B

Microchip SST26VF032B

Microchip 24AA02E48

With 3.3V/1.8V power switch

–

With 5V power switch

–

Connector not mounted

Embedded J-Link-OB and J-Link-CDC (ATSAM3U4C TFBGA100)

One RGB (Red, Green, Blue) LED

Board monitor

Expansion

Board supply From USB A and USB J-Link-OB 5VDC

Backup power supply SuperCap ELNA DSK-3R3H204T614-H2L

Four push button switches

One set of XPRO WINGS connectors

One ITO FLEX connector

One Port B connector

One PIOBU connector

One mikroBUS™ connector

–

DisableBoot, Reset, WakeUp, User Free

Dedicated PTC QTouch

Optional

–

®

DS50002709B-page 4

2.2 SAMA5D2-PTC-EK Content

The SAMA5D2-PTC-EK evaluation kit includes the following:

• The SAMA5D2-PTC-EK board

• A USB cable

2.3 Evaluation Kit Specifications

Table 2-2. Evaluation Kit Specifications

Characteristic Specification

Board SAMA5D2-PTC-EK

Board supply voltage USB-powered

Temperature Operating: 0°C to +70°C

Storage: –40°C to +85°C

Relative humidity 0 to 90% (non-condensing)

Main board dimensions 135 × 90 × 20 mm

SAMA5D2-PTC-EK

Product Overview

RoHS status Compliant

Board identification SAMA5D2 Peripheral Touch Controller Evaluation Kit

2.4 Power Sources

Several options are available to power up the SAMA5D2-PTC-EK board:

• USB powering through the USB Micro-AB connector (J4 - default configuration)

• Powering through the USB Micro-AB connector on the J-Link-OB Embedded Debugger interface (J9)

Table 2-3. Electrical Characteristics

Electrical Parameter Value

Input voltage 5VCC

Maximum input voltage 6VCC

Maximum 3.3VDC current available 1.2A

I/O voltage 3.3V only

DS50002709B-page 5

3. Board Components

This section covers the specifications of the SAMA5D2-PTC-EK and provides a high-level description of the board's major components and interfaces. This document is not intended to provide detailed documentation about the processor or about any other component used on the board. It is expected that the user will refer to the appropriate documents of these devices to access detailed information.

3.1 Board Overview

The fully-featured SAMA5D2-PTC-EK board integrates multiple peripherals and interface connectors, as shown in the figure below.

SAMA5D2-PTC-EK

Board Components

3.1.1 Default Jumper Settings

The figure below shows the default jumper settings. Jumpers in red are configuration items and current measurement points. Jumpers in blue are not populated.

DS50002709B-page 6

Figure 3-1. Default Jumper Settings

SAMA5D2-PTC-EK

Board Components

The following table describes the functionality of the jumpers.

Table 3-1. SAMA5D2-PTC-EK Jumper Settings

Jumper Default Function

JP1 Closed VDD_MAIN_5V current measurement

JP2 Closed VDDOSC, VDDUTMII, VDDANA, VDDAUDIOPLL current measurement

JP3 Closed VDDISC + VDDIOP0/1/2 current measurement

JP4 Closed VDDIODDR_MPU current measurement

JP5 Closed VDDCORE current measurement

JP6 Closed VDDBU current measurement

JP7 Open PIOBU1, PIOBU7

JP8 Closed Disables NAND_CS (open=disable)

JP9 Open Enables JTAG-CDC (closed=disable)

JP10 Open Enables JTAG-OB (closed=disable)

DS50002709B-page 7

...........continued

WARNING

Jumper Default Function

Erases SAM3U Flash Code (closed = erase)

SAMA5D2-PTC-EK

Board Components

JP11 Open

JP12 Closed Powers mikroBUS extension (3.3V)

JP13 Open Disables QSPI

1-2 Enables 3.3V J-Link-OB, connected to shutdown circuitry

JP14

2-3 Enables 3.3V J-Link-OB, always ON

3.1.2 Connectors on Board

The following table describes the interface connectors on the SAMA5D2-PTC-EK.

Table 3-2. SAMA5D2-PTC-EK Board Interface Connectors

Connector Interfaces to

J1 PIOBU, tamper and analog comparator connector (not populated)

J2 JTAG, 10-pin IDC connector

J3 USB Host B. Supports USB host using a type A connector

J4 USB A Device. Supports USB device using a type Micro-AB connector

J5 USB-C™ HSIC header (not populated)

J6 Standard SDMMC connector

This jumper is reserved for factory configuration and should never be used by the end user.

J7 microSD connector

J8 Ethernet 10/100 RJ45

J9 USB-A Micro-AB, J-Link-OB port

J10 PCB connector for factory-programming the J-Link-OB/SAM3U

J11, J12 Xplained Pro expansion connectors (PTC-dedicated add-on boards)

J13 PIOs PortB connector

J14 ITO connector

J15 A&B mikroBUS connector

J16 Expansion TFT LCD connector for display module

DS50002709B-page 8

3.2 Function Blocks

POWER

MONITOR

J-Link Power

5V/3.3V

USB

Connector

Function Select

System Supplies

POWER

REGULATORS

SHDN

UART

MPU JTAG

Interface

JTAG Switch

JTAG

LCD (18 bits)

TWI/SPI

RJ45

USB A&B

SDHC0

SDHC1

SAMA5D2-PTC-EK

Push

Button

FPC Connector

DEBUG

Interface

Reset, Wkup

DisBoot, User

3.3V, 2.5V,1.8V, 1.2V

VDDBU

GPIO

USB

Detection

ETH PHY

PTC

QSPI Flash

DDR2

SDRAM

DDR2

SDRAM

Power

Cap

Serial

EEPROM

NAND Flash

PIOBU Connector

MikroBUS

Interface

ITO Connector

XPRO (1&2)

PTC Interface

GPIO

PortB[0-7]

Power Switch

VBUS

5V

USB-B

Connector

USB-A

Connector

SPI

Flash

LEDs

J-Link-OB

J-Link-CDC

SAMA5D27

RGB LEDs

Tri

State

SD Card

Connector

uSD

Connector

J-Link-OB

JTAG Interface

Figure 3-2. SAMA5D2-PTC-EK Block Diagram

SAMA5D2-PTC-EK

Board Components

3.2.1 Processor

The SAMA5D2 Series is a high-performance, power-efficient embedded MPU based on the ARM® Cortex®-A5 processor.

Please refer to the SAMA5D2 Series datasheet for more information.

3.2.2 Power Supply Topology and Power Distribution

3.2.2.1 Input Power Options

Two options are available to power the SAMA5D2-PTC-EK board. The USB-powered operation is the default configuration and comes from the USB device ports (J4-J9) connected to a PC or a 5VDC supply. Such USB power source is sufficient to supply the board in most applications. It is important to note that when the USB-powered operation is used, the USB port down the way has a limited powering capability. If the USB-B Host port (J3) is required to provide full powering capabilities to the target application, it is recommended to use an external DC supply instead of a USB power source.

The following figure is a schematic of the power options.

DS50002709B-page 9

Figure 3-3. Input Powering

VDD_MAIN_5V

GND_POWER

VBUS_USBA

VBUS_JLINK

U1A

DMP2160UFD

1

2

6

7

C1 100nF C0402

U4A DMP2160UFD

1

2

6

7

R5 100K

R0402

R6 DNP

R0402

U1B

DMP2160UFD

4

5

3

8

JP1

Header 1X2

1

2

C12 100nF C0402

R1

10K R0402

U4B DMP2160UFD

4

5

3

8

R2 100K R0402

JPR1

Jumper

C2

100nF C0402

CAUTION

Note: USB-powered operation eliminates additional wires and batteries. It is the preferred mode of operation for any

project that requires only a 5V source at up to 500 mA.

Jumper JP1 is used to perform MAIN_5V current measurements on the SAMA5D2-PTC-EK board.

3.2.2.2 Power Supply Requirements and Restrictions

Detailed information on the device power supplies is provided in tables “SAMA5D2 Power Supplies” and “Power Supply Connections” in the SAMA5D2 Series datasheet.

SAMA5D2-PTC-EK

Board Components

3.2.2.3 Power-up and Power-down Considerations

Power-up and power-down considerations are described in section “Power Considerations” of the SAMA5D2 Series datasheet.

The power-up and power-down sequences provided in the SAMA5D2 Series datasheet must be respected for reliable operation of the device.

3.2.2.4 Power Management

The board power management uses three types of regulators:

• One dual synchronous step-down DC-DC regulator (U2 MIC2230) generates the 3.3V/800mA and 1.8V/800mA power lines and utilizes a high-efficiency, fixed-frequency (2.5 MHz), current-mode PWM control architecture that requires a minimum number of external components.

• One ultra low-dropout linear regulator (U3 MIC47053) generates the 1.25V/500mA from the 1.8V source.

• One high-performance single 2.5V/150mA is used as a VDDFUSE generator (U5 MIC5366).

The main regulators are enabled through a Field Effect Transistor (FET) scheme. The processor can assert SHDN (a VDDBU-powered I/O) to shut down the regulators to enter Backup mode. All regulators on the board are also shut down by the action of the SHDN signal.

A 3.3V battery (supercap) is implemented to permanently maintain VDDBU voltage (note: jumper JP6 must be in place). The board can be woken up by action on the PB4 button, which drives the WKUP signal (also a VDDBUpowered I/O).

The figure below shows the power management scheme.

DS50002709B-page 10

Figure 3-4. Board Power Management

EN_1

EN_VDD_1V25

STARTB

FPWM#

EN_1

EN_VDD_1V25

VDD_MAIN_5V

GND_POWER

VDD_3V3

VDD_1V8

VDD_MAIN_5V

VDD_1V8

VDD_1V25

VDD_MAIN_5V

GND_POWER

VDD_MAIN_5V

VDD_3V3

VDD_MAIN_5V

GND_POWER

VDD_3V3

GND_POWER

VDD_3V3

GND_POWER

GND_POWERGND_POWER

GND_POWER

SHDN

C4 10uF

C0603

U2

MIC2230-GSYML

MLF3x3mm

AVIN

3

EN1

11

FPWM#

7

SW1

8

OUT1

12

AGND5PGND

6

OUT2

1

SW2

4

PGOOD

10

EN2

2

VIN

9

EPAD

13

R249 4.7K

R0402

R13 39K

R0402

C6 10uF

C0603

R3 100K

R0402

R251 10K

R0402

R12 220K

R0402

C10 390pF

C0402

C7 100nF

C0402

L2 LQH43CN2R2M03L

L1812

C3 10uF

C0603

R248 20K

R0402

R10

DNP

R0402

R11 100K

R0402

C13

4.7nF

C0402

R250

3.3K

R0402

L1 LQH43CN2R2M03L

L1812

C5 1uF

C0603

Q1 BSS138

SOT23_123

1

3

2

R4 10K

R0402

C9 1uF

C0603

D1 PMEG6010CEGWX

sod123

Q2 BSS138

SOT23_123

1

3

2

C8 100nF

C0402

R9 100K

R0402

C11 10uF

C0603

Q3 BSS138

SOT23_123

1

3

2

U3

MIC47053YMT

BIAS

1

GND

2

IN1

3

IN2

4

ADJ

6

OUT

5

EPAD

9

PGOOD

7

EN

8

Q4

BC847C

SOT-23

1

32

R8 100K

R0402

C14

2.2uF

C0603

NRST

SAMA5D2-PTC-EK

Board Components

3.2.2.5 Supply Group Configuration

The main regulators provide all power supplies required by the SAMA5D2 device:

• 1.25V VDDCORE, VDDPLLA, VDDUTMIC, VDDHSIC

• 1.8V VDDIODDR, VDDSDHC1V8

• 2.5V VDDFUSE

• 3.3V VDDIOP0, VDDIOP1, VDDIOP2, VDDISC

• 3.3V VDDOSC, VDDUTMI, VDDANA, VDDAUDIOPLL

• 3.3V VDDBU

DS50002709B-page 11

Figure 3-5. Power Lines Distribution

For DDR2 For MPU

VDDHSIC

V

DD_3V3

VDD_1V25

VDDCORE

VDDIOP0

VDDIOP2

VDDIOP1

VDDPLLA

VDDUTMIC

VDDIODDR

VDDAUDIOPLL

VDDANA

VDDOSC

VDDUTMII

VDDISC

VDD_1V8 VDDSDHC1V8

L3

BLM18PG181SN1D R0603

1 2

R16 2R2 R0603

R15

2R2 R0603

R17 0R R0603

L7 MLZ1608N100L L0603

L11

BLM18PG181SN1D R0603

1 2

L10

BLM18PG181SN1D R0603

1

2

JP5 Header 1X2

1

2

R18 0R R0603

L4

BLM18PG181SN1D R0603

1 2

L14

BLM18PG181SN1D

1

2

L9 MLZ1608N100L L0603

JP4 Header 1X2

1

2

L13

BLM18PG181SN1D R0603

1 2

L6

BLM18PG181SN1D R0603

1

2

L8 MLZ1608N100L

L0603

R19 2R2 R0603

L5

BLM18PG181SN1D R0603

1 2

L12

BLM18PG181SN1D R0603

1 2

JP3 Header 1X2

1

2

JP2 Header 1X2

1

2

(3V3)

(1V2)

(1V8)

(3V3)

)3

V3(

)3V3()3V3

(

)5V2(

)

2V1(

(3V3)

(1V8)

(1V2)

(2V5)

(3V3)

(1V2)

)3

V3(

)2V1(

(3V3)

(3V3 or 1V8)

VDDBU

VDDCORE

VDDPLLA

VDDIOP0

VDDIOP1

VDDIOP2

VDDHSIC

VDDUTMIC

VDDUTMII

VDDSDHC

VDDPLLA

VDDOSC

VDDISC

VDDFUSE

VDDAUDIOPLL

VDDBU

VDDIODDR

VDDANA

VDDIOP0

VDDIOP1

VDDIOP2

VDDHSIC

VDDFUSE

VDDUTMII

VDDSDHC

VDDOSC VDDISC

VDDUTMIC

VDDCORE

VDDIODDR

VDDAUDIOPLL

GND_POWER

VDDBU

GND_POWER

VDDCORE

GND_POWER

VDDIODDR

VDDANA

GND_POWER

VDDIOP0

GND_POWER

VDDIOP1

GND_POWER

VDDIOP2

GND_POWER

VDDHSIC

GND_POWER

VDDFUSE

GND_POWER

VDDUTMII

GND_POWER

VDDSDHC

GND_POWER

VDDPLLA

GND_POWER

VDDOSC

VDDISC

GND_POWER

VDDUTMIC

GND_POWER

GNDUTMII

GND_POWER

VDDAUDIOPLL

C35 100nF C0402

C51 1nF C0402

C54

4.7uF C0805

C31 100nF C0402

C25

4.7uF C0805

C61 1nF C0402

C56 100nF C0402

C37 100nF C0402

C59 1nF C0402

C20 10uF C0603

C19 10uF C0603

C21 100nF C0402

C42 100nF C0402

C40 100nF C0402

C52 1nF C0402

C50 100nF C0402

C48 100nF C0402

C26 100nF C0402

C53 100nF C0402

C28 10uF C0603

C30 100nF C0402

C34 100nF C0402

C60 1nF C0402

C46 100nF C0402

C41

4.7uF C0805

C49 100nF C0402

C27 10uF C0603

C44 100nF C0402

R20 1R-1% R0603

C29 100nF C0402

C36 100nF C0402

R21 1R-1% R0603

C24

4.7uF C0805

C47 100nF C0402

C32 100nF C0402

ATSAMA5D27C-CN

U6G

bga289p8

GNDADC

K5

GNDANA

L3

GNDBU

N6

GNDCORE_1

E7

GNDCORE_2

E9

GNDCORE_3

H4

GNDCORE_4

K12

GNDCORE_5

M5

GNDCORE_6

M9

GNDDDR_1

D14

GNDDDR_2

E11

GNDDDR_3

E12

GNDDDR_4

E14

GNDDDR_5

H14

GNDDDR_6

J14

GNDDDR_7

L14

GNDDPLL

T5

GNDAUDIOPLL

T4

GNDIOP0_1

F6

GNDIOP0_2

G7

GNDIOP1_1

M13

GNDIOP1_2

P14

GNDIOP2

F9

GNDISC

G4

GNDOSC

T6

GNDPLLA

U5

GNDSDMMC

R11

GNDUTMII

P9

GNDUTMIC

R7

VDDADC

L5

VDDANA

K3

VDDBU

N7

VDDCORE_1

D7

VDDCORE_2

D9

VDDCORE_3

H3

VDDCORE_4

K13

VDDCORE_5

N5

VDDCORE_6

N9

VDDDDR_1

D11

VDDDDR_2

D12

VDDDDR_3

D15

VDDDDR_4

E15

VDDDDR_5

H15

VDDDDR_6

J15

VDDDDR_7

L15

VDDAUDIOPLL

T3

VDDFUSE

M12

VDDHSIC

R9

VDDIOP0_1

E6

VDDIOP0_2

F7

VDDIOP1_1

N13

VDDIOP1_2

R14

VDDIOP2

F10

VDDISC

F4

VDDOSC

T7

VDDPLLA

U4

VDDSDMMC

P11

VDDUTMII

P8

VDDUTMIC

P7

C55 100nF C0402

C23 100nF C0402

C43 100nF C0402

C38 100nF C0402

C58 1nF C0402

C57 100nF C0402

C33 100nF C0402

C39 100nF C0402

C45 100nF C0402

C22 100nF C0402

Figure 3-6. Processor Power Lines Supplies

SAMA5D2-PTC-EK

Board Components

DS50002709B-page 12

3.2.2.6 VDDFUSE

VDD_3V3

GND_POWER

VDDFUSE

EN_1 12

C16 1uF C0603

U5

MIC5366-2.5YMT MLF1x1mm

VIN

4

GND

2

VOUT

1

EN

3

EPAD

5

C15 1uF C0603

(Super)-Capa citor energy storage

VDDBU

GND_POWER

VDD_3V3

C18 100nF C0402

JP6

Header 1X2

1

2

+

C17

0.2F/3.3V c117x68

D2

PMEG6010CEGWX sod123

R14 100R-1%

R0402

D3 BAT54C

SOT23_123

3

1

2

STARTB

GND_POWER

VDD_MAIN_5V

VDD_3V3

NRST

R13 39K R0402

R12 220K R0402

R11 100K R0402

D1 PMEG6010CEGWX sod123

Q3 BSS138 SOT23_123

1

3

2

Q4

BC847C

SOT-23

1

32

C14

2.2uF C0603

PowerGood VDD_1V25

The SAMA5D2-PTC-EK board embeds a 2.5V regulator for fuse box programming.

Figure 3-7. VDDFUSE Regulator

3.2.2.7 Backup Power Supply

The SAMA5D2-PTC-EK board requires a power source in order to permanently power the backup part of the SAMA5D2 device (refer to SAMA5D2 Series datasheet). The super capacitor C17 sustains such permanent power to VDDBU when all system power sources are off.

Figure 3-8. VDDBU Powering Options

SAMA5D2-PTC-EK

Board Components

3.2.3 Reset Circuitry

3.2.4 Shutdown Circuitry

The reset sources for the SAMA5D2-PTC-EK board are:

• Power-on Reset from the power management unit,

• Push button reset BP3,

• JTAG or J-Link-OB reset from an in-circuit emulator.

Figure 3-9. Main Reset Control

The SHDN signal, output of Shutdown Controller (SHDN), drives the shutdown request to the power supply. This output signal is supplied by VDDBU, which is present in Backup mode.

The Shutdown Controller manages the main power supply and is connected to the ENABLE input pin of the DC/DC converter providing the main power supplies of the system.

DS50002709B-page 13

Figure 3-10. Shutdown Controller

STARTB

EN_1

VDD_MAIN_5V

GND_POWER GND_POWER

VDD_3V3

GND_POWER

SHDN

R3 100K R0402

Q1 BSS138 SOT23_123

1

3

2

R4 10K R0402

Q2 BSS138 SOT23_123

1

3

2

C8 100nF C0402

WAKE UP

RESET

DIS BOOT

GND_POWER

VDDBU

DISABLE_BOOT

NRST

WKUP

R146 100R-1%

r0402

BP3 Tact Switch

FSM2JSML

R147 100R-1%

r0402

R238 10K

R0402

BP2 Tact Switch

FSM2JSML

R145 100R-1%

r0402

BP4 Tact Switch

FSM2JSML

USER BUTTON

PA10_USER_BT

R144 0R

R0402

BP1 Tact Switch

FSM2JSML

GND_POWER

XIN

XOUT

XOUT32

XIN32

GND_POWERGND_POWER

GND_POWER

R122

DNP R0402

C98 20pF C0402

C97 20pF C0402

R123 DNP

R0402

C96 20pF C0402

Y1

24MHz CL=10pF

x4s32x25

1 4

32

C99 20pF C0402

Y2

32.768KHz CL=12.5pF

X4S70X15

1

23

4

3.2.5 Push Button Switches

The SAMA5D2-PTC-EK features four push buttons:

• One board reset push button (BP3). When pressed and released, it causes a power-on reset of the board.

• One wakeup push button (BP4) connected to the SAMA5D2 WKUP pin, used to exit the processor from LowPower mode.

• One disable boot push button (BP2) used to devalidate the boot memories (refer to 3.2.8.3 CS Disable).

Figure 3-11. System Push Buttons

SAMA5D2-PTC-EK

Board Components

• One user push button (BP1) connected to PIO PB10.

Figure 3-12. User Push Button

3.2.6 Clock Circuitry

The embedded microcontroller generates its necessary clocks based on two crystal oscillators: one slow clock (SLCK) oscillator running at 32.768 KHz and one main clock oscillator running at 24 MHz.

The SAMA5D2-PTC-EK board includes four clock sources:

• The two clocks mentioned above are alternatives for the SAMA5D2 processor (24 MHz, 32.768 kHz)

• One crystal oscillator for the Ethernet RMII chip (25 MHz)

• One crystal oscillator for the J-Link-OB microcontroller (12 MHz)

Figure 3-13. MPU Clock Circuitry

DS50002709B-page 14

3.2.7 Memory

DDR_VREFDDR_VREF

DDR_DQM0 DDR_DQM1

DDR_DQM2 DDR_DQM3

DDR_DQS0-

DDR_DQS0+

DDR_DQS1+ DDR_DQS1-

DDR_DQS2+ DDR_DQS2DDR_DQS3+ DDR_DQS3-

DDR_BA1

DDR_BA0

DDR_BA1

DDR_BA0

DDR_WE DDR_WE

DDR_CSDDR_CS

DDR_CLK-

DDR_CLK+

DDR_CLK-

DDR_CLK+

DDR_CKE DDR_CKE

DDR_CAS

DDR_RAS

DDR_CAS

DDR_RAS

DDR_D16 DDR_D17 DDR_D18 DDR_D19 DDR_D20 DDR_D21 DDR_D22 DDR_D23 DDR_D24 DDR_D25 DDR_D26 DDR_D27 DDR_D28 DDR_D29 DDR_D30 DDR_D31

DDR_D0 DDR_D1 DDR_D2 DDR_D3 DDR_D4 DDR_D5 DDR_D6 DDR_D7 DDR_D8 DDR_D9 DDR_D10 DDR_D11 DDR_D12 DDR_D13 DDR_D14 DDR_D15

DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12

DDR_BA2 DDR_BA2

DDR_A13DDR_A13

GND_POWER

VDD_1V8

GND_POWER

VDD_1V8

GND_POWER

VDD_1V8

GND_POWER

VDD_1V8

GND_POWER

C94 100nF C0402

R29 DNP R0402

C95 1nF C0402

U8

W972GG6KB-25 bga84-32-1509e

A0

M8

A1

M3

A2

M7

A3

N2

A4

N8

A5

N3

A6

N7

A7

P2

A8

P8

A9

P3

A10

M2

A11

P7

A12

R2

A13

R8

BA0

L2

BA1

L3

BA2

L1

CKE

K2

CK_P

J8

CK_N

K8

RAS

K7

CAS

L7

WE

K3

CS

L8

DQ0

G8

DQ1

G2

DQ2

H7

DQ3

H3

DQ4

H1

DQ5

H9

DQ6

F1

DQ7

F9

DQ8

C8

DQ9

C2

DQ10

D7

DQ11

D3

DQ12

D1

DQ13

D9

DQ14

B1

DQ15

B9

LDQS_P

F7

NU/LDQS_N

E8

UDQS_P

B7

NU/UDQS_N

A8

LDM

F3

UDM

B3

ODT

K9

NC1

A2

NC2

E2

NC3

R3

NC4

R7

VDD1

A1

VDD2

E1

VDD3

J9

VDD4

M9

VDD5

R1

VDDQ1

A9

VDDQ2

C1

VDDQ3

C3

VDDQ4

C7

VDDQ5

C9

VDDQ6

E9

VDDQ7

G1

VDDQ8

G3

VDDQ9

G7

VDDQ10

G9

VDDL

J1

VREF

J2

VSS1

A3

VSS2

E3

VSS3

J3

VSS4

N1

VSS5

P9

VSSQ1

A7

VSSQ2

B2

VSSQ3

B8

VSSQ4

D2

VSSQ5

D8

VSSQ6

E7

VSSQ7

F2

VSSQ8

F8

VSSQ9

H2

VSSQ10

H8

VSSDL

J7

U7

W972GG6KB-25 bga84-32-1509e

A0

M8

A1

M3

A2

M7

A3

N2

A4

N8

A5

N3

A6

N7

A7

P2

A8

P8

A9

P3

A10

M2

A11

P7

A12

R2

A13

R8

BA0

L2

BA1

L3

BA2

L1

CKE

K2

CK_P

J8

CK_N

K8

RAS

K7

CAS

L7

WE

K3

CS

L8

DQ0

G8

DQ1

G2

DQ2

H7

DQ3

H3

DQ4

H1

DQ5

H9

DQ6

F1

DQ7

F9

DQ8

C8

DQ9

C2

DQ10

D7

DQ11

D3

DQ12

D1

DQ13

D9

DQ14

B1

DQ15

B9

LDQS_P

F7

NU/LDQS_N

E8

UDQS_P

B7

NU/UDQS_N

A8

LDM

F3

UDM

B3

ODT

K9

NC1

A2

NC2

E2

NC3

R3

NC4

R7

VDD1

A1

VDD2

E1

VDD3

J9

VDD4

M9

VDD5

R1

VDDQ1

A9

VDDQ2

C1

VDDQ3

C3

VDDQ4

C7

VDDQ5

C9

VDDQ6

E9

VDDQ7

G1

VDDQ8

G3

VDDQ9

G7

VDDQ10

G9

VDDL

J1

VREF

J2

VSS1

A3

VSS2

E3

VSS3

J3

VSS4

N1

VSS5

P9

VSSQ1

A7

VSSQ2

B2

VSSQ3

B8

VSSQ4

D2

VSSQ5

D8

VSSQ6

E7

VSSQ7

F2

VSSQ8

F8

VSSQ9

H2

VSSQ10

H8

VSSDL

J7

C72 100nF C0402

R32 0R

R0402

C75 1nF C0402

R31

DNP R0402

R30 0R

R0402

3.2.7.1 Memory Organization

The SAMA5D2 features a DDR/SDR memory interface and an External Bus Interface (EBI) to enable interfacing to a wide range of external memories and to almost any kind of parallel peripheral.

This section describes the memory devices mounted on the SAMA5D2-PTC-EK board:

• Two DDR2 SDRAMs

• One NAND Flash

• One QSPI Flash

• One SPI Flash (optional)

• One serial EEPROM

Additional memory can be added to the board by:

• Installing an SD or MMC card in the SD/MMC0 or SD/MMC1 slot,

• Using the USB-B port.

Support is dependent upon driver support in the OS.

3.2.7.2 DDR2/SDRAMs

Two DDR2/SDRAMs (W972GG6KB-25-2 Gbits = 16 Mbits x 16 x 8 banks) are used as main system memory, totalling 4 Gbits of SDRAM on the board. The memory bus is 32 bits wide and operates with a frequency of up to 166 MHz.

The figure below illustrates the implementation for the DDR2 memories.

Figure 3-14. DDR2 SDRAMs

SAMA5D2-PTC-EK

Board Components

3.2.7.3 DDR_CAL Analog Input

One specific analog input, DDR_CAL, is used to calibrate all DDR I/Os.

DS50002709B-page 15

Table 3-3. Calibration Cell DDR_CAL Value

DDR_D0 DDR_D1 DDR_D2 DDR_D3 DDR_D4 DDR_D5 DDR_D6 DDR_D7 DDR_D8 DDR_D9 DDR_D10 DDR_D11 DDR_D12 DDR_D13 DDR_D14 DDR_D15 DDR_D16 DDR_D17 DDR_D18 DDR_D19 DDR_D20 DDR_D21 DDR_D22 DDR_D23 DDR_D24 DDR_D25 DDR_D26 DDR_D27 DDR_D28 DDR_D29 DDR_D30 DDR_D31

DDR_DQM0 DDR_DQM1 DDR_DQM2 DDR_DQM3

DDR_DQS0+ DDR_DQS0-

DDR_DQS1+ DDR_DQS1-

DDR_DQS2+ DDR_DQS2-

DDR_DQS3+ DDR_DQS3-

DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13

DDR_BA0 DDR_BA1

DDR_RAS DDR_CAS

DDR_BA2

DDR_CS DDR_WE

DDR_VREF

DDR_RESETN

DDR_CLK+ DDR_CLKDDR_CKE

GND_POWER

VDDIODDR

R23 100K R0402

R24

21K-1%

R0402

R25 100K R0402

C64

22pF

C0402

ATSAMA5D27C-CN

U6E

bga289p8

DDR_A0

F12

DDR_A1

C17

DDR_A10

C15

DDR_A11

A16

DDR_A12

A17

DDR_A13

G11

DDR_A2

B17

DDR_A3

B16

DDR_A4

C16

DDR_A5

G14

DDR_A6

F14

DDR_A7

F11

DDR_A8

C14

DDR_A9

D13

DDR_BA0

H12

DDR_BA1

H13

DDR_BA2

F17

DDR_CAL

E13

DDR_CAS

G12

DDR_CKE

F16

DDR_CLK

E17

DDR_CLKN

D17

DDR_CS

G13

DDR_D0

B12

DDR_D1

A12

DDR_D10

H17

DDR_D11

K17

DDR_D12

K16

DDR_D13

J13

DDR_D14

K14

DDR_D15

K15

DDR_D16

B8

DDR_D17

B9

DDR_D18

C9

DDR_D19

A9

DDR_D2

C12

DDR_D20

A10

DDR_D21

D10

DDR_D22

B11

DDR_D23

A11

DDR_D24

J12

DDR_D25

H10

DDR_D26

J11

DDR_D27

K11

DDR_D28

L13

DDR_D29

L11

DDR_D3

A13

DDR_D30

L12

DDR_D31

M17

DDR_D4

A14

DDR_D5

C13

DDR_D6

A15

DDR_D7

B15

DDR_D8

G17

DDR_D9

G16

DDR_DQM0

C11

DDR_DQM1

G15

DDR_DQM2

C8

DDR_DQM3

H11

DDR_DQS0

B13

DDR_DQS1

J17

DDR_DQS2

C10

DDR_DQS3

L17

DDR_DQSN0

B14

DDR_DQSN1

J16

DDR_DQSN2

B10

DDR_DQSN3

L16

DDR_RAS

F13

DDR_RESETN

E16

DDR_VREFCM

D16

DDR_VREFB0

H16

DDR_WE

F15

C62 100nF C0402

C63 100nF C0402

CAUTION

Memory Resistor value

LPDDR2/LPDDR3 24K

DDR3L 23K

DDR3 22K

DDR2/LPDDR1 21K

Figure 3-15. DDR Signals and CAL Analog Input

SAMA5D2-PTC-EK

Board Components

3.2.7.4 NAND Flash

The SAMA5D2-PTC-EK has native support for NAND Flash memory through its NAND Flash Controller. The board implements one MT29F4G08ABA 4Gb x 16 NAND Flash connected to Chip Select three (NCS3) of the microcontroller.

The figure below illustrates the NAND Flash memory implementation.

The NAND Flash interface is shared with the SDMMC1 and QSPI interfaces.

DS50002709B-page 16

NAND_WPn

3V3_NAND

VDD_3V3 3V3_NAND

3V3_NAND

NAND_CLE_PB1

NAND_ALE_PB0

NAND_REn_PB2

NAND_WEn_PA30

NAND_RDY_PC8

NAND_IO5_PA27 NAND_IO6_PA28 NAND_IO7_PA29

NAND_IO0_PA22 NAND_IO1_PA23 NAND_IO2_PA24 NAND_IO3_PA25 NAND_IO4_PA26

NAND_CS_PA31

R175 100K

MT29F4G08ABADAWP

U13

NC1

1

NC2

2

NC3

3

NC4

4

NC5

5

NC6

6

R/B#

7

CE#

9

NC7

10

VCC_1

12

VSS_1

13

NC9

14

NC10

15

CLE

16

ALE

17

NC21

47

VSS_4

48

RE#

8

NC8

11

WE#

18

WP#

19

DNU2

20

DNU1

21

NC11

22

NC12

23

NC13

24

VSS_2

25

NC14

26

NC15

27

NC16

28

DQ0

29

DQ1

30

DQ2

31

DQ3

32

NC17

33

VCC_2

34

DNU3

35

VSS_3

36

VCC_3

37

DNU4

38

VCC_4

39

NC18

40

DQ4

41

DQ5

42

DQ6

43

DQ7

44

NC19

45

NC20

46

R177 DNP

R174 0R

C113

100nF

R180 100K

C112

100nF

JP8 Header 1X2

1

2

C114

100nF

R179 0R

C115

100nF

R176 10K

SAMA5D2-PTC-EK

Figure 3-16. NAND Flash

Table 3-4. NAND Flash Signal Descriptions

PIO Signal Name Shared PIO Signal Description

Board Components

PA22 NAND_D0 SDMMC1-QSPI Data 0

PA23 NAND_D1 QSPI Data 1

PA24 NAND_D2 QSPI Data 2

PA25 NAND_D3 QSPI Data 3

PA26 NAND_D4 QSPI Data 4

PA27 NAND_D5 QSPI Data 5

PA28 NAND_D6 SDMMC1 Data 6

PA29 NAND_D7 – Data 7

PA30 NANDWE SDMMC1 –

PA31 NCS3 – Chip Select

PB00 NANDALE – –

PB01 NANDCLE – –

PB02 NANDOE – –

PC08 NANRDY – –

3.2.7.5 NAND Flash CS Disable

On-board jumper JP8 controls the selection (CS#) of the NAND Flash memory.

3.2.8 Additional Memories

3.2.8.1 Serial Flash

The SAMA5D2 includes two high-speed Serial Peripheral Interface (SPI) controllers. The SPI is a full duplex synchronous bus supporting a single master and multiple slave devices. The SPI bus consists of the following items:

• a serial clock line (generated by the master)

• a data output line from the master

• a data input line to the master

• one or more active low Chip Select signals (output from the master)

DS50002709B-page 17

One SPI port is used to interface with the on-board serial Flash.

SPI0_CS0_PA17

GND_POWER

VDD_3V3

SPI0_MOSI_PA15 SPI0_MISO_PA16

SPI0_SPCK_PA14

C119 100nF C0402

U16

SST26VF032B-104I/SM soic8jg

HOLD

7

GND

4

VCC

8

CS

1

SCK

6

SI

5

SO

2

WP

3

QSPI0_CS_PA23

VDD_3V3

GND_POWER

VDD_3V3

QSPI0_IO0_PA24 QSPI0_IO1_PA25 QSPI0_IO2_PA26 QSPI0_IO3_PA27 QSPI0_SCK_PA22

U14

SST26VF064B-104I/SM soic8jg

SI/SIO0

5

SO/SIO1

2

SIO2

3

SIO37SCLK

6

CS#

1

GND

4

VCC

8

C120 100nF C0402

R186 10K R0402

R187 10K R0402

JP13 Header 1X2

1

2

R242 10K

The following figure illustrates the implementation of an SPI Flash memory.

Figure 3-17. Serial Flash

Note: The serial Flash is optional and not mounted on board.

3.2.8.2 QSPI Serial Flash

The SAMA5D2 provides two Quad Serial Peripheral Interfaces (QSPI).

A QSPI is a synchronous serial data link that provides communication with external devices in Master mode.

The QSPI can be used in SPI mode to interface with serial peripherals (such as ADCs, DACs, LCD controllers, CAN controllers and sensors), or in Serial Memory mode to interface with serial Flash memories.

The QSPI allows the system to execute code directly from a serial Flash memory (XIP, or Execute In place, technology) without code shadowing to RAM. The serial Flash memory mapping is seen in the system as other memories (ROM, SRAM, DRAM, etc.).

With the support of the Quad SPI protocol, the QSPI allows the system to use high-performance serial Flash memories which are small and inexpensive, instead of larger and more expensive parallel Flash memories.

The figure below illustrates the implementation of a QSPI Flash memory.

Figure 3-18. QSPI Serial Flash

SAMA5D2-PTC-EK

Board Components

A jumper (JP13) is used to disable the QSPI Flash.

Table 3-5. SPI and QSPI Signal Descriptions

PIO Signal Name Shared PIO Signal Description

PA14 SPI0_SPCK – SPI clock

PA15 SPI0_MOSI – Master out - Slave in

PA16 SPI0_MISO – Master in - Slave out

PA17 SPI0_NPCS0 – Chip Select

– – – –

PA22 QSPI0_SCK SDMMC1-NAND Flash QSPI clock

PA23 QSPI0_CS NAND Flash Chip Select

DS50002709B-page 18

...........continued

BOOT_DIS

QSPI Flash CS

SPI Flash CS

QSPI0_CS_PA23

SPI0_CS0_PA17

GND_POWER

VDD_3V3

SPI0_NPCS0_PA17

QSPI0_NPCS_PA23

DISABLE_BOOT

C116 100nF

VCC

GND

U11

NL17SZ126DFT2G

1

2

3

4

5

VCC

GND

U12

NL17SZ126DFT2G

1

2

3

4

5

R184 10K

C117 100nF

R185 10K

R178 10K

CAUTION

PIO Signal Name Shared PIO Signal Description

PA24 QSPI0_IO0 NAND Flash Data0

PA25 QSPI0_IO1 NAND Flash Data1

PA26 QSPI0_IO2 NAND Flash Data2

PA27 QSPI0_IO3 NAND Flash Data3

3.2.8.3 CS Disable

On-board push button PB2 controls the selection (CS#) of the bootable memory components (QSPI and serial Flash) using a non-inverting 3-state buffer.

Figure 3-19. CS Disable

SAMA5D2-PTC-EK

Board Components

The rule of operation is:

• PB2 (DISABLE_BOOT) and PB3 (RESET) pressed = booting from QSPI or optional serial Flash is disabled.

Refer to the SAMA5D2 Series datasheet for more information on standard boot strategies and sequencing.

3.2.8.4 Serial EEPROM with Unique MAC Address

The SAMA5D2-PTC-EK board embeds one Microchip 24AA02E48 I²C serial EEPROM connected on the TWI1 interface.

The TWI interface is I2C-compatible and similarly uses only two lines, namely serial data (SDA) and serial clock (SCL). According to the standard, the TWI clock rate is limited to 400 kHz in Fast mode and 100 kHz in Normal mode, but configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies. The TWI is used in Master mode.

The 24AA02E48 features 2048 bits of Serial Electrically-Erasable Programmable Read-Only Memory (EEPROM) organized as 256 words of eight bits each and is accessed via an I2C-compatible (2-wire) serial interface. In addition, the 24AA02E48 incorporates an easy and inexpensive method to obtain a globally unique MAC or EUI address (EUI-48™).

The EUI-48 addresses can be assigned as the actual physical address of a system hardware device or node, or it can be assigned to a software instance. These addresses are factory-programmed by Microchip and guaranteed unique. They are permanently write-protected in an extended memory block located outside the standard 2-Kbit memory array.

The EEPROM device is used as a “software label” to store board information such as chip type,

manufacturer name and production date, using the last two 16-byte blocks in memory. The information contained in these blocks should not be modified.

DS50002709B-page 19

Table 3-6. EEPROM PIOs Signal Descriptions

TWD1 TWCK1

GND_POWER

VDD_3V3

GND_POWER

TWD1_PC6

TWCK1_PC7

C118 100nF C0402

R188 10K R0402

U15

24AA02E48 8MA2

A0

1

A1

2

A2

3

GND

4

SDA

5

SCL

6

WP

7

VCC

8

(MCI0_C D)

(MCI0_WP)

(MCI0_DA1) (MCI0_DA0)

(MCI0_CK)

(MCI0_CD A) (MCI0_DA3) (MCI0_DA2)

(MCI0_DA4) (MCI0_DA5)

(MCI0_DA7)

(MCI0_DA6)

GND_POWER

VDDSDHC

VDD_3V3

SDMMC0_CK_PA0

SDMMC0_CMD_PA1

SDMMC0_DAT1_PA3

SDMMC0_DAT2_PA4

SDMMC0_DAT3_PA5

SDMMC0_DAT4_PA6 SDMMC0_DAT5_PA7 SDMMC0_DAT6_PA8 SDMMC0_DAT7_PA9

SDMMC0_WP_PA12

SDMMC0_CD_PA13

SDMMC0_DAT0_PA2

R154 0R R0402

R169 10k R0402

R167 68k R0603

R173 10k R0402

C110 10uF

C0603 R161 68k R0603

R155 68k R0603

R163 68k R0603

J6

7SDMM-B0-2211 con_kingconn_7sdmm_2211

8

5

7 6

4 3 2 1 9

14

15

16

13 12 11 10

R165 68k R0603

R171 0R

R0402

R157 68k R0603

R172 10k R0402

C111 100nF

C0402

R158 68k R0603

R159 68k R0603

PIO Signal Name Shared Signal Description

PC6 TWD1 XPRO TWI Data

PC7 TWCL1 XPRO TWI Clock

The figure below illustrates the implementation for the EEPROM.

Figure 3-20. EEPROM 24AA02E48

3.2.9 Secure Digital Multimedia Card (SDMMC) Interface

The SD (Secure Digital) Card is a non-volatile memory card format used as a mass storage memory in mobile devices.

SAMA5D2-PTC-EK

Board Components

3.2.9.1 Secure Digital Multimedia Card (SDMMC) Controller

The SAMA5D2-PTC-EK board has two Secure Digital Multimedia Card (SDMMC) interfaces that support the MultiMedia Card (e.MMC) Specification V4.41, the SD Memory Card Specification V3.0, and the SDIO V3.0 specification. It is compliant with the SD Host Controller Standard V3.0 Specification.

• The SDMMC0 interface is connected to a standard SD card interface.

• The SDMMC1 interface is connected to a microSD card interface.

3.2.9.2 SDMMC0 Card Connector

A standard MMC/SD card connector, connected to SDMMC0, is mounted on the top side of the board. The SDMMC0 communication is based on a 12-pin interface (clock, command, data (8) and power lines (2)). A card detection switch is included.

The figure below illustrates the implementation for the SDMMC0 interface.

Figure 3-21. SDMMC0 Standard SD Socket

DS50002709B-page 20

Figure 3-22. Standard SD Socket J6 Location

SAMA5D2-PTC-EK

Board Components

The table below describes the pin assignment of SD/MMC connector J6.

Table 3-7. Standard SD Socket J6 Pin Assignment

Pin No Signal Name Signal Description

1 MCI0_DA3 SDMMC0_DAT3_PA5

2 MCI0_CDA SDMMC0_CMD_PA1

3 GND GND

4 VCC VDDSDHC (3.3V or 1.8V)

5 MCI0_CK SDMMC0_CK_PA0

6 MCI0_CD SDMMC0_CD_PA13 (card detect)

7 MCI0_DA0 SDMMC0_DAT0_PA2

8 MCI0_DA1 SDMMC0_DAT1_PA3

9 MCI0_DA2 SDMMC0_DAT2_PA4

10 MCI0_DA4 SDMMC0_DAT4_PA6

11 MCI0_DA5 SDMMC0_DAT5_PA7

12 MCI0_DA6 SDMMC0_DAT6_PA8

13 MCI0_DA7 SDMMC0_DAT7_PA9

14 MCI0_WP SDMMC0_WP_PA12

DS50002709B-page 21

...........continued

GND_POWER

VDD_3V3

VDDSDHC1V8

VDDSDHC

SDMMC0_VDDSEL_PA11

U9

ADG849YKSZ-REEL SC70

S2

6

S1

4

IN

1

GND

3

D

5

VDD

2

R151 DNP

R0402

R150 10k R0402

R152 DNP

R0402

C107 100nF C0402

(MCI1_DA1) (MCI1_DA0)

(MCI1_CK)

(MCI1_CD A) (MCI1_DA3) (MCI1_DA2)

(MCI1_C D)

GND_POWER

VDD_3V3

SDMMC1_CK_PA22

SDMMC1_CD_PA30

SDMMC1_CMD_PA28

SDMMC1_DAT1_PA19 SDMMC1_DAT0_PA18

SDMMC1_DAT2_PA20

SDMMC1_DAT3_PA21

R160 10k R0402

R162 68k R0603

R170 10k R0402

R164 68k R0603

R166 68k R0603

R168 68k R0603

C109

100nF C0402

C108 10uF C0603

SW1

SW2

J7

PJS008-2120-0 Micro_SD_PJS008

8

5

7 6

4 3 2 1

9

13

12

11

10

14

Pin No Signal Name Signal Description

15 GND GND

16 GND GND

3.2.9.3 SDMMC0 VDDHC Voltage Switching

The board uses an ADG849 to switch the power line VDDSDHC_3V3 or VDDSDHC_1V8 through the command line SDMMC0_VDDSEL_PA11.

Figure 3-23. SDMMC0 VDDSDHC Voltage Switching

SAMA5D2-PTC-EK

Board Components

Table 3-8. SDMMC1 Power Command

PIO Signal Name Signal Description

PA11 SDMMC0_VDDSEL Selects 3.3V or 1.8V

3.2.9.4 SDMMC1 Card Connector

A microSD card connector, connected to SDMMC1, is mounted on the top side of the board. The SDMMC1 communication is based on a 9-pin interface (clock, command, card detect, four data and power lines). A card detection switch is included. The microSD connector can be used to connect any microSD card for mass storage.

Figure 3-24. SDMMC1 microSD Socket

DS50002709B-page 22

Figure 3-25. microSD Socket J7 Location

SAMA5D2-PTC-EK

Board Components

The table below describes the pin assignment of microSD connector J7.

Table 3-9. microSD Socket J7 Pin Assignment

Pin No Signal Name PIO Shared Signal Description

1 SDMMC1_DAT2 PA20 – Data bit 2

2 SDMMC1_DAT3 PA21 – Data bit 3

3 SDMMC1_CDA PA28 – Command

4 VCC – – 3.3V supply voltage

5 SDMMC1_CK PA22 – Clock

6 GND – – Common ground

7 SDMMC1_DAT0 PA18 – Data bit 0

8 SDMMC1_DAT1 PA19 – Data bit 1

9 SW1 GND – Not used

10 SDMMC1_CD PA30 – Card detection switch

11 GND – – Common ground

DS50002709B-page 23

...........continued

top/bo t

ETH_LED0

TX+

ETH_XI

ETH_XO

ETH_LED1

TX-

RX+

RX-

GND_POWER

VDDA_3V3

VDD_3V3

ETH_INT_PB24

ETH_GTXCK_PB14

ETH_GTXEN_PB15

ETH_GRXDV_PB16 ETH_GRXER_PB17

ETH_GRX0_PB18

ETH_GRX1_PB19

ETH_GTX0_PB20

ETH_GTX1_PB21

ETH_GMDC_PB22 ETH_GMDIO_PB23

NRST

R200 10K R0402

R198 1K R0402

R202

10K

R0402

U17

KSZ8081RNB qfn32_1p5h

RXC/B-CAST_OFF

19

CRS/CONFIG1

29

COL/CONFIG0

28

TXD1

25

TXD0

24

TXEN

23

RXD3/PHYAD0

13

RXD2/PHYAD1

14

RXD1/PHYAD2

15

RXD0/DUPLEX

16

RXDV/CONFIG2

18

RXER/ISO

20

MDC

12

MDIO

11

INTRP/NAND

21

VDDA_3V3

3

VDDIO

17

RESET

32

TXP

7

TXM

6

RXP

5

RXM

4

VDD_1V2

2

GND

1

PADDLE

33

TXC

22

TXD2

26

TXD3

27

REXT

10

XO

8

XI

9

LED0/NWAYEN

30

LED1/SPEED

31

R193 10K R0402

R197 1K R0402

C130 100nF C0402

R192 10K R0402

C128 10uF C0603

R199 10K R0402

C129 100nF C0402

R203 10K R0402

R204

10K

R0402

C123 2.2uF

C0603

C127 10uF C0603

C124 100nF

C0402

R205

10K

R0402

L19 BLM18PG181SN1D

R0603

1 2

R206

10K

R0402

R194 6.49K 1%

R0402

R196 0R

R0402

R201

10K

R0402

Pin No Signal Name PIO Shared Signal Description

12 GND – – Common ground

13 GND – – Common ground

14 GND – – Common ground

3.2.10 Communication Interfaces

The SAMA5D2-PTC-EK board is equipped with Ethernet and USB host/device communication interfaces. This section describes the signals and connectors related to the ETH and USB communication interfaces.

3.2.10.1 Ethernet 10/100 (GMAC) Port

The SAMA5D2-PTC-EK board features a Micrel PHY device (KSZ8081) operating at 10/100 Mb/s. The board supports RMII interface modes. The Ethernet interface consists of two pairs of low-voltage differential pair signals designated from GRX± and GTX± plus control signals for link activity indicators. These signals can be used to connect to a 10/100 Base-T RJ45 connector integrated on the SAMA5D2-PTC-EK board.

An individual 48-bit MAC address (Ethernet hardware address) is allocated to each product. This number is stored in the Microchip 24AA02E48 I2C serial EEPROM (refer to Serial EEPROM with Unique MAC Address).

Additionally, for monitoring and control purposes, a LED functionality is carried on the RJ45 connectors to indicate activity, link, and speed status.

For more information about the Ethernet controller device, refer to the Micrel KSZ8081RN controller manufacturer's datasheet.

Figure 3-26. Ethernet Interface

SAMA5D2-PTC-EK

Board Components

Table 3-10. Ethernet PHY 10/100 Signal Descriptions

PIO Signal Name Shared Signal Description

PB14 ETH_GTXCK _ Transmit clock

PB15 ETH_GTXEN _ Transmit enable

PB16 ETH_GRXDV _ Receive data valid

DS50002709B-page 24

LINK

ACT

ETH_LED0

TX+

ETH_LED1

RX-

RX+

TX-

EARTH_ETH

GND_ETH

VDD_3V3

R190 510R

R0402

C122 100nF C0402

C121 100nF C0402

1

2

3

6

4

5

7

8

75

75 75

1nF

TD+

TD-

CT

NC

RD-

CT

TX+

TX-

RX+

RX-

RD+

Left Green LED

Right yellow LED

J8 13F-64GYD2PL2NL

rj45_13f-64gy_P12_4

1

2

7

8

3

6

5

4

9

10

11

12

13 14

15 16

R189 510R

R0402

SAMA5D2-PTC-EK

...........continued

PIO Signal Name Shared Signal Description

PB17 ETH_GRXER _ Receive error

PB18 ETH_GRX0 _ Receive data 0

PB19 ETH_GRX1 _ Receive data 1

PB20 ETH_GTX0 _ Transmit data 0

PB21 ETH_GTX1 _ Transmit data 1

PB22 ETH_GMDC _ Management data clock

PB23 ETH_GMDIO _ Management data in/out

PB24 ETH_GTX_INT _ Interrupt (open drain)

Figure 3-27. Ethernet PHY Connector J8

Board Components

DS50002709B-page 25

Figure 3-28. Ethernet RJ45 Connector J8 Location

SAMA5D2-PTC-EK

Board Components

The table below describes the pin assignment of Ethernet connector J8.

Table 3-11. Ethernet RJ45 Connector J8 Pin Assignment

Pin No Signal Name Signal Description

1 TX+ Transmit

2 TX- Transmit

3 RX+ Receive

4 Decoupling capacitor –

5 Decoupling capacitor –

6 RX- Receive

7 NC –

8 EARTH / GND Common ground

9 ACT LED LED activity

10 ACT LED LED activity

11 LINK LED LED link connection

12 LINK LED LED link connection

13 EARTH / GND Common ground

14 EARTH / GND Common ground

DS50002709B-page 26

...........continued

Pin No Signal Name Signal Description

15 NC –

16 NC –

3.2.10.2 USB Host/Device A, B

The USB (Universal Serial Bus) is a hot-pluggable general-purpose high-speed I/O standard for computer peripherals. The standard defines connector types, cabling, and communication protocols for interconnecting a wide variety of electronic devices. The USB 2.0 Specification defines data transfer rates as high as 480 Mbps (also known as High Speed USB). A USB host bus connector uses 4 pins: a power supply pin (5V), a differential pair (D+ and Dpins) and a ground pin.

The SAMA5D2-PTC-EK board features three USB communication ports named USB-A to USB-C:

• USB-A device interface – One USB device standard micro-AB connector. – This port has a VBUS detection function made through the R148-R149 resistor bridge. – The USB-A port is used as a primary power source and as a communication link for the board, and derives

power from the PC over the USB cable. In most cases, this port is limited to 500 mA.

• USB-B (host port B high- and full-speed interface) – One USB host type A connector. – The USB-B host port is equipped with a 500 mA high-side power switch to enable powering devices

connected to it.

• UBC-C (High-Speed Inter-Chip/HSIC port) – One USB high-speed host port with an HSIC interface. – The port is connected to a single 2-pin jumper.

SAMA5D2-PTC-EK

Board Components

DS50002709B-page 27

3.2.10.3 USB-A Interface

GND_POWER

EARTH_USB_A

GND_POWER

VBUS_USBA

USBA_VBUS_5V_PB11

USBA_DP

USBA_DM

C103 20pF C0402

VBUS

SHD

DM

DP

ID

GND

J4

MicroUSB AB Connector

USBMICRO5_6A

1 2 3 4 5

8

6

11

7

9

10

R149 200K R0402

R148 100K

R0402

Figure 3-29. USB-A Type Micro-AB Connector J4 Location

SAMA5D2-PTC-EK

Board Components

3.2.10.4 USB-A VBUS Detection

The USB-A port (J4) features a VBUS detection function provided by the R148-R149 resistor bridge.

The figure below shows the USB implementation on the USBA port.

Figure 3-30. USB-A Power and VBUS Detection

Table 3-12. USB-A PIO Signal Descriptions

PIO Signal Name Shared Signal Description

PB11 USBA_VBUS_5V – VBUS insertion detection

DS50002709B-page 28

3.2.10.5 USB-B Interface

USBB_VBUS_5V

GND_POWER

EARTH_USB_B

USBB_DP

USBB_DM

A

J3 Single USB Type A USB4_2AL

VBUS

1

DM

2

DP

3

GND

4

SH1

5

SH2

6

The figure below shows the USB implementation on the USB-B port.

Figure 3-31. USB-B Interface

Figure 3-32. USB-B Type A Connector J3 Location

SAMA5D2-PTC-EK

Board Components

Table 3-13. USB-B PIO Signal Descriptions

PIO Signal Name Shared Signal Description

PB12 USBB_EN_5V – Power switch enable (active high)

PB13 USBB_OVCUR – Indicates overcurrent (open drain)

3.2.10.5.1 USB-B Power Switch

The USB-B Host port is equipped with a 500 mA high-side power switch for self-powered and bus-powered applications. If the client device is bus-powered, the carrier can supply a 5V, 500mA power to the client device. The USBB_EN_5V_PB12 signal controls the power switch and current limiter, the Micrel MIC2025, which in turn supplies power to a bus-powered client device. Per the USB specification, bus-powered USB 2.0 devices are limited to a

DS50002709B-page 29

maximum of 500 mA. The MIC2025 limits the current and indicates an overcurrent with the USBB_OVCUR_PB13

HSIC_DATA HSIC_STRB

J5

DNP

1 2

signal.

The table below describes the pin assignment of the USB-A and USB-B connectors.

Table 3-14. USB-A and USB-B Connector Signal Descriptions

3.2.10.6 HSIC

High-Speed Inter-Chip (HSIC) is a standard for USB chip-to-chip interconnect with a 2-signal (strobe, data) source synchronous serial interface using 240 MHz DDR signaling to provide only high-speed 480 Mbps data rate.

The interface operates at high speed, 480 Mbps, and is fully compatible with existing USB software stacks. It meets all data transfer needs through a single unified USB software stack.

The HSIC interface is not used on the board and is connected to two-point jumper J5 (not mounted).

Figure 3-33. HSIC Interface

SAMA5D2-PTC-EK

Board Components

Pin No Signal Name Signal Description

1 VBUS 5V power

2 DM Data minus

3 DP Data plus

4 ID On-the-go identification

5 GND Common ground

3.3 External Interfaces

3.3.1 LCD TFT Interface

This section describes the signals and connectors related to the LCD interface.

3.3.1.1 LCD Interface

The SAMA5D2-PTC-EK board provides a connector with 18 bits of data and control signals to the LCD interface. Other signals are used to control the LCD and are available on connector J16: TWI, SPI, two GPIOs for interrupt, 1wire and power supply lines.

This connector is used to connect LCD display series 43xx or 70xx from PDA.

3.3.1.2 LCD Expansion Header

J16 is a 1.27-mm pitch, 50-pin header. It gives access to the LCD signals.

DS50002709B-page 30

Figure 3-34. LCD Expansion Header Interface

GND_POWER

VDD_3V3VDD_MAIN_5V

LCD_D2_PC10 LCD_D3_PC11

LCD_D4_PC12 LCD_D5_PC13 LCD_D6_PC14 LCD_D7_PC15

LCD_D10_PC16 LCD_D11_PC17

LCD_D12_PC18 LCD_D13_PC19 LCD_D14_PC20 LCD_D15_PC21

LCD_D18_PC22 LCD_D19_PC23

LCD_D20_PC24 LCD_D21_PC25 LCD_D22_PC26 LCD_D23_PC27

LCD_PCLK_PD0 LCD_VSYNC_PC30 LCD_HSYNC_PC31

LCD_DE_PD1

LCD_EN_PC29

LCD_IRQ1_PC9 LCD_IRQ2_PD2

LCD_PWM_PC28

SPI_CS_PB31

SPI_SCK_PB30

SPI_MISO_PB29

SPI_MOSI_PB28

TWI_SCL_PB29

TWI_SDA_PB28

NRST

SPI_CS_PB31

R230

DNP R0603

R231 0R R0603

R234

100R-1% R0402

J16

XF2M-5015-1A FPC50-0p5mm

ID

1

GND1

2

D0

3

D1

4

D2

5

D3

6

GND2

7

D4

8

D5

9

D6

10

D7

11

GND3

12

D8

13

D9

14

D10

15

D11

16

GND4

17

D12

18

D13

19

D14

20

D15

21

GND5

22

D16

23

D17

24

D18

25

D19

26

GND6

27

D20

28

D21

29

D22

30

D23

31

GND7

32

PCLK/CMD

33

VSYNC/CS

34

HSYNC/WE

35

DE/RE

36

SPI_SCK

37

SPI_MOSI

38

SPI_MISO

39

SPI_CS

40

ENABLE

41

TWI_SDA

42

TWI_SCL

43

IRQ1

44

IRQ2

45

PWM

46

RESET

47

VCC1

48

VCC2

49

GND8

50

SAMA5D2-PTC-EK

Board Components

3.3.1.3 LCD Power

In order to operate correctly with various LCD modules, two voltage lines are available: 3.3V and 5VCC (default). The selection is made with 0R resistors R230 and R231.

DS50002709B-page 31

3.3.1.4 LCD Connector JX

Figure 3-35. LCD Connector J16 Location

SAMA5D2-PTC-EK

Board Components

The table below describes the pin assignment of LCD FPC connector J16.

Table 3-15. LCD Connector J16 Signal Descriptions

Pin No Signal PIO Signal RGB Interface Function

1 ID PB31 _ ID LCD module

2 GND – GND GND

3 LCDDAT0 – D0 –

4 LCDDAT1 – D1 –

5 LCDDAT2 PC10 D2 Data line

6 LCDDAT3 PC11 D3 Data line

7 GND – GND GND

8 LCDDAT4 PC12 D4 Data line

9 LCDDAT5 PC13 D5 Data line

10 LCDDAT6 PC14 D6 Data line

11 LCDDAT7 PC15 D7 Data line

12 GND – GND GND

DS50002709B-page 32

SAMA5D2-PTC-EK

...........continued

Pin No Signal PIO Signal RGB Interface Function

13 LCDDAT8 – D8 –

14 LCDDAT9 – D9 –

15 LCDDAT10 PC16 D10 Data line

16 LCDDAT11 PC17 D11 Data line

17 GND GND GND GND

18 LCDDAT12 PC18 D12 Data line

19 LCDDAT13 PC19 D13 Data line

20 LCDDAT14 PC20 D14 Data line

21 LCDDAT15 PC21 D15 Data line

22 GND – GND GND

23 LCDDAT16 – D16 –

24 LCDDAT17 – D17 –

25 LCDDAT18 PC22 D18 Data line

Board Components

26 LCDDAT19 PC23 D19 Data line

27 GND – GND GND

28 LCDDAT20 PC24 D20 Data line

29 LCDDAT21 PC25 D21 Data line

30 LCDDAT22 PC26 D22 Data line

31 LCDDAT23 PC27 D23 Data line

32 GND – GND GND

33 LCDPCK PD0 PCLK Pixel clock

34 LCDVSYNC PC30 VSYNC/CS Vertical sync

35 LCDHSYNC PC31 HSYNC/WE Horizontal sync

36 LCDDEN PD1 DATA_ENABLE Data enable

37 SPI_SPCK PB30 SPI_SCK –

38 SPI_MOSI PB28 SPI_MOSI (Shared with TWI)

39 SPI_MISO PB29 SPI_MISO (Shared with TWI)

40 SPI_NPCS0 PB31 SPI_CS –

41 LCDDISP PC29 ENABLE Display enable signal

42 TWD PB28 TWI_SDA I2C data line (maXTouch)

43 TWCK PB29 TWI_SCL I2C clock line (maXTouch)

44 GPIO PC9 IRQ1 maXTouch interrupt line

45 GPIO PD2 IRQ2 Interrupt line for other I2C devices

46 LCDPWM PC28 PWM Backlight control

47 RESET – RESET Reset for both display and maXTouch

DS50002709B-page 33

...........continued

LED

VDD_3V3

GND_POWER

LED_RED_PB10

LED_GREEN_PB8

LED_BLUE_PB6

R240 1K

R0402

R182 100R-1%

R0402

R183 100R-1%

R0402

R244 10K

Q7 BSS138 SOT23_123

1

3

2

R181 100R-1%

R0402

D4

CLV1A-FKB-CJ1M1F1BB7R4S3

Red

1

Green

4

Blue

3

Anode

2

R241 1K

R0402

R239 2.2K-1%

R0402

Q5 BSS138 SOT23_123

1

3

2

R243 10K

Q6 BSS138 SOT23_123

1

3

2

Pin No Signal PIO Signal RGB Interface Function

48 Main_5V/3.3V VCC VCC 3.3V or 5V supply (0R)

49 Main_5V/3.3V VCC VCC 3.3V or 5V supply (0R)

50 GND – GND GND

3.3.2 RGB LED

The SAMA5D2-PTC-EK board features one RGB LED which can be controlled by the user. The three LED cathodes are controlled via GPIO PWM or timer/counter pins.

Figure 3-36. RGB LED Indicators

SAMA5D2-PTC-EK

Board Components

Table 3-16. RGB LED PIOS

3.4 Debugging Capabilities

The SAMA5D2-PTC-EK includes two main debugging interfaces to provide debug-level access to the SAMA5D2:

• One UART through USB J-Link-CDC

• Two JTAG interfaces, one connected directly to the MPU using connector J2 and one through the J-Link-OB interface USB port J9

3.4.1 Debug JTAG

This section describes the signals and connectors related to the JTAG interface.

A 10-pin JTAG header is provided on the SAMA5D2-PTC-EK board to facilitate software development and debugging using various JTAG emulators. The interface signals have a voltage level of 3.3V.

Signal PIO Function

LED_RED PB10 TIOB3

LED_GREEN PB8 PWML3

LED_BLUE PB6 PWML2

DS50002709B-page 34

Figure 3-37. JTAG Interface

GND_POWER

VDD_3V3

GND_POWER

NRST

CON_JTAG_Pin2 CON_JTAG_Pin4 CON_JTAG_Pin6 CON_JTAG_Pin8RTCKIN

R140 100K R0402

R236 10K R0402

R142 100K R0402

R143 100R-1% R0402

R141 100K R0402

R138 DNP

R0402

J2

Header 2X5 FTSH-105-01-F-DV-P-TR

1

2

3

4

5

6

7

8

9

10

Figure 3-38. JTAG Connector J2 Location

SAMA5D2-PTC-EK

Board Components

The table below describes the pin assignment of JTAG connector J2.

Table 3-17. JTAG/ICE Connector J2 Pin Assignment

Pin No Signal Name Signal Description

1 VTref. 3.3V power This is the target reference voltage (main 3.3V).

2 TMS TEST MODE SELECT JTAG mode set input into target CPU

3 GND Common ground

DS50002709B-page 35

...........continued

Pin No Signal Name Signal Description

TCK TEST CLOCK - Output timing signal, for

4

synchronizing test logic and control register access

5 GND Common ground

TDO JTAG TEST DATA OUTPUT - Serial data

6

input from the target

RTCK - Input return test clock signal from the

7

target

TDI TEST DATA INPUT - Serial data output line,

8

sampled on the rising edge of the TCK signal

9 GND Common ground

10 nRST RESET Active-low reset signal. Target CPU reset signal.

3.4.2 Embedded Debugger (J-Link-OB) Interface

The SAMA5D2-PTC-EK includes a built-in SEGGER J-Link-On-Board device. The functionality is implemented with an ATSAM3U4C microcontroller in an LFBGA100 package. The ATSAM3U4C provides the functions of JTAG and a bridge USB/Serial debug port (CDC). One two-colored LED (D6) mounted near the SAM3 chip (U20) shows the status of the J-Link-On-Board device.

J-Link-OB-ATSAM3U4C was designed in order to provide an efficient, low-cost, on-board alternative to the standard J-Link.

The USB J-Link-OB port is used as a secondary power source and as a communication link for the board, and derives power from the PC over the USB cable. This port is limited in most cases to 500 mA. A single PC USB port is sufficient to power the board.

SAMA5D2-PTC-EK

Board Components

JTAG clock signal into target CPU

JTAG data output from target CPU

Some targets with a slow system clock must synchronize the JTAG inputs to internal clocks. In the present case, such synchronization is unneeded and TCK is merely looped back into RTCK.

JTAG data input into target CPU

DS50002709B-page 36

Figure 3-39. J-Link-OB Interface

EDBG_USB_DP

EDBG_USB_DM

ENSPI

ERASE_3U

TDI_3U TDO_3U TCK_3U TMS_3U

NRST_3U

TRSTIN TRSTOUT

TRESIN TRESOUT

TDIIN

TMSIN

TCKOUT TMSOUT

TDIOUT TDOIN TCKIN ENSPI TCKOUT PA25_3U PA26_3U

LED2_3U

LED1_3U

EDBG_XIN

RX_3U TX_3U

EARTH_USB_EDBG

VDD_3V3_3U

VDD_OUT_3U

VDD_3V3_3U

GND_POWER

VDD_3V3_3U

GND_POWER

VDD_3V3_3U

GND_POWER

VDD_3V3_3U

VBUS_JLINK

VDD_3V3_3U

GND_POWER

RTCKIN

R210 100R-1% R0402

R211 39R R0402

R209

100R-1% R0402

R215

100K R0402

VBUS

SHD

DM

DP

ID

GND

J9

MicroUSB AB Connector

USBMICRO5_6A

1 2 3 4 5

8

6

11

7

9

10

R212 39R R0402

C156 100nF C0402

R208

10K R0402

R245

0R

R214

6.8K-1% R0402

C136 10nF

C0402

D5 PMEG6010CEGWX

sod123

Y4

ASE-12.000MHz-LC-T

NC

1

VCC4Out

3

GND

2

U20

ATSAM3U4CA-CU TFBGA100

VBG

A1

XIN

A2

XOUT

A3

PB17

A4

PB21A5PB23

A6

TCK/SWCLK

A7

VDDIN

A8

VDDOUT

A9

XIN32

A10

VDDCORE_1

B1

GNDUTMI

B2

VDDUTMI

B3

PB10

B4

PB18

B5

PB24

B6

NRST

B7

TDO/TRACESWO

B8

TDI

B9

XOUT32

B10

DFSDP

C1

DHSDP

C2

GNDPLL

C3

PB14

C4

PB19

C5

PB22

C6

TMS/SWDIO

C7

NRSTB

C8

JTAGSEL

C9

VDDBU

C10

DFSDM

D1

DHSDM

D2

VDDPLL

D3

VDDCORE_2

D4

PB20

D5

ERASE

D6

TST

D7

FWUP

D8

PA11/PGMD3

D9

PA12/PGMD4

D10

PA29

E1

GND_1

E2

PA28

E3

PB9

E4

GNDBU

E5

VDDIO_3

E6

VDDCORE_3

E7

PA10/PGMD2

E8

PA9/PGMD1

E9

PA8/PGMD0

E10

PB1

F1

PB12

F2

VDDIO_1

F3

PA31

F4

VDDIO_2

F5

GND_2

F6

PB16

F7

PA6/PGMM2

F8

VDDCORE_6

F9

PA7/PGMM3

F10

PB11

G1

PB2G2PB0

G3

PB13

G4

VDDCORE_5

G5

GND_3

G6

PB15

G7

PA3/PGMNVALID

G8

PA5/PGMM1

G9

PA4/PGMM0

G10

VDDCORE_4

H1

PB5

H2

PA27

H3

PA22/PGMD14

H4

PA13/PGMD5

H5

PA15/PGMD7

H6

PA18/PGMD10

H7

PA24

H8

PA1/PGMRDY

H9

PA2/PGMNOE

H10

PB6J1PB8

J2

ADVREF

J3

PA30

J4

PB3

J5

PA16/PGMD8

J6

PA19/PGMD11

J7

PA21/PGMD13

J8

PA26

J9

PA0/PGMNCMD

J10

PB7

K1

VDDANA

K2

GNDANA

K3

AD12BVREF

K4

PB4

K5

PA14/PGMD6

K6

PA17/PGMD9

K7

PA20/PGMD12

K8

PA23/PGMD15

K9

PA25

K10

C137 10pF

C0402

C132 10nF

C0402

R213

DNP R0402

VDD_3V3_3U

R216 150R-1%

R0402

R217 150R-1%

R0402

D6

KPTB-1615

Green

4

1

RED

2

3

LED1_3U

LED2_3U

ERASE_3U

VDD_3V3_3U

JP11

Header 1X2

1

2

JTAG-OB disable

JTAG-CDC disable

PA25_3U

PA26_3U

VDD_3V3_3U

GND_POWER

VDD_3V3_3U

JP9

Header 1X2

1

2

R224 10K R0402

R225 10K R0402

JP10

Header 1X2

1

2

SAMA5D2-PTC-EK

Board Components

3.4.2.1 Disabling J-Link-OB (ATSAM3U4C)

Jumper JP10 disables the J-Link-OB-ATSAM3U4C JTAG functionality. When the jumper is installed, it grounds pin 26 of the ATSAM3U4C that is normally pulled high. A quad analog switch is used to select the JTAG interface.

• Jumper JP10 not installed: J-Link-OB-ATSAM3U4C is enabled and fully functional.

• Jumper JP10 installed: J-Link-OB-ATSAM3U4C is disabled and an external JTAG controller can be used through the 10-pin JTAG port J2.

Jumper JP10 disables only the J-Link functionality. The debug serial com port that is emulated through a Communication Device Class (CDC) of the same USB connector remains operational (if JP9 is open).

Figure 3-40. Enabling/Disabling J-Link-OB and J-Link-CDC

DS50002709B-page 37

Figure 3-41. JTAG Switch

TDIOUT

TDIIN

PA26_3U

TDOIN

TMSIN

TMSOUT

TCKIN

TCKOUT

VDD_3V3_3U

GND_POWER

JTAG_TCK_PD27

JTAG_TMS_PD30

JTAG_TDI_PD28

CON_JTAG_Pin2

CON_JTAG_Pin4

CON_JTAG_Pin8

JTAG_TDO_PD29

CON_JTAG_Pin6

R223 150R-1%

R0402

U22

NLAS3899BMNTWG WQFN-16

NCA

1

COMA

16

NOA

15

NOB

3

COMB

4

NCB

5

ABIN

2

NOC

7

COMC

8

NCC

9

CDIN

10

NOD

11

COMD

12

NCD

13

VCC

14

GND

6

R222 150R-1%

R0402

R218 150R-1%

R0402

3.4.3 Hardware UART via CDC

In addition to the J-Link-OB functionality, the ATSAM3U4C microcontroller provides a bridge to a debug serial port (UART DBGU) of the SOM's processor. The port is made accessible over the same USB connection used by JTAG by implementing Communication Device Class (CDC), which allows terminal communication with the target device.

This feature is enabled only if the SAM3U/PA25 (pin K10) is not grounded. The pin is normally pulled high and controlled by jumper JP9.

• Jumper JP9 not installed: the J-Link-CDC is enabled and fully functional.

• Jumper JP9 installed: the J-Link-CDC device is disabled.

The USB Communications Device Class (CDC) enables conversion of the USB device into a serial communication device. The target device running USB-Device CDC is recognized by the host as a serial interface (USB2COM, virtual COM port) without the need to install a special host driver (since the CDC is standard). All PC software using a COM port work without modifications with this virtual COM port. Under Windows, the device shows up as a COM port; under Linux®, as a /dev/ACMx device. This enables the user to use host software which was not designed to be used with USB, such as a terminal program.

Table 3-18. Debug COM Port PIOs Signal Descriptions

SAMA5D2-PTC-EK

Board Components

PIO Signal Name Shared Signal Description

PB26 URXD0 – Receive data

PB27 UTXD0 – Transmit data

DS50002709B-page 38

Figure 3-42. J-Link-OB and CDC USB Connector J9 Location

SAMA5D2-PTC-EK

Board Components

The table below describes the pin assignment of USB connector J9.

Table 3-19. USB Connector J9 Pin Assignment

Pin No Signal Name Signal Description

1 VBUS 5V power

2 DM Data minus

3 DP Data plus

4 ID Not used

5 GND Common ground

3.4.3.1 Board Edge Connector

This connector is used to upgrade or download code to the ATSAM3U4C microcontroller J-Link-OB.

3.5 PIO Usage on Expansion Connectors

3.5.1 PIOBU Interface

The SAMA5D2-PTC-EK board features eight tamper pins for static or dynamic intrusion detection, UART reception, and two analog pins for comparison.

For a description of intrusion detection, refer to the SAMA5D2 datasheet, chapter "Security Module".

DS50002709B-page 39

Figure 3-43. PIOBU Connector

RXD

PIOBU0

ACN

PIOBU2 PIOBU4 PIOBU6

PIOBU3 PIOBU5

ACP

GND_POWER

R132 0R R0402R127 330R R0402

R130 330R

R0402

R124 330R R0402 R129 330R R0402

R131 0R R0402

R125 330R

R0402

J1 DNP

FTSH-105-01-F-DV-P-TR

1

2 3 4 5

6 7 8 9

10

R126 330R R0402

R128 0R R0402

Figure 3-44. PIOBU Connector J1 Location

SAMA5D2-PTC-EK

Board Components

The table below describes the pin assignment of PIOBU connector J1.

Table 3-20. PIOBU Connector J1 Pin Assignment

3.5.2 mikroBUS Interface

The SAMA5D2-PTC-EK hosts a pair of 8-pin female headers as mikroBus interface. The mikroBUS interface defines the main board sockets and add-on boards used for interfacing microprocessors with integrated modules with proprietary pin configuration and silkscreen markings. The pinout consists of three groups of communication pins (SPI, UART and TWI), four additional pins (PWM, interrupt, analog input and reset) and two power groups (+3.3V and GND on the left, and 5V and GND on the right 1x8 header).

Signal Pin No. Signal

PIOBU0 1 2 PIOBU3

PIOBU2 3 4 PIOBU5

PIOBU4 5 6 RXD

PIOBU6 7 8 ACN

ACP 9 10 GND

DS50002709B-page 40

Figure 3-45. mikroBUS Interface

PD25 RST NPCS0 SPCK MISO MOSI 3V3

PWM INT RX TX SCL SDA

+5v

VDD_3V3

VDD_MAIN_5V

GND_POWER

AN-AD6

NPCS0_PC04

SPCK_PC01

MISO_PC03 MOSI_PC02

PWM_PD20 INT_PD19 RX_PD23 TX_PD24

TWCK0_PD22

TWD0_PD21

MBUS_RST_PC05

JP12 Header 1X2

1

2

J15A

SSQ-108-01-G-S

1 2 3 4 5 6 7 8

J15B

SSQ-108-01-G-S

1 2 3 4 5 6 7 8

R229 DNP

R0402

Figure 3-46. mikroBUS Connector J15 Location

SAMA5D2-PTC-EK

Board Components

The table below describes the pin assignment of mikroBUS1 connector J15.

Table 3-21. mikroBUS Connector J15 Pin Assignment

SAMA5D27

Function PIO PIO Function

MBUS Signal Pin No MBUS Signal

Analog input PD25 AN 1 1 PWM PD20 PWM

Reset PC05 RST 2 2 INT PD19 Interrupt

SPI Chip Select PC04 SPI_NPCS 3 3 UART_RX PD23 UART receive

SPI clock PC01 SPI_SPCK 4 4 UART_TX PD24 UART transmit

SPI MISO PC03 SPI_MISO 5 5 TWI_SCL PD22 TWI clock

SPI MOSI PC02 SPI_MOSI 6 6 TWI_SDA PD21 TWI data

3.3VCC – 3.3V Supply 7 7 5V Supply _ 5VDD

SAMA5D27

DS50002709B-page 41

...........continued

PD16

PD26

PD17

PD11 PD13 PB9 PD15

7CP6CP

PD18 PD17

PC0

PD14

PD12

VDD_3V3

GND_POWER

PTC_YLINE0 PTC_YLINE2

XPRO1_GPIO_PB9

PTC_YLINE4

PTC_YLINE6

PTC_YLINE1 PTC_YLINE3

PTC_YLINE5

PTC_YLINE7 PTC_YLINE6XPRO1_GPIO_PD26

XPRO1_GPIO_PC0

XPRO_PC6 XPRO_PC7

R227 DNP

R226 0R

J11

Header 2X10

1 2 3 4 5 6 7

8

9

10

11

12 13 15 17 19

14

16

18

20

XPRO2_GPIO_PD31

R235 0R

SAMA5D27

SAMA5D2-PTC-EK

Board Components

SAMA5D27

Function PIO PIO Function

GROUND – GND 8 8 GND _ GROUND

3.5.3 XPRO Interface

The SAMA5D2-PTC-EK board hosts two connectors to interface XPRO QT boards. The QTouch Xplained Pro are extension boards that enable evaluation of Self-capacitance and Mutual capacitance modes using the Peripheral Touch Controller (PTC). The boards show how easy it is to design a capacitive touch board solution using the PTC without the need for any external components.

Nevertheless, the PTC IO pins available on XPRO connectors can be used as GPIO pins. Each of these can be configured as an input or output pin according to the PIO peripheral functions.

The GPIO voltage levels depend on the VDDIOP level supported by the SAMA5D2, 3.3V in this case.

Figure 3-47. XPRO EXT1 Connector

Figure 3-48. XPRO EXT1 Connector J11 Location

MBUS Signal Pin No MBUS Signal

The following table describes the pin assignment of XPRO EXT1 connector J11.

DS50002709B-page 42

Table 3-22. XPRO EXT1 Connector J11 Pin Assignment

PD10

PB25

PD4

PD8

PD3

PD6PD5 PD7 PD9

PD31

VDD_3V3

GND_POWER

PTC_XLINE0 PTC_XLINE2 PTC_XLINE4 PTC_XLINE6

XPRO2_GPIO_PB25

PTC_XLINE1 PTC_XLINE3 PTC_XLINE5 PTC_XLINE7 XPRO2_GPIO_PD31

J12

Header 2X10

1

2

3

4

5

6

7

8

9

10

11

12 13 15 17 19

14

16

18

20

R228 0R

R235 0R

XPRO1

SAMA5D2-PTC-EK

Board Components

SAMA5D27

Function PIO PIO Function

XPRO Signal Pin No XPRO Signal

SAMA5D27

– Not used ID 1 2 GND – GROUND

PTC_YLINE0 PD11 ADC(+) 3 4 ADC(-) PD12 PTC_YLINE1

PTC_YLINE2 PD13 GPIO 5 6 GPIO PD14 PTC_YLINE3

GPIO PA10 PWM(+) 7 8 PWM(-) PC0 GPIO

PTC_YLINE4 PD15 IRQ/GPIO 9 10 SPI_SS_B/GPIO PD16 PTC_YLINE5

XPRO_TWD PC6 TWI_SDA 11 12 TWI_SCL PC7 XPRO_TWCK

– – UART_RX 13 14 UART_TX – –

PTC_YLINE6 PD17 SPI_SS_A 15 16 SPI_MOSI PD18 PTC_YLINE7

GPIO PD26 SPI_MISO 17 18 SPI_SCK PD31 or PD17 PTC_YLINE6

GROUND – GND 19 20 3.3VCC – 3.3V Supply

Figure 3-49. XPRO EXT2 Connector

DS50002709B-page 43

Figure 3-50. XPRO EXT2 Connector J12 Location

SAMA5D2-PTC-EK

Board Components

The table below describes the pin assignment of XPRO EXT2 connector J12.

Table 3-23. XPRO EXT2 Connector J12 Pin Assignment

SAMA5D27

Function PIO PIO Function

– Not used ID 1 2 GND – GROUND

PTC_XLINE0 PD3 ADC(+) 3 4 ADC(-) PD4 PTC_XLINE1

PTC_XLINE2 PD5 GPIO 5 6 GPIO PD6 PTC_XLINE3

PTC_XLINE4 PD7 PWM(+) 7 8 PWM(-) PD8 PTC_XLINE5

PTC_XLINE6 PD9 IRQ/GPIO 9 10

– – TWI_SDA 11 12 TWI_SCL PD31 GPIO

– – UART_RX 13 14 UART_TX – –

GPIO PB25 SPI_SS_A 15 16 SPI_MOSI – –

– – SPI_MISO 17 18 SPI_SCK – –

GROUND – GND 19 20 3.3VCC – 3.3V Supply

3.5.4 Miscellaneous PIOB[0-7]

PIOs PB00 to PB07 are available on connector J13 and can be used as GPIO pins. Each of these can be configured as an input or output pin according to the PIO peripheral functions.

XPRO Signal Pin No XPRO Signal

SPI_SS_B/

GPIO

SAMA5D27

PD10 PTC_XLINE7

DS50002709B-page 44

Figure 3-51. PIOs PB[0-7] Connector

VDD_3V3

GND_POWER

PB_PORT_0 PB_PORT_1 PB_PORT_2 PB_PORT_3 PB_PORT_4 PB_PORT_5 PB_PORT_6 PB_PORT_7

J13

PIOB[0-7] connecto

r

1 2 3 4 5 6 7 8 9

10

Figure 3-52. PIOB[0-7] Connector J13 Location

SAMA5D2-PTC-EK

Board Components

The table below describes the pin assignment of PIOs PB[0-7] connector J13.

Table 3-24. PIOs PB[0-7] Connector J13 Pin Assignment

Pin No PIO Signal Name Shared Signal Description

1 – VDD_3V3 – Main 3.3V

2 PB0 GPIO NAND Flash PIO port B

3 PB1 GPIO NAND Flash PIO port B

4 PB2 GPIO NAND Flash PIO port B

5 PB3 GPIO – PIO port B

6 PB4 GPIO – PIO port B

7 PB5 GPIO – PIO port B

8 PB6 GPIO LED_BLUE PIO port B

DS50002709B-page 45

SAMA5D2-PTC-EK

...........continued

Pin No PIO Signal Name Shared Signal Description

9 PB7 GPIO – PIO port B

10 – GND – Common ground

Board Components

DS50002709B-page 46

4. Installation and Operation

4.1 System and Configuration Requirements

The SAMA5D2-PTC-EK requires the following:

• Personal Computer

• USB cable

4.2 Board Setup

Follow these steps before using the SAMA5D2-PTC-EK:

1. Unpack the board, taking care to avoid electrostatic discharge.

2. Check the default jumper settings.

3. Connect the USB Micro-AB cable to connector J9.

4. Connect the other end of the cable to a free port of your PC.

5. Open a terminal (console 115200, N, 8, 1) on your Personal Computer.

6. Reset the board. A startup message appears on the console.

SAMA5D2-PTC-EK

Installation and Operation

DS50002709B-page 47

5. Appendix A. Schematics and Layouts

5

4

3

2

1

D D

C

B B

A

03

02

01

SHEET NAMESHEET

Schematic: A5D2-PTC-EK

08

07

06

05

04

13

12

11

10

09

Power domains

Block Diagram

Title & Revision History

SYSTEM

PIOA&PIOB

DDR2-SDRAM

JLINK-OB

MEMORIES&RGBLED

MPU_POWER

Ethernet_10/100M

PIOC&PIOD

USB&TF

EXT_CONNECTORS

DATE

RevA-20160107

06 Jan 2017

NOITPIRCSEDNOISIVER

Revision History

Init edit

RevA release07-MAR-17 Rev A

RevB

RevB release03-OCT-17 Rev B

RevB

6-DEC-17 RevB Cosmetic changes

Removed erroneous comment in sheet 4

5-jun-19 RevB

RevB

REV

DATEMODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A RevA

1

13

B

XX-XXX-XXZhouB XXX

01) Title & Revision History

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XXZhouB 07-MAR-17

03-OCT-17THR XX-XXX-XXXXXB

06-DEC-17PPnB2

05-JUN-19PPnB3

REV

DATEMODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A RevA

1

13

B

XX-XXX-XXZhouB XXX

01) Title & Revision History

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XXZhouB 07-MAR-17

03-OCT-17THR XX-XXX-XXXXXB

06-DEC-17PPnB2

05-JUN-19PPnB3

REV

DATEMODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A RevA

1

13

B

XX-XXX-XXZhouB XXX

01) Title & Revision History

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XXZhouB 07-MAR-17

03-OCT-17THR XX-XXX-XXXXXB

06-DEC-17PPnB2

05-JUN-19PPnB3

This appendix contains the following schematics and layouts for the SAMA5D2-PTC-EK board:

• Title and Revision History

• Block Diagram

• Power Domains

• MPU Power

• DDR2-SDRAM

• PIOA & PIOB

• PIOC & PIOD

• System

• USB & TF

• Memories & RGB LED

• Ethernet 10/100M

• JLINK-OB

• EXT Connectors

Figure 5-1. Title and Revision History

SAMA5D2-PTC-EK

Appendix A. Schematics and Layouts

DS50002709B-page 48

Figure 5-2. Block Diagram

5

4

3

2

1

D D

C

B

A

USB A OTG

POWER

5V INPUT

USB A,B,C

Reset Force PwrOn

Push Buttons

JTAG JLINK-OB

User LEDs QSPI Flash NAND Flash

PIO

SPI Data Flash

PIO A,B,C,D

Atmel SAMA5D27 Cortex(R)-A5 Processor

XPRO Connectors

5V & 3V3

EBI

2Gb DDR2 SDRAM

Power rails

ANALOG Reference

USB DEVICE

JTAG Connector

Sheet 8

Sheet 13

Sheet 9

5V INPUT

Sheet 12

01 teehS01 teehS

Sheet 5

Sheet 10

Sheet 3

Sheet 8

Sheet 4: MPU_POWER Sheet 5: DDR2-SDRAM Sheet 6: PIOA & PIOB Sheet 7: PIOC & PIOD Sheet 8: SYSTEM

11 teehS01 teehS

Ethernet 10/100M bps

USB B Host

USB C HSIC

QSPI Flash

PTC PORT

Sheet 13

24AA02E48

Sheet 13

LCD CON

USB TO UART

Sheet 09

SDCARD CON

RevB RevB RevB

REV

DATEMODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A R evA

2

13

B

XX-XXX-XXZhouB XXX

02) Block Diagram

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XXZhouB 07-MAR-17

03-OCT-17THR XX-XXX-XXXXXB

06-DEC-17PPnB2

05-JUN-19

PPnB3

REV

DATEMODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A R evA

2

13

B

XX-XXX-XXZhouB XXX

02) Block Diagram

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XXZhouB 07-MAR-17

03-OCT-17THR XX-XXX-XXXXXB

06-DEC-17PPnB2

05-JUN-19

PPnB3

REV

DATEMODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A R evA

2

13

B

XX-XXX-XXZhouB XXX

02) Block Diagram

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XXZhouB 07-MAR-17

03-OCT-17THR XX-XXX-XXXXXB

06-DEC-17PPnB2

05-JUN-19

PPnB3

SAMA5D2-PTC-EK

Appendix A. Schematics and Layouts

DS50002709B-page 49

Figure 5-3. Power Domains

5

4

3

2

1

D D

C

B

A

For DDR2 For MPU

Switching Power lines

(Super)-Capacitor energy storage

POWER SUPPLY VDDBU Power Supply

Fixed output 1V8, 3v3,

Fixed output 1V25

RevB RevB RevB

EN_1

EN_VDD_1V25

STARTB

FPWM#

EN_1

EN_VDD_1V25

VDDHSIC

VDD_3V3

VDD_1V25 VDDCORE

VDDIOP0

VDDIOP2

VDDIOP1

VDDPLLA

VDDUTMIC

VDDIODDR

VDDAUDIOPLL

VDDANA

VDDOSC

VDDUTMII

VDDISC

VDD_1V8

VDD_MAIN_5V

VDDBU

GND_POWER

VDD_3V3

VDD_MAIN_5V

GND_POWER

VDD_3V3VDD_1V8

VDD_MAIN_5V

VDD_1V8

VDD_1V25

VDD_MAIN_5V

GND_POWER GND_POWER

GND_POWER

VDD_MAIN_5V

VDD_3V3

VDDSDHC1V8

VDD_3V3

GND_POWER

VDDFUSE

GND_POWER

VDD_MAIN_5V

GND_POWER

VDD_3V3

GND_POWER

VDD_3V3

VBUS_USBA

VBUS_JLINK

GND_POWER GND_POWER

GND_POWER

NRST 8,11,12,13

SHDN8

EN_1 12

REV

DATEMODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A R evA

3

13

B

XX-XXX-XXZhouB XXX

03) Power domains

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XXZhouB 07-MAR-17

03-OCT-17THR XX-XXX-XXXXXB

06-DEC-17PPnB2

05-JUN-19PPnB3

REV

DATEMODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A R evA

3

13

B

XX-XXX-XXZhouB XXX

03) Power domains

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XXZhouB 07-MAR-17

03-OCT-17THR XX-XXX-XXXXXB

06-DEC-17PPnB2

05-JUN-19PPnB3

REV

DATEMODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A R evA

3

13

B

XX-XXX-XXZhouB XXX

03) Power domains

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XXZhouB 07-MAR-17

03-OCT-17THR XX-XXX-XXXXXB

06-DEC-17PPnB2

05-JUN-19PPnB3

R6 DNP

R0402

Q1 BSS138

SOT23_123

1

3

2

JPR6 JUMPER

L11

BLM18PG181SN1D

R0603

1

2

JP1

Header 1X2

1

2

JP6 Header 1X2

1

2

U3

MIC47053YMT

BIAS

1

GND

2

IN1

3

IN2

4

ADJ

6

OUT

5

EPAD

9

PGOOD

7

EN

8

R15

2R2

R0603

JP2 Header 1X2

1

2

C7 100nF

C0402

C13

4.7nF

C0402

JP4 Header 1X2

1

2

L13

BLM18PG181SN1D

R0603

1 2

R14 100R-1%

R0402

R2 100K

R0402

C11 10uF

C0603

C15 1uF

C0603

R16 2R2

R0603

C4 10uF

C0603

C2 100nF

C0402

R18 0R

R0603

R248 20K

R0402

U5

MIC5366-2.5YMT

MLF1x1mm

VIN

4

GND

2

VOUT

1

EN

3

EPAD

5

C14

2.2uF

C0603

JPR1 JUMPER

R10

DNP

R0402

R11 100K

R0402

L6

BLM18PG181SN1D

R0603

1 2

R251 10K

R0402

JPR3 JUMPER

C18 100nF

C0402

R12 220K

R0402

JPR5 JUMPER

Q4

BC847CW

SOT-323

1

32

R249 4.7K

R0402

L3

BLM18PG181SN1D

R0603

1 2

L7 MLZ1608N100L

L0603

U2

MIC2230-GSYML

MLF3x3mm

AVIN

3

EN1

11

FPWM#

7

SW1

8

OUT1

12

AGND5PGND

6

OUT2

1

SW2

4

PGOOD

10

EN2

2

VIN

9

EPAD

13

R13 39K

R0402

JP3 Header 1X2

1

2

R5 100K

R0402

JP5 Header 1X2

1

2

C9 1uF

C0603

L10

BLM18PG181SN1D

R0603

1 2

C6 10uF

C0603

L4

BLM18PG181SN1D

R0603

1 2

D2

PMEG6010CEGWX

sod123

L5

BLM18PG181SN1D

R0603

1 2

R8 100K

R0402

R3 100K

R0402

L14

BLM18PG181SN1D

R0603

1

2

D1 PMEG6010CEGWX

sod123

L8 MLZ1608N100L

L0603

L1 LQH43CN2R2M03L

L1812

C12 100nF

C0402

R4 10K

R0402

C16 1uF

C0603

D3 BAT54C

SOT23_123

3

1

2

R9 100K

R0402

R17 0R

R0603

U1A

DMP2160UFD

1

2

6

7

C10 390pF

C0402

U4A DMP2160UFD

1

2

6

7

L2 LQH43CN2R2M03L

L1812

+

C17

0.2F/3.3V

c117x68

U1B

DMP2160UFD

4

5

3

8

R250

3.3K

R0402

C5 1uF

C0603

U4B DMP2160UFD

4

5

3

8

R19 2R2

R0603

C8 100nF

C0402

JPR2 JUMPER

C1 100nF

C0402

L12

BLM18PG181SN1D

R0603

1 2

Q3 BSS138

SOT23_123

1

3

2

C3 10uF

C0603

JPR4 JUMPER

L9 MLZ1608N100L

L0603

R1 10K

R0402

Q2 BSS138

SOT23_123

1

3

2

SAMA5D2-PTC-EK

Appendix A. Schematics and Layouts

DS50002709B-page 50

Figure 5-4. MPU Power

5

4

3

2

1

D D

C

B B

A

POWER TEST POINTS

(3V3)

(1V2)

(1V8)

(3V3)

)3V3()3V3()3V3(

)5V2()2V1(

(3V3)

(1V8)

(1V2)

(2V5)

(3V3)

(1V2)

)3V3()2V1(

(3V3)

All 100nF 0402 capacitors close to the the Pin of VDD***.

(3V3)

(3V3 or 1V8)

RevB RevB RevB

VDDBU

VDDCORE

VDDPLLA

VDDIOP0

VDDIOP1

VDDIOP2

VDDHSIC

VDDUTMIC

VDDUTMII

VDDSDHC

VDDPLLA

VDDOSC

VDDISC

VDDFUSE

VDDAUDIOPLL

VDDBU

VDDIODDR

VDDANA

VDDIOP0

VDDIOP1

VDDIOP2

VDDHSIC VDDFUSE

VDDUTMII

VDDSDHC

VDDOSC

VDDISC

VDDUTMIC

VDDCORE

VDDIODDR

VDDAUDIOPLL

GNDUTMIIGND_POWER

GND_POWER

VDDBU

GND_POWER

VDDCORE

GND_POWER

VDDIODDR

VDDANA

GND_POWER

VDDIOP0

GND_POWER

VDDIOP1

GND_POWER

VDDIOP2

GND_POWER

VDDHSIC

GND_POWER

VDDFUSE

GND_POWER

VDDUTMII

GND_POWER

VDDSDHC

GND_POWER

VDDPLLA

GND_POWER

VDDOSC

VDDISC

GND_POWER

VDDUTMIC

GND_POWER

GNDUTMII

VDD_MAIN_5V

VDD_1V25

VDD_1V8

VDDFUSE

VDD_3V3

VDDSDHC1V8

VDDCORE

VDDIODDR

VDDBU

VDDHSIC

VDDFUSE

VDDUTMIC

VDDUTMII

VDDPLLA

VDDOSC

VDDSDHC

GND_POWER

VDDAUDIOPLL

REV

DATEMODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A R evA

4

13

B

XX-XXX-XXZhouB XXX

04) MPU_POWER

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XXZhouB 07-MAR-17

03-OCT-17THR XX-XXX-XXXXXB

06-DEC-17PPnB2

05-JUN-19PPnB3

REV

DATEMODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A R evA

4

13

B

XX-XXX-XXZhouB XXX

04) MPU_POWER

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XXZhouB 07-MAR-17

03-OCT-17THR XX-XXX-XXXXXB

06-DEC-17PPnB2

05-JUN-19PPnB3

REV

DATEMODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A R evA

4

13

B

XX-XXX-XXZhouB XXX

04) MPU_POWER

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XXZhouB 07-MAR-17

03-OCT-17THR XX-XXX-XXXXXB

06-DEC-17PPnB2

05-JUN-19PPnB3

C33

100nF

C0402

C22 100nF

C0402

C42 100nF

C0402

C47 100nF

C0402

C25

4.7uF

C0805

C21 100nF

C0402

C49 100nF

C0402

TP12 SMD

TP11 SMD

C57 100nF

C0402

TP15 SMD

C32 100nF

C0402

TP13 SMD

TP10 SMD

TP4 SMD

C37 100nF

C0402

C44 100nF

C0402

C29 100nF

C0402

R21 1R-1%

R0603

TP9 SMD

C48 100nF

C0402

C27 10uF

C0603

C20 10uF

C0603

TP3 SMD

C23 100nF

C0402

TP14 SMD

C39 100nF

C0402

TP19 SMD

C45 100nF

C0402

C51 1nF

C0402

C61 1nF

C0402

TP1 SMD

C35 100nF

C0402

C19 10uF

C0603

TP7 SMD

TP2 SMD

C60 1nF

C0402

C41

4.7uF

C0805

C43 100nF

C0402

C56 100nF

C0402

TP18 SMD

C55 100nF

C0402

R20 1R-1%

R0603

C38 100nF

C0402

TP8 SMD

R22 0R

R0603

C28 10uF

C0603

C36 100nF

C0402

C40 100nF

C0402

C52 1nF

C0402

C53 100nF

C0402

C26 100nF

C0402

C34

100nF

C0402

C30 100nF

C0402

TP5 SMD

C50 100nF

C0402

TP17 SMD

ATSAMA5D27C-CN

U6G

bga289p8

GNDADC

K5

GNDANA

L3

GNDBU

N6

GNDCORE_1

E7

GNDCORE_2

E9

GNDCORE_3

H4

GNDCORE_4

K12

GNDCORE_5

M5

GNDCORE_6

M9

GNDDDR_1

D14

GNDDDR_2

E11

GNDDDR_3

E12

GNDDDR_4

E14

GNDDDR_5

H14

GNDDDR_6

J14

GNDDDR_7

L14

GNDDPLL

T5

GNDAUDIOPLL

T4

GNDIOP0_1

F6

GNDIOP0_2

G7

GNDIOP1_1

M13

GNDIOP1_2

P14

GNDIOP2

F9

GNDISC

G4

GNDOSC

T6

GNDPLLA

U5

GNDSDMMC

R11

GNDUTMII

P9

GNDUTMIC

R7

VDDADC

L5

VDDANA

K3

VDDBU

N7

VDDCORE_1

D7

VDDCORE_2

D9

VDDCORE_3

H3

VDDCORE_4

K13

VDDCORE_5

N5

VDDCORE_6

N9

VDDDDR_1

D11

VDDDDR_2

D12

VDDDDR_3

D15

VDDDDR_4

E15

VDDDDR_5

H15

VDDDDR_6

J15

VDDDDR_7

L15

VDDAUDIOPLL

T3

VDDFUSE

M12

VDDHSIC

R9

VDDIOP0_1

E6

VDDIOP0_2

F7

VDDIOP1_1

N13

VDDIOP1_2

R14

VDDIOP2

F10

VDDISC

F4

VDDOSC

T7

VDDPLLA

U4

VDDSDMMC

P11

VDDUTMII

P8

VDDUTMIC

P7

C59 1nF

C0402

TP6 SMD

C46 100nF

C0402

C24

4.7uF

C0805

C58 1nF

C0402

C54

4.7uF

C0805

C31 100nF

C0402

TP16 SMD

SAMA5D2-PTC-EK

Appendix A. Schematics and Layouts

DS50002709B-page 51

Figure 5-5. DDR2-SDRAM

5

4

3

2

1

D

C

B

A

Keep nets as short as possible, therefore, DDR devices have to be placed close as possible of SAMA5D27 The layout DDR should use controlled impedance traces of ZO= 50ohm characteristic impedance.

Address, control and data traces may not exceed 1.3 inches (33.0 mm). Address, control and data traces must be length-matched to within 0.1 inch (2.54mm). Address, control and data traces must match the data group trace lengths to within 0.25 inches (6.35mm).

2 x W972GG6KB-25, DDR2-800, 16 Meg x 16 x 8

RevB RevB RevB

DDR_D0 DDR_D1 DDR_D2 DDR_D3 DDR_D4 DDR_D5 DDR_D6 DDR_D7 DDR_D8 DDR_D9 DDR_D10 DDR_D11 DDR_D12 DDR_D13 DDR_D14 DDR_D15 DDR_D16 DDR_D17 DDR_D18 DDR_D19 DDR_D20 DDR_D21 DDR_D22 DDR_D23 DDR_D24 DDR_D25 DDR_D26 DDR_D27 DDR_D28 DDR_D29 DDR_D30 DDR_D31

DDR_DQM0 DDR_DQM1 DDR_DQM2 DDR_DQM3

DDR_DQS0+ DDR_DQS0-

DDR_DQS1+ DDR_DQS1-

DDR_DQS2+ DDR_DQS2-

DDR_DQS3+ DDR_DQS3-

DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13

DDR_BA0 DDR_BA1

DDR_RAS DDR_CAS

DDR_BA2

DDR_CS DDR_WE

DDR_CLK+

DDR_CLK-

DDR_VREF

DDR_RESETN

DDR_CLK+ DDR_CLKDDR_CKE

DDR_VREF

DDR_VREFDDR_VREF

DDR_DQM0 DDR_DQM1

DDR_DQM2 DDR_DQM3

DDR_DQS0-

DDR_DQS0+

DDR_DQS1+ DDR_DQS1-

DDR_DQS2+ DDR_DQS2DDR_DQS3+ DDR_DQS3-

DDR_BA1

DDR_BA0

DDR_BA1

DDR_BA0

DDR_WE DDR_WE

DDR_CSDDR_CS

DDR_CLK-

DDR_CLK+

DDR_CLK-

DDR_CLK+

DDR_CKE DDR_CKE

DDR_CAS

DDR_RAS

DDR_CAS

DDR_RAS

DDR_D16 DDR_D17 DDR_D18 DDR_D19 DDR_D20 DDR_D21 DDR_D22 DDR_D23 DDR_D24 DDR_D25 DDR_D26 DDR_D27 DDR_D28 DDR_D29 DDR_D30 DDR_D31

DDR_D0 DDR_D1 DDR_D2 DDR_D3 DDR_D4 DDR_D5 DDR_D6 DDR_D7 DDR_D8 DDR_D9 DDR_D10 DDR_D11 DDR_D12 DDR_D13 DDR_D14 DDR_D15

DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12

DDR_BA2 DDR_BA2

DDR_A13DDR_A13

GND_POWER

VDD_1V8

GND_POWER

VDD_1V8

GND_POWER

VDDIODDR

GND_POWER

VDD_1V8

GND_POWER

VDD_1V8

GND_POWER

VDD_1V8

GND_POWER

VDD_1V8

GND_POWER

VDDIODDR

REV

DATEMODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A RevA

5

13

B

XX-XXX-XXZhouB XXX

05) DDR2-SDRAM

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XXZhouB 07-MAR-17

03-OCT-17THR XX-XXX-XXXXXB

06-DEC-17PPnB2

05-JUN-19PPnB3

REV

DATEMODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A RevA

5

13

B

XX-XXX-XXZhouB XXX

05) DDR2-SDRAM

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XXZhouB 07-MAR-17

03-OCT-17THR XX-XXX-XXXXXB

06-DEC-17PPnB2

05-JUN-19PPnB3

REV

DATEMODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A RevA

5

13

B

XX-XXX-XXZhouB XXX

05) DDR2-SDRAM

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XXZhouB 07-MAR-17

03-OCT-17THR XX-XXX-XXXXXB

06-DEC-17PPnB2

05-JUN-19PPnB3

R23 100K

R0402

R25 100K

R0402

C82 100nF

C0402

C84 100nF

C0402

C91 1nF

C0402

C63 100nF

C0402

C71 1uF

C0603

C64

22pF

C0402

C74 1uF

C0603

C89 1nF

C0402

C67 100nF

C0402

R24

21K-1%

R0402

C87 100nF

C0402

C79 100nF

C0402

R32 0R R0402

C95 1nF

C0402

C85 100nF

C0402

C68 10uF

C0603

C66 100nF

C0402

C92 1nF

C0402

R30 0R R0402

C65

4.7uF

C0805

C76 100nF

C0402

C83 100nF

C0402

C75 1nF

C0402

C80 100nF

C0402

R31 DNP R0402

R27

2.2K-1%

R0402

U7

W972GG6KB-25

bga84-32-1509e

A0

M8

A1

M3

A2

M7

A3

N2

A4

N8

A5

N3

A6

N7

A7

P2

A8

P8

A9

P3

A10

M2

A11

P7

A12

R2

A13

R8

BA0

L2

BA1

L3

BA2

L1

CKE

K2

CK_P

J8

CK_N

K8

RAS

K7

CAS

L7

WE

K3

CS

L8

DQ0

G8

DQ1

G2

DQ2

H7

DQ3

H3

DQ4

H1

DQ5

H9

DQ6

F1

DQ7

F9

DQ8

C8

DQ9

C2

DQ10

D7

DQ11

D3

DQ12

D1

DQ13

D9

DQ14

B1

DQ15

B9

LDQS_P

F7

NU/LDQS_N

E8

UDQS_P

B7

NU/UDQS_N

A8

LDM

F3

UDM

B3

ODT

K9

NC1

A2

NC2

E2

NC3

R3

NC4

R7

VDD1

A1

VDD2

E1

VDD3

J9

VDD4

M9

VDD5

R1

VDDQ1

A9

VDDQ2

C1

VDDQ3

C3

VDDQ4

C7

VDDQ5

C9

VDDQ6

E9

VDDQ7

G1

VDDQ8

G3

VDDQ9

G7

VDDQ10

G9

VDDL

J1

VREF

J2

VSS1

A3

VSS2

E3

VSS3

J3

VSS4

N1

VSS5

P9

VSSQ1

A7

VSSQ2

B2

VSSQ3

B8

VSSQ4

D2

VSSQ5

D8

VSSQ6

E7

VSSQ7

F2

VSSQ8

F8

VSSQ9

H2

VSSQ10

H8

VSSDL

J7

C69 10uF

C0603

C94 100nF

C0402

C93 1nF

C0402

ATSAMA5D27C-CN

U6E

bga289p8

DDR_A0

F12

DDR_A1

C17

DDR_A10

C15

DDR_A11

A16

DDR_A12

A17

DDR_A13

G11

DDR_A2

B17

DDR_A3

B16

DDR_A4

C16

DDR_A5

G14

DDR_A6

F14

DDR_A7

F11

DDR_A8

C14

DDR_A9

D13

DDR_BA0

H12

DDR_BA1

H13

DDR_BA2

F17

DDR_CAL

E13

DDR_CAS

G12

DDR_CKE

F16

DDR_CLK

E17

DDR_CLKN

D17

DDR_CS

G13

DDR_D0

B12

DDR_D1

A12

DDR_D10

H17

DDR_D11

K17

DDR_D12

K16

DDR_D13

J13

DDR_D14

K14

DDR_D15

K15

DDR_D16

B8

DDR_D17

B9

DDR_D18

C9

DDR_D19

A9

DDR_D2

C12

DDR_D20

A10

DDR_D21

D10

DDR_D22

B11

DDR_D23

A11

DDR_D24

J12

DDR_D25

H10

DDR_D26

J11

DDR_D27

K11

DDR_D28

L13

DDR_D29

L11

DDR_D3

A13

DDR_D30

L12

DDR_D31

M17

DDR_D4

A14

DDR_D5

C13

DDR_D6

A15

DDR_D7

B15

DDR_D8

G17

DDR_D9

G16

DDR_DQM0

C11

DDR_DQM1

G15

DDR_DQM2

C8

DDR_DQM3

H11

DDR_DQS0

B13

DDR_DQS1

J17

DDR_DQS2

C10

DDR_DQS3

L17

DDR_DQSN0

B14

DDR_DQSN1

J16

DDR_DQSN2

B10

DDR_DQSN3

L16

DDR_RAS

F13

DDR_RESETN

E16

DDR_VREFCM

D16

DDR_VREFB0

H16

DDR_WE

F15

C62 100nF

C0402

R29 DNP R0402

C77 100nF

C0402

C81 100nF

C0402

C86 100nF

C0402

C90 1nF

C0402

C70 1uF

C0603

C73 1uF

C0603

C88 1nF

C0402

C72 100nF

C0402

C78 100nF

C0402

R28

DNP

U8

W972GG6KB-25

bga84-32-1509e

A0

M8

A1

M3

A2

M7

A3

N2

A4

N8

A5

N3

A6

N7

A7

P2

A8

P8

A9

P3

A10

M2

A11

P7

A12

R2

A13

R8

BA0

L2

BA1

L3

BA2

L1

CKE

K2

CK_P

J8

CK_N

K8

RAS

K7

CAS

L7

WE

K3

CS

L8

DQ0

G8

DQ1

G2

DQ2

H7

DQ3

H3

DQ4

H1

DQ5

H9

DQ6

F1

DQ7

F9

DQ8

C8

DQ9

C2

DQ10

D7

DQ11

D3

DQ12

D1

DQ13

D9

DQ14

B1

DQ15

B9

LDQS_P

F7

NU/LDQS_N

E8

UDQS_P

B7

NU/UDQS_N

A8

LDM

F3

UDM

B3

ODT

K9

NC1

A2

NC2

E2

NC3

R3

NC4

R7

VDD1

A1

VDD2

E1

VDD3

J9

VDD4

M9

VDD5

R1

VDDQ1

A9

VDDQ2

C1

VDDQ3

C3

VDDQ4

C7

VDDQ5

C9

VDDQ6

E9

VDDQ7

G1

VDDQ8

G3

VDDQ9

G7

VDDQ10

G9

VDDL

J1

VREF

J2

VSS1

A3

VSS2

E3

VSS3

J3

VSS4

N1

VSS5

P9

VSSQ1

A7

VSSQ2

B2

VSSQ3

B8

VSSQ4

D2

VSSQ5

D8

VSSQ6

E7

VSSQ7

F2

VSSQ8

F8

VSSQ9

H2

VSSQ10

H8

VSSDL

J7

R26

2.2K-1%

R0402

SAMA5D2-PTC-EK

Appendix A. Schematics and Layouts

DS50002709B-page 52

Figure 5-6. PIOA & PIOB

5

4

3

2

1

D D

C

B B

A A

All resistors on this page connected to PIOs populated close to MPU

RevB RevB RevB

PA14 PA15 PA16

PA22

PA28

PB1 PB2 PB3 PB4

PB0

PB7

PB5 PB6

PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23

PB14

PB15

PB16

PB17

PB18

PB19

PB20

PB21

PB22

PB23

PA15

PA16

PA14

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PA30

PA27

PA24 PA25 PA26

PA23

PA22

PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9

PA11 PA12 PA13

PB24

PB28 PB29 PB30 PB31

PB28

PB29

PB30

PB31

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

PA9

PA8

PA11

PA12

PA13

PA23

PA24

PA25

PA26

PA27

PA28

PA30

PB9

PB_PORT_0 13

PB_PORT_1 13

PB_PORT_2 13

PB_PORT_3 13

PB_PORT_4 13

PB_PORT_5 13

PB_PORT_6 13

PB_PORT_7 13

ETH_GTXCK_PB14 11

ETH_GTXEN_PB15 11

ETH_GRXDV_PB16 11

ETH_GRXER_PB17 11

ETH_GRX0_PB18 11

ETH_GRX1_PB19 11

ETH_GTX0_PB20 11

ETH_GTX1_PB21 11

ETH_GMDC_PB22 11

ETH_GMDIO_PB23 11

SPI0_NPCS0_PA17 10 SDMMC1_DAT0_PA18 9 SDMMC1_DAT1_PA19 9 SDMMC1_DAT2_PA20 9 SDMMC1_DAT3_PA21 9

SPI0_SPCK_PA14 10

SPI0_MOSI_PA15 10

SPI0_MISO_PA16 10

QSPI0_SCK_PA22 10

SDMMC1_CK_PA22 9

ETH_INT_PB24 11

SPI_SCK_PB30 13

SPI_CS_PB31 13

SPI_MOSI_PB28 13

SPI_MISO_PB29 13

TWI_SDA_PB28 13

TWI_SCL_PB29 13

SDMMC0_CK_PA0 9

SDMMC0_CMD_PA1 9

SDMMC0_DAT0_PA2 9

SDMMC0_DAT1_PA3 9

SDMMC0_DAT2_PA4 9

SDMMC0_DAT3_PA5 9

SDMMC0_DAT4_PA6 9

SDMMC0_DAT5_PA7 9

SDMMC0_DAT7_PA9 9

SDMMC0_DAT6_PA8 9

SDMMC0_VDDSEL_PA11 9

SDMMC0_WP_PA12 9

SDMMC0_CD_PA13 9

XPRO2_GPIO_PB25 13

NAND_IO7_PA29 10

NAND_IO0_PA22 10

NAND_IO5_PA27 10

NAND_IO6_PA28 10

NAND_IO1_PA23 10

NAND_IO2_PA24 10

NAND_IO3_PA25 10

NAND_IO4_PA26 10

SDMMC1_CMD_PA28 9

QSPI0_IO0_PA24 10

QSPI0_IO1_PA25 10

QSPI0_IO2_PA26 10

QSPI0_IO3_PA27 10

QSPI0_NPCS_PA23 10

NAND_REn_PB2 10

NAND_ALE_PB0 10

NAND_CLE_PB1 10

NAND_CS_PA31 10

NAND_WEn_PA30 10

SDMMC1_CD_PA30 9

USBA_VBUS_5V_PB11 9 USBB_EN_5V_PB12 9

USBB_OVCUR_PB13 9

LED_BLUE_PB6 10

LED_GREEN_PB8 10

LED_RED_PB10 10

PA10_USER_BT 8

XPRO1_GPIO_PB9 13

DBGU_UTXD0_PB27 12

DBGU_URXD0_PB26 12

REV

DATE

MODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A R evA

6

13

B

XX-XXX-XXZhouB XXX

06) PIOA&PIOB

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XXZhouB 07-MAR-17

03-OCT-17THR XX-XXX-XXXXXB

06-DEC-17PPnB2

05-JUN-19PPnB3

REV

DATE

MODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A R evA

6

13

B

XX-XXX-XXZhouB XXX

06) PIOA&PIOB

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XXZhouB 07-MAR-17

03-OCT-17THR XX-XXX-XXXXXB

06-DEC-17PPnB2

05-JUN-19PPnB3

REV

DATE

MODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A R evA

6

13

B

XX-XXX-XXZhouB XXX

06) PIOA&PIOB

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XXZhouB 07-MAR-17

03-OCT-17THR XX-XXX-XXXXXB

06-DEC-17PPnB2

05-JUN-19PPnB3

R34 22R R0402

R45 22R R0402

R56 22R R0402

R79 22R R0402

R51 22R R0402

R35 22R R0402

R46 22R R0402

R80 100R-1% R0402

R36 22R R0402

R81 22R R0402

R57 22R R0402

R49 22R R0402

R42 22R R0402

R95 DNP R0402

R71 22R R0402

R82 100R-1%

R0402

ATSAMA5D27C-CN

U6A

bga289p8

PA00

U11

PA01

P10

PA02

T11

PA03

R10

PA04

U12

PA05

T12

PA06

R12

PA07

T13

PA08

N10

PA09

N11

PA10

U13

PA11

P15

PA12

N15

PA13

P16

PA14

M14

PA15

N16

PA16

M10

PA17

N17

PA18

U14

PA19

T14

PA20

P12

PA21

R13

PA22

U15

PA23

U16

PA24

T15

PA25

U17

PA26

P13

PA27

T16

PA28

R16

PA29

T17

PA30

R15

PA31

R17

R66 22R R0402

R85 100R-1% R0402

R44 22R R0402

R58 22R R0402

R74 22R R0402

R93 22R R0402

R84 100R-1% R0402

R94 DNP R0402

R59 22R R0402

R55 22R R0402

R77 22R R0402

R92 DNP R0402

R64 22R R0402

R78 100R-1% R0402

R54 22R R0402

ATSAMA5D27C-CN

U6B

bga289p8

PB01

A8

PB02

A7

PB03

A6

PB04

B6

PB05

B7

PB06

C7

PB07

C6

PB08

A5

PB09

A4

PB10

H8

PB11

B5

PB12

D6

PB13

B4

PB14

C5

PB15

H7

PB16

D5

PB17

C4

PB18

A3

PB19

D4

PB20

B3

PB21

A2

PB22

C3

PB23

A1

PB24

E5

PB25

B2

PB26

E4

PB27

B1

PB28

C2

PB29

D3

PB30

D2

PB31

C1

PB00

J8

R69 22R R0402

R72 22R R0402

R60 22R R0402

R43 22R R0402

R33 39R R0402

R91 22R R0402

R62 39R R0402

R61 39R R0402

R53 22R R0402

R86 100R-1% R0402

R37 22R R0402

R87 100R-1% R0402

R63 22R R0402

R52 22R R0402

R88 22R R0402

R67 22R R0402

R38 22R R0402

R90 DNP R0402

R70 22R R0402

R39 22R R0402

R75 22R R0402

R41 22R R0402

R89 100R-1% R0402

R47 39R R0402

R40 22R R0402

R50 39R R0402

R65 22R R0402

R83 22R R0402

R48 22R R0402

R76 22R R0402

R73 22R R0402

R68 22R R0402

SAMA5D2-PTC-EK

Appendix A. Schematics and Layouts

DS50002709B-page 53

Figure 5-7. PIOC & PIOD

5

4

3

2

1

D D

C

B B

A

TWI1

TWI0

All resistors on this page connected to PIOs populated close to MPU

RevB RevB RevB

PC6 PC7

PD21 PD22

MPU_PD5

MPU_PD4

PD21

PD22

MPU_PD14

PC6

PC7

MPU_PD11

MPU_PD15

MPU_PD17

MPU_PD16

MPU_PD18

MPU_PD3

MPU_PD7

MPU_PD9

MPU_PD6

MPU_PD8

MPU_PD10

MPU_PD13

MPU_PD12

MPU_PD3 MPU_PD4 MPU_PD5 MPU_PD6 MPU_PD7 MPU_PD8 MPU_PD9 MPU_PD10 MPU_PD11 MPU_PD12 MPU_PD13 MPU_PD14 MPU_PD15 MPU_PD16 MPU_PD17 MPU_PD18

VDD_3V3

TWD1_PC6 10

TWCK1_PC7 10

TWD0_PD21 13

TWCK0_PD22 13

NPCS0_PC04 13

SPCK_PC01 13

MISO_PC03 13

MOSI_PC02 13

JTAG_TDI_PD28 12 JTAG_TDO_PD29 12

JTAG_TCK_PD27 12

JTAG_TMS_PD30 12

LCD_D2_PC10 13 LCD_D3_PC11 13 LCD_D4_PC12 13 LCD_D5_PC13 13 LCD_D6_PC14 13 LCD_D7_PC15 13 LCD_D10_PC16 13 LCD_D11_PC17 13 LCD_D12_PC18 13 LCD_D13_PC19 13 LCD_D14_PC20 13 LCD_D15_PC21 13 LCD_D18_PC22 13 LCD_D19_PC23 13 LCD_D20_PC24 13 LCD_D21_PC25 13 LCD_D22_PC26 13 LCD_D23_PC27 13

LCD_PCLK_PD0 13 LCD_DE_PD1 13 LCD_IRQ2_PD2 13

LCD_VSYNC_PC30 13 LCD_HSYNC_PC31 13

LCD_EN_PC29 13

LCD_PWM_PC28 13

LCD_IRQ1_PC9 13

XPRO1_GPIO_PD26 13

PTC_YLINE0 13

PTC_YLINE1 13

PTC_YLINE2 13

PTC_YLINE3 13

PTC_YLINE4 13

PTC_YLINE5 13

PTC_YLINE7 13

PTC_XLINE0 13

PTC_XLINE1 13

PTC_XLINE2 13

PTC_XLINE3 13

PTC_XLINE4 13

PTC_XLINE5 13

PTC_XLINE6 13

PTC_XLINE7 13

XPRO1_GPIO_PC0 13

PTC_YLINE6 13

MBUS_RST_PC05 13

AN-AD6 13

PWM_PD20 13

INT_PD19 13

RX_PD23 13 TX_PD24 13

XPRO_PC6 13

XPRO_PC7 13

XPRO2_GPIO_PD31 13

NAND_RDY_PC8 10

REV

DATEMODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A R evA

7

13

B

XX-XXX-XXZhouB XXX

07) PIOC&PIOD

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XXZhouB 07-MAR-17

03-OCT-17THR XX-XXX-XXXXXB

06-DEC-17PPnB2

05-JUN-19PPnB3

REV

DATEMODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A R evA

7

13

B

XX-XXX-XXZhouB XXX

07) PIOC&PIOD

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XXZhouB 07-MAR-17

03-OCT-17THR XX-XXX-XXXXXB

06-DEC-17PPnB2

05-JUN-19PPnB3

REV

DATEMODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A R evA

7

13

B

XX-XXX-XXZhouB XXX

07) PIOC&PIOD

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XXZhouB 07-MAR-17

03-OCT-17THR XX-XXX-XXXXXB

06-DEC-17PPnB2

05-JUN-19PPnB3

R114 0R

R115 0R

R116 0R

R117 0R

R121 22R

R0402

R118 22R

R0402

R102 0R

R103 0R

R104 0R

R105 0R

R98

2.2K-1%

R0402

ATSAMA5D27C-CN

U6C

bga289p8

PC00

P17

PC01

N12

PC02

N14

PC03

M15

PC04

M11

PC05

L10

PC06

K10

PC07

M16

PC08

J10

PC09

D1

PC10

E3

PC11

E2

PC12

E1

PC13

F3

PC14

F5

PC15

F2

PC16

G6

PC17

F1

PC18

H6

PC19

G2

PC20

G3

PC21

G1

PC22

H2

PC23

G5

PC24

H1

PC25

H5

PC26

J9

PC27

H9

PC28

E8

PC29

G8

PC30

F8

PC31

D8

R101 22R

R0402

R100 22R

R0402

R99

2.2K-1%

R0402

R106 0R

R120 22R

R0402

R107 0R

R108 0R

ATSAMA5D27C-CN

U6D

bga289p8

PD00

G10

PD01

E10

PD02

G9

PD03

K1

PD04

J6

PD05

J4

PD06

J2

PD07

J7

PD08

J1

PD09

K9

PD10

J3

PD11

M1

PD12

K8

PD13

L2

PD14

K4

PD15

K7

PD16

L1

PD17

K2

PD18

J5

PD19

K6

PD20

M2

PD21

N1

PD22

L4

PD23

M3

PD24

L7

PD25

L6

PD26

N2

PD27

L8

PD28

M4

PD29

N3

PD30

L9

PD31

M7

R109 0R

R110 0R

R96

2.2K-1%

R0402

R97

2.2K-1%

R0402

R111 0R

R112 0R

R113 0R

R119 22R

R0402

SAMA5D2-PTC-EK

Appendix A. Schematics and Layouts

DS50002709B-page 54

Figure 5-8. System

5

4

3

2

1

D D

C

B

A

Routing USB

Routing top or bottom

Max trace-length mismatch between USB signals pairs should be no greater than 3.8mm

90 ohms differential trace impedance

SAMA5D2 System Pins

R&C as close as possible

Top/Bot

JTAG

USER BUTTON

WAKE UP

RESET

DIS BOOT

Clock sources

RevB RevB RevB

RXD

PIOBU0

ACN

PIOBU2 PIOBU4 PIOBU6

XIN

XOUT

PIOBU3 PIOBU5

XIN XOUT

XIN32 XOUT32

ACP ACN

PIOBU3

PIOBU2

PIOBU4 PIOBU5

ACP

RXD

XOUT32

XIN32

PIOBU1

PIOBU7

PIOBU0

PIOBU6

PIOBU1

PIOBU7

GND_POWER

VDDBU

GNDUTMII

VDDANA

GND_POWER

VDD_3V3

GND_POWER

VDDBU

USBA_DP 9 USBA_DM 9

USBB_DP 9 USBB_DM 9

NRST3,8,11,12,13

SHDN3 WKUP8

DISABLE_BOOT10

NRST3,8,11,12,13

WKUP8

NRST 3,8,11,12,13

HSIC_DATA 9 HSIC_STRB 9

CON_JTAG_Pin2 12 CON_JTAG_Pin4 12 CON_JTAG_Pin6 12 CON_JTAG_Pin8 12

RTCKIN12

PA10_USER_BT6

REV

DATEMODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A R evA

8

13

B

XX-XXX-XXZhouB XXX

08) SYSTEM

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XXZhouB 07-MAR-17

03-OCT-17THR XX-XXX-XXXXXB

06-DEC-17PPnB2

05-JUN-19PPnB3

REV

DATEMODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A R evA

8

13

B

XX-XXX-XXZhouB XXX

08) SYSTEM

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XXZhouB 07-MAR-17

03-OCT-17THR XX-XXX-XXXXXB

06-DEC-17PPnB2

05-JUN-19PPnB3

REV

DATEMODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A R evA

8

13

B

XX-XXX-XXZhouB XXX

08) SYSTEM

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XXZhouB 07-MAR-17

03-OCT-17THR XX-XXX-XXXXXB

06-DEC-17PPnB2

05-JUN-19PPnB3

R124 330R R0402

R144 0R

R0402

R125 330R R0402

C101 100nF

C0402

J2

Header 2X5

FTSH-105-01-F-DV-P-TR

1 2 3 4 5 6 7 8 9 10

R122

DNP

R0402

R132 0R R0402

R143 100R-1% R0402

J1

DNP

FTSH-105-01-F-DV-P-TR

1

2

3

4

5

6 7 8 9 10

Y2

32.768KHz CL=12.5pF

X4S70X15

1

23

4

R133 DNP

R0402

R145 100R-1%

r0402

R135 10K

R0402

R236 10K

R0402

R142 100K

R0402

R128 0R R0402

R140 100K

R0402

R131 0R R0402

BP1 Tact Switch

FSM2JSML

BP2 Tact Switch

FSM2JSML

R137 0R

R0402

BP4 Tact Switch

FSM2JSML

R134 0R

R0402

C97 20pF

C0402

C100 22pF

C0402

C96 20pF

C0402

R238 10K

R0402

R136 20K-1%

R0402

C99 20pF

C0402

R130 330R R0402

C98 20pF

C0402

R123 DNP

R0402

R139

5.62K-1%

R0402

Y1

24MHz CL=10pF

x4s32x25

1 4

32

C102 10pF

C0402

JP7

DNP

1

2

R146 100R-1%

r0402

BP3 Tact Switch

FSM2JSML

R138 DNP

R0402

R141 100K

R0402

R126 330R R0402 R127 330R R0402

R147 100R-1%

r0402

ATSAMA5D27C-CN

U6F

bga289p8

ADVREFP

M6

CLK_AUDIO

U3

ACN

T1

ACP

U1

HHSDMA

R8

HHSDMB

U9

HSIC_STRB

U10

HHSDPA

T8

HHSDPB

U8

HSIC_DATA

T9

JTAGSEL

T2

NRST

U2

PIOBU0

R3

PIOBU1

N8

PIOBU2

R2

PIOBU3

R5

PIOBU4

R4

PIOBU5

P5

PIOBU6

P6

PIOBU7

M8

RXD

N4

SDCAL

T10

SHDN

R1

TST

P3

VBG

R6

WKUP

P4

XIN

U7

XIN32

P1

XOUT

U6

XOUT32

P2

R129 330R R0402

SAMA5D2-PTC-EK

Appendix A. Schematics and Layouts

DS50002709B-page 55

Figure 5-9. USB & TF

5

4

3

2

1

D D

C

B

A

USB A

USB B

EN: Active High

Through Holes

(MCI0_CD)

(MCI0_WP)

SD/MMCPlus CARD INTERFACE - MCI0

(MCI0_DA1) (MCI0_DA0)

(MCI0_CK)

(MCI0_CDA) (MCI0_DA3) (MCI0_DA2)

(MCI0_DA4) (MCI0_DA5)

(MCI0_DA7)

(MCI0_DA6)

MCI0

Micro SD

MCI1

(MCI1_DA1) (MCI1_DA0)

(MCI1_CK)

(MCI1_CDA) (MCI1_DA3) (MCI1_DA2)

(MCI1_CD)

USB C

RevB RevB RevB

USBB_VBUS_5V

GND_POWER

EARTH_USB_A

EARTH_USB_AGND_POWER

GND_POWER

EARTH_USB_B

GND_POWER

EARTH_USB_B

GND_POWERGND_POWER

GND_POWER

VDD_3V3

GND_POWER

VDD_3V3

VDDSDHC1V8

VDDSDHC

VDD_MAIN_5V

VBUS_USBA

VDDSDHC

VDD_3V3

USBB_DP 8

USBB_DM 8

USBB_EN_5V_PB12 6

USBB_OVCUR_PB13 6

USBA_VBUS_5V_PB11 6

SDMMC0_CK_PA06

SDMMC0_CMD_PA16

SDMMC0_DAT1_PA36

SDMMC0_DAT2_PA46

SDMMC0_DAT3_PA56

SDMMC0_DAT4_PA66 SDMMC0_DAT5_PA76 SDMMC0_DAT6_PA86 SDMMC0_DAT7_PA96

SDMMC0_VDDSEL_PA116

SDMMC0_WP_PA126 SDMMC0_CD_PA136

SDMMC0_DAT0_PA26

SDMMC1_CK_PA226

SDMMC1_CD_PA306

SDMMC1_CMD_PA286

SDMMC1_DAT1_PA196 SDMMC1_DAT0_PA186

SDMMC1_DAT2_PA206

SDMMC1_DAT3_PA216

HSIC_DATA 8 HSIC_STRB 8

USBA_DP 8

USBA_DM 8

REV

DATE

MODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A R evA

9

13

B

XX-XXX-XXZhouB XXX

09) USB&TF

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XXZhouB 07-MAR-17

03-OCT-17THR XX-XXX-XXXXXB

06-DEC-17PPnB2

05-JUN-19PPnB3

REV

DATE

MODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A R evA

9

13

B

XX-XXX-XXZhouB XXX

09) USB&TF

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XXZhouB 07-MAR-17

03-OCT-17THR XX-XXX-XXXXXB

06-DEC-17PPnB2

05-JUN-19PPnB3

REV

DATE

MODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A R evA

9

13

B

XX-XXX-XXZhouB XXX

09) USB&TF

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XXZhouB 07-MAR-17

03-OCT-17THR XX-XXX-XXXXXB

06-DEC-17PPnB2

05-JUN-19PPnB3

J6

7SDMM-B0-2211

con_kingconn_7sdmm_2211

8

5

7 6

4 3 2 1 9

14

15

16

13 12 11 10

MH4 PTH

MHC50D30

1

MH3 PTH

MHC50D30

1

R148 100K

R0402

R157 68k

R0603

R171 0R

R0402

R168 68k

R0603

C110 10uF

C0603

R158 68k

R0603

R156 10K

R0402

C108 10uF

C0603

VBUS

SHD

DM

DP

ID

GND

J4

MicroUSB AB Connector

USBMICRO5_6A

1 2 3 4 5

8

6

11

7

9

10

R167 68k

R0603

C105 10uF

C0603

R172 10k

R0402

R152 DNP

R0402

L15 BLM18PG181SN1D

R0603

1 2

R163 68k

R0603

R166 68k

R0603

J5

DNP

1

2

SW1

SW2

J7

PJS008-2120-0

Micro_SD_PJS008

8

5

7 6

4 3 2 1

9

13

12

11

10

14

L17 BLM18PG181SN1D

R0603

1 2

R151 DNP

R0402

R155 68k

R0603

R173 10k

R0402

R170 10k

R0402

R162 68k

R0603

MH2 PTH

MHC50D30

1

C106 100nF

C0402

R169 10k

R0402

R154 0R

R0402

C111 100nF

C0402

C103 20pF

C0402

MH1 PTH

MHC50D30

1

C107 100nF

C0402

R149 200K

R0402

A

J3

Single USB Type A

VBUS

1

DM

2

DP

3

GND

4

SH1

5

SH2

6

C109 100nF

C0402

R153 10K

R0402

R159 68k

R0603

L16 BLM18PG181SN1D

R0603

1 2

R150 10k

R0402

U10

MIC2025-1YM-TR

soic8ja

EN

1

FLG

2

NC

4

OUT_2

8

OUT_1

6

GND3IN_2

7

IN_1

5

U9

ADG849YKSZ-REEL

SC70

S2

6

S1

4

IN

1

GND

3

D

5

VDD

2

R165 68k

R0603

C104 100nF

C0402

R161 68k

R0603

R164 68k

R0603

R160 10k

R0402

SAMA5D2-PTC-EK

Appendix A. Schematics and Layouts

DS50002709B-page 56

Figure 5-10. Memories & RGB LED

5

4

3

2

1

D D

C

B

A

QSPI Flash & SPI Flash CS

BOOT_DIS

QSPI Flash CS

LED

SPI Flash

SPI Flash CS

QSPI Flash

TWD1 TWCK1

EEPROM+MAC

NAND Flash

RevB RevB RevB

QSPI0_CS_PA23

SPI0_CS0_PA17

NAND_WPn

QSPI0_CS_PA23

GND_POWER

VDD_3V3

GND_POWER

VDD_3V3

GND_POWER

VDD_3V3

GND_POWER

3V3_NAND

VDD_3V3

3V3_NAND

GND_POWER

VDD_3V3

GND_POWER

SPI0_MOSI_PA156 SPI0_MISO_PA166

SPI0_SPCK_PA146

SPI0_NPCS0_PA176

QSPI0_NPCS_PA236

QSPI0_IO0_PA246 QSPI0_IO1_PA256 QSPI0_IO2_PA266 QSPI0_IO3_PA276 QSPI0_SCK_PA22 6

TWD1_PC67

TWCK1_PC7

7

DISABLE_BOOT8

NAND_CLE_PB1

6

NAND_ALE_PB06 NAND_REn_PB26

NAND_WEn_PA306

NAND_RDY_PC87

NAND_IO5_PA27 6 NAND_IO6_PA28 6 NAND_IO7_PA29 6

NAND_IO0_PA22 6 NAND_IO1_PA23 6 NAND_IO2_PA24 6 NAND_IO3_PA25 6 NAND_IO4_PA26 6

NAND_CS_PA316

LED_RED_PB106

LED_GREEN_PB86

LED_BLUE_PB6

6

REV

DATE

MODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A R evA

10

13

B

XX-XXX-XXZhouB XXX

10) MEMORIES&RGBLED

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XXZhouB 07-MAR-17

03-OCT-17THR XX-XXX-XXXXXB

06-DEC-17PPnB2

05-JUN-19PPnB3

REV

DATE

MODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A R evA

10

13

B

XX-XXX-XXZhouB XXX

10) MEMORIES&RGBLED

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XXZhouB 07-MAR-17

03-OCT-17THR XX-XXX-XXXXXB

06-DEC-17PPnB2

05-JUN-19PPnB3

REV

DATE

MODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A R evA

10

13

B

XX-XXX-XXZhouB XXX

10) MEMORIES&RGBLED

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XXZhouB 07-MAR-17

03-OCT-17THR XX-XXX-XXXXXB

06-DEC-17PPnB2

05-JUN-19PPnB3

U15

24AA02E48

8MA2

A0

1

A1

2

A2

3

GND

4

SDA

5

SCL

6

WP

7

VCC

8

Q5 BSS138

SOT23_123

1

3

2

JP13 Header 1X2

1

2

R243 10K

R187 10K

R0402

MT29F4G08ABADAWP

U13

NC1

1

NC2

2

NC3

3

NC4

4

NC5

5

NC6

6

R/B#

7

CE#

9

NC7

10

VCC_1

12

VSS_1

13

NC9

14

NC10

15

CLE

16

ALE

17

NC21

47

VSS_4

48

RE#

8

NC8

11

WE#

18

WP#

19

DNU2

20

DNU1

21

NC11

22

NC12

23

NC13

24

VSS_2

25

NC14

26

NC15

27

NC16

28

DQ0

29

DQ1

30

DQ2

31

DQ3

32

NC17

33

VCC_2

34

DNU3

35

VSS_3

36

VCC_3

37

DNU4

38

VCC_4

39

NC18

40

DQ4

41

DQ5

42

DQ6

43

DQ7

44

NC19

45

NC20

46

R240 1K

R0402

R188 10K

R0402

R241 1K

R0402

JPR12 JUMPER

C115

100nF

Q6 BSS138

SOT23_123

1

3

2

D4

CLV1A-FKB-CJ1M1F1BB7R4S3

Red

1

Green

4

Blue

3

Anode

2

VCC

GND

U12

NL17SZ126DFT2G

1

2

3

4

5

R244 10K

C114

100nF

R185 10K

C117 100nF

R186 10K

R0402

R178 10K

C113

100nF

R174 0R

R184 10K

C120 100nF

C0402

R177

DNP

R181 100R-1%

R0402

R183 100R-1%

R0402

U14

SST26VF064B-104I/SM

soic8jg

SI/SIO0

5

SO/SIO1

2

SIO2

3

SIO3

7

SCLK

6

CS#

1

GND

4

VCC

8

JPR7 JUMPER

R175 100K

R176 10K

JP8 Header 1X2

1

2

R180 100K

R242 10K

R239 2.2K-1%

R0402

U16

DNP

soic8jg

SST26VF032B-104I/SM

HOLD

7

GND

4

VCC

8

CS

1

SCK

6

SI

5

SO

2

WP

3

C119 100nF

C0402

Q7 BSS138

SOT23_123

1

3

2

VCC

GND

U11

NL17SZ126DFT2G

1

2

3

4

5

R179 0R

C118 100nF

C0402

C112

100nF

C116 100nF

R182 100R-1%

R0402

SAMA5D2-PTC-EK

Appendix A. Schematics and Layouts

DS50002709B-page 57

Figure 5-11. Ethernet 10/100M

5

4

3

2

1

D D

C

B B

A

10Base-T/100Base-TX

Ethernet

LINK

ACT

Routing top or bottom

100 ohms differential trace impedance

At the De-Assertion of Reset:

PHY ADD[2:0]-pin15/14/13: 001 = 1 CONFIG[2:0]-pin18/29/28:001,RMII mode Duplex Mode-pin16: 1,Half Duplex Isolate Mode-pin20: 0,Disable Speed Mode-pin31: 1,100Mbps Nway Auto-Negotiation-p30: 1,Enable

top/bot

RevB RevB RevB

RevB

ETH_LED0

ETH_XI

ETH_XO

TX+

ETH_XI

ETH_XO

ETH_LED1

TX-

RX+

RX-

RX+

TX-

GND_POWER

EARTH_ETH

GND_ETH

GND_POWER

GND_ETHGND_POWEREARTH_ETH

GND_POWER

VDDA_3V3

VDD_3V3

ETH_INT_PB24 6

ETH_GTXCK_PB14 6

ETH_GTXEN_PB15 6

ETH_GRXDV_PB16 6 ETH_GRXER_PB17 6

ETH_GRX0_PB18 6

ETH_GRX1_PB19 6

ETH_GTX0_PB20 6

ETH_GTX1_PB21 6

ETH_GMDC_PB22 6 ETH_GMDIO_PB23 6

NRST 3,8,12,13

REV

DATEMODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A R evA

11

13

B

XX-XXX-XXZhouB XXX

11) Ethernet_10/100M

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XXZhouB 07-MAR-17

03-OCT-17THR XX-XXX-XXXXXB

06-DEC-17PPnB2

05-JUN-19PPnB3

REV

DATEMODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A R evA

11

13

B

XX-XXX-XXZhouB XXX

11) Ethernet_10/100M

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XXZhouB 07-MAR-17

03-OCT-17THR XX-XXX-XXXXXB

06-DEC-17PPnB2

05-JUN-19PPnB3

REV

DATEMODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A R evA

11

13

B

XX-XXX-XXZhouB XXX

11) Ethernet_10/100M

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XXZhouB 07-MAR-17

03-OCT-17THR XX-XXX-XXXXXB

06-DEC-17PPnB2

05-JUN-19PPnB3

R197 1K

R0402

C130 100nF

C0402

C124 100nF

C0402

1

2

3

6

4

5

7

8

75

75 75

1nF

TD+

TD-

CT

NC

RD-

CT

TX+

TX-

RX+

RX-

RD+

Left Green LED Right yellow LED

J8 SI-60110-F

1

2

7

8

3

6

5

4

9

10

11

12

13 14

15 16

R198 1K

R0402

R202

10K

R0402

C123 2.2uF

C0603

L19 BLM18PG181SN1D

R0603

1 2

L18 BLM18PG181SN1D

R0603

1

2

C129 100nF

C0402

R191 0R

R0603

R196 0R

R0402

R206

10K

R0402

C122 100nF

C0402

R192 10K

R0402

R190 510R

R0402

R204

10K

R0402

R194 6.49K 1%

R0402

R200 10K

R0402

C128 10uF

C0603

R199 10K

R0402

C127 10uF

C0603

R189 510R

R0402

R201

10K

R0402

R203 10K

R0402

R205

10K

R0402

R195

DNP

R0402

C126 22pF

C0402

R193 10K

R0402

U17

KSZ8081RNB

qfn32_1p5h

RXC/B-CAST_OFF

19

CRS/CONFIG1

29

COL/CONFIG0

28

TXD1

25

TXD0

24

TXEN

23

RXD3/PHYAD0

13

RXD2/PHYAD1

14

RXD1/PHYAD2

15

RXD0/DUPLEX

16

RXDV/CONFIG2

18

RXER/ISO

20

MDC

12

MDIO

11

INTRP/NAND

21

VDDA_3V3

3

VDDIO

17

RESET

32

TXP

7

TXM

6

RXP

5

RXM

4

VDD_1V2

2

GND

1

PADDLE

33

TXC

22

TXD2

26

TXD3

27

REXT

10

XO

8

XI

9

LED0/NWAYEN

30

LED1/SPEED

31

Y3

25MHz CL=20pF

x4s32x25

1

23

4

C125 22pF

C0402

C121 100nF

C0402

SAMA5D2-PTC-EK

Appendix A. Schematics and Layouts

DS50002709B-page 58

Figure 5-12. J-Link-OB

5

4

3

2

1

D D

C

B B

A A

JLINK-OB

PCB connector for SAMTEC MEC1-108-02

(3V3)

Max 500mA @ 3.3V

JTAG-OB disable

DBGU function switches

JTAG-CDC disable

RevB RevB RevB

EDBG_USB_DP

EDBG_USB_DM

ERASE_3U

ENSPI

ERASE_3U

TDI_3U TDO_3U TCK_3U TMS_3U

NRST_3U

TRSTIN TRSTOUT

TRESIN TRESOUT

TDIIN

TMSIN

TCKOUT TMSOUT

TDIOUT TDOIN TCKIN ENSPI TCKOUT PA25_3U PA26_3U

PA25_3U

PA26_3U

LED2_3U

LED1_3U

TDIOUT

TDIIN

PA26_3U

TDOIN

TMSIN

TMSOUT

TCKIN

TCKOUT

TRESIN

TRESOUT

TRSTIN

TRSTOUT

RX_3U

TX_3U

TDI_3U TDO_3U TCK_3U TMS_3U

NRST_3U

PA25_3U

EDBG_XIN

RX_3U TX_3U

EARTH_USB_EDBG

VDD_3V3_3U

GND_POWER

VDD_3V3_3U

VDD_OUT_3U

VDD_3V3_3U

GND_POWER

VDD_OUT_3U

GND_POWER

VDD_3V3_3U

GND_POWER

VDD_3V3_3U

GND_POWER

VDD_3V3_3U

GND_POWER

VDD_3V3_3U

GND_POWER

VDD_3V3_3U

GND_POWER

VDD_3V3_3U

GND_POWER

VDD_3V3_3U

VBUS_JLINK

VDD_MAIN_5V

VDD_3V3_3U

GND_POWER

JTAG_TCK_PD27 7

JTAG_TMS_PD30 7

JTAG_TDI_PD287

CON_JTAG_Pin2 8

CON_JTAG_Pin4 8

CON_JTAG_Pin88

JTAG_TDO_PD297

CON_JTAG_Pin68

NRST 3,8,11,13

DBGU_UTXD0_PB276

DBGU_URXD0_PB26 6

RTCKIN 8

EN_1 3

REV

DATEMODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A R evA

12

13

B

XX-XXX-XXZhouB XXX

12) JLINK-OB

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XX

ZhouB 07-MAR-17

03-OCT-17

THR

XX-X

XX-XXXXX

B

06-DEC-17PPnB2

05-JUN-19PPnB3

REV

DATEMODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A R evA

12

13

B

XX-XXX-XXZhouB XXX

12) JLINK-OB

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XX

ZhouB 07-MAR-17

03-OCT-17

THR

XX-X

XX-XXXXX

B

06-DEC-17PPnB2

05-JUN-19PPnB3

REV

DATEMODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A R evA

12

13

B

XX-XXX-XXZhouB XXX

12) JLINK-OB

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XX

ZhouB 07-MAR-17

03-OCT-17

THR

XX-X

XX-XXXXX

B

06-DEC-17PPnB2

05-JUN-19PPnB3

C138

2.2uF

C0603

C146 100nF

C0402

R224 10K

R0402

JPR8 JUMPER

D6

KPTB-1615

Green

4

11RED

2

3

C141 100nF

C0402

C135

2.2uF

C0603

C143 100nF

C0402

R225 10K

R0402

JPR10 JUMPER

R215

100K

R0402

J10

PADS ON PCB

Pin-16

TGTPOWER

1

GND2

2

GND13NRST

4

TRACE D37TDI

8

TRACE D29TDO/SWO

10

TRACE D1

11

SWCLK/TCK

12

TRACE D013SDWIO/TMS

14

TRACE_CK15VCC

16

R214

6.8K-1%

R0402

R212 39R R0402

C140 100nF

C0402

R213

DNP

R0402

R217 150R-1%

R0402

R222 150R-1%

R0402

JP11 Header 1X2

1

2

R211 39R R0402

JP9 Header 1X2

1

2

U20

ATSAM3U4CA-CU

TFBGA100

VBG

A1

XIN

A2

XOUT

A3

PB17A4PB21A5PB23

A6

TCK/SWCLK

A7

VDDINA8VDDOUT

A9

XIN32

A10

VDDCORE_1

B1

GNDUTMI

B2

VDDUTMI

B3

PB10

B4

PB18B5PB24

B6

NRST

B7

TDO/TRACESWO

B8

TDI

B9

XOUT32

B10

DFSDP

C1

DHSDP

C2

GNDPLL

C3

PB14C4PB19C5PB22

C6

TMS/SWDIO

C7

NRSTB

C8

JTAGSEL

C9

VDDBU

C10

DFSDM

D1

DHSDM

D2

VDDPLLD3VDDCORE_2

D4

PB20

D5

ERASE

D6

TST

D7

FWUP

D8

PA11/PGMD3

D9

PA12/PGMD4

D10

PA29

E1

GND_1

E2

PA28

E3

PB9

E4

GNDBUE5VDDIO_3

E6

VDDCORE_3

E7

PA10/PGMD2

E8

PA9/PGMD1

E9

PA8/PGMD0

E10

PB1

F1

PB12

F2

VDDIO_1

F3

PA31

F4

VDDIO_2

F5

GND_2

F6

PB16

F7

PA6/PGMM2

F8

VDDCORE_6

F9

PA7/PGMM3

F10

PB11

G1

PB2G2PB0

G3

PB13

G4

VDDCORE_5

G5

GND_3

G6

PB15

G7

PA3/PGMNVALID

G8

PA5/PGMM1

G9

PA4/PGMM0

G10

VDDCORE_4

H1

PB5

H2

PA27

H3

PA22/PGMD14

H4

PA13/PGMD5

H5

PA15/PGMD7

H6

PA18/PGMD10

H7

PA24

H8

PA1/PGMRDY

H9

PA2/PGMNOE

H10

PB6J1PB8

J2

ADVREF

J3

PA30

J4

PB3

J5

PA16/PGMD8

J6

PA19/PGMD11

J7

PA21/PGMD13

J8

PA26

J9

PA0/PGMNCMD

J10

PB7

K1

VDDANA

K2

GNDANA

K3

AD12BVREF

K4

PB4

K5

PA14/PGMD6

K6

PA17/PGMD9

K7

PA20/PGMD12

K8

PA23/PGMD15

K9

PA25

K10

C150 100nF

C0402

U19

NL17SZ126DFT2G

OE

1

IN

2

GND

3

VCC

5

OUT

4

R247 0R

C137 10pF

C0402

L20 BLM18PG181SN1D

R0603

1 2

C144 100nF

C0402

C134

2.2uF

C0603

JP14

123

Y4

ASE-12.000MHz-LC-T

NC

1

VCC4Out

3

GND

2

R219 150R-1%

R0402

C152

2.2uF

C0603

R209

100R-1%

R0402

JPR9 JUMPER

C132 10nF

C0402

C145 100nF

C0402

C139

2.2uF

C0603

C155 100nF

C0402

C151 100nF

C0402

R246 10K

R0402

R223 150R-1%

R0402

U18

NL17SZ126DFT2G

OE

1

IN

2

GND

3

VCC

5

OUT

4

R216 150R-1%

R0402

D5 PMEG6010CEGWX

sod123

JPR13 JUMPER

U22

NLAS3899BMNTBG

NCA

1

COMA

16

NOA

15

NOB

3

COMB

4

NCB

5

ABIN

2

NOC

7

COMC

8

NCC

9

CDIN

10

NOD

11

COMD

12

NCD

13

VCC

14

GND

6

U21

MIC5528-3.3YMTDFN6

VIN

6

GND

3

EN

4

VOUT1

1

VOUT2

2

NC

5

EP

7

C147 100nF

C0402

R245

0R

C153

2.2uF

C0603

R210 100R-1%

R0402

C154 100nF

C0402

JP10 Header 1X2

1

2

R218 150R-1%

R0402

R208

10K

R0402

C142 100nF

C0402

C148 100nF

C0402

C149 100nF

C0402

VBUS

SHD

DM

DP

ID

GND

J9

MicroUSB AB Connector

USBMICRO5_6A

1 2 3 4 5

8

6

11

7

9

10

C136 10nF

C0402

R221 100R-1%

R0402

C156 100nF

C0402

R220 0R

SAMA5D2-PTC-EK

Appendix A. Schematics and Layouts

DS50002709B-page 59

Figure 5-13. EXT Connectors

5

4

3

2

1

D D

C

B

A

PD16

PD26

PD17

XPRO Connectors

XPRO EXT1

PD11 PD13 PB9 PD15

7CP6CP

PD18 PD17

PC0

PD14

PD12

XPRO EXT2

PD10

PB25

PD4

PD8

PD3

PD6PD5 PD7 PD9

PIOB[0-7] Connector

PD31

PD25 RST NPCS0 SPCK MISO MOSI 3V3

PWM INT RX TX SCL SDA

+5v

MikroBUS

LCD-50PIN

close to connecter

PTC Connector

RevB RevB RevB

TWI_SCL_PB29

TWI_SDA_PB28

VDD_3V3

GND_POWER

VDD_3V3

GND_POWER

VDD_3V3

GND_POWER

VDD_3V3VDD_MAIN_5V

VDD_3V3 VDD_MAIN_5V

GND_POWER

VDD_3V3

LCD_D2_PC107 LCD_D3_PC117

LCD_D4_PC127 LCD_D5_PC137 LCD_D6_PC147 LCD_D7_PC157

LCD_D10_PC167 LCD_D11_PC177

LCD_D12_PC187 LCD_D13_PC197 LCD_D14_PC207 LCD_D15_PC217

LCD_D18_PC227 LCD_D19_PC237

LCD_D20_PC247 LCD_D21_PC257 LCD_D22_PC267 LCD_D23_PC277

LCD_PCLK_PD07 LCD_VSYNC_PC307 LCD_HSYNC_PC317

LCD_DE_PD17

LCD_EN_PC297

LCD_IRQ1_PC97 LCD_IRQ2_PD27

LCD_PWM_PC287

PTC_YLINE07,13 PTC_YLINE27,13

XPRO1_GPIO_PB96

PTC_YLINE47,13

PTC_YLINE67,13

PTC_YLINE1 7,13 PTC_YLINE3 7,13

PTC_YLINE5 7,13

PTC_YLINE7 7,13 PTC_YLINE6 7,13

PTC_XLINE07,13 PTC_XLINE27,13 PTC_XLINE47,13 PTC_XLINE67,13

XPRO2_GPIO_PB256

PTC_XLINE1 7,13 PTC_XLINE3 7,13 PTC_XLINE5 7,13 PTC_XLINE7 7,13

XPRO1_GPIO_PD267

XPRO1_GPIO_PC0 7

XPRO2_GPIO_PD31 7

SPI_CS_PB316

SPI_SCK_PB306

SPI_MISO_PB296

SPI_MOSI_PB286

TWI_SCL_PB296

TWI_SDA_PB286

PB_PORT_06 PB_PORT_16 PB_PORT_26 PB_PORT_36 PB_PORT_46 PB_PORT_56 PB_PORT_66 PB_PORT_76

AN-AD67

NPCS0_PC047

SPCK_PC017

MISO_PC037 MOSI_PC027

PWM_PD20 7 INT_PD19 7 RX_PD23 7 TX_PD24 7 TWCK0_PD22 7

TWD0_PD21 7

PTC_YLINE07,13

PTC_YLINE17,13

PTC_YLINE27,13

PTC_YLINE37,13

PTC_YLINE47,13

PTC_YLINE57,13

PTC_YLINE67,13

PTC_YLINE77,13

PTC_XLINE07,13 PTC_XLINE17,13 PTC_XLINE27,13 PTC_XLINE37,13 PTC_XLINE47,13 PTC_XLINE57,13 PTC_XLINE67,13 PTC_XLINE77,13

MBUS_RST_PC057

XPRO_PC67

XPRO_PC7 7

NRST3,8,11,12

SPI_CS_PB3113

REV

DATEMODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A R evA

13

B

XX-XXX-XXZhouB XXX

13) EXT_CONNECTORS

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XXZhouB 07-MAR-17

03-OCT-17THR XX-XXX-XXXXXB

06-DEC-17PPnB2

05-JUN-19PPnB3

REV

DATEMODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A R evA

13

B

XX-XXX-XXZhouB XXX

13) EXT_CONNECTORS

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XXZhouB 07-MAR-17

03-OCT-17THR XX-XXX-XXXXXB

06-DEC-17PPnB2

05-JUN-19PPnB3

REV

DATEMODIF.

DES.

DATE

VER.

SCALE

1/1

REV.

SHEET

INIT EDIT

A

A R evA

13

B

XX-XXX-XXZhouB XXX

13) EXT_CONNECTORS

06-JAN-17

SAMA5D2-PTC-EK

XXX XX-XXX-XXZhouB 07-MAR-17

03-OCT-17THR XX-XXX-XXXXXB

06-DEC-17PPnB2

05-JUN-19PPnB3

R228 0R

J15A

SSQ-108-01-G-S

1 2 3 4 5 6 7 8

J14

046288026000846

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

R233

2.2K-1%

J13

PIOB[0-7] connector

1 2 3 4 5 6 7 8 9

10

R234

100R-1%

R0402

J12

1 2 3 4 5 6 7 8 9

10

11

12 13 15 17 19

14

16

18

20

R235 0R

R227 DNP

R232

2.2K-1%

R231 0R

R0603

JPR11 JUMPER

J16

XF2M-5015-1A

FPC50-0p5mm

ID

1

GND1

2

D0

3

D1

4

D2

5

D3

6

GND2

7

D4

8

D5

9

D6

10

D7

11

GND3

12

D8

13

D9

14

D10

15

D11

16

GND4

17

D12

18

D13

19

D14

20

D15

21

GND5

22

D16

23

D17

24

D18

25

D19

26

GND6

27

D20

28

D21

29

D22

30

D23

31

GND7

32

PCLK/CMD

33

VSYNC/CS

34

HSYNC/WE

35

DE/RE

36

SPI_SCK

37

SPI_MOSI

38

SPI_MISO

39

SPI_CS

40

ENABLE

41

TWI_SDA

42

TWI_SCL

43

IRQ1

44

IRQ2

45

PWM

46

RESET

47

VCC1

48

VCC2

49

GND8

50

R226 0R

R230

DNP

R0603

R229 DNP

R0402

J15B

SSQ-108-01-G-S

1 2 3 4 5 6 7 8

J11

1 2 3 4 5 6 7

8

9

10 11

12 13 15 17 19

14

16

18

20

JP12 Header 1X2

1

2

SAMA5D2-PTC-EK

Appendix A. Schematics and Layouts

DS50002709B-page 60

6. Revision History

6.1 DS50002709B - 09/2019

Changes

5. Appendix A. Schematics and Layouts: updated all schematics and layouts

6.2 DS50002709A - 12/2017

Changes

First issue.

SAMA5D2-PTC-EK

Revision History

DS50002709B-page 61

SAMA5D2-PTC-EK

The Microchip Website

Microchip provides online support via our website at http://www.microchip.com/. This website is used to make files and information easily available to customers. Some of the content available includes:

• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software

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To register, go to http://www.microchip.com/pcn and follow the registration instructions.

Customer Support

Users of Microchip products can receive assistance through several channels:

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Customers should contact their distributor, representative or ESE for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in this document.

Technical support is available through the website at: http://www.microchip.com/support

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Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Legal Notice

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with

DS50002709B-page 62

SAMA5D2-PTC-EK

your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their respective companies.

©

ISBN: 978-1-5224-5002-3

AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink, CoreSight, Cortex, DesignStart, DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore, Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS, ULINKpro, µVision, Versatile are trademarks or registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

Quality Management System

For information regarding Microchip’s Quality Management Systems, please visit http://www.microchip.com/quality.

DS50002709B-page 63

Worldwide Sales and Service

AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/support

Web Address:

http://www.microchip.com

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Austin, TX

Tel: 512-257-3370

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Tel: 774-760-0087

Fax: 774-760-0088

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

Detroit

Novi, MI

Tel: 248-848-4000

Houston, TX

Tel: 281-894-5983

Indianapolis

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Fax: 317-773-5453

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Fax: 43-7242-2244-393

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Sweden - Gothenberg

Tel: 46-31-704-60-40

Sweden - Stockholm

Tel: 46-8-5090-4654

UK - Wokingham

Tel: 44-118-921-5800

Fax: 44-118-921-5820

DS50002709B-page 64

Microchip SAMA5D2-PTC-EK User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Scope

Table of Contents

1. Introduction

1.1 Document Layout

1.2 Recommended Reading

2. Product Overview

2.1 SAMA5D2-PTC-EK Features

2.2 SAMA5D2-PTC-EK Content

2.3 Evaluation Kit Specifications

2.4 Power Sources

3. Board Components

3.1 Board Overview

3.1.1 Default Jumper Settings

3.1.2 Connectors on Board

3.2 Function Blocks

3.2.1 Processor

3.2.2 Power Supply Topology and Power Distribution

3.2.2.1 Input Power Options

3.2.2.2 Power Supply Requirements and Restrictions

3.2.2.3 Power-up and Power-down Considerations

3.2.2.4 Power Management

3.2.2.5 Supply Group Configuration

VDDFUSE

3.2.2.7 Backup Power Supply

3.2.3 Reset Circuitry

3.2.4 Shutdown Circuitry

3.2.5 Push Button Switches

3.2.6 Clock Circuitry

3.2.7 Memory

3.2.7.1 Memory Organization

3.2.7.2 DDR2/SDRAMs

3.2.7.3 DDR_CAL Analog Input

3.2.7.4 NAND Flash

3.2.7.5 NAND Flash CS Disable

3.2.8 Additional Memories

3.2.8.1 Serial Flash

3.2.8.2 QSPI Serial Flash

3.2.8.3 CS Disable

3.2.8.4 Serial EEPROM with Unique MAC Address

3.2.9 Secure Digital Multimedia Card (SDMMC) Interface

3.2.9.1 Secure Digital Multimedia Card (SDMMC) Controller

3.2.9.2 SDMMC0 Card Connector

3.2.9.3 SDMMC0 VDDHC Voltage Switching

3.2.9.4 SDMMC1 Card Connector

3.2.10 Communication Interfaces

3.2.10.1 Ethernet 10/100 (GMAC) Port

3.2.10.2 USB Host/Device A, B

3.2.10.3 USB-A Interface

3.2.10.4 USB-A VBUS Detection

3.2.10.5 USB-B Interface

3.2.10.5.1 USB-B Power Switch

3.2.10.6 HSIC

3.3 External Interfaces

3.3.1 LCD TFT Interface

3.3.1.1 LCD Interface

3.3.1.2 LCD Expansion Header

3.3.1.3 LCD Power

3.3.1.4 LCD Connector JX

3.3.2 RGB LED

3.4 Debugging Capabilities

3.4.1 Debug JTAG

3.4.2 Embedded Debugger (J-Link-OB) Interface

3.4.2.1 Disabling J-Link-OB (ATSAM3U4C)

3.4.3 Hardware UART via CDC

3.4.3.1 Board Edge Connector

3.5 PIO Usage on Expansion Connectors

3.5.1 PIOBU Interface

3.5.2 mikroBUS Interface

3.5.3 XPRO Interface

3.5.4 Miscellaneous PIOB[0-7]

4. Installation and Operation

4.1 System and Configuration Requirements

4.2 Board Setup

5. Appendix A. Schematics and Layouts

6. Revision History

6.1 DS50002709B - 09/2019