MICROCHIP rfRXD0420, rfRXD0920 User Manual

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rfRXD0420/0920

UHF ASK/FSK/FM Receiver

Features:

• Low cost single conversion superheterodyne
receiver architecture

• Compatible with rfPIC™ and rfHCS series of RF
transmitters

®

• Easy interface to PICmicro
(MCU) and K

EELOQ

®

microcontroller

decoders

• VCO phase locked to quartz crystal reference:

- Narrow receiver bandwidth

- Maximizes range and interference immunity

• Selectable LNA gain control for improved dynamic
range

• Selectable IF bandwidth via external ceramic IF
filter

• Received Signal Strength Indicator (RSSI) for
signal strength indication (FSK, FM) and ASK
demodulation

• FSK/FM quadrature (phase coincidence) detector
demodulator

• 32-Lead LQFP package

UHF ASK/FSK Receiver:

• Single frequency receiver set by crystal frequency

• Receive frequency range:

Device Frequency Range

rfRXD0420 300 MHz to 450 MHz

rfRXD0920 800 MHz to 930 MHz

• Maximum data rate:

- ASK: 80 Kbps NRZ

- FSK: 40 Kbps NRZ

• IF frequency range: 455 kHz to 21.4 MHz

• RSSI range: 70 dB

• Frequency deviation range: ±5 kHz to ±120 kHz

• Maximum FM modulation frequency: 15 kHz

Pin Diagram:

LNA

LNA

LQFP

V

SS

GAIN

OUT

1IF

IN

V

SS

1IF+

1IF­V

DD

VDD

LNAINVSSLF

323130

1
2
3

rfRXD0420

4
5

rfRXD0920

6
7
8

101112

9

2IFINVSS

1IFOUT

29

FBC1

ENRX

28

13

14

VDD

FBC2

VDD

272526

15

2IF

OUT

XTAL

16

DEM

IN

SS

V

24
23
22
21
20
19
18
17

DEM
DEM

SS

V

RSSI
OPA+
OPA-

OPA

DD

V

Applications:

• Wireless remote command and control

• Wireless security systems

• Remote Keyless Entry (RKE)

• Low power telemetry

• Low power FM receiver

• Home automation

• Remote sensing

Bi-CMOS Technology:

• Wide operating voltage range

• Low current consumption in Active and Standby
modes

- rfRXD0420

- 8.2 mA (typical, LNA High Gain mode)

- <100 nA standby

- rfRXD0920

- 9.2 mA (typical, LNA High Gain mode)

- <100 nA standby

• Wide temperature range:

- Industrial: -40°C to +85°C

OUT
OUT

­+

 2003 Microchip Technology Inc. Preliminary DS70090A-page 1

rfRXD0420/0920

1.0 DEVICE OVERVIEW

The rfRXD0420/0920 are low cost, compact single
frequency short-range radio receivers requiring only a
minimum number of external components for a
complete receiver system. The rfRXD0420 covers the
receive frequency range of 300 MHz to 450 MHz and
the rfRXD0920 covers 800 MHz to 930 MHz. The
rfRXD0420 and rfRXD0920 share a common architec­ture. They can be configured for Amplitude Shift Keying
(ASK), Frequency Shift Keying (FSK), or FM modula­tion. The rfRXD0420/0920 are compatible with rfPIC™
and rfHCS series of RF transmitters.

• High frequency stability over temperature and
power supply variations

• Low spurious signal emission

• High large-signal handling capability with
selectable LNA gain control for improved dynamic
range

• Selectable IF bandwidth via external low cost
ceramic IF filter. The IF Frequency range is
selectable between 455 kHz to 21.4 MHz. This
facilitates the use of readily available low cost

10.7 MHz ceramic IF filters in a variety of
bandwidths.

• ASK or FSK for digital data reception

• FM modulation for analog signal reception

• FSK/FM demodulation using quadrature detector
(phase coincidence detector)

• Received Signal Strength Indication (RSSI) for
signal strength indication and ASK detection

• Wide supply voltage range

• Low active current consumption

• Very low standby current

The rfRXD0420/0920 is a single conversion superhet­erodyne architecture. A block diagram is illustrated in
Figure 1-1. The rfRXD0420/0920 consists of:

• Low-noise amplifier (LNA) - Gain selectable

• Mixer for down-conversion of the RF signal to the
Intermediate Frequency (IF) followed by an IF
preamplifier

• Fully integrated Phase-Locked Loop (PLL)
frequency synthesizer for generation of the Local
Oscillator (LO) signal. The frequency synthesizer
consists of:

- Crystal oscillator

- Phase-frequency detector and charge pump

- High-frequency Voltage Controlled Oscillator

(VCO)

- Fixed feedback divider

- rfRXD0420 = divide by 16

- rfRXD0920 = divide by 32

• IF limiting amplifier to amplify and limit the IF
signal and for Received Signal Strength Indication
(RSSI) generation

• Demodulator (DEMOD) section consists of a
phase detector (MIXER2) and amplifier creating a
quadrature detector (also known as a phase
coincidence detector) to demodulate the IF signal
in FSK and FM modulation applications

• Operational amplifier (OPA) that can be config­ured as a comparator for ASK or FSK data
decision or as a filter for FM modulation.

• Bias circuitry for bandgap biasing and circuit
shutdown

DS70090A-page 2 Preliminary  2003 Microchip Technology Inc.

FIGURE 1-1: rfRXD0420/0920 BLOCK DIAGRAM

-

19

OPA-

OPA

OPA

18

VDD

17

DEM

IN

1615

2IF

OUT

VDD

14

FBC2

+-

DEMOD

OPA+

MIXER2

rfRXD0420/0920

20

21

RSSI

VSS

22

DEM

OUT+

+-

OUT-

DEM

24 23

FBC1

IN

2IF

VSS

10

OUT

1IF

VDD

8

IF Preamp

1IF-

76 9 11 12 13

1IF+

VSS

5

MIXER1

1IF

IN

LNA

OUT

34

GAIN

LNA

2

VSS

1

DD

V

32

with RSSI

IF Limiting Amplifier

Frequency

Synthesizer

16: rfRXD0420

32: rfRXD0920

Fixed Divide by

LNA

IN

LNA

31

Crystal

Oscillator

and

Charge Pump

Phase Detector

Voltage

Oscillator

Controlled

SS

V

30

Bias

VSS

25

XTAL

VDD

27

ENRX

28

LF

29 26

 2003 Microchip Technology Inc. Preliminary DS70090A-page 3

rfRXD0420/0920

TABLE 1-1: rfRXD0420/0920 PINOUT I/O DESCRIPTION

Pin Name Pin Number Pin Type Buffer Type Description

LNA

GAIN 2 I CMOS LNA gain control (with hysteresis)

OUT 3 O Analog LNA output (open collector)

LNA

IN 4 I Analog 1st IF stage input

1IF

1IF+ 6 -- Analog MIXER1 bias (open collector)

1IF- 7 -- Analog MIXER1 bias (open collector)

OUT 9 O Analog 1st IF stage output

1IF

IN 11 I Analog 2nd IF stage input

2IF

FBC1 12 -- Analog Limiter IF Amplifier external feedback capacitor

FBC2 13 -- Analog Limiter IF Amplifier external feedback capacitor

OUT 15 O Analog 2nd IF stage output

2IF

DEM

IN 16 I Analog Demodulator input

OPA 18 O Analog Operational amplifier output

OPA- 19 I Analog Operational amplifier input (negative)

OPA+ 20 I Analog Operational amplifier input (positive)

RSSI 21 O Analog Received signal strength indicator output

OUT+ 23 O Analog Demodulator output (positive)

DEM

OUT- 24 O Analog Demodulator output (negative)

DEM

XTAL 26 I Analog Crystal oscillator input

ENRX 28 I CMOS Receiver enable input

LF 29 I Analog External loop filter connection. Common node of

charge pump output and VCO tuning input.

IN 31 I Analog LNA input

LNA

V

DD 8, 14, 17, 27, 32 P Positive supply

SS 1, 5, 10, 25, 30 P Ground reference

V

Legend: I = Input, O = Output, I/O = Input/Output, P = Power, CMOS = CMOS compatible input or output

DS70090A-page 4 Preliminary  2003 Microchip Technology Inc.

rfRXD0420/0920

A

2.0 CIRCUIT DESCRIPTION

This section gives a circuit description of the internal
circuitry of the rfRXD0420/0920 receiver. External
connections and components are given in the
APPLICATION CIRCUITS section.

2.1 Bias Circuitry

Bias circuitry provides bandgap biasing and circuit
shutdown capabilities. The ENRX (Pin 28) modes are
summarized in Table 2-1. The ENRX pin is a CMOS
compatible input and is internally pulled down to Vss.

TABLE 2-1: BIAS CIRCUITRY CONTROL

(1)

ENRX

0 Standby mode

1 Receiver enabled

Note 1: ENRX has internal pull-down to Vss

2.2 Frequency Synthesizer

The Phase-locked Loop (PLL) frequency synthesizer
generates the Local Oscillator (LO) signal. It consists
of:

• Crystal oscillator

• Phase-frequency detector and charge pump

• Voltage Controlled Oscillator (VCO)

• Fixed feedback divider:

- rfRXD0420 = divide by 16

- rfRXD0920 = divide by 32

Description

The PLL consists of a phase-frequency detector,
charge pump, voltage-controlled oscillator (VCO), and
fixed divide-by-16 (rfRXD0420) or divide-by-32
(rfRXD0920) divider. The rfRXD0420/0920 employs a
charge pump PLL that offers many advantages over
the classical voltage phase detector PLL: infinite pull-in
range and zero steady state phase error. The charge
pump PLL allows the use of passive loop filters that are
lower cost and minimize noise. Charge pump PLLs
have reduced flicker noise thus limiting phase noise.

An external loop filter is connected to pin LF (Pin 29).
The loop filter controls the dynamic behavior of the
PLL, primarily lock time and spur levels. The applica­tion determines the loop filter requirements.

The VCO gain for the rfRXD0420/0920 receivers are
listed in Table 2-2.

TABLE 2-2: PLL PARAMETERS

Device

K

VCO

(1)

rfRXD0420 250 MHz/V at

433 MHz

rfRXD0920 300 MHz/V at

868 MHz

Note 1: Typical value

The LF pin is illustrated in Figure 2-2.

(1)

ICP

Divider

60 µA16

60 µA32

FIGURE 2-2: BLOCK DIAGRAM OF LOOP

FILTER PIN

2.2.1 CRYSTAL OSCILLATOR

The internal crystal oscillator is a Colpitts type oscilla­tor. It provides the reference frequency to the PLL. A
crystal is normally connected to the XTAL (Pin 26) and
ground. The internal capacitance of the crystal oscilla­tor is 15 pF. Alternatively, a signal can be injected into
the XTAL pin from a signal source. The signal should
be AC coupled via a series capacitor at a level of
approximately 600 mV

.

pp

The XTAL pin is illustrated in Figure 2-1.

FIGURE 2-1: BLOCK DIAGRAM OF

XTAL PIN

VDD

VDD VDD

XTAL

26

VSS

50 kΩ

30 pF

30 pF

VSS VSS

40 µ

VDD

LF

29

VSS

200 Ω

400 Ω

4 pF

VSS

VSS

2.3 Low Noise Amplifier

The Low-Noise Amplifier (LNA) is a high-gain amplifier
whose primary purpose is to lower the overall noise
figure of the entire receiver thus enhancing the receiver
sensitivity. The LNA is an open-collector cascode
design. The benefits of a cascode design are:

• high gain with low noise

• high-frequency

• wide bandwidth

• low effective input capacitance with stable input
impedance

• high output resistance

• high reverse isolation that provides improved
stability and reduces LO leakage

 2003 Microchip Technology Inc. Preliminary DS70090A-page 5

rfRXD0420/0920

Approximate LNA noise figures are listed in Table 2-3.

TABLE 2-3: LNA NOISE FIGURES

Device

Noise Figure

rfRXD0420 TBD

rfRXD0920 TBD

Note 1: Approximate value

LNA

IN (Pin 31) has an input impedance of approxi-

mately 26 Ω || 2 pF single-ended.

OUT (Pin 3) has an open-collector output and is

LNA
pulled up to V

DD via a tuned circuit.

Important: To ensure LNA stability the V

must be connected to a low impedance ground.

The LNA pins are illustrated in Figure 2-3.

(1)

SS pin (Pin 1)

FIGURE 2-3: BLOCK DIAGRAM OF LNA

PINS

LNA

VSS

V

VSS

OUT

3

DD

VSS

1

LNA

31

1.6V

0.8V

VDD

5 kΩ

IN

VSS

The gain of the LNA can be selected between High and
Low Gain modes by the LNA

GAIN pin (Pin 2). LNAGAIN

is a CMOS input with hysteresis. Table 2-4 summarizes
the voltage levels and modes for LNA gain.

In the High Gain mode the LNA operates normally. In
Low Gain mode the gain of the LNA is reduced approx­imately 25 dB, reduces total supply current, and
increases maximum input signal levels (see Electrical
Characteristics section for values).

TABLE 2-4: LNA GAIN CONTROL

LNAGAIN Description

< 0.8 V High Gain mode

> 1.4 V Low Gain mode

The 1IF+ (Pin 6) and 1IF- (Pin 7) are bias connections
to the MIXER1 balanced collectors. Both pins are
open-collector outputs and are individually pulled up to

DD by a load resistor. The MIXER1 bias pins are illus-

V
trated in Figure 2-5.

1IF

OUT (Pin 9) has an approximately 330 Ω single-

ended output impedance. The 330 Ω impedance
provides a direct match to low cost ceramic IF filters.
The 1IF

OUT pins is illustrated in Figure 2-6.

FIGURE 2-4: BLOCK DIAGRAM OF MIXER1

PIN

1IF

4

VDD

IN

VSS

13 Ω

13 Ω

500 µA

VSS

FIGURE 2-5: BLOCK DIAGRAM OF MIXER1

BIAS PINS

VDD VDD

VSS

20 pF

500 µA

1IF-

7

VSS

1IF+

6

20 pF

VSS

500 µA

VSS

FIGURE 2-6: BLOCK DIAGRAM OF IF

PREAMP PIN

VDD VDD

6.8 kΩ

130 Ω

230 µA

VSS

1IF

9

VDD

OUT

VSS

2.5 IF Limiting Amplifier with RSSI

2.4 MIXER1 and IF Preamp

MIXER1 performs down-conversion of the RF signal to
the Intermediate Frequency (IF) and is followed by an

The IF Limiting Amplifier amplifies and limits the IF
signal at the 2IF

IN pin (Pin 11). It also generates the

Received Signal Strength Indicator (RSSI) signal
(Pin 21).

IF preamplifier.

IN (Pin 4) has an approximately 33 Ω single-ended

1IF
input impedance. The 1IF

IN pin is illustrated in Figure 2-

4.

2.5.1 IF LIMITING AMPLIFIER

Magnitude control circuitry is used in the last stage of
the receiver to keep the signal constant for demodula­tion. It can consist of a limiting or Automatic Gain
Control (AGC) amplifier. A limiting amplifier is

DS70090A-page 6 Preliminary  2003 Microchip Technology Inc.

rfRXD0420/0920

employed in this design because it can handle a larger
dynamic range while consuming less power with simple
circuitry than AGC circuitry.

The internal resistance of the 2IF

IN pin is approximately

2.2 kΩ. In order to terminate ceramic IF filters whose
output impedance is 330 Ω, a 390 Ω resistor can be
paralleled to the 2IF

IN and FBC2 pins.

FBC1 (Pin 12) and FBC2 (Pin 13) are connected to
external feedback capacitors.

The IF Limiting Amplifier pins are illustrated in
Figures 2-7 and 2-8.

FIGURE 2-7: BLOCK DIAGRAM OF IF

LIMITING AMPLIFIER INPUT
PINS

2IF

11

FBC2

13

VDD

IN

VSS

VDD

VSS

2.2 kΩ

2.2 kΩ

200 µA

Vss

VDD

FBC1

12

VSS

FIGURE 2-8: BLOCK DIAGRAM OF IF

LIMITING AMPLIFIER OUTPUT
PIN

VDD

VDD

OUT

2IF

15

VSS

40 µA

VSS

2.5.2 RECEIVED SIGNAL STRENGTH
INDICATOR (RSSI)

The RSSI signal is proportional to the log of the signal
at 2IF

IN. The 2IFIN input RSSI range is approximately

40 µV to 160 mV. The slope of the RSSI output is
approximately 26 mV/dB of RF signal.

The RSSI output has an internal 36 kΩ resister to Vss
fed by a current source. This resistor converts the
RSSI current to voltage.

For Amplitude Shift Keying (ASK) demodulation, RSSI
is compared to a reference voltage (static or dynamic).
Post detector filtering is easily implemented by
connecting a capacitor to ground from the RSSI pin
effectively creating an RC filter with the internal 36 kΩ
resistor.

For FSK and FM demodulation, the RSSI represents
the received signal strength of the incoming RF signal.

The RSSI pin is illustrated in Figure 2-9.

FIGURE 2-9: BLOCK DIAGRAM OF RSSI

PIN

VDD

RSSI

21

50 Ω

VSS

I (Pi)

36 kΩ

VSS

2.6 Demodulator

The demodulator (DEMOD) section consists of a phase
detector (MIXER2) and amplifier creating a quadrature
detector (also known as a phase coincidence detector)
to demodulate the IF signal in FSK and FM modulation
applications. The quadrature detector provides all the
IF functions required for FSK and FM demodulation
with only a few external parts.

The in-phase signal comes directly from the output of
the IF limiting amplifier to MIXER2. The quadrature
signal is created by an external tuned circuit from the
output of the IF limiting amplifier (2IF
coupled to the MIXER2 DEM
impedance of the DEM

IN (Pin 16) input. The input

IN pin is approximately 47 kΩ.

The external tuned circuit can be constructed from sim­ple inductor-capacitor (LC) components but will require
one of the elements to be tunable. A no-tune solution
can be constructed with a ceramic discriminator.

The output voltage of the DEMOD amplifier (DEMout+
and DEMout-, Pins 23 and 24) depends on the peak
deviation of the FSK or FM signal and the Q of the
external tuned circuit. DEMout+ and DEMout- are high
impedance outputs with only a 20 µA current capability.

The Demodulator pins are illustrated in Figures 2-10
and 2-11.

FIGURE 2-10: BLOCK DIAGRAM OF

DEMODULATOR INPUT PIN

VDD

VDD VDD

DEM

IN

16

VSS

OUT, Pin 15) AC-

47 kΩ

 2003 Microchip Technology Inc. Preliminary DS70090A-page 7

rfRXD0420/0920

FIGURE 2-11: BLOCK DIAGRAM OF

DEMODULATOR OUTPTUT
PINS

VDD

VSS

V

VSS

50 Ω

20 µA20 µA

VSS VSS

DD

50 Ω

20 µA20 µA

VSS VSS

DEM

OUT+

23

DEM

OUT-

24

2.7 Operational Amplifier

The internal operational amplifier (OPA) can be
configured as a comparator for ASK or FSK or as a filter
for FM modulation applications.

The Op Amp pins are illustrated in Figures 2-12 and
2-13.

FIGURE 2-12: BLOCK DIAGRAM OF OP AMP

INPUT PINS

VDD

VDD VDD

OPA-

19

50 Ω 50 Ω

VSS VSS

20 µA

OPA+

20

FIGURE 2-13: BLOCK DIAGRAM OF OP AMP

OUTPUT PIN

VDD

OPA

18

VSS

VDD

50 Ω

VSS

DS70090A-page 8 Preliminary  2003 Microchip Technology Inc.

rfRXD0420/0920

)

3.0 APPLICATION CIRCUITS

This section provides general information on applica­tion circuits for the rfRXD0420/0920 receiver. The
following connections and external components
provide starting points for designs and list the minimum
circuitry recommended for general purpose
applications.

Performance of the radio system (transmitter and
receiver) is affected by component selection and the
environment in which it operates. Each system design
has its own unique requirements. Specifications for a
particular design requires careful analysis of the appli­cation and compromises for a practical implementation.

3.1 General

This subsection lists connections and components that
are common between applications. The following
subsections give specific circuit connections and
components for ASK, FSK and FM applications.

3.1.1 BYPASS CAPACITORS

Bypass capacitors should be placed as physically close
as possible to V
respectively. Additional bypassing and board level low­pass filtering of the power supply may be required
depending on the application.

3.1.2 FREQUENCY PLANNING

The rfRXD0420/0920 receivers are single-conversion
superheterodyne architecture with a single IF
frequency. The receive frequency is set by the crystal
frequency (f
a majority of applications an external crystal is
connected to XTAL (Pin 26). Figure 3-1 illustrates an
example circuit with an optional trim capacitor.

FIGURE 3-1: XTAL EXAMPLE CIRCUIT

DD pins 8, 14, 17, 27 and 32

) and intermediate frequency (fif). For

XTAL

WITH OPTIONAL TRIM
CAPACITOR

XTAL

26

C TRIM

(OPTIONAL

X1

effect the trim capacitor has on the receive frequency
for the rfRXD0420 at 433.92 MHz. Keep in mind that
this graph represents one example circuit and the
actual results depends on the crystal and PCB layout.

FIGURE 3-2: RECEIVE FREQUENCY VS.

TRIM CAPACITANCE

434.10

434.05

434.00

433.95

433.90

433.85

433.80

Receive Frequency (MHz)

433.75

82 pF

0 ohms

68 pF

56 pF

47 pF

Trim Capacitor (pF)

39 pF

33 pF

27 pF

22 pF

18 pF

15 pF

12 pF

10 pF

5 pF

Note that a 0 Ω resistor, in the lower left of the graph,
represents an infinite capacitance. This will be the
lowest frequency obtainable for the crystal and PCB
combination.

Calculation of the crystal frequency requires knowl­edge of the receive frequency (f
frequency (f

). Figure 3-3 is a worksheet to assist the

if

) and intermediate

rf

designer in calculating the crystal frequency. Table 3-1
lists crystal frequencies for popular receive frequen­cies. Table 3-2 lists crystal parameters required for
ordering crystals. For background information on
crystal selection see Application Note AN826, Crystal
Oscillator Basics and Crystal Selection for rfPIC
PICmicro

®

Devices.

TM

and

TABLE 3-1: CRYSTAL FREQUENCIES FOR

POPULAR RECEIVE
FREQUENCIES

Receive

Frequency

rfRXD0420

315 MHz 20.35625 MHz

433.92 MHz 26.45125 MHz

rfRXD0920

868.3 MHz 26.8 MHz

915 MHz 28.259375 MHz

(1) Low-side injection (2) High-side injection

Crystal

Frequency

(2)

(1)

(1)

(1)

TABLE 3-2: CRYSTAL PARAMETERS

Parameter Value

The crystal load capacitance should be specified to
include the internal load capacitance of the XTAL pin of
15 pF plus PCB stray capacitance (approximately 2 to
3 pF). A trim capacitor can be used to trim the crystal
on frequency within the limitations of the crystal’s trim
sensitivity and pullability. Figure 3-2 illustrates the

 2003 Microchip Technology Inc. Preliminary DS70090A-page 9

Frequency: (see Figure 3-1)

Mode: Fundamental

Load Capacitance: 15-20 pF

ESR: 60 Ω Maximum

These values are for design guidance only.

rfRXD0420/0920

FIGURE 3-3: FREQUENCY PLANNING WORKSHEET

Step 1: Identify receive (f

= ____________________

f

rf

f

= ____________________

if

Step 2: Calculate crystal frequencies for high- and low-side injection:

High-side Injection

f

lo-HIGH

=

=

= f

f

XTAL-HIGH

Low-side Injection

f

XTAL-LOW

Step 3: Calculate Local Oscillator (LO) frequencies (f

High-side Injection

Low-side Injection

) and IF frequency (fif).

rf

( f

+ f

rf

PLL divide ratio 16 if rfRXD0420

( f

- f

rf

PLL divide ratio 16 if rfRXD0420

XTAL-HIGH

)

if

)

if

x PLL Divide Ratio

=

=

( _________ + _________ )

32 if rfRXD0920

( _________ - _________ )

32 if rfRXD0920

) using f

lo

= _________ x

XTAL-HIGH

f

rf

f

x PLL divide ratio

XTAL

= _______________

= _______________

and f

XTAL-LOW

16 if rfRXD0420

32 if rfRXD0920

f

f

lo

:

= _____________

if

= f

f

lo-LOW

Step 4: Select high-side injection (f

that is between the ranges of:

Step 5: From the chosen injection mode in Step 4, write the selected crystal frequency (f

injection mode.

f

XTAL

Step 6: Calculate image frequency (f

if High-side Injection

f

rf-image

if Low-side Injection

f

rf-image

Note: Image frequency should be sufficiently filtered by the preselector for the application.

XTAL-LOW

= ____________________ High-side Injection Low-side Injection

= frf + (2 x fif)

= frf - (2 x fif)

x PLL Divide Ratio

) or low-side injection (f

lo-HIGH

Device LO Frequency Range

rfRXD0420 300 to 430 MHz

rfRXD0920 800 to 915 MHz

rf-image

= ___________ + ( 2 x ___________ ) = ______________

= ___________ - ( 2 x ___________ ) = ______________

= _________ x

) for the Injection mode chosen:

16 if rfRXD0420

32 if rfRXD0920

) that corresponds to the LO frequency

lo-LOW

(circle one)

= _____________

) and circle

XTAL

DS70090A-page 10 Preliminary  2003 Microchip Technology Inc.