Microchip PIC33FJ32MC202, PIC33FJ32MC204, PIC33FJ16MC304 Specifications

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Page 1

dsPIC33FJ32MC202/204 and

dsPIC33FJ16MC304

16-bit Digital Signal Controllers (up to 32 KB Flash and

2 KB SRAM) with Motor Control and Advanced Analog

Operating Conditions

• 3.0V to 3.6V, -40ºC to +150ºC, DC to 20 MIPS

• 3.0V to 3.6V, -40ºC to +125ºC, DC to 40 MIPS

Core: 16-bit dsPIC33F CPU

• Code-efficient (C and Assembly) architecture

• Two 40-bit wide accumulators

• Single-cycle (MAC/MPY) with dual data fetch

• Single-cycle mixed-sign MUL plus hardware divide

Clock Management

• 2% internal oscillator

• Programmable PLLs and oscillator clock sources

• Fail-Safe Clock Monitor (FSCM)

• Independent Watchdog Timer (WDT)

• Fast wake-up and start-up

Power Management

• Low-power management modes (Sleep, Idle, Doze)

• Integrated Power-on Reset and Brown-out Reset

• 1.35 mA/MHz dynamic current (typical)

• 55 μA IPD current (typical)

High-Speed PWM

• Up to four PWM pairs with independent timing

• Dead time for rising and falling edges

• 12.5 ns PWM resolution

• PWM support for:

- DC/DC, AC/DC, Inverters, PFC, Lighting

- BLDC, PMSM, ACIM, SRM

• Programmable Fault inputs

• Flexible trigger configurations for ADC conversions

Advanced Analog Features

• ADC module:

- Configurable as 10-bit, 1.1 Msps with four S&H or 12-bit, 500 ksps with one S&H

• Six analog inputs on 28-pin devices and up to nine analog inputs on 44-pin devices

• Flexible and independent ADC trigger sources

Timers/Output Compare/Input Capture

• Three 16-bit timers/counters. Can pair up two to make one 32-bit.

• Two Output Capture modules configurable as timers/counters

• Four Input Capture modules

• Peripheral Pin Select (PPS) to allow function remap

Communication Interfaces

• One UART module (10 Mbps)

• With support for LIN 2.0 protocols and IrDA

• One 4-wire SPI module (15 Mbps)

• One I

• PPS to allow function remap

C™ module (up to 1 Mbaud) with SMBus

support

Input/Output

• Sink/Source up to 10 mA (pin specific) for standard VOH/VOL, up to 16 mA (pin specific) for non-standard VOH1

• 5V-tolerant pins

• Selectable open drain, pull-ups, and pull-downs

• Up to 5 mA overvoltage clamp current

• External interrupts on all I/O pins

Qualification and Class B Support

• AEC-Q100 REVG (Grade 0 -40ºC to +150ºC)

• Class B Safety Library, IEC 60730

Debugger Development Support

• In-circuit and in-application programming

• Two program and two complex data breakpoints

• IEEE 1149.2-compatible (JTAG) boundary scan

• Trace and run-time watch

Packages

Type SPDIP SOIC SSOP QFN-S QFN TQFP

Pin Count 28 28 28 28 44 44

Contact Lead/Pitch .100'' 1.27 0.65 0.65 0.65 0.80

I/O Pins 21 21 21 21 35 35

Dimensions 1.365x.285x.135'' 17.9xx7.50x2.05 10.2x5.3x1.75 6x6x0.9 8x8x0.9 10x10x1

Note: All dimensions are in millimeters (mm) unless specified.

Page 2

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

dsPIC33FJ32MC202/204 and

dsPIC33FJ16MC304 Product Families

The device names, pin counts, memory sizes and peripheral availability of each device are listed below. The following pages show their pinout diagrams.

TABLE 1: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 CONTROLLER FAMILIES

Remappable Peripherals

(3)

Device Pins

RAM (Kbyte)

16-bit Timer

Input Capture

Remappable Pins

Program Flash Memory (Kbyte)

(1)

dsPIC33FJ32MC202 28 32 2

dsPIC33FJ32MC204 44 32 2

dsPIC33FJ16MC304 44 16 2

426ch

(1)

426ch

(1)

426ch

Note 1: Only two out of three timers are remappable.

2: Only PWM fault inputs are remappable. 3: Only two out of three interrupts are remappable.

C™

10-Bit/12-Bit ADC

121

I/O Pins

Packages

SPDIP

SOIC

SSOP

UART

Interface

Standard PWM

Output Compare

Motor Control PWM

Quadrature Encoder

(2)

1 1 3 1 1ADC,

(2)

2ch

SPI

External Interrupts

6 ch

QFN-S

(2)

2ch

1 1 3 1 1ADC,

(2)

1 1 3 1 1ADC,

(2)

9 ch

135QFN

TQFP

135QFN

TQFP

Page 3

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

dsPIC33FJ32MC202

MCLR

VSS

VDD

AN0/VREF+/CN2/RA0

AN1/V

REF-/CN3/RA1

AVDD AVSS

PGED1/AN2/C2IN-/RP0

(1)

/CN4/RB0

PGEC3/ASCL1/RP6

(1)

/CN24/RB6

SOSCO/T1CK/CN0/RA4

SOSCI/RP4

(1)

/CN1/RB4

OSC2/CLKO/CN29/RA3

OSC1/CLKI/CN30/RA2

CAP

INT0/RP7/CN23/RB7

TDO/PWM2L1/SDA1/RP9

(1)

/CN21/RB9

TCK/PWM2H1/SCL1/RP8

(1)

/CN22/RB8

AN5/RP3

(1)

/CN7/RB3

AN4/RP2

(1)

/CN6/RB2

PGEC1/AN3/C2IN+/RP1

(1)

/CN5/RB1

1 2 3 4 5

6 7 8 9 10 11 12 13 14

28 27 26 25 24

23 22 21 20 19 18 17 16 15

PWM1L1/RP15

(1)

/CN11/RB15

PWM1H1/RP14

(1)

/CN12/RB14

PWM1L2/RP13

(1)

/CN13/RB13

PWM1H2/RP12

(1)

/CN14/RB12

PGED2/TDI/PWM1H3/RP10

(1)

/CN16/RB10

PGEC2/TMS/PWM1L3/RP11

(1)

/CN15/RB11

PGED3/ASDA1/RP5

(1)

/CN27/RB5

28-PIN SPDIP, SOIC, SSOP

28-Pin QFN-S

(2)

10 11

12 13 14

232425262728

dsPIC33FJ32MC202

MCLR

VSS

VDD

AN0/VREF+/CN2/RA0

AN1/V

REF-/CN3/RA1

AVSS

PGED1/EMUD1/AN2/C2IN-/RP0

(1)

/CN4/RB0

PGEC3/EMUC3/ASCL1/RP6

(1)

/CN24/RB6

SOSCO/T1CK/CN0/RA4

SOSCI/RP4/CN1/RB4

VSS

OSC2/CLKO/CN29/RA3

OSC1/CLKI/CN30/RA2

CAP

INT0/RP7

(1)

/CN23/RB7

TDO/PWM2L1/SDA1/RP9

(1)

/CN21/RB9

TCK/PWM2H1/SCL1/RP8

(1)

/CN22/RB8

AN5/RP3

(1)

/CN7/RB3

AN4/RP2

(1)

/CN6/RB2

PGEC1/EMUC1/AN3/C2IN+/RP1

(1)

/CN5/RB1

PWM1L1/RP15

(1)

/CN11/RB15

PWM1H1/RP14

(1)

/CN12/RB14

PWM1L2/RP13

(1)

/CN13/RB13

PWM1H2/RP12

(1)

/CN14/RB12

PGED2/EMUD2/TDI/PWM1H3/RP10

(1)

/CN16/RB10

PGEC2/EMUC2/TMS/PWM1L3/RP11

(1)

/CN15/RB11

PGED3/EMUD3/ASDA1/RP5

(1)

/CN27/RB5

Note 1: The RPn pins can be used by any remappable peripheral. See Ta b le 1 for the list of available

peripherals.

2: The metal plane at the bottom of the device is not connected to any pins and is recommended to

be connected to V

SS externally.

= Pins are up to 5V tolerant

Pin Diagrams

Page 4

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

44-Pin QFN

(2)

44434241403938373635

12131415161718192021

232

dsPIC33FJ32MC204

PGEC1/EMUC1/AN3/C2IN+/RP1

(1)

/CN5/RB1

PGED1/EMUD1/AN2/C2IN-/RP0

(1)

/CN4/RB0

AN1/V

REF-/CN3/RA1

AN0/V

REF+/CN2/RA0

MCLR

TMS/RA10

AVDDAVSS

PWM1L1/RP15

(1)

/CN11/RB15

PWM1H1/RP14

(1)

/CN12/RB14

TCK/RA7

SCL1/RP8

(1)

/CN22/RB8

INT0/RP7/CN23/RB7

PGEC3/EMUC3/ASCL1/RP6

(1)

/CN24/RB6

PGED3/EMUD3/ASDA1/RP5

(1)

/CN27/RB5

TDI/RA9

SOSCO/T1CK/CN0/RA4

RP21

(1)

/CN26/RC5

RP20

(1)

/CN25/RC4

RP19

(1)

/CN28/RC3

PWM1H2/RP12

(1)

/CN14/RB12

PGEC2/EMUC2/PWM1L3/RP11

(1)

/CN15/RB11

PGED2/EMUD2/PWM1H3/RP10

(1)

/CN16/RB10

CAP

VSS

RP25/CN19/RC9

RP24/CN20/RC8

PWM2L1/RP23

(1)

/CN17/RC7

PWM2H1/RP22

(1)

/CN18/RC6

SDA1/RP9

(1)

/CN21/RB9

PWM1L2/RP13

(1)

/CN13/RB13

AN4/RP2

(1)

/CN6/RB2

AN5/RP3

(1)

/CN7/RB3

AN6/RP16

(1)

/CN8/RC0

AN7/RP17

(1)

/CN9/RC1

AN8/RP18

(1)

/CN10/RC2

SOSCI/RP4

(1)

/CN1/RB4

VSS

OSC1/CLKI/CN30/RA2

OSC2/CLKO/CN29/RA3

TDO/RA8

dsPIC33FJ16MC304

= Pins are up to 5V tolerant

Note 1: The RPn pins can be used by any remappable peripheral. See Ta bl e 1 for the list of available

peripherals.

2: The metal plane at the bottom of the device is not connected to any pins and is recommended to

be connected to V

SS externally.

Pin Diagrams (Continued)

Page 5

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

8 7

29 30 31 32 33

23 24 25

363435937

SCL1/RP8

(1)

/CN22/RB8

INT0/RP7

(1)

/CN23/RB7

PGEC3/EMUC3/ASCL1/RP6

(1)

/CN24/RB6

PGED3/EMUD3/ASDA1/RP5

(1)

/CN27/RB5

TDI/RA9

SOSCO/T1CK/CN0/RA4

RP21

(1)

/CN26/RC5

RP20

(1)

/CN25/RC4

RP19/

(1)

CN28/RC3

PGEC1/EMUC1/AN3/C2IN+/RP1

(1)

/CN5/RB1

PGED1/EMUD1/AN2/C2IN-/RP0

(1)

/CN4/RB0

AN1/V

REF-/CN3/RA1

AN0/V

REF+/CN2/RA0

MCLR

TMS/RA10

AVDDAVSS

PWM1L1/RP15

(1)

/CN11/RB15

PWM1H1/RP14

(1)

/CN12/RB14

PWM1H2/RP12

(1)

/CN14/RB12

PGEC2/EMUC2/PWM1L3/RP11

(1)

/CN15/RB11

PGED2/EMUD2/PWM1H3/RP10

(1)

/CN16/RB10

CAP

VSS RP25

(1)

/CN19/RC9

RP24

(1)

/CN20/RC8

PWM2L1/RP23

(1)

/CN17/RC7

PWM2H1/RP22

(1)

/CN18/RC6

SDA1/RP9

(1)

/CN21/RB9

AN4/RP2

(1)

/CN6/RB2

AN5/RP3

(1)

/CN7/RB3

AN6/RP16

(1)

/CN8/RC0

AN7/RP17

(1)

/CN9/RC1

AN8/RP18

(1)

/CN10/RC2

SOSCI/RP4

(1)

/CN1/RB4

VSS

OSC1/CLKI/CN30/RA2

OSC2/CLKO/CN29/RA3

TDO/RA8

44-Pin TQFP

PWM1L2/RP13

(1)

/CN13/RB13

TCK/RA7

dsPIC33FJ32MC204 dsPIC33FJ16MC304

Note 1: The RPn pins can be used by any remappable peripheral. See Ta b le 1 for the list of available

peripherals.

= Pins are up to 5V tolerant

Pin Diagrams (Continued)

Page 6

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

Table of Contents

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Product Families.................................................................................................. 2

1.0 Device Overview .......................................................................................................................................................................... 9

2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers .......................................................................................... 13

3.0 CPU ............................................................................................................................................................................................ 17

4.0 Memory Organization ................................................................................................................................................................. 29

5.0 Flash Program Memory .............................................................................................................................................................. 55

6.0 Resets ....................................................................................................................................................................................... 61

7.0 Interrupt Controller ..................................................................................................................................................................... 71

8.0 Oscillator Configuration ............................................................................................................................................................ 101

9.0 Power-Saving Features ............................................................................................................................................................ 111

10.0 I/O Ports ................................................................................................................................................................................... 117

11.0 Timer1 ...................................................................................................................................................................................... 143

12.0 Timer2/3 feature ...................................................................................................................................................................... 147

13.0 Input Capture............................................................................................................................................................................ 151

14.0 Output Compare ....................................................................................................................................................................... 155

15.0 Motor Control PWM Module ..................................................................................................................................................... 159

16.0 Quadrature Encoder Interface (QEI) Module ........................................................................................................................... 173

17.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 179

18.0 Inter-Integrated Circuit™ (I

19.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 193

20.0 10-bit/12-bit Analog-to-Digital Converter (ADC) ....................................................................................................................... 199

21.0 Special Features ...................................................................................................................................................................... 211

22.0 Instruction Set Summary .......................................................................................................................................................... 219

23.0 Development Support............................................................................................................................................................... 227

24.0 Electrical Characteristics .......................................................................................................................................................... 231

25.0 High Temperature Electrical Characteristics ............................................................................................................................ 281

26.0 DC and AC Device Characteristics Graphs.............................................................................................................................. 291

27.0 Packaging Information.............................................................................................................................................................. 295

Appendix A: Revision History............................................................................................................................................................. 309

Index ................................................................................................................................................................................................. 321

The Microchip Web Site ..................................................................................................................................................................... 325

Customer Change Notification Service .............................................................................................................................................. 325

Customer Support .............................................................................................................................................................................. 325

Reader Response .............................................................................................................................................................................. 326

Product Identification System............................................................................................................................................................. 327

C™).............................................................................................................................................. 185

Page 7

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We wel- come your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

Page 8

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

Referenced Sources

This device data sheet is based on the following individual chapters of the “dsPIC33F/PIC24H Family Reference Manual”. These documents should be considered as the general reference for the operation of a particular module or device feature.

Note 1: To access the documents listed below,

browse to the documentation section of the dsPIC33FJ32MC204 product page of the Microchip web site (www.microchip.com) or select a family reference manual section from the following list.

In addition to parameters, features, and other documentation, the resulting page provides links to the related family reference manual sections.

• Section 1. “Introduction” (DS70197)

• Section 2. “CPU” (DS70204)

• Section 3. “Data Memory” (DS70202)

• Section 4. “Program Memory” (DS70202)

• Section 5. “Flash Programming” (DS70191)

• Section 7. “Oscillator” (DS70186)

• Section 8. “Reset” (DS70192)

• Section 9. “Watchdog Timer and Power-Saving Modes” (DS70196)

• Section 10. “I/O Ports” (DS70193)

• Section 11. “Timers” (DS70205)

• Section 12. “Input Capture” (DS70198)

• Section 13. “Output Compare” (DS70209)

• Section 14. “Motor Control PWM” (DS70187)

• Section 15. “Quadrature Encoder Interface (QEI)” (DS70208)

• Section 16. “Analog-to-Digital Converter (ADC)” (DS70183)

• Section 17. “UART” (DS70188)

• Section 18. “Serial Peripheral Interface (SPI)” (DS70206)

• Section 19. “Inter-Integrated Circuit™ (I

• Section 23. “CodeGuard™ Security” (DS70199)

• Section 25. “Device Configuration” (DS70194)

• Section 32. “Interrupts (Part III)” (DS70214)

C™)” (DS70195)

Page 9

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

1.0 DEVICE OVERVIEW

Note 1: This data sheet summarizes the features

of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the

“dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web

site (www.microchip.com) for the latest dsPIC33F/PIC24H Family Reference Manual sections.

2: Some registers and associated bits

described in this section may not be available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register and bit information.

This document contains device-specific information for the following Digital Signal Controller (DSC) devices:

• dsPIC33FJ32MC202

• dsPIC33FJ32MC204

• dsPIC33FJ16MC304

The dsPIC33F devices contain extensive Digital Signal Processor (DSP) functionality with a high performance 16-bit microcontroller (MCU) architecture.

Figure 1-1 shows a general block diagram of the core

and peripheral modules in the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams.

Page 10

OSC1/CLKI

OSC2/CLKO

DD, VSS

Timing

Generation

MCLR

Power-up

Time r

Oscillator

Star t- up Timer

Power-on

Reset

Watchdog

Time r

Brown-out

Reset

Precision

Reference

Band Gap

FRC/LPRC

Oscillators

Regulator

Voltage

VCAP

IC1,2,7,8

I2C1

PORTA

Note: Not all pins or features are implemented on all device pinout configurations. See “Pin Diagrams” for the specific pins

and features present on each device.

Instruction

Decode and

Control

PCH PCL

Program Counter

16-bit ALU

Instruction Reg

PCU

16 x 16

W Register Array

ROM Latch

EA MUX

Interrupt

Controller

PSV and Table Data Access

Control Block

Stac k

Control

Logic

Loop

Control

Logic

Data Latch

Address

Latch

Address Latch

Program Memory

Data Latch

Literal Data

Data Latch

Address

Latch

X RAM

Y RAM

Y Data Bus

X Data Bus

DSP Engine

Divide Support

Control Signals to Various Blocks

ADC1

Timers

PORTB

Address Generator Units

1-3

CNx

UART1

OC/

PWM1-2

QEI

PWM

2 Ch

PWM

6 Ch

Remappable

Pins

PORTC

SPI1

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

FIGURE 1-1: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 BLOCK DIAGRAM

Page 11

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

TABLE 1-1: PINOUT I/O DESCRIPTIONS

Pin Name

AN0-AN8 I Analog No Analog input channels.

CLKI CLKO

OSC1

OSC2

SOSCI SOSCO

CN0-CN30 I ST No Change notification inputs.

IC1-IC2 IC7-IC8

OCFA OC1-OC2

INT0 INT1 INT2

RA0-RA4 RA7-RA10

RB0-RB15 I/O ST No PORTB is a bidirectional I/O port.

RC0-RC9 I/O ST No PORTC is a bidirectional I/O port.

T1CK T2CK T3CK

U1CTS U1RTS U1RX U1TX

SCK1 SDI1 SDO1 SS1

SCL1 SDA1 ASCL1 ASDA1

TMS TCK TDI TDO

Legend: CMOS = CMOS compatible input or output; Analog = Analog input; P = Power

Type

I/O

I I

I I I

I/O ST NoNoPORTA is a bidirectional I/O port.

I I I

I/O

I/O I/O I/O I/O

I I I

ST = Schmitt Trigger input with CMOS levels; O = Output; I = Input PPS = Peripheral Pin Select

Buffer

Type

ST/CMOS—NoNoExternal clock source input. Always associated with OSC1 pin function.

ST/CMOS—NoNoOscillator crystal input. ST buffer when configured in RC mode; CMOS

ST/CMOS—NoNo32.768 kHz low-power oscillator crystal input; CMOS otherwise.

ST ST

—

ST ST ST

—

ST ST

—

ST ST ST ST

ST ST ST

—

PPS Description

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function.

otherwise. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes.

32.768 kHz low-power oscillator crystal output.

Can be software programmed for internal weak pull-ups on all inputs.

Yes

Capture inputs 1/2.

Yes

Capture inputs 7/8.

Yes

Compare Fault A input (for Compare Channels 1 and 2).

Yes

Compare outputs 1 through 2.

External interrupt 0.

Yes

External interrupt 1.

Yes

External interrupt 2.

Timer1 external clock input.

Yes

Timer2 external clock input.

Yes

Timer3 external clock input.

Yes

UART1 clear to send.

Yes

UART1 ready to send.

Yes

UART1 receive.

Yes

UART1 transmit.

Yes

Synchronous serial clock input/output for SPI1.

Yes

SPI1 data in.

Yes

SPI1 data out.

Yes

SPI1 slave synchronization or frame pulse I/O.

Synchronous serial clock input/output for I2C1.

Synchronous serial data input/output for I2C1.

Alternate synchronous serial clock input/output for I2C1.

Alternate synchronous serial data input/output for I2C1.

JTAG Test mode select pin.

JTAG test clock input pin.

JTAG test data input pin.

JTAG test data output pin.

Page 12

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

INDX QEA

QEB

UPDN

FLTA1 PWM1L1 PWM1H1 PWM1L2 PWM1H2 PWM1L3 PWM1H3 FLTA2 PWM2L1 PWM2H1

PGED1 PGEC1 PGED2 PGEC2 PGED3 PGEC3

MCLR

AVDD P P No Positive supply for analog modules. This pin must be connected at all times.

AVSS P P No Ground reference for analog modules.

DD P — No Positive supply for peripheral logic and I/O pins.

CAP P — No CPU logic filter capacitor connection.

VSS P — No Ground reference for logic and I/O pins.

REF+ I Analog No Analog voltage reference (high) input.

REF- I Analog No Analog voltage reference (low) input.

Legend: CMOS = CMOS compatible input or output; Analog = Analog input; P = Power

Type

I I

I O O O O O O

I O O

I/O

I/P ST No Master Clear (Reset) input. This pin is an active-low Reset to the device.

ST = Schmitt Trigger input with CMOS levels; O = Output; I = Input PPS = Peripheral Pin Select

Buffer

Type

ST ST

CMOS

— — — — — —

— —

ST ST ST ST ST ST

PPS Description

Yes

Quadrature Encoder Index Pulse input.

Yes

Quadrature Encoder Phase A input in QEI mode. Auxiliary Timer External Clock/Gate input in Timer mode.

Yes

Quadrature Encoder Phase A input in QEI mode. Auxiliary Timer External Clock/Gate input in Timer mode.

Yes

Position Up/Down Counter Direction State.

Yes

PWM1 Fault A input.

PWM1 Low output 1.

PWM1 High output 1.

PWM1 Low output 2.

PWM1 High output 2.

PWM1 Low output 3.

PWM1 High output 3.

Yes

PWM2 Fault A input.

PWM2 Low output 1.

PWM2 High output 1.

Data I/O pin for programming/debugging communication channel 1.

Clock input pin for programming/debugging communication channel 1.

Data I/O pin for programming/debugging communication channel 2.

Clock input pin for programming/debugging communication channel 2.

Data I/O pin for programming/debugging communication channel 3.

Clock input pin for programming/debugging communication channel 3.

Page 13

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT DIGITAL SIGNAL CONTROLLERS

Note 1: This data sheet summarizes the features

of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the

“dsPIC33F/PIC24H Family Reference Manual”, which is available from the

Microchip web site (www.microchip.com).

2: Some registers and associated bits

described in this section may not be available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register and bit information.

2.1 Basic Connection Requirements

Getting started with the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of 16-bit Digital Signal Controllers (DSCs) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected:

DD and VSS pins

• All V

(see Section 2.2 “Decoupling Capacitors”)

• All AV

•V

•MCLR

• PGECx/PGEDx pins used for In-Circuit Serial

• OSC1 and OSC2 pins when external oscillator

Additionally, the following pins may be required:

•V

DD and AVSS pins (even if the ADC module is

not used) (see Section 2.2 “Decoupling Capacitors”)

CAP

(see Section 2.3 “CPU Logic Filter Capacitor

Connection (V

(see Section 2.4 “Master Clear (MCLR) Pin”)

Programming™ (ICSP™) and debugging purposes (see Section 2.5 “ICSP Pins”)

source is used (see Section 2.6 “External Oscillator Pins”)

REF+/VREF- pins used when external voltage

reference for ADC module is implemented

Note: The AV

CAP)”)

DD and AVSS pins must be

connected independent of the ADC voltage reference source.

2.2 Decoupling Capacitors

The use of decoupling capacitors on every pair of power supply pins, such as V AVSS is required.

Consider the following criteria when using decoupling capacitors:

• Value and type of capacitor: Recommendation of 0.1 µF (100 nF), 10-20V. This capacitor should be a low-ESR and have a resonance frequency in the range of 20 MHz and higher. It is recommended that ceramic capacitors be used.

• Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length.

• Handling high frequency noise: If the board is experiencing high frequency noise, upward of tens of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 µF to 0.001 µF. Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. For example, 0.1 µF in parallel with 0.001 µF.

• Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum thereby reducing PCB track inductance.

DD, VSS, AVDD and

Page 14

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

dsPIC33F

VDD

VSS

VDD

VSS

VDD

AVDD

AVSS

VDD

VSS

0.1 µF

Ceramic

0.1 µF

Ceramic

0.1 µF

Ceramic

0.1 µF

Ceramic

MCLR

0.1 µF

Ceramic

VCAP

(1)

10 µF

Tantalum

Note 1: As an option, instead of a hard-wired connection, an

inductor (L1) can be substituted between V

DD and

DD to improve ADC noise rejection. The inductor

impedance should be less than 1Ω and the inductor capacity greater than 10 mA.

Where:

FCNV

--------------=

2π LC()

-----------------------=

2πfC()

---------------------

⎝⎠

⎛⎞

(i.e., ADC conversion rate/2)

Note 1: R ≤ 10 kΩ is recommended. A suggested

starting value is 10 kΩ. Ensure that the MCLR pin VIH and VIL specifications are met.

2: R1 ≤ 470W will limit any current flowing into

MCLR

from the external capacitor C, in the

event of MCLR

pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR

IH and VIL specifications are met.

(2)

(1)

VDD

MCLR

dsPIC33F

FIGURE 2-1: RECOMMENDED

MINIMUM CONNECTION

The placement of this capacitor should be close to the

CAP. It is recommended that the trace length not

V exceed one-quarter inch (6 mm). Refer to Section 21.2

“On-Chip Voltage Regulator” for details.

2.4 Master Clear (MCLR) Pin

The MCLR pin provides for two specific device functions:

• Device Reset

• Device programming and debugging

During device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR specific voltage levels (V transitions must not be adversely affected. Therefore, specific values of R and C will need to be adjusted based on the application and PCB requirements.

For example, as shown in Figure 2-2, it is recommended that capacitor C is isolated from the

pin during programming and debugging

MCLR operations.

Place the components shown in Figure 2-2 within one-quarter inch (6 mm) from the MCLR

pin. Consequently,

IH and VIL) and fast signal

pin.

2.2.1 TANK CAPACITORS

On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits including DSCs to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7 µF to 47 µF.

2.3 CPU Logic Filter Capacitor

A low-ESR (<5 Ohms) capacitor is required on the VCAP pin, which is used to stabilize the voltage regulator output voltage. The V connected to VDD, and must have a capacitor between

4.7 µF and 10 µF, 16V connected to ground. The type can be ceramic or tantalum. Refer to Section 24.0

“Electrical Characteristics” for additional

information.

Connection (V

CAP)

FIGURE 2-2: EXAMPLE OF MCLR PIN

CONNECTIONS

CAP pin must not be

Page 15

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

Main Oscillator

Guard Ring

Guard Trace

Secondary Oscillator

2.5 ICSP Pins

The PGECx and PGEDx pins are used for In-Circuit Serial Programming (ICSP) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms.

Pull-up resistors, series diodes and capacitors on the PGECx and PGEDx pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high

IH) and input low (VIL) requirements.

Ensure that the “Communication Channel Select” (i.e., PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to

MPLAB lator.

For more information on MPLAB ICD 3 or MPLAB REAL ICE™ in-circuit emulator connection requirements, refer to the following documents that are available on the Microchip web site.

• “Using MPLAB

• “MPLAB® ICD 3 Design Advisory” DS51764

• “MPLAB

• “Using MPLAB

ICD 3 or MPLAB REAL ICE™ in-circuit emu-

ICD 3” (poster) DS51765

REAL ICE™ In-Circuit Emulator User’s

Guide” DS51616

REAL ICE™ In-Circuit Emulator”

(poster) DS51749

2.6 External Oscillator Pins

Many DSCs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 8.0 “Oscillator

Configuration” for details).

The oscillator circuit should be placed on the same side of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested layout is shown in Figure 2-3.

FIGURE 2-3: SUGGESTED PLACEMENT

OF THE OSCILLATOR CIRCUIT

Page 16

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

2.7 Oscillator Value Conditions on Device Start-up

If the PLL of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to ≤ 8 MHz for start-up with PLL enabled. This means that if the external oscillator frequency is outside this range, the application must start-up in FRC mode first. The default PLL settings after a POR with an oscillator frequency outside this range will violate the device operating speed.

Once the device powers up, the application firmware can initialize the PLL SFRs, CLKDIV and PLLDBF to a suitable value, and then perform a clock switch to the Oscillator + PLL clock source. Note that clock switching must be enabled in the device Configuration word.

2.8 Configuration of Analog and Digital Pins During ICSP Operations

If MPLAB ICD 2, MPLAB ICD 3 or MPLAB REAL ICE™ in-circuit emulator is selected as a debugger, it automatically initializes all of the A/D input pins (ANx) as “digital” pins, by setting all bits in the AD1PCFGL register.

The bits in the registers that correspond to the A/D pins that are initialized by MPLAB ICD 3 or MPLAB REAL ICE™ in-circuit emulator, must not be cleared by the user application firmware; otherwise, communication errors will result between the debugger and the device.

If your application needs to use certain A/D pins as analog input pins during the debug session, the user application must clear the corresponding bits in the AD1PCFGL register during initialization of the ADC module.

When MPLAB ICD 3 or MPLAB REAL ICE™ in-circuit emulator is used as a programmer, the user application firmware must correctly configure the AD1PCFGL register. Automatic initialization of this register is only done during debugger operation. Failure to correctly configure the register(s) will result in all A/D pins being recognized as analog input pins, resulting in the port value being read as a logic ‘0’, which may affect user application functionality.

2.9 Unused I/Os

Unused I/O pins should be configured as outputs and driven to a logic-low state.

Alternatively, connect a 1k to 10k resistor between V and the unused pins.

Page 17

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

3.0 CPU

Note 1: This data sheet summarizes the features

of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 2. “CPU” (DS70204) of the

“dsPIC33F/PIC24H Family Reference Manual”, which is available from the

Microchip web site (www.microchip.com).

2: Some registers and associated bits

described in this section may not be available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register and bit information.

The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 CPU module has a 16-bit (data) modified Harvard architecture with an enhanced instruction set, including significant support for DSP. The CPU has a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M x 24 bits of user program memory space. The actual amount of program memory implemented varies by device. A single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a single cycle, with the exception of instructions that change the program flow, the double-word move (MOV.D) instruction and the table instructions. Overhead-free program loop constructs are supported using the DO and REPEAT instructions, both of which are interruptible at any point.

The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices have sixteen, 16-bit working registers in the programmer’s model. Each of the working registers can serve as a data, address or address offset register. The 16th working register (W15) operates as a software Stack Pointer (SP) for interrupts and calls.

There are two classes of instruction in the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices: MCU and DSP. These two instruction classes are seamlessly integrated into a single CPU. The instruction set includes many addressing modes and is designed for optimum C compiler efficiency. For most instructions, the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three parameter instructions can be supported, allowing A + B = C operations to be executed in a single cycle.

A block diagram of the CPU is shown in Figure 3-1, and the programmer’s model for the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 is shown in Figure 3-2.

3.1 Data Addressing Overview

The data space can be addressed as 32K words or 64 Kbytes and is split into two blocks, referred to as X and Y data memory. Each memory block has its own independent Address Generation Unit (AGU). The MCU class of instructions operates solely through the X memory AGU, which accesses the entire memory map as one linear data space. Certain DSP instructions operate through the X and Y AGUs to support dual operand reads, which splits the data address space into two parts. The X and Y data space boundary is device-specific.

Overhead-free circular buffers (Modulo Addressing mode) are supported in both X and Y address spaces. The Modulo Addressing removes the software boundary checking overhead for DSP algorithms. Furthermore, the X AGU circular addressing can be used with any of the MCU class of instructions. The X AGU also supports Bit-Reversed Addressing to greatly simplify input or output data reordering for radix-2 FFT algorithms.

The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K program word boundary defined by the 8-bit Program Space Visibility Page register (PSVPAG). The program-to-data-space mapping feature lets any instruction access program space as if it were data space.

3.2 DSP Engine Overview

The DSP engine features a high-speed 17-bit by 17-bit multiplier, a 40-bit ALU, two 40-bit saturating accumulators and a 40-bit bidirectional barrel shifter. The barrel shifter is capable of shifting a 40-bit value up to 16 bits right or left, in a single cycle. The DSP instructions operate seamlessly with all other instructions and have been designed for optimal real-time performance. The MAC instruction and other associated instructions can concurrently fetch two data operands from memory while multiplying two W registers and accumulating and optionally saturating the result in the same cycle. This instruction functionality requires that the RAM data space be split for these instructions and linear for all others. Data space partitioning is achieved in a transparent and flexible manner through dedicating certain working registers to each address space.

Page 18

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

Instruction

Decode and

Control

PCH PCL

Program Counter

16-bit ALU

Instruction Reg

PCU

16 x 16

W Register Array

ROM Latch

EA MUX

Interrupt

Controller

Stac k

Control

Logic

Loop

Control

Logic

Data Latch

Address

Latch

Control Signals

to Various Blocks

Literal Data

To Peripheral Modules

Data Latch

Address

Latch

X RAM

Y RAM

Address Generator Units

Y Data Bus

X Data Bus

DSP Engine

Divide Support

PSV and Table Data Access

Control Block

Program Memory

Data Latch

Address Latch

3.3 Special MCU Features

The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 features a 17-bit by 17-bit single-cycle multiplier that is shared by both the MCU ALU and DSP engine. The multiplier can perform signed, unsigned and mixed-sign multiplication. Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication not only allows you to perform mixed-sign multiplication, it also achieves accurate results for special operations, such as (-1.0) x (-1.0).

The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 supports 16/16 and 32/16 divide operations, both fractional and integer. All divide instructions are iterative operations. They must be executed within a REPEAT loop, resulting in a total execution time of 19 instruction cycles. The divide operation can be interrupted during any of those 19 cycles without loss of data.

A 40-bit barrel shifter is used to perform up to a 16-bit left or right shift in a single cycle. The barrel shifter can be used by both MCU and DSP instructions.

FIGURE 3-1: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 CPU CORE BLOCK DIAGRAM

Page 19

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

PC22

PC0

D0D15

Program Counter

Data Table Page Address

STATUS Register

Working Registers

DSP Operand Registers

W10

W11

W12/DSP Offset

W13/DSP Write Back

W14/Frame Pointer

W15/Stack Pointer

DSP Address Registers

AD39 AD0AD31

DSP Accumulators

ACCA

ACCB

Program Space Visibility Page Address

OA OB SA SB

RCOUNT

REPEAT Loop Counter

DCOUNT

DO Loop Counter

DOSTART

DO Loop Start Address

IPL2 IPL1

SPLIM

Stack Pointer Limit Register

AD15

SRL

PUSH.S Shadow

DO Shadow

OAB SAB

Core Configuration Register

Legend

CORCON

DA DC

TBLPAG

PSVPAG

IPL0 OV

W0/WREG

SRH

DO Loop End Address

DOEND

FIGURE 3-2: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 PROGRAMMER’S MODEL

Page 20

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

3.4 CPU Resources

Many useful resources are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information.

Note: In the event you are not able to access

the product page using the link above, enter this URL in your browser:

http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en530334

3.4.1 KEY RESOURCES

• Section 2. “CPU” (DS70204)

• Code Samples

• Application Notes

• Software Libraries

• Webinars

• All related dsPIC33F/PIC24H Family Reference

Manuals Sections

• Development Tools

Page 21

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

3.5 CPU Control Registers

R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R -0 R/W-0

OA OB SA

(1)

bit 15 bit 8

(1)

OAB SAB DA DC

R/W-0

(3)

IPL<2:0>

R/W-0

(3)

(2)

R/W-0

(3)

R-0 R/W-0 R/W-0 R/W-0 R/W-0

RA N OV Z C

bit 7 bit 0

Legend:

C = Clear only bit R = Readable bit U = Unimplemented bit, read as ‘0’

S = Set only bit W = Writable bit -n = Value at POR

‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 OA: Accumulator A Overflow Status bit

1 = Accumulator A overflowed 0 = Accumulator A has not overflowed

bit 14 OB: Accumulator B Overflow Status bit

1 = Accumulator B overflowed 0 = Accumulator B has not overflowed

bit 13 SA: Accumulator A Saturation ‘Sticky’ Status bit

(1)

1 = Accumulator A is saturated or has been saturated at some time 0 = Accumulator A is not saturated

bit 12 SB: Accumulator B Saturation ‘Sticky’ Status bit

(1)

1 = Accumulator B is saturated or has been saturated at some time 0 = Accumulator B is not saturated

bit 11 OAB: OA || OB Combined Accumulator Overflow Status bit

1 = Accumulators A or B have overflowed 0 = Neither Accumulators A or B have overflowed

bit 10 SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit

1 = Accumulators A or B are saturated or have been saturated at some time in the past 0 = Neither Accumulator A or B are saturated

Note: This bit may be read or cleared (not set). Clearing this bit will clear SA and SB.

bit 9 DA: DO Loop Active bit

1 = DO loop in progress 0 = DO loop not in progress

bit 8 DC: MCU ALU Half Carry/Borrow

bit

1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)

of the result occurred

0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized

data) of the result occurred

Note 1: This bit can be read or cleared (not set).

2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority

Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3> = 1.

3: The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>).

Page 22

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits

111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8)

bit 4 RA: REPEAT Loop Active bit

1 = REPEAT loop in progress 0 = REPEAT loop not in progress

bit 3 N: MCU ALU Negative bit

1 = Result was negative 0 = Result was non-negative (zero or positive)

bit 2 OV: MCU ALU Overflow bit

This bit is used for signed arithmetic (2’s complement). It indicates an overflow of a magnitude that causes the sign bit to change state.

1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred

bit 1 Z: MCU ALU Zero bit

1 = An operation that affects the Z bit has set it at some time in the past 0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)

bit 0 C: MCU ALU Carry/Borrow

1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred

bit

(2)

Note 1: This bit can be read or cleared (not set).

2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority

Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3> = 1.

3: The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>).

Page 23

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

REGISTER 3-2: CORCON: CORE CONTROL REGISTER

U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0

— — —USEDT

bit 15 bit 8

R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0

SATA SATB SATDW ACCSAT IPL3

bit 7 bit 0

Legend: C = Clear only bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set 0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’

bit 15-13 Unimplemented: Read as ‘0’ bit 12 US: DSP Multiply Unsigned/Signed Control bit

1 = DSP engine multiplies are unsigned 0 = DSP engine multiplies are signed

bit 11 EDT: Early DO Loop Termination Control bit

1 = Terminate executing DO loop at end of current loop iteration 0 = No effect

bit 10-8 DL<2:0>: DO Loop Nesting Level Status bits

111 = 7 DO loops active

•

001 = 1 DO loop active 000 = 0 DO loops active

bit 7 SATA: ACCA Saturation Enable bit

1 = Accumulator A saturation enabled 0 = Accumulator A saturation disabled

bit 6 SATB: ACCB Saturation Enable bit

1 = Accumulator B saturation enabled 0 = Accumulator B saturation disabled

bit 5 SATDW: Data Space Write from DSP Engine Saturation Enable bit

1 = Data space write saturation enabled 0 = Data space write saturation disabled

bit 4 ACCSAT: Accumulator Saturation Mode Select bit

1 = 9.31 saturation (super saturation) 0 = 1.31 saturation (normal saturation)

bit 3 IPL3: CPU Interrupt Priority Level Status bit 3

1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less

bit 2 PSV: Program Space Visibility in Data Space Enable bit

1 = Program space visible in data space 0 = Program space not visible in data space

bit 1 RND: Rounding Mode Select bit

1 = Biased (conventional) rounding enabled 0 = Unbiased (convergent) rounding enabled

bit 0 IF: Integer or Fractional Multiplier Mode Select bit

1 = Integer mode enabled for DSP multiply ops 0 = Fractional mode enabled for DSP multiply ops

(1)

(2)

(1)

(2)

DL<2:0>

PSV RND IF

Note 1: This bit will always read as ‘0’.

2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.

Page 24

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

3.6 Arithmetic Logic Unit (ALU)

The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU can affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register. The C and DC Status bits operate as Borrow Digit Borrow bits, respectively, for subtraction operations.

The ALU can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. Data for the ALU operation can come from the W register array or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location.

Refer to the “16-bit MCU and DSC Programmer’s Ref- erence Manual” (DS70157) for information on the SR bits affected by each instruction.

The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 CPU incorporates hardware support for both multiplication and division. This includes a dedicated hardware multiplier and support hardware for 16-bit-divisor division.

3.6.1 MULTIPLIER

Using the high-speed 17-bit x 17-bit multiplier of the DSP engine, the ALU supports unsigned, signed or mixed-sign operation in several MCU multiplication modes:

• 16-bit x 16-bit signed

• 16-bit x 16-bit unsigned

• 16-bit signed x 5-bit (literal) unsigned

• 16-bit unsigned x 16-bit unsigned

• 16-bit unsigned x 5-bit (literal) unsigned

• 16-bit unsigned x 16-bit signed

• 8-bit unsigned x 8-bit unsigned

3.6.2 DIVIDER

The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes:

1. 32-bit signed/16-bit signed divide

2. 32-bit unsigned/16-bit unsigned divide

3. 16-bit signed/16-bit signed divide

4. 16-bit unsigned/16-bit unsigned divide

The quotient for all divide instructions ends up in W0 and the remainder in W1. 16-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn) and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute.

and

3.7 DSP Engine

The DSP engine consists of a high-speed 17-bit x 17-bit multiplier, a barrel shifter and a 40-bit adder/subtracter (with two target accumulators, round and saturation logic).

The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 is a single-cycle instruction flow architecture; therefore, concurrent operation of the DSP engine with MCU instruction flow is not possible. However, some MCU ALU and DSP engine resources can be used concurrently by the same instruction (e.g., ED, EDAC).

The DSP engine can also perform inherent accumulator-to-accumulator operations that require no additional data. These instructions are ADD, SUB and NEG.

The DSP engine has options selected through bits in the CPU Core Control register (CORCON), as listed below:

• Fractional or integer DSP multiply (IF)

• Signed or unsigned DSP multiply (US)

• Conventional or convergent rounding (RND)

• Automatic saturation on/off for ACCA (SATA)

• Automatic saturation on/off for ACCB (SATB)

• Automatic saturation on/off for writes to data memory (SATDW)

• Accumulator Saturation mode selection (ACCSAT)

A block diagram of the DSP engine is shown in

Figure 3-3.

TABLE 3-1: DSP INSTRUCTIONS

SUMMARY

Instruction

CLR A = 0

ED A = (x - y)

EDAC A = A + (x – y) MAC A = A + (x * y) Ye s

MAC A = A + x MOVSAC No change in A Yes MPY A = x • y No

MPY A = x MPY.N A = – x • y No MSC A = A – x • y Yes

Algebraic

Operation

ACC Write

Back

Yes

No No

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dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

Zero Backfill

Sign-Extend

Barrel Shifter

40-bit Accumulator A 40-bit Accumulator B

Round

Logic

X Data Bus

To/ F ro m W Ar r ay

Adder

Saturate

Negate

S a

Y Data Bus

Carry/Borrow Out

Carry/Borrow In

Multiplier/Scaler

17-bit

FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM

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dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

3.7.1 MULTIPLIER

The 17-bit x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value. The output of the 17-bit x 17-bit multiplier/scaler is a 33-bit value that is sign-extended to 40 bits. Integer data is inherently represented as a signed 2’s complement value, where the Most Significant bit (MSb) is defined as a sign bit. The range of an N-bit 2’s complement integer is -2

• For a 16-bit integer, the data range is -32768 (0x8000) to 32767 (0x7FFF) including 0.

• For a 32-bit integer, the data range is

-2,147,483,648 (0x8000 0000) to 2,147,483,647 (0x7FFF FFFF).

When the multiplier is configured for fractional multiplication, the data is represented as a 2’s complement fraction, where the MSb is defined as a sign bit and the radix point is implied to lie just after the sign bit (QX format). The range of an N-bit 2’s complement fraction with this implied radix point is -1.0 to (1 - 2 16-bit fraction, the Q15 data range is -1.0 (0x8000) to

0.999969482 (0x7FFF) including 0 and has a precision

of 3.01518x10 ply operation generates a 1.31 product that has a precision of 4.65661 x 10

The same multiplier is used to support the MCU multiply instructions, which include integer 16-bit signed, unsigned and mixed sign multiply operations.

The MUL instruction can be directed to use byte or word-sized operands. Byte operands will direct a 16-bit result, and word operands will direct a 32-bit result to the specified register(s) in the W array.

-5

. In Fractional mode, the 16 x 16 multi-

-10

N-1

to 2

1-N

N-1

- 1.

). For a

3.7.2 DATA ACCUMULATORS AND

ADDER/SUBTRACTER

The data accumulator consists of a 40-bit adder/subtracter with automatic sign extension logic. It can select one of two accumulators (A or B) as its pre-accumulation source and post-accumulation destination. For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled using the barrel shifter prior to accumulation.

3.7.2.1 Adder/Subtracter, Overflow and Saturation

The adder/subtracter is a 40-bit adder with an optional zero input into one side, and either true or complement data into the other input.

• In the case of addition, the Carry/B

active-high and the other input is true data (not complemented).

• In the case of subtraction, the Carry/Borrow

is active-low and the other input is complemented.

The adder/subtracter generates Overflow Status bits, SA/SB and OA/OB, which are latched and reflected in the STATUS register:

• Overflow from bit 39: this is a catastrophic

overflow in which the sign of the accumulator is destroyed.

• Overflow into guard bits 32 through 39: this is a

recoverable overflow. This bit is set whenever all the guard bits are not identical to each other.

The adder has an additional saturation block that controls accumulator data saturation, if selected. It uses the result of the adder, the Overflow Status bits described previously and the SAT<A:B> (CORCON<7:6>) and ACCSAT (CORCON<4>) mode control bits to determine when and to what value to saturate.

Six STATUS register bits support saturation and overflow:

• OA: ACCA overflowed into guard bits

• OB: ACCB overflowed into guard bits

• SA: ACCA saturated (bit 31 overflow and

saturation)

ACCA overflowed into guard bits and saturated (bit 39 overflow and saturation)

• SB: ACCB saturated (bit 31 overflow and

saturation)

ACCB overflowed into guard bits and saturated (bit 39 overflow and saturation)

• OAB: Logical OR of OA and OB

• SAB: Logical OR of SA and SB

The OA and OB bits are modified each time data passes through the adder/subtracter. When set, they indicate that the most recent operation has overflowed into the accumulator guard bits (bits 32 through 39). The OA and OB bits can also optionally generate an arithmetic warning trap when set and the corresponding Overflow Trap Flag Enable bits (OVATE, OVBTE) in the INTCON1 register are set (refer to

Section 7.0 “Interrupt Controller”). This allows the

user application to take immediate action, for example, to correct system gain.

orrow input is

input

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dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

The SA and SB bits are modified each time data passes through the adder/subtracter, but can only be cleared by the user application. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled). When saturation is not enabled, SA and SB default to bit 39 overflow and thus indicate that a catastrophic overflow has occurred. If the COVTE bit in the INTCON1 register is set, SA and SB bits will generate an arithmetic warning trap when saturation is disabled.

The Overflow and Saturation Status bits can optionally be viewed in the STATUS Register (SR) as the logical OR of OA and OB (in bit OAB) and the logical OR of SA and SB (in bit SAB). Programmers can check one bit in the STATUS register to determine if either accumulator has overflowed, or one bit to determine if either accumulator has saturated. This is useful for complex number arithmetic, which typically uses both accumulators.

The device supports three Saturation and Overflow modes:

• Bit 39 Overflow and Saturation: When bit 39 overflow and saturation occurs, the saturation logic loads the maximally positive 9.31 (0x7FFFFFFFFF) or maximally negative 9.31 value (0x8000000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user application. This condition is referred to as ‘super saturation’ and provides protection against erroneous data or unexpected algorithm problems (such as gain calculations).

• Bit 31 Overflow and Saturation: When bit 31 overflow and saturation occurs, the saturation logic then loads the maximally positive

1.31 value (0x007FFFFFFF) or maximally negative 1.31 value (0x0080000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user application. When this Saturation mode is in effect, the guard bits are not used, so the OA, OB or OAB bits are never set.

• Bit 39 Catastrophic Overflow: The bit 39 Overflow Status bit from the adder is used to set the SA or SB bit, which remains set until cleared by the user application. No saturation operation is performed, and the accumulator is allowed to overflow, destroying its sign. If the COVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap exception.

3.7.3 ACCUMULATOR ‘WRITE BACK’

The MAC class of instructions (with the exception of MPY, MPY.N, ED and EDAC) can optionally write a rounded version of the high word (bits 31 through 16) of the accumulator that is not targeted by the instruction

into data space memory. The write is performed across the X bus into combined X and Y address space. The following addressing modes are supported:

• W13, Register Direct: The rounded contents of the non-target accumulator are written into W13 as a

1.15 fraction.

• [W13] + = 2, Register Indirect with Post-Increment: The rounded contents of the non-target accumulator are written into the address pointed to by W13 as a 1.15 fraction. W13 is then incremented by 2 (for a word write).

3.7.3.1 Round Logic

The round logic is a combinational block that performs a conventional (biased) or convergent (unbiased) round function during an accumulator write (store). The Round mode is determined by the state of the RND bit in the CORCON register. It generates a 16-bit, 1.15 data value that is passed to the data space write saturation logic. If rounding is not indicated by the instruction, a truncated 1.15 data value is stored and the least significant word (lsw) is simply discarded.

Conventional rounding zero-extends bit 15 of the accumulator and adds it to the ACCxH word (bits 16 through 31 of the accumulator).

• If the ACCxL word (bits 0 through 15 of the accumulator) is between 0x8000 and 0xFFFF (0x8000 included), ACCxH is incremented.

• If ACCxL is between 0x0000 and 0x7FFF, ACCxH is left unchanged.

A consequence of this algorithm is that over a succession of random rounding operations, the value tends to be biased slightly positive.

Convergent (or unbiased) rounding operates in the same manner as conventional rounding, except when ACCxL equals 0x8000. In this case, the Least Significant bit (bit 16 of the accumulator) of ACCxH is examined:

• If it is ‘1’, ACCxH is incremented.

• If it is ‘0’, ACCxH is not modified.

Assuming that bit 16 is effectively random in nature, this scheme removes any rounding bias that may accumulate.

The SAC and SAC.R instructions store either a truncated (SAC), or rounded (SAC.R) version of the contents of the target accumulator to data memory via the X bus, subject to data saturation (see

Section 3.7.3.2 “Data Space Write Saturation”). For

the MAC class of instructions, the accumulator write-back operation functions in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding.

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dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

3.7.3.2 Data Space Write Saturation

In addition to adder/subtracter saturation, writes to data space can also be saturated, but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder. These inputs are combined and used to select the appropriate 1.15 fractional value as output to write to data space memory.

If the SATDW bit in the CORCON register is set, data (after rounding or truncation) is tested for overflow and adjusted accordingly:

• For input data greater than 0x007FFF, data written to memory is forced to the maximum positive

1.15 value, 0x7FFF.

• For input data less than 0xFF8000, data written to memory is forced to the maximum negative 1.15 value, 0x8000.

The Most Significant bit of the source (bit 39) is used to determine the sign of the operand being tested.

If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions.

3.7.4 BARREL SHIFTER

The barrel shifter can perform up to 16-bit arithmetic or logic right shifts, or up to 16-bit left shifts in a single cycle. The source can be either of the two DSP accumulators or the X bus (to support multi-bit shifts of register or memory data).

The shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. A positive value shifts the operand right. A negative value shifts the operand left. A value of ‘0’ does not modify the operand.

The barrel shifter is 40 bits wide, thereby obtaining a 40-bit result for DSP shift operations and a 16-bit result for MCU shift operations. Data from the X bus is presented to the barrel shifter between bit positions 16 and 31 for right shifts, and between bit positions 0 and 16 for left shifts.

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dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

Reset Address

0x000000

0x0000FE

0x000002

0x000100

Device Configuration

User Program Flash Memory

0x005800

0x0057FE

(11264 instructions)

0x800000

0xF80000

Registers

0xF80017 0xF80018

DEVID (2)

0xFEFFFE 0xFF0000

0xFFFFFE

0xF7FFFE

Unimplemented

(Read ‘0’s)

GOTO

Instruction

0x000004

Reserved

0x7FFFFE

Reserved

0x000200

0x0001FE

0x000104

Alternate Vector Table

Reserved

Interrupt Vector Table

dsPIC33FJ32MC202/204

Configuration Memory Space

User Memory Space

Reset Address

0x000000

0x0000FE

0x000002

0x000100

Device Configuration

User Program Flash Memory

0x002C00

0x002BFE

(5632 instructions)

0x800000

0xF80000

Registers

0xF80017 0xF80018

DEVID (2)

0xFEFFFE 0xFF0000

0xFFFFFE

0xF7FFFE

Unimplemented

(Read ‘0’s)

GOTO

Instruction

0x000004

Reserved

0x7FFFFE

Reserved

0x000200

0x0001FE

0x000104

Alternate Vector Table

Reserved

Interrupt Vector Table

dsPIC33FJ16MC304

Configuration Memory Space

User Memory Space

4.0 MEMORY ORGANIZATION

Note: This data sheet summarizes the features

of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to

Section 4. “Program Memory”

(DS70202) of the “dsPIC33F/PIC24H Family Reference Manual”, which is avail-

able from the Microchip web site (www.microchip.com).

4.1 Program Address Space

The program address memory space of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices is 4M instructions. The space is addressable by a 24-bit value derived either from the 23-bit Program Counter (PC) during program execution, or from table operation or data space remapping as described in

Section 4.8 “Interfacing Program and Data Memory Spaces”.

User application access to the program memory space is restricted to the lower half of the address range (0x000000 to 0x7FFFFF). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG<7> to

The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 architecture features separate program and data memory spaces and buses. This architecture also allows the direct access of program memory from the data space during code execution.

permit access to the Configuration bits and Device ID sections of the configuration memory space.

The memory maps for the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices are shown in

Figure 4-1.

FIGURE 4-1: PROGRAM MEMORY MAPS FOR dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

DEVICES

Page 30

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

0816

PC Address

0x000000 0x000002

0x000004 0x000006

00000000

Program Memory

‘Phantom’ Byte

(read as ‘0’)

least significant word

most significant word

Instruction Width

0x000001 0x000003

0x000005 0x000007

msw

Address (lsw Address)

4.1.1 PROGRAM MEMORY

ORGANIZATION

The program memory space is organized in word-addressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. The lower word always has an even address, while the upper word has an odd address (Figure 4-2).

Program memory addresses are always word-aligned on the lower word, and addresses are incremented or decremented by two during code execution. This arrangement provides compatibility with data memory space addressing and makes data in the program memory space accessible.

4.1.2 INTERRUPT AND TRAP VECTORS

All dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices reserve the addresses between 0x00000 and 0x000200 for hard-coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user application at 0x000000, with the actual address for the start of code at 0x000002.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices also have two interrupt vector tables, located from 0x000004 to 0x0000FF and 0x000100 to 0x0001FF. These vector tables allow each of the device interrupt sources to be handled by separate Interrupt Service Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in

Section 7.1 “Interrupt Vector Table”.

FIGURE 4-2: PROGRAM MEMORY ORGANIZATION

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dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

4.2 Data Address Space

The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 CPU has a separate 16-bit-wide data memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and write operations. The data memory maps is shown in Figure 4-3.

All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space. This arrangement gives a data space address range of 64 Kbytes or 32K words. The lower half of the data memory space (that is, when EA<15> = 0) is used for implemented memory addresses, while the upper half (EA<15> = 1) is reserved for the Program Space Visibility area (see Section 4.8.3 “Reading Data from

Program Memory Using Program Space Visibility”).

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices implement up to 2 Kbytes of data memory. Should an EA point to a location outside of this area, an all-zero word or byte will be returned.

4.2.1 DATA SPACE WIDTH

The data memory space is organized in byte addressable, 16-bit wide blocks. Data is aligned in data memory and registers as 16-bit words, but all data space EAs resolve to bytes. The Least Significant Bytes (LSBs) of each word have even addresses, while the Most Significant Bytes (MSBs) have odd addresses.

4.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT

To maintain backward compatibility with PIC® MCU devices and improve data space memory usage efficiency, the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 instruction set supports both word and byte operations. As a consequence of byte accessibility, all effective address calculations are internally scaled to step through word-aligned memory. For example, the core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] will result in a value of Ws + 1 for byte operations and Ws + 2 for word operations.

Data byte reads will read the complete word that contains the byte, using the LSB of any EA to determine which byte to select. The selected byte is placed onto the LSB of the data path. That is, data memory and registers are organized as two parallel byte-wide entities with shared (word) address decode but separate write lines. Data byte writes only write to the corresponding side of the array or register that matches the byte address.

All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error trap is generated. If the error occurred on a read, the instruction underway is completed. If the error occurred on a write, the instruction is executed but the write does not occur. In either case, a trap is then executed, allowing the system and/or user application to examine the machine state prior to execution of the address Fault.

All byte loads into any W register are loaded into the Least Significant Byte. The Most Significant Byte is not modified.

A sign-extend instruction (SE) is provided to allow user applications to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, user applications can clear the MSB of any W register by executing a zero-extend (ZE) instruction on the appropriate address.

4.2.3 SFR SPACE

The first 2 Kbytes of the Near Data Space, from 0x0000 to 0x07FF, is primarily occupied by Special Function Registers (SFRs). These are used by the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 core and peripheral modules for controlling the operation of the device.

SFRs are distributed among the modules that they control, and are generally grouped together by module. Much of the SFR space contains unused addresses; these are read as ‘0’.

Note: The actual set of peripheral features and

interrupts varies by the device. Refer to the corresponding device tables and pinout diagrams for device-specific information.

4.2.4 NEAR DATA SPACE

The 8 Kbyte area between 0x0000 and 0x1FFF is referred to as the near data space. Locations in this space are directly addressable via a 13-bit absolute address field within all memory direct instructions. Additionally, the whole data space is addressable using MOV instructions, which support Memory Direct Addressing mode with a 16-bit address field, or by using Indirect Addressing mode using a working register as an address pointer.

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dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

0x0000

0x07FE

0x0FFE

0xFFFE

LSB

Address

16 bits

LSbMSb

MSB

Address

0x0001

0x07FF

0xFFFF

Optionally Mapped into Program Memory

0x0801

0x0800

0x1000

2 Kbyte SFR Space

2 Kbyte

SRAM Space

0x8001

0x8000

SFR Space

X Data RAM (X)

X Data

Unimplemented (X)

Y Data RAM (Y)

0x0BFE 0x0C00

0x0BFF 0x0001

0x0FFF 0x1001

0x1FFF

0x1FFE

0x2001

0x2000

8 Kbyte Near Data Space

FIGURE 4-3: DATA MEMORY MAP FOR dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

DEVICES WITH 2 KB RAM

Page 33

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

4.2.5 X AND Y DATA SPACES

The core has two data spaces, X and Y. These data spaces can be considered either separate (for some DSP instructions), or as one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths. This feature allows certain instructions to concurrently fetch two words from RAM, thereby enabling efficient execution of DSP algorithms such as Finite Impulse Response (FIR) filtering and Fast Fourier Transform (FFT).

The X data space is used by all instructions and supports all addressing modes. X data space has separate read and write data buses. The X read data bus is the read data path for all instructions that view data space as combined X and Y address space. It is also the X data prefetch path for the dual operand DSP instructions (MAC class).

The Y data space is used in concert with the X data space by the MAC class of instructions (CLR, ED, EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide two concurrent data read paths.

Both the X and Y data spaces support Modulo Addressing mode for all instructions, subject to addressing mode restrictions. Bit-Reversed Addressing mode is only supported for writes to X data space.

All data memory writes, including in DSP instructions, view data space as combined X and Y address space. The boundary between the X and Y data spaces is device-dependent and is not user-programmable.

All effective addresses are 16 bits wide and point to bytes within the data space. Therefore, the data space address range is 64 Kbytes, or 32K words, though the implemented memory locations vary by device.

4.3 Program Memory Resources

Note: In the event you are not able to access

the product page using the link above, enter this URL in your browser:

http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en530334

4.3.1 KEY RESOURCES

• Section 4. “Program Memory” (DS70202)

• Code Samples

• Application Notes

• Software Libraries

• Webinars

• All related dsPIC33F/PIC24H Family Reference Manuals Sections

• Development Tools

Page 34

4.4 Special Function Register Maps

TABLE 4-1: CPU CORE REGISTERS MAP

SFR Name

WREG0 0000 Working Register 0

WREG1 0002 Working Register 1

WREG2 0004 Working Register 2

WREG3 0006 Working Register 3

WREG4 0008 Working Register 4

WREG5 000A Working Register 5

WREG6 000C Working Register 6

WREG7 000E Working Register 7

WREG8 0010 Working Register 8

WREG9 0012 Working Register 9

WREG10 0014 Working Register 10

WREG11 0016 Working Register 11

WREG12 0018 Working Register 12

WREG13 001A Working Register 13

WREG14 001C Working Register 14

WREG15 001E Working Register 15

SPLIM 0020 Stack Pointer Limit Register

ACCAL 0022 Accumulator A Low Word Register

ACCAH 0024 Accumulator A High Word Register

ACCAU 0026 Accumulator A Upper Word Register

ACCBL 0028 Accumulator B Low Word Register

ACCBH 002A Accumulator B High Word Register

ACCBU 002C Accumulator B Upper Word Register

PCL 002E Program Counter Low Word Register

PCH 0030 — — — — — — — — Program Counter High Byte Register

TBLPAG 0032 — — — — — — — — Table Page Address Pointer Register

PSVPAG 0034 — — — — — — — — Program Memory Visibility Page Address Pointer Register

RCOUNT 0036 Repeat Loop Counter Register

DCOUNT 0038 DCOUNT<15:0> xxxx

DOSTARTL 003A DOSTARTL<15:1> 0xxxx

DOSTARTH 003C

DOENDL 003E DOENDL<15:1> 0xxxx

DOENDH 0040

SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C

CORCON 0044 — — — US EDT DL<2:0>

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

SFR

Addr

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

— — — — — — — — — —

SATA SATB SATDW ACCSAT IPL3 PSV RND IF

DOSTARTH<5:0> 00xx

DOENDH 00xx

All

Resets

0000

0800

xxxx

0000

xxxx

0000

0020

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

Page 35

TABLE 4-1: CPU CORE REGISTERS MAP (CONTINUED)

SFR Name

MODCON 0046 XMODEN YMODEN

XMODSRT 0048 XS<15:1> 0xxxx

XMODEND 004A XE<15:1> 1xxxx

YMODSRT 004C YS<15:1> 0xxxx

YMODEND 004E YE<15:1> 1xxxx

XBREV 0050 BREN XB<14:0> xxxx

DISICNT 0052 —

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

SFR

Addr

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

— —

— Disable Interrupts Counter

BWM<3:0> YWM<3:0> XWM<3:0> 0000

All

Resets

xxxx

TABLE 4-2: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ32MC202

SFR

Name

CNEN1

CNEN2

CNPU1

CNPU2

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

SFR

Addr

0060 CN15IE CN14IE CN13IE CN12IE CN11IE

0062

0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE

006A

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

—

CN30IE CN29IE

—

CN30PUE CN29PUE

—

CN27IE

—

CN27PUE

— — —

— —

— — —

— —

CN24IE CN23IE CN22IE CN21IE

CN24PUE CN23PUE CN22PUE CN21PUE

CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE

— — — —

CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE

— — — —

CN16IE

CN16PUE

All

Resets

0000

TABLE 4-3: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ32MC204 and dsPIC33FJ16MC304

SFR

Name

CNEN1

CNEN2

CNPU1

CNPU2

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

SFR

Addr

0060

0062

0068

006A

Bit 15Bit 14Bit 13Bit 12Bit 11Bit 10Bit 9Bit 8Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE

— CN30IE CN29IE CN28IE CN27IE CN26IE CN25IE CN24IE CN23IE CN22IE CN21IE CN20IE CN19IE CN18IE CN17IE CN16IE

CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE

— CN30PUE CN29PUE CN28PUE CN27PUE CN26PUE CN25PUE CN24PUE CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE

All

Resets

0000

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

Page 36

TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP

SFR

Name

INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR

INTCON2 0082 ALTIVT DISI

IFS0 0084

IFS1 0086

IFS3 008A FLTA1IF

IFS4 008C

IEC0 0094

IEC1 0096

IEC3 009A FLTA1IE

IEC4 009C

IPC0 00A4

IPC1 00A6

IPC2 00A8

IPC3 00AA

IPC4 00AC

IPC5 00AE

IPC7 00B2

IPC14 00C0

IPC15 00C2

IPC16 00C4

IPC18 00C8

INTTREG 00E0

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

SFR

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Addr

— — — — — — — — — — — INT2EP INT1EP INT0EP 0000

— — AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF 0000

— —INT2IF — — — — —IC8IFIC7IF—INT1IFCNIF—MI2C1IFSI2C1IF0000

— — — — QEIIF PWM1IF — — — — — — — — — 0000

— — — — — FLTA2IF PWM2IF — — — — — — —U1EIF— 0000

— — AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE 0000

— —INT2IE — — — — —IC8IEIC7IE — INT1IE CNIE — MI2C1IE SI2C1IE 0000

— — — —QEIIEPWM1IE— — — — — — — — — 0000

— — — — — FLTA2IE PWM2IE — — — — — — —U1EIE— 0000

— T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 4444

— T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> — — — — 4440

— U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0> 4444

— — — — — — — — — AD1IP<2:0> — U1TXIP<2:0> 0044

— CNIP<2:0> — — — — — MI2C1IP<2:0> — SI2C1IP<2:0> 4044

—IC8IP<2:0> —IC7IP<2:0> — — — — — INT1IP<2:0> 4404

— — — — — — — — — INT2IP<2:0> — — — — 0040

— — — — —QEIIP<2:0>— PWM1IP<2:0> — — — — 0440

—FLTA1IP<2:0> — — — — — — — — — — — — 4000

— — — — — — — — — U1EIP<2:0> — — — — 0040

— — — — —FLTA2IP<2:0> — PWM2IP<2:0> — — — — 0440

— — — —ILR<3:0> — VECNUM<6:0> 0000

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

All

Resets

— MATHERR ADDRERR STKERR OSCFAIL — 0000

Page 37

TABLE 4-5: TIMER REGISTER MAP

SFR

Name

TMR1 0100 Timer1 Register

PR1 0102 Period Register 1

T1CON 0104 TON

TMR2 0106 Timer2 Register

TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only)

TMR3 010A Timer3 Register

PR2 010C Period Register 2

PR3 010E Period Register 3

T2CON 0110 TON

T3CON 0112 TON

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Addr

—

TSIDL

—

TSIDL

—

TSIDL

— — — — — —

TGATE TCKPS<1:0>

TGATE TCKPS<1:0> T32

TGATE TCKPS<1:0>

TABLE 4-6: INPUT CAPTURE REGISTER MAP

SFR Name

IC1BUF 0140 Input 1 Capture Register

IC1CON 0142

IC2BUF 0144 Input 2 Capture Register

IC2CON 0146

IC7BUF 0158 Input 7 Capture Register

IC7CON 015A

IC8BUF 015C Input 8 Capture Register

IC8CON 015E

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

SFR

Addr

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

— —

ICSIDL

— — — — —

ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>

—

TSYNC TCS

— —

All

Resets

0000

FFFF

—

0000

xxxx

0000

FFFF

—

TCS

—

0000

—

0000

All

Resets

xxxx

0000

xxxx

0000

xxxx

0000

xxxx

0000

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

TABLE 4-7: OUTPUT COMPARE REGISTER MAP

SFR Name

OC1RS 0180 Output Compare 1 Secondary Register

OC1R 0182 Output Compare 1 Register

OC1CON 0184

OC2RS 0186 Output Compare 2 Secondary Register

OC2R 0188 Output Compare 2 Register

OC2CON 018A

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

SFR

Addr

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

— —

OCSIDL

— — — — — — — —

OCFLT OCTSEL OCM<2:0>

All

Resets

xxxx

0000

xxxx

0000

Page 38

TABLE 4-8: 6-OUTPUT PWM1 REGISTER MAP

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

P1TCON 01C0 PTEN

P1TMR 01C2 PTDIR PWM Timer Count Value Register

P1TPER 01C4 — PWM Time Base Period Register

P1SECMP 01C6 SEVTDIR PWM Special Event Compare Register

PWM1CON1

PWM1CON2

P1DTCON1 01CC DTBPS<1:0> DTB<5:0> DTAPS<1:0> DTA<5:0>

P1DTCON2 01CE — — — — — — — — — — DTS3A DTS3I DTS2A DTS2I DTS1A DTS1I

P1FLTACON 01D0 — — FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L FLTAM — — — — FAEN3 FAEN2 FAEN1

P1OVDCON 01D4 — — POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L — — POUT3H POUT3L POUT2H POUT2L POUT1H POUT1L

P1DC1 01D6 PWM Duty Cycle #1 Register

P1DC2 01D8 PWM Duty Cycle #2 Register

P1DC3 01DA PWM Duty Cycle #3 Register

Legend: u = uninitialized bit, — = unimplemented, read as ‘0’

01C8 — — — — —PMOD3PMOD2PMOD1 — PEN3H PEN2H PEN1H — PEN3L PEN2L PEN1L

01CA — — — — SEVOPS<3:0> — — — — — IUE OSYNC UDIS

—PTSIDL — — — — — PTOPS<3:0> PTCKPS<1:0> PTMOD<1:0>

0000 0000 0000 0000

0000 0000 1111 1111

0000 0000 0000 0000

1111 1111 0000 0000

0000 0000 0000 0000

TABLE 4-9: 2-OUTPUT PWM2 REGISTER MAP

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

P2TCON 05C0 PTEN

P2TMR 05C2 PTDIR PWM Timer Count Value Register 0000 0000 0000 0000

P2TPER 05C4

P2SECMP 05C6 SEVTDIR PWM Special Event Compare Register 0000 0000 0000 0000

PWM2CON1 05C8

PWM2CON2 05CA

P2DTCON1 05CC DTBPS<1:0> DTB<5:0> DTAPS<1:0> DTA<5:0> 0000 0000 0000 0000

P2DTCON2 05CE

P2FLTACON 05D0

P2OVDCON 05D4

P2DC1 05D6 PWM Duty Cycle #1 Register 0000 0000 0000 0000

Legend: u = uninitialized bit, — = unimplemented, read as ‘0’

— PWM Time Base Period Register 0000 0000 0000 0000

— — — — — — —PMOD1— — —PEN1H— — — PEN1L 0000 0000 1111 1111

— — — — SEVOPS<3:0> — — — — — IUE OSYNC UDIS 0000 0000 0000 0000

— — — — — — — — — — — — — —DTS1ADTS1I0000 0000 0000 0000

— — — — — — FAOV1H FAOV1L FLTAM — — — — — —FAEN10000 0000 0000 0000

— — — — — — POVD1H POVD1L — — — — — — POUT1H POUT1L 1111 1111 0000 0000

—PTSIDL— — — — — PTOPS<3:0> PTCKPS<1:0> PTMOD<1:0> 0000 0000 0000 0000

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

Page 39

TABLE 4-10: QEI1 REGISTER MAP

SFR

Name

QEI1CON 01E0 CNTERR

DFLT1CON 01E2

POS1CNT 01E4 Position Counter<15:0> 0000 0000 0000 0000

MAX1CNT 01E6 Maximum Count<15:0> 1111 1111 1111 1111

Legend: u = uninitialized bit, — = unimplemented, read as ‘0’

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11

—

— — — — — IMV<1:0> CEID QEOUT QECK<2:0> — — — — 0000 0000 0000 0000

TABLE 4-11: I2C1 REGISTER MAP

SFR Name

I2C1RCV 0200 — — — — — — — — Receive Register

I2C1TRN 0202 — — — — — — — — Transmit Register

I2C1BRG 0204 — — — — — — — Baud Rate Generator Register

I2C1CON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN

I2C1STAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF

I2C1ADD 020A — — — — — — Address Register

I2C1MSK 020C — — — — — — Address Mask Register

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

SFR

Addr

Bit 15Bit 14Bit 13Bit 12Bit 11Bit 10Bit 9Bit 8Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

TABLE 4-12: UART1 REGISTER MAP

SFR Name

U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL

U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA

U1TXREG 0224 — — — — — — — UART Transmit Register

U1RXREG 0226 — — — — — — — UART Receive Register

U1BRG 0228 Baud Rate Generator Prescaler

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

SFR

Addr

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bit

Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

QEISIDL INDEX UPDN QEIM<2:0> SWPAB PCDOUT TQGATE TQCKPS<1:0> POSRES TQCS UPDN_SRC 0000 0000 0000 0000

All

Resets

0000

00FF

0000

1000

0000

All

Resets

0000

0110

xxxx

0000

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

TABLE 4-13: SPI1 REGISTER MAP

SFR

Name

SPI1STAT 0240 SPIEN — SPISIDL — — — — — — SPIROV — — — — SPITBF SPIRBF

SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE<2:0> PPRE<1:0>

SPI1CON2 0244 FRMEN SPIFSD FRMPOL — — — — — — — — — — — FRMDLY —

SPI1BUF 0248 SPI1 Transmit and Receive Buffer Register

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

SFR

Addr

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

All

Resets

0000

Page 40

TABLE 4-14: ADC1 REGISTER MAP FOR dsPIC33FJ32MC202

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ADC1BUF0 0300 ADC Data Buffer 0 xxxx

ADC1BUF1 0302

ADC1BUF2 0304

ADC1BUF3 0306

ADC1BUF4 0308

ADC1BUF5 030A

ADC1BUF6 030C

ADC1BUF7 030E

ADC1BUF8 0310

ADC1BUF9 0312

ADC1BUFA 0314

ADC1BUFB 0316

ADC1BUFC 0318

ADC1BUFD 031A

ADC1BUFE 031C

ADC1BUFF 031E

AD1CON1 0320 ADON

AD1CON2 0322 VCFG<2:0>

AD1CON3 0324 ADRC

AD1CHS123 0326

AD1CHS0 0328 CH0NB

AD1PCFGL 032C

AD1CSSL 0330

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

— — — — — CH123NB<1:0> CH123SB — — — — — CH123NA<1:0> CH123SA 0000

— — — — — — — — — — PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000

— — — — — — — — — — CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 0000

—ADSIDL — — AD12B FORM<1:0> SSRC<2:0> — SIMSAM ASAM SAMP DONE 0000

— — CSCNA CHPS<1:0> BUFS — SMPI<3:0> BUFM ALTS 0000

— — SAMC<4:0> ADCS<7:0> 0000

— — CH0SB<4:0> CH0NA — — CH0SA<4:0> 0000

All

Reset

ADC Data Buffer 1 xxxx

ADC Data Buffer 2 xxxx

ADC Data Buffer 3 xxxx

ADC Data Buffer 4 xxxx

ADC Data Buffer 5 xxxx

ADC Data Buffer 6 xxxx

ADC Data Buffer 7 xxxx

ADC Data Buffer 8 xxxx

ADC Data Buffer 9 xxxx

ADC Data Buffer 10 xxxx

ADC Data Buffer 11 xxxx

ADC Data Buffer 12 xxxx

ADC Data Buffer 13 xxxx

ADC Data Buffer 14 xxxx

ADC Data Buffer 15 xxxx

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

Page 41

TABLE 4-15: ADC1 REGISTER MAP FOR dsPIC33FJ32MC204 AND dsPIC33FJ16MC304

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ADC1BUF0

ADC1BUF1 0302

ADC1BUF2 0304

ADC1BUF3 0306

ADC1BUF4 0308

ADC1BUF5 030A

ADC1BUF6 030C

ADC1BUF7 030E

ADC1BUF8 0310

ADC1BUF9 0312

ADC1BUFA 0314

ADC1BUFB 0316

ADC1BUFC 0318

ADC1BUFD 031A

ADC1BUFE 031C

ADC1BUFF 031E

AD1CON1 0320 ADON

AD1CON2 0322 VCFG<2:0>

AD1CON3 0324 ADRC

AD1CHS123 0326

AD1CHS0 0328 CH0NB

AD1PCFGL 032C

AD1CSSL 0330

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

0300

ADC Data Buffer 0 xxxx

ADC Data Buffer 1 xxxx

ADC Data Buffer 2 xxxx

ADC Data Buffer 3 xxxx

ADC Data Buffer 4 xxxx

ADC Data Buffer 5 xxxx

ADC Data Buffer 6 xxxx

ADC Data Buffer 7 xxxx

ADC Data Buffer 8 xxxx

ADC Data Buffer 9 xxxx

ADC Data Buffer 10 xxxx

ADC Data Buffer 11 xxxx

ADC Data Buffer 12 xxxx

ADC Data Buffer 13 xxxx

ADC Data Buffer 14 xxxx

ADC Data Buffer 15 xxxx

—ADSIDL — — AD12B FORM<1:0> SSRC<2:0> — SIMSAM ASAM SAMP DONE 0000

— — CSCNA CHPS<1:0> BUFS — SMPI<3:0> BUFM ALTS 0000

— — SAMC<4:0> ADCS<7:0> 0000

— — — — — CH123NB<1:0> CH123SB — — — — — CH123NA<1:0> CH123SA 0000

— — CH0SB<4:0> CH0NA — — CH0SA<4:0> 0000

— — — — — — — PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000

— — — — — — — CSS8 CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 0000

All

Resets

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

Page 42

TABLE 4-16: PERIPHERAL PIN SELECT INPUT REGISTER MAP

File

Name

RPINR0

RPINR1

RPINR3

RPINR7

RPINR10

RPINR11

RPINR12

RPINR13

RPINR14

RPINR15

RPINR18

RPINR20

RPINR21

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0680

0682

0686

068E

0694

0696

0698

069A

069C

069E

06A4

06A8

06AA

— — — INT1R<4:0> — — — — — — — —

— — — — — — — — — — —INT2R<4:0>

— — —T3CKR<4:0>— — —T2CKR<4:0>

— — — IC2R<4:0> — — — IC1R<4:0>

— — — IC8R<4:0> — — — IC7R<4:0>

— — — — — — — — — — —OCFAR<4:0>

— — — — — — — — — — —FLTA1R<4:0>

— — — — — — — — — — —FLTA2R<4:0>

— — — QEB1R<4:0> — — —QEA1R<4:0>

— — — — — — — — — — — INDX1R<4:0>

— — — U1CTSR<4:0> — — —U1RXR<4:0>

— — —SCK1R<4:0> — — —SDI1R<4:0>

— — — — — — — — — — — SS1R<4:0>

TABLE 4-17: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ32MC202

File

Name

RPOR0

RPOR1

RPOR2

RPOR3

RPOR4

RPOR5

RPOR6

RPOR7

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

06C0 — — — RP1R<4:0> — — — RP0R<4:0>

06C2

06C4

06C6

06C8

06CA

06CC

06CE

— — — RP3R<4:0> — — — RP2R<4:0>

— — — RP5R<4:0> — — — RP4R<4:0>

— — — RP7R<4:0> — — — RP6R<4:0>

— — — RP9R<4:0> — — — RP8R<4:0>

— — —RP11R<4:0>— — — RP10R<4:0>

— — —RP13R<4:0>— — — RP12R<4:0>

— — —RP15R<4:0>— — — RP14R<4:0>

All

Resets

1F00

001F

1F1F

001F

1F1F

001F

1F1F

001F

All

Resets

0000

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

Page 43

TABLE 4-18: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ32MC204 AND dsPIC33FJ16MC304

File

Name

RPOR0

RPOR1

RPOR2

RPOR3

RPOR4

RPOR5

RPOR6

RPOR7

RPOR8

RPOR9

RPOR10

RPOR11

RPOR12

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets

06C0 — — — RP1R<4:0> — — — RP0R<4:0>

06C2

06C4

06C6

06C8

06CA

06CC

06CE

06D0

06D2

06D4

06D6

06D8

— — — RP3R<4:0> — — —RP2R<4:0>

— — — RP5R<4:0> — — —RP4R<4:0>

— — — RP7R<4:0> — — —RP6R<4:0>

— — — RP9R<4:0> — — —RP8R<4:0>

— — —RP11R<4:0>— — — RP10R<4:0>

— — —RP13R<4:0>— — — RP12R<4:0>

— — —RP15R<4:0>— — — RP14R<4:0>

— — —RP17R<4:0>— — — RP16R<4:0>

— — —RP19R<4:0>— — — RP18R<4:0>

— — —RP21R<4:0>— — — RP20R<4:0>

— — —RP23R<4:0>— — — RP22R<4:0>

— — —RP25R<4:0>— — — RP24R<4:0>

TABLE 4-19: PORTA REGISTER MAP FOR dsPIC33FJ32MC202

File

Name

TRISA 02C0

PORTA 02C2

LATA 02C4

ODCA 02C6

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets

— — — — — — — — — — —

— — — — — — — — — — — RA4 RA3 RA2 RA1 RA0

— — — — — — — — — — — L ATA4 L ATA3 L ATA2 L ATA1 LATA 0

— — — — — — — — — — —

TRISA4 TRISA3 TRISA2 TRISA1 TRISA0

ODCA4 ODCA3 ODCA2 ODCA1 ODCA0

0000

001F

xxxx

0000

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

TABLE 4-20: PORTA REGISTER MAP FOR dsPIC33FJ32MC204 AND dsPIC33FJ16MC304

File

Name

TRISA 02C0

PORTA 02C2

LATA 02C4

ODCA 02C6

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets

— — — — — TRISA10 TRISA9 TRISA8 TRISA7 — —

— — — — — RA10 RA9 RA8 RA7 — — RA4 RA3 RA2 RA1 RA0

— — — — — LAT10 LAT8 LAT8 LAT7 — — L ATA4 LATA 3 L ATA2 L ATA1 LATA 0

— — — — — ODCA10 ODCA9 ODCA8 ODCA7 — —

TRISA4 TRISA3 TRISA2 TRISA1 TRISA0

ODCA4 ODCA3 ODCA2 ODCA1 ODCA0

079F

xxxx

0000

Page 44

TABLE 4-21: PORTB REGISTER MAP

File

Name

TRISB 02C8 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB6 TRISB5 TRISB1 TRISB0

PORTB 02CA RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB6 RB5 RB1 RB0

LATB 02CC LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB6 LATB5 LATB1 LATB0

ODCB 02CE

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets

ODCB15 ODCB14 ODCB13 ODCB12 ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 ODCB4 ODCB6 ODCB5 ODCB1 ODCB0

TABLE 4-22: PORTC REGISTER MAP FOR dsPIC33FJ32MC204 AND dsPIC33FJ16MC304

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets

TRISC

PORTC

LATC

ODCC

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

02D0

02D2

02D4

02D6

— — — — — —

TRISC9 TRISC8 TRISC7

RC9 RC8 RC7

LATC9 LATC8 LATC7

ODCC9 ODCC8 ODCC7

TABLE 4-23: SYSTEM CONTROL REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

RCON 0740 TRAPR IOPUWR — — — — CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR

OSCCON 0742 —COSC<2:0>— NOSC<2:0> CLKLOCK IOLOCK LOCK —CF— LPOSCEN OSWEN 0300

CLKDIV 0744 ROI DOZE<2:0> DOZEN FRCDIV<2:0> PLLPOST<1:0> — PLLPRE<4:0> 3040

PLLFBD 0746

OSCTUN 0748

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: RCON register Reset values dependent on type of Reset.

2: OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset.

— — — — — — — PLLDIV<8:0> 0030

— — — — — — — — — —TUN<5:0>0000

TRISC6 TRISC5

RC6 RC5

LATC6 LATC5

ODCC6 ODCC5

TRISC4

RC4

LATC4

ODCC4

TRISC6 TRISC5

RC6 RC5

LATC6 LATC5

ODCC6 ODCC5

TRISC1 TRISC0

RC1 RC0

LATC1 LATC0

ODCC1 ODCC0

FFFF

xxxx

0000

03FF

xxxx

0000

All

Resets

xxxx

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

(1)

(2)

Page 45

TABLE 4-24: NVM REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

NVMCON 0760 WR WREN WRERR — — — — — — ERASE — —NVMOP<3:0>

NVMKEY 0766

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.

— — — — — — — — NVMKEY<7:0>

TABLE 4-25: PMD REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PMD1 0770

PMD2 0772 IC8MD IC7MD

PMD3 0774

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

— —

— — — — — — — — — — —PWM2MD— — — — 0000

T3MD T2MD T1MD QEIMD PWM1MD

— — — —IC2MDIC1MD— — — — — —OC2MDOC1MD0000

—

I2C1MD

—

U1MD

—

SPI1MD

— —

AD1MD 0000

All

Resets

0000

All

Resets

(1)

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

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dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

PC<15:0>

000000000

015

W15 (before CALL)

W15 (after CALL)

Stack Grows Toward

Higher Address

0x0000

PC<22:16>

POP : [--W15] PUSH : [W15++]

4.4.1 SOFTWARE STACK

In addition to its use as a working register, the W15 register in the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It predecrements for stack pops and post-increments for stack pushes, as shown in Figure 4-4. For a PC push during any CALL instruction, the MSb of the PC is zero-extended before the push, ensuring that the MSb is always clear.

Note: A PC push during exception processing

concatenates the SRL register to the MSb of the PC prior to the push.

The Stack Pointer Limit register (SPLIM) associated with the Stack Pointer sets an upper address boundary for the stack. SPLIM is uninitialized at Reset. As is the case for the Stack Pointer, SPLIM<0> is forced to ‘0’ because all stack operations must be word-aligned.

Whenever an EA is generated using W15 as a source or destination pointer, the resulting address is compared with the value in SPLIM. If the contents of the Stack Pointer (W15) and the SPLIM register are equal and a push operation is performed, a stack error trap will not occur. The stack error trap will occur on a subsequent push operation. For example, to cause a stack error trap when the stack grows beyond address 0x1000 in RAM, initialize the SPLIM with the value 0x0FFE.

Similarly, a Stack Pointer underflow (stack error) trap is generated when the Stack Pointer address is found to be less than 0x0800. This prevents the stack from interfering with the Special Function Register (SFR) space.

A write to the SPLIM register should not be immediately followed by an indirect read operation using W15.

FIGURE 4-4: CALL STACK FRAME

4.4.2 DATA RAM PROTECTION FEATURE

The dsPIC33F product family supports Data RAM protection features that enable segments of RAM to be protected when used in conjunction with Boot and Secure Code Segment Security. BSRAM (Secure RAM segment for BS) is accessible only from the Boot Segment Flash code when enabled. SSRAM (Secure RAM segment for RAM) is accessible only from the Secure Segment Flash code when enabled. See

Table 4-1 for an overview of the BSRAM and SSRAM

SFRs.

4.5 Instruction Addressing Modes

The addressing modes shown in Table 4-26 form the basis of the addressing modes optimized to support the specific features of individual instructions. The addressing modes provided in the MAC class of instructions differ from those in the other instruction types.

4.5.1 FILE REGISTER INSTRUCTIONS

Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space). Most file register instructions employ a working register, W0, which is denoted as WREG in these instructions. The destination is typically either the same file register or WREG (with the exception of the MUL instruction), which writes the result to a register or register pair. The MOV instruction allows additional flexibility and can access the entire data space.

4.5.2 MCU INSTRUCTIONS

The three-operand MCU instructions are of the form:

Operand 3 = Operand 1 <function> Operand 2

where Operand 1 is always a working register (that is, the addressing mode can only be register direct), which is referred to as Wb. Operand 2 can be a W register, fetched from data memory, or a 5-bit literal. The result location can be either a W register or a data memory location. The following addressing modes are supported by MCU instructions:

• Register Direct

• Register Indirect

• Register Indirect Post-Modified

• Register Indirect Pre-Modified

• 5-bit or 10-bit Literal

Note: Not all instructions support all the

addressing modes given above. Individual instructions can support different subsets of these addressing modes.

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TABLE 4-26: FUNDAMENTAL ADDRESSING MODES SUPPORTED

Addressing Mode Description

File Register Direct The address of the file register is specified explicitly.

or decremented) by a constant value.

to form the EA.

The sum of Wn and Wb forms the EA.

4.5.3 MOVE AND ACCUMULATOR INSTRUCTIONS

Move instructions and the DSP accumulator class of instructions provide a greater degree of addressing flexibility than other instructions. In addition to the addressing modes supported by most MCU instructions, move and accumulator instructions also support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode.

Note: For the MOV instructions, the addressing

mode specified in the instruction can differ for the source and destination EA. However, the 4-bit Wb (Register Offset) field is shared by both source and destination (but typically only used by one).

In summary, the following addressing modes are supported by move and accumulator instructions:

• Register Direct

• Register Indirect

• Register Indirect Post-modified

• Register Indirect Pre-modified

• Register Indirect with Register Offset (Indexed)

• Register Indirect with Literal Offset

• 8-bit Literal

• 16-bit Literal

Note: Not all instructions support all the

addressing modes given above. Individual instructions may support different subsets of these addressing modes.

4.5.4 MAC INSTRUCTIONS

The dual source operand DSP instructions (CLR, ED, EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also referred to as MAC instructions, use a simplified set of addressing modes to allow the user application to effectively manipulate the data pointers through register indirect tables.

The two-source operand prefetch registers must be members of the set {W8, W9, W10, W11}. For data reads, W8 and W9 are always directed to the X RAGU, and W10 and W11 are always directed to the Y AGU. The effective addresses generated (before and after modification) must, therefore, be valid addresses within X data space for W8 and W9 and Y data space for W10 and W11.

Note: Register Indirect with Register Offset

Addressing mode is available only for W9 (in X space) and W11 (in Y space).

In summary, the following addressing modes are supported by the MAC class of instructions:

• Register Indirect

• Register Indirect Post-Modified by 2

• Register Indirect Post-Modified by 4

• Register Indirect Post-Modified by 6

• Register Indirect with Register Offset (Indexed)

4.5.5 OTHER INSTRUCTIONS

Besides the addressing modes outlined previously, some instructions use literal constants of various sizes. For example, BRA (branch) instructions use 16-bit signed literals to specify the branch destination directly, whereas the DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ADD Acc, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands.

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0x1100

0x1163

Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words

Byte

Address

MOV #0x1100, W0 MOV W0, XMODSRT ;set modulo start address MOV #0x1163, W0 MOV W0, MODEND ;set modulo end address MOV #0x8001, W0 MOV W0, MODCON ;enable W1, X AGU for modulo

MOV #0x0000, W0 ;W0 holds buffer fill value

MOV #0x1110, W1 ;point W1 to buffer

DO AGAIN, #0x31 ;fill the 50 buffer locations MOV W0, [W1++] ;fill the next location AGAIN: INC W0, W0 ;increment the fill value

4.6 Modulo Addressing

Modulo Addressing mode is a method of providing an automated means to support circular data buffers using hardware. The objective is to remove the need for software to perform data address boundary checks when executing tightly looped code, as is typical in many DSP algorithms.

Modulo Addressing can operate in either data or program space (since the data pointer mechanism is essentially the same for both). One circular buffer can be supported in each of the X (which also provides the pointers into program space) and Y data spaces. Modulo Addressing can operate on any W register pointer. However, it is not advisable to use W14 or W15 for Modulo Addressing since these two registers are used as the Stack Frame Pointer and Stack Pointer, respectively.

In general, any particular circular buffer can be configured to operate in only one direction as there are certain restrictions on the buffer start address (for incrementing buffers), or end address (for decrementing buffers), based upon the direction of the buffer.

The only exception to the usage restrictions is for buffers that have a power-of-two length. As these buffers satisfy the start and end address criteria, they can operate in a bidirectional mode (that is, address boundary checks are performed on both the lower and upper address boundaries).

4.6.1 START AND END ADDRESS

The Modulo Addressing scheme requires that a starting and ending address be specified and loaded into the 16-bit Modulo Buffer Address registers: XMODSRT, XMODEND, YMODSRT and YMODEND (see Ta bl e 4 - 1).

Note: Y space Modulo Addressing EA

calculations assume word-sized data (LSb of every EA is always clear).

The length of a circular buffer is not directly specified. It is determined by the difference between the corresponding start and end addresses. The maximum possible length of the circular buffer is 32K words (64 Kbytes).

4.6.2 W ADDRESS REGISTER SELECTION

The Modulo and Bit-Reversed Addressing Control register, MODCON<15:0>, contains enable flags as well as a W register field to specify the W Address registers. The XWM and YWM fields select the registers that will operate with Modulo Addressing:

•If XWM = 15, X RAGU and X WAGU Modulo

Addressing is disabled.

•If YWM = 15, Y AGU Modulo Addressing is

disabled.

The X Address Space Pointer W register (XWM), to which Modulo Addressing is to be applied, is stored in MODCON<3:0> (see Table 4-1). Modulo Addressing is enabled for X data space when XWM is set to any value other than ‘15’ and the XMODEN bit is set at MODCON<15>.

The Y Address Space Pointer W register (YWM) to which Modulo Addressing is to be applied is stored in MODCON<7:4>. Modulo Addressing is enabled for Y data space when YWM is set to any value other than ‘15’ and the YMODEN bit is set at MODCON<14>.

FIGURE 4-5: MODULO ADDRESSING OPERATION EXAMPLE

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dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

4.6.3 MODULO ADDRESSING APPLICABILITY

Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W register. Address boundaries check for addresses equal to:

• The upper boundary addresses for incrementing

buffers

• The lower boundary addresses for decrementing

buffers

It is important to realize that the address boundaries check for addresses less than or greater than the upper (for incrementing buffers) and lower (for decrementing buffers) boundary addresses (not just equal to). Address changes can, therefore, jump beyond boundaries and still be adjusted correctly.

Note: The modulo corrected effective address is

written back to the register only when Pre-Modify or Post-Modify Addressing mode is used to compute the effective address. When an address offset (such as [W7 + W2]) is used, Modulo Address correction is performed but the contents of the register remain unchanged.

4.7 Bit-Reversed Addressing

Bit-Reversed Addressing mode is intended to simplify data re-ordering for radix-2 FFT algorithms. It is supported by the X AGU for data writes only.

The modifier, which can be a constant value or register contents, is regarded as having its bit order reversed. The address source and destination are kept in normal order. Thus, the only operand requiring reversal is the modifier.

4.7.1 BIT-REVERSED ADDRESSING IMPLEMENTATION

Bit-Reversed Addressing mode is enabled in any of these situations:

• BWM bits (W register selection) in the MODCON

• The BREN bit is set in the XBREV register

• The addressing mode used is Register Indirect

with Pre-Increment or Post-Increment

If the length of a bit-reversed buffer is M = 2 the last ‘N’ bits of the data buffer start address must be zeros.

XB<14:0> is the Bit-Reversed Address modifier, or ‘pivot point’, which is typically a constant. In the case of an FFT computation, its value is equal to half of the FFT data buffer size.

Note: All bit-reversed EA calculations assume

word-sized data (LSb of every EA is always clear). The XB value is scaled accordingly to generate compatible (byte) addresses.

When enabled, Bit-Reversed Addressing is executed only for Register Indirect with Pre-Increment or Post-Increment Addressing and word-sized data writes. It will not function for any other addressing mode or for byte-sized data, and normal addresses are generated instead. When Bit-Reversed Addressing is active, the W Address Pointer is always added to the address modifier (XB), and the offset associated with the Register Indirect Addressing mode is ignored. In addition, as word-sized data is a requirement, the LSb of the EA is ignored (and always clear).

Note: Modulo Addressing and Bit-Reversed

Addressing should not be enabled together. If an application attempts to do so, Bit-Reversed Addressing will assume priority when active for the X WAGU and X WAGU, Modulo Addressing will be disabled. However, Modulo Addressing will continue to function in the X RAGU.

If Bit-Reversed Addressing has already been enabled by setting the BREN bit (XBREV<15>), a write to the XBREV register should not be immediately followed by an indirect read operation using the W register that has been designated as the bit-reversed pointer.

bytes,

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dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

b3 b2 b1 0

b2 b3 b4

Bit Locations Swapped Left-to-Right Around Center of Binary Value

Bit-Reversed Address

XB = 0x0008 for a 16-Word Bit-Reversed Buffer

b7 b6 b5 b1

b7 b6 b5 b4

b11 b10 b9 b8

b15 b14 b13 b12

Sequential Address

Pivot Point

FIGURE 4-6: BIT-REVERSED ADDRESS EXAMPLE

TABLE 4-27: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)

Normal Address Bit-Reversed Address

A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal

0000 0 0000 0

0001 1 1000 8

0010 2 0100 4

0011 3 1100 12

0100 4 0010 2

0101 5 1010 10

0110 6 0110 6

0111 7 1110 14

1000 8 0001 1

1001 9 1001 9

1010 10 0101 5

1011 11 1101 13

1100 12 0011 3

1101 13 1011 11

1110 14 0111 7

1111 15 1111 15

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dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

4.8 Interfacing Program and Data

Memory Spaces

The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 architecture uses a 24-bit-wide program space and a 16-bit-wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces.

Aside from normal execution, the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 architecture provides two methods by which program space can be accessed during operation:

• Using table instructions to access individual bytes

or words anywhere in the program space

• Remapping a portion of the program space into

the data space (Program Space Visibility)

Table instructions allow an application to read or write to small areas of the program memory. This capability makes the method ideal for accessing data tables that need to be updated periodically. It also allows access to all bytes of the program word. The remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look-ups from a large table of static data. The application can only access the least significant word of the program word.

4.8.1 ADDRESSING PROGRAM SPACE

Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. The solution depends on the interface method to be used.

For table operations, the 8-bit Table Page register (TBLPAG) is used to define a 32K word region within the program space. This is concatenated with a 16-bit EA to arrive at a full 24-bit program space address. In this format, the Most Significant bit of TBLPAG is used to determine if the operation occurs in the user memory (TBLPAG<7> = 0) or the configuration memory (TBLPAG<7> = 1).

For remapping operations, the 8-bit Program Space Visibility register (PSVPAG) is used to define a 16K word page in the program space. When the Most Significant bit of the EA is ‘1’, PSVPAG is concatenated with the lower 15 bits of the EA to form a 23-bit program space address. Unlike table operations, this limits remapping operations strictly to the user memory area.

Table 4-28 and Figure 4-7 show how the program EA is

created for table operations and remapping accesses from the data EA. Here, P<23:0> refers to a program space word, and D<15:0> refers to a data space word.

TABLE 4-28: PROGRAM SPACE ADDRESS CONSTRUCTION

Access Type

Instruction Access (Code Execution)

TBLRD/TBLWT

(Byte/Word Read/Write)

Program Space Visibility (Block Remap/Read)

Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of

the address is PSVPAG<0>.

Access

Space

User 0 PC<22:1> 0

User TBLPAG<7:0> Data EA<15:0>

Configuration TBLPAG<7:0> Data EA<15:0>

User 0 PSVPAG<7:0> Data EA<14:0>

<23> <22:16> <15> <14:1> <0>

0xx xxxx xxxx xxxx xxxx xxx0

0xxx xxxx xxxx xxxx xxxx xxxx

1xxx xxxx xxxx xxxx xxxx xxxx

0 xxxx xxxx xxx xxxx xxxx xxxx

Program Space Address

(1)

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dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

0Program Counter

23 bits

PSVPAG

8 bits

15 bits

Program Counter

(1)

Select

TBLPAG

8 bits

16 bits

Byte Select

1/0

User/Configuration

Table Operations

(2)

Program Space Visibility

(1)

Space Se lect

24 bits

23 bits

(Remapping)

1/0

Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to

maintain word alignment of data in the program and data spaces.

2: Table operations are not required to be word-aligned. Table read operations are permitted

in the configuration memory space.

FIGURE 4-7: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

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dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

081623

00000000

‘Phantom’ Byte

TBLRDH.B (Wn<0> = 0)

TBLRDL.W

TBLRDL.B (Wn<0> = 1)

TBLRDL.B (Wn<0> = 0)

23 15 0

TBLPAG

0x000000

0x800000

0x020000

0x030000

Program Space

The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in the user memory area.

4.8.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS

The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data.

The PC is incremented by two for each successive 24-bit program word. This allows program memory addresses to directly map to data space addresses. Program memory can thus be regarded as two 16-bit-wide word address spaces, residing side by side, each with the same address range. TBLRDL and TBLWTL access the space that contains the least significant data word. TBLRDH and TBLWTH access the space that contains the upper data byte.

Two table instructions are provided to move byte or word-sized (16-bit) data to and from program space. Both function as either byte or word operations.

• TBLRDL (Table Read Low):

- In Word mode, this instruction maps the lower word of the program space location (P<15:0>) to a data address (D<15:0>).

- In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower byte is selected when it is ‘0’.

• TBLRDH (Table Read High):

- In Word mode, this instruction maps the entire upper word of a program address (P<23:16>) to a data address. Note that D<15:8>, the ‘phantom byte’, will always be ‘0’.

- In Byte mode, this instruction maps the upper or lower byte of the program word to D<7:0> of the data address, in the TBLRDL instruction. The data is always ‘0’ when the upper ‘phantom’ byte is selected (Byte Select = 1).

In a similar fashion, two table instructions, TBLWTH and TBLWTL, are used to write individual bytes or words to a program space address. The details of their operation are explained in Section 5.0 “Flash

Program Memory”.

For all table operations, the area of program memory space to be accessed is determined by the Table Page register (TBLPAG). TBLPAG covers the entire program memory space of the device, including user and configuration spaces. When TBLPAG<7> = 0, the table page is located in the user memory space. When TBLPAG<7> = 1, the page is located in configuration space.

FIGURE 4-8: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS

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23 15 0

PSVPAG

Data Space

Program Space

0x0000

0x8000

0xFFFF

0x000000

0x800000

0x010000

0x018000

When CORCON<2> = 1 and EA<15> = 1:

The data in the page designated by PSVPAG is mapped into the upper half of the data memory space...

Data EA<14:0>

...while the lower 15 bits of the EA specify an exact address within the PSV area. This corresponds exactly to the same lower 15 bits of the actual program space address.

PSV Area

4.8.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY

The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This option provides transparent access to stored constant data from the data space without the need to use special instructions (such as TBLRDL/H).

Program space access through the data space occurs if the Most Significant bit of the data space EA is ‘1’ and program space visibility is enabled by setting the PSV bit in the Core Control register (CORCON<2>). The location of the program memory space to be mapped into the data space is determined by the Program Space Visibility Page register (PSVPAG). This 8-bit register defines any one of 256 possible pages of 16K words in program space. In effect, PSVPAG functions as the upper 8 bits of the program memory address, with the 15 bits of the EA functioning as the lower bits. By incrementing the PC by 2 for each program memory word, the lower 15 bits of data space addresses directly map to the lower 15 bits in the corresponding program space addresses.

Data reads to this area add a cycle to the instruction being executed, since two program memory fetches are required.

Although each data space address 8000h and higher maps directly into a corresponding program memory address (see Figure 4-9), only the lower 16 bits of the

24-bit program word are used to contain the data. The upper 8 bits of any program space location used as data should be programmed with ‘1111 1111’ or ‘0000 0000’ to force a NOP. This prevents possible issues should the area of code ever be accidentally executed.

Note: PSV access is temporarily disabled during

table reads/writes.

For operations that use PSV and are executed outside a REPEAT loop, the MOV and MOV.D instructions require one instruction cycle in addition to the specified execution time. All other instructions require two instruction cycles in addition to the specified execution time.

For operations that use PSV, and are executed inside a REPEAT loop, these instances require two instruction cycles in addition to the specified execution time of the instruction:

• Execution in the first iteration

• Execution in the last iteration

• Execution prior to exiting the loop due to an interrupt

• Execution upon re-entering the loop after an interrupt is serviced

Any other iteration of the REPEAT loop will allow the instruction using PSV to access data, to execute in a single cycle.

FIGURE 4-9: PROGRAM SPACE VISIBILITY OPERATION

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Program Counter

24 bits

Program Counter

TBLPAG Reg

8 bits

Working Reg EA

16 bits

Byte

24-bit EA

1/0

Select

Using Table Instruction

Using

User/Configuration Space Select

5.0 FLASH PROGRAM MEMORY

Note 1: This data sheet summarizes the features

of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section

5. “Flash Programming” (DS70191) of the “dsPIC33F/PIC24H Family Refer- ence Manual” which is available from the Microchip web site (www.microchip.com)

2: Some registers and associated bits

described in this section may not be available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register and bit information.

The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices contain internal Flash program memory for storing and executing application code. The memory is readable, writable and erasable during normal operation over the entire V

Flash memory can be programmed in two ways:

• In-Circuit Serial Programming™ (ICSP™) programming capability

• Run-Time Self-Programming (RTSP)

ICSP allows a dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 device to be serially programmed while in the end application circuit. This is done with two lines for programming clock and programming data (one of the alternate programming pin pairs: PGECx/PGEDx), and three other lines for power (V ground (VSS) and Master Clear (MCLR). This allows

DD range.

DD),

customers to manufacture boards with unprogrammed devices and then program the digital signal controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed.

RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user application can write program memory data either in blocks or ‘rows’ of 64 instructions (192 bytes) at a time or a single program memory word, and erase program memory in blocks or ‘pages’ of 512 instructions (1536 bytes) at a time.

5.1 Table Instructions and Flash

Programming

Regardless of the method used, all programming of Flash memory is done with the table read and table write instructions. These allow direct read and write access to the program memory space from the data memory while the device is in normal operating mode. The 24-bit target address in the program memory is formed using bits <7:0> of the TBLPAG register and the Effective Address (EA) from a W register specified in the table instruction, as shown in Figure 5-1.

The TBLRDL and the TBLWTL instructions are used to read or write to bits <15:0> of program memory. TBLRDL and TBLWTL can access program memory in both Word and Byte modes.

The TBLRDH and TBLWTH instructions are used to read or write to bits <23:16> of program memory. TBLRDH and TBLWTH can also access program memory in Word or Byte mode.

FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS

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7.37 MHz FRC Accuracy()% FRC Tuning()%××

----------------------------------------------------------------------------------------------------------------------------

11064 Cycles

7.37 MHz 10.05+()1 0.00375–()××

------------------------------------------------------------------------------------------------

1.435ms==

11064 Cycles

7.37 MHz 10.05–()1 0.00375–()××

------------------------------------------------------------------------------------------------

1.586ms==

5.2 RTSP Operation

The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of eight rows (512 instructions) at a time, and to program one row or one word at a time. Table 24-12 shows typical erase and programming times. The 8-row erase pages and single row write rows are edge-aligned from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively.

The program memory implements holding buffers that can contain 64 instructions of programming data. Prior to the actual programming operation, the write data must be loaded into the buffers sequentially. The instruction words loaded must always be from a group of 64 boundary.

The basic sequence for RTSP programming is to set up a Table Pointer, then do a series of TBLWT instructions to load the buffers. Programming is performed by setting the control bits in the NVMCON register. A total of 64 TBLWTL and TBLWTH instructions are required to load the instructions.

All of the table write operations are single-word writes (two instruction cycles) because only the buffers are written. A programming cycle is required for programming each row.

5.3 Programming Operations

A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. The processor stalls (waits) until the programming operation is finished.

The programming time depends on the FRC accuracy (see Table 24-18, “AC Characteristics: Internal RC

Accuracy”) and the value of the FRC Oscillator Tuning

register (see Register 8-4). Use the following formula to calculate the minimum and maximum values for the Row Write Time, Page Erase Time, and Word Write Cycle Time parameters (see Table 24-12, “DC

Characteristics: Program Memory”).

EQUATION 5-1: PROGRAMMING TIME

EQUATION 5-2: MINIMUM ROW WRITE

TIME

The maximum row write time is equal to Equation 5-3.

EQUATION 5-3: MAXIMUM ROW WRITE

TIME

Setting the WR bit (NVMCON<15>) starts the operation, and the WR bit is automatically cleared when the operation is finished.

5.4 Flash Memory Resources

Note: In the event you are not able to access

the product page using the link above, enter this URL in your browser:

http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en530334

5.4.1 KEY RESOURCES

• Section 5. “Flash Programming” (DS70191)

• Code Samples

• Application Notes

• Software Libraries

• Webinars

• All related dsPIC33F/PIC24H Family Reference Manuals Sections

• Development Tools

5.5 Control Registers

For example, if the device is operating at +125° C, the FRC accuracy will be ±5%. If the TUN<5:0> bits (see

write time is equal to Equation 5-2.

Two SFRs are used to read and write the program Flash memory: NVMCON and NVMKEY.

The NVMCON register (Register 5-1) controls which blocks are to be erased, which memory type is to be programmed and the start of the programming cycle.

NVMKEY is a write-only register that is used for write protection. To start a programming or erase sequence, the user application must consecutively write 0x55 and 0xAA to the NVMKEY register. Refer to Section 5.3

“Programming Operations” for further details.

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dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER

R/SO-0

(1)

WR WREN WRERR

bit 15 bit 8

R/W-0

(1)

R/W-0

(1)

U-0 U-0 U-0 U-0 U-0

— — — — —

U-0 R/W-0

(1)

U-0 U-0 R/W-0

— ERASE — —NVMOP<3:0>

(1)

R/W-0

(1)

R/W-0

(2)

(1)

R/W-0

(1)

bit 7 bit 0

Legend: SO = Settable Only bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 WR: Write Control bit

1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is

cleared by hardware once operation is complete

0 = Program or erase operation is complete and inactive

bit 14 WREN: Write Enable bit

1 = Enable Flash program/erase operations 0 = Inhibit Flash program/erase operations

bit 13 WRERR: Write Sequence Error Flag bit

1 = An improper program or erase sequence attempt or termination has occurred (bit is set

automatically on any set attempt of the WR bit)

0 = The program or erase operation completed normally

bit 12-7 Unimplemented: Read as ‘0’

bit 6 ERASE: Erase/Program Enable bit

1 = Perform the erase operation specified by NVMOP<3:0> on the next WR command 0 = Perform the program operation specified by NVMOP<3:0> on the next WR command

bit 5-4 Unimplemented: Read as ‘0’

bit 3-0 NVMOP<3:0>: NVM Operation Select bits

(2)

If ERASE = 1:

1111 = Memory bulk erase operation 1101 = Erase General Segment 1100 = Erase Secure Segment 0011 = No operation 0010 = Memory page erase operation 0001 = No operation 0000 = Erase a single Configuration register byte

If ERASE =

1111 = No operation 1101 = No operation 1100 = No operation 0011 = Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte

Note 1: These bits can only be Reset on a POR.

2: All other combinations of NVMOP<3:0> are unimplemented.

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dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

REGISTER 5-2: NVMKEY: NONVOLATILE MEMORY KEY REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0

NVMKEY<7:0>

bit 7 bit 0

Legend: SO = Settable Only bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-8 Unimplemented: Read as ‘0’

bit 7-0 NVMKEY<7:0>: Key Register (write-only) bits

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dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

; Set up NVMCON for block erase operation

MOV #0x4042, W0 ; MOV W0, NVMCON ; Initialize NVMCON

; Init pointer to row to be ERASED

MOV #tblpage(PROG_ADDR), W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #tbloffset(PROG_ADDR), W0 ; Initialize in-page EA[15:0] pointer TBLWTL W0, [W0] ; Set base address of erase block DISI #5 ; Block all interrupts with priority <7

; for next 5 instructions MOV #0x55, W0 MOV W0, NVMKEY ; Write the 55 key MOV #0xAA, W1 ; MOV W1, NVMKEY ; Write the AA key BSET NVMCON, #WR ; Start the erase sequence NOP ; Insert two NOPs after the erase NOP ; command is asserted

5.5.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY

Programmers can program one row of program Flash memory at a time. To do this, it is necessary to erase the 8-row erase page that contains the desired row. The general process is:

1. Read eight rows of program memory

(512 instructions) and store in data RAM.

2. Update the program data in RAM with the

desired new data.

3. Erase the block (see Example 5-1):

a) Set the NVMOP bits (NVMCON<3:0>) to

‘0010’ to configure for block erase. Set the ERASE (NVMCON<6>) and WREN (NVMCON<14>) bits.

b) Write the starting address of the page to be

erased into the TBLPAG and W registers. c) Write 0x55 to NVMKEY. d) Write 0xAA to NVMKEY. e) Set the WR bit (NVMCON<15>). The erase

cycle begins and the CPU stalls for the

duration of the erase cycle. When the erase is

done, the WR bit is cleared automatically.

4. Write the first 64 instructions from data RAM into the program memory buffers (see Example 5-2).

5. Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure

for row programming. Clear the ERASE bit

and set the WREN bit. b) Write 0x55 to NVMKEY. c) Write 0xAA to NVMKEY. d) Set the WR bit. The programming cycle

begins and the CPU stalls for the duration of

the write cycle. When the write to Flash

memory is done, the WR bit is cleared

automatically.

6. Repeat steps 4 and 5, using the next available 64 instructions from the block in data RAM by incrementing the value in TBLPAG, until all 512 instructions are written back to Flash memory.

For protection against accidental operations, the write initiate sequence for NVMKEY must be used to allow any erase or program operation to proceed. After the programming command has been executed, the user application must wait for the programming time until programming is complete. The two instructions following the start of the programming sequence should be NOPs, as shown in Example 5-3.

EXAMPLE 5-1: ERASING A PROGRAM MEMORY PAGE

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; Set up NVMCON for row programming operations

MOV #0x4001, W0 ;

MOV W0, NVMCON ; Initialize NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled

MOV #0x0000, W0 ;

MOV W0, TBLPAG ; Initialize PM Page Boundary SFR

MOV #0x6000, W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word

MOV #LOW_WORD_0, W2 ;

MOV #HIGH_BYTE_0, W3 ;

TBLWTL W2, [W0] ; Write PM low word into program latch

TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 1st_program_word

MOV #LOW_WORD_1, W2 ;

MOV #HIGH_BYTE_1, W3 ;

TBLWTL W2, [W0] ; Write PM low word into program latch

TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 2nd_program_word

MOV #LOW_WORD_2, W2 ;

MOV #HIGH_BYTE_2, W3 ;

TBLWTL W2, [W0] ; Write PM low word into program latch

TBLWTH W3, [W0++] ; Write PM high byte into program latch

•

; 63rd_program_word

MOV #LOW_WORD_31, W2 ;

MOV #HIGH_BYTE_31, W3 ;

TBLWTL W2, [W0] ; Write PM low word into program latch

TBLWTH W3, [W0++] ; Write PM high byte into program latch

DISI #5 ; Block all interrupts with priority <7

EXAMPLE 5-2: LOADING THE WRITE BUFFERS

EXAMPLE 5-3: INITIATING A PROGRAMMING SEQUENCE

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dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

MCLR

VDD

Internal

Regulator

BOR

Sleep or Idle

RESET Instruction

WDT

Module

Glitch Filter

Trap Conflict

Illegal Opcode

Uninitialized W Register

SYSRST

VDD Rise

Detect

POR

Configuration Mismatch

6.0 RESETS

Note 1: This data sheet summarizes the features

“dsPIC33F/PIC24H Family Reference Manual”, which is available from the

Microchip web site (www.microchip.com).

2: Some registers and associated bits

described in this section may not be available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register and bit information.

The Reset module combines all reset sources and controls the device Master Reset Signal, SYSRST. The following is a list of device Reset sources:

• POR: Power-on Reset

• BOR: Brown-out Reset

•MCLR

•SWR: RESET Instruction

• WDTO: Watchdog Timer Reset

• CM: Configuration Mismatch Reset

• TRAPR: Trap Conflict Reset

• IOPUWR: Illegal Condition Device Reset

: Master Clear Pin Reset

- Illegal Opcode Reset

- Uninitialized W Register Reset

- Security Reset

A simplified block diagram of the Reset module is shown in Figure 6-1.

Any active source of reset will make the SYSRST signal active. On system Reset, some of the registers associated with the CPU and peripherals are forced to a known Reset state and some are unaffected.

Note: Refer to the specific peripheral section or

Section 3.0 “CPU” of this manual for

All types of device Reset sets a corresponding status bit in the RCON register to indicate the type of Reset (see Register 6-1).

A POR clears all the bits, except for the POR bit (RCON<0>), that are set. The user application can set or clear any bit at any time during code execution. The RCON bits only serve as status bits. Setting a particular Reset status bit in software does not cause a device Reset to occur.

The RCON register also has other bits associated with the Watchdog Timer and device power-saving states. The function of these bits is discussed in other sections of this manual.

Note: The status bits in the RCON register

should be cleared after they are read so that the next RCON register value after a device Reset is meaningful.

FIGURE 6-1: RESET SYSTEM BLOCK DIAGRAM

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6.1 Resets Resources

Note: In the event you are not able to access

the product page using the link above, enter this URL in your browser:

http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en530334

6.1.1 KEY RESOURCES

• Section 8. “Reset” (DS70192)

• Code Samples

• Application Notes

• Software Libraries

• Webinars

• All related dsPIC33F/PIC24H Family Reference Manuals Sections

• Development Tools

Page 63

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

6.2 Reset Control Registers

R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

TRAPR IOPUWR

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1

EXTR SWR SWDTEN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 TRAPR: Trap Reset Flag bit

1 = A Trap Conflict Reset has occurred 0 = A Trap Conflict Reset has not occurred

bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit

1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an

Address Pointer caused a Reset

0 = An illegal opcode or uninitialized W Reset has not occurred

bit 13-10 Unimplemented: Read as ‘0’

bit 9 CM: Configuration Mismatch Flag bit

1 = A configuration mismatch Reset has occurred 0 = A configuration mismatch Reset has NOT occurred

bit 8 VREGS: Voltage Regulator Standby During Sleep bit

1 = Voltage regulator is active during Sleep 0 = Voltage regulator goes into Standby mode during Sleep

bit 7 EXTR: External Reset (MCLR

1 = A Master Clear (pin) Reset has occurred 0 = A Master Clear (pin) Reset has not occurred

bit 6 SWR: Software Reset (Instruction) Flag bit

1 = A RESET instruction has been executed 0 = A RESET instruction has not been executed

bit 5 SWDTEN: Software Enable/Disable of WDT bit

1 = WDT is enabled 0 = WDT is disabled

bit 4 WDTO: Watchdog Timer Time-out Flag bit

1 = WDT time-out has occurred 0 = WDT time-out has not occurred

bit 3 SLEEP: Wake-up from Sleep Flag bit

1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode

— — — —CMVREGS

(2)

WDTO SLEEP IDLE BOR POR

) Pin bit

(1)

(2)

Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not

cause a device Reset.

2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the

SWDTEN bit setting.

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dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

bit 2 IDLE: Wake-up from Idle Flag bit

1 = Device was in Idle mode 0 = Device was not in Idle mode

bit 1 BOR: Brown-out Reset Flag bit

1 = A Brown-out Reset has occurred 0 = A Brown-out Reset has not occurred

bit 0 POR: Power-on Reset Flag bit

1 = A Power-on Reset has occurred 0 = A Power-on Reset has not occurred

Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not

cause a device Reset.

2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the

SWDTEN bit setting.

(1)

(CONTINUED)

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dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

6.3 System Reset

The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices have two types of Reset:

• Cold Reset

• Warm Reset

A cold Reset is the result of a Power-on Reset (POR) or a Brown-out Reset (BOR). On a cold Reset, the FNOSC configuration bits in the FOSC device configuration register selects the device clock source.

A warm Reset is the result of all other reset sources, including the RESET instruction. On warm Reset, the device will continue to operate from the current clock source as indicated by the Current Oscillator Selection bits (COSC<2:0>) in the Oscillator Control register (OSCCON<14:12>).

The device is kept in a Reset state until the system power supplies have stabilized at appropriate levels and the oscillator clock is ready. The sequence in which this occurs is shown in Figure 6-2.

TABLE 6-1: OSCILLATOR PARAMETERS

Oscillator Mode

FRC, FRCDIV16, FRCDIVN

FRCPLL TOSCD —TLOCK TOSCD + TLOCK

XT TOSCD TOST —TOSCD + TOST

HS TOSCD TOST —TOSCD + TOST

EC ————

XTPLL T

HSPLL TOSCD TOST TLOCK TOSCD + TOST + TLOCK

ECPLL — — TLOCK TLOCK

SOSC TOSCD TOST —TOSCD + TOST

LPRC TOSCD ——TOSCD Note 1: TOSCD = Oscillator Start-up Delay (1.1 μs max for FRC, 70 μs max for LPRC). Crystal Oscillator start-up

times vary with crystal characteristics, load capacitance, etc.

OST = Oscillator Start-up Timer Delay (1024 oscillator clock period). For example, TOST = 102.4 μs for a

2: T

10 MHz crystal and TOST = 32 ms for a 32 kHz crystal.

LOCK = PLL lock time (1.5 ms nominal), if PLL is enabled.

3: T

Oscillator

Start-up Delay

OSCD ——TOSCD

OSCD TOST TLOCK TOSCD + TOST + TLOCK

Oscillator Start-up

Timer

PLL Lock Time Total Delay

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dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

Reset

Run

Device Status

VPOR

Vbor

VBOR

POR

BOR

SYSRST

TPWRT

TPOR

TBOR

Oscillator Clock

OSCD TOST

TLOCK

Time

FSCM

Note 1: POR: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active

until V

DD crosses the VPOR threshold and the delay TPOR has elapsed.

2: BOR: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until V

DD crosses the

BOR threshold and the delay TBOR has elapsed. The delay TBOR ensures the voltage regulator output

becomes stable.

3: PWRT Timer: The programmable power-up timer continues to hold the processor in Reset for a specific

period of time (T

PWRT) after a BOR. The delay TPWRT ensures that the system power supplies have stabilized

at the appropriate level for full-speed operation. After the delay T

PWRT has elapsed, the SYSRST becomes

inactive, which in turn enables the selected oscillator to start generating clock cycles.

4: Oscillator Delay: The total delay for the clock to be ready for various clock source selections are given in

Table 6-1. Refer to Section 8.0 “Oscillator Configuration” for more information.

5: When the oscillator clock is ready, the processor begins execution from location 0x000000. The user

application programs a GOTO instruction at the reset address, which redirects program execution to the appropriate start-up routine.

6: The Fail-Safe Clock Monitor (FSCM), if enabled, begins to monitor the system clock when the system clock

is ready and the delay T

FSCM elapsed.

FIGURE 6-2: SYSTEM RESET TIMING

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TABLE 6-2: OSCILLATOR DELAY

Symbol Parameter Value

VPOR POR threshold 1.8V nominal

POR POR extension time 30 μs maximum

BOR BOR threshold 2.5V nominal

BOR BOR extension time 100 μs maximum

PWRT Programmable power-up time delay 0-128 ms nominal

TFSCM Fail-Safe Clock Monitor Delay 900 μs maximum

Note: When the device exits the Reset

condition (begins normal operation), the device operating parameters (voltage, frequency, temperature, etc.) must be within their operating ranges, otherwise the device may not function correctly. The user application must ensure that the delay between the time power is first applied, and the time SYSRST

becomes inactive, is long enough to get all operating parameters within specification.

6.4 Power-on Reset (POR)

A Power-on Reset (POR) circuit ensures the device is reset from power-on. The POR circuit is active until

DD crosses the VPOR threshold and the delay TPOR

V has elapsed. The delay TPOR ensures the internal device bias circuits become stable.

The device supply voltage characteristics must meet the specified starting voltage and rise rate requirements to generate the POR. Refer to

Section 24.0 “Electrical Characteristics” for details.

The POR status bit (POR) in the Reset Control register (RCON<0>) is set to indicate the Power-on Reset.

6.4.1 Brown-out Reset (BOR) and Power-up timer (PWRT)

The on-chip regulator has a Brown-out Reset (BOR) circuit that resets the device when the VDD is too low

DD < VBOR) for proper device operation. The BOR

(V circuit keeps the device in Reset until VDD crosses VBOR threshold and the delay TBOR has elapsed. The delay T becomes stable.

The BOR status bit (BOR) in the Reset Control register (RCON<1>) is set to indicate the Brown-out Reset.

The device will not run at full speed after a BOR as the V operation. The PWRT provides power-up time delay (TPWRT) to ensure that the system power supplies have stabilized at the appropriate levels for full-speed operation before the SYSRST

The power-up timer delay (T the Power-on Reset Timer Value Select bits (FPWRT<2:0>) in the POR Configuration register (FPOR<2:0>), which provides eight settings (from 0 ms to 128 ms). Refer to Section 21.0 “Special Features” for further details.

Figure 6-3 shows the typical brown-out scenarios. The

reset delay (T rises above the VBOR trip point

BOR ensures the voltage regulator output

DD should rise to acceptable levels for full-speed

is released.

PWRT) is programmed by

BOR + TPWRT) is initiated each time VDD

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dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

VDD

SYSRST

VBOR

SYSRST

VBOR

SYSRST

VBOR

BOR + TPWRT

VDD dips before PWRT expires

BOR + TPWRT

TBOR + TPWRT

FIGURE 6-3: BROWN-OUT SITUATIONS

6.5 External Reset (EXTR)

The external Reset is generated by driving the MCLR pin low. The MCLR pin is a Schmitt trigger input with an additional glitch filter. Reset pulses that are longer than the minimum pulse-width will generate a Reset. Refer to Section 24.0 “Electrical Characteristics” for minimum pulse-width specifications. The External Reset (MCLR

) Pin (EXTR) bit in the Reset Control

6.5.1 EXTERNAL SUPERVISORY CIRCUIT

Many systems have external supervisory circuits that generate reset signals to Reset multiple devices in the system. This external Reset signal can be directly connected to the MCLR

pin to Reset the device when

the rest of system is Reset.

6.5.2 INTERNAL SUPERVISORY CIRCUIT

When using the internal power supervisory circuit to Reset the device, the external reset pin (MCLR) should be tied directly or resistively to V

pin will not be used to generate a Reset. The

MCLR external reset pin (MCLR) does not have an internal pull-up and must not be left unconnected.

DD. In this case, the

6.6 Software RESET Instruction (SWR)

Whenever the RESET instruction is executed, the device will assert SYSRST, placing the device in a special Reset state. This Reset state will not re-initialize the clock. The clock source in effect prior to the RESET instruction will remain. SYSRST at the next instruction cycle, and the reset vector fetch will commence.

is released

The Software Reset (Instruction) Flag (SWR) bit in the Reset Control register (RCON<6>) is set to indicate the software Reset.

6.7 Watchdog Time-out Reset (WDTO)

Whenever a Watchdog time-out occurs, the device will asynchronously assert SYSRST. The clock source will remain unchanged. A WDT time-out during Sleep or Idle mode will wake-up the processor, but will not reset the processor.

The Watchdog Timer Time-out Flag bit (WDTO) in the Reset Control register (RCON<4>) is set to indicate the Watchdog Reset. Refer to Section 21.4

“Watchdog Timer (WDT)” for more information on

Watchdog Reset.

6.8 Trap Conflict Reset

If a lower-priority hard trap occurs while a higher-priority trap is being processed, a hard trap conflict Reset occurs. The hard traps include exceptions of priority level 13 through level 15, inclusive. The address error (level 13) and oscillator error (level 14) traps fall into this category.

The Trap Reset Flag bit (TRAPR) in the Reset Control register (RCON<15>) is set to indicate the Trap Conflict Reset. Refer to Section 7.0 “Interrupt Controller” for more information on trap conflict Resets.

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6.9 Configuration Mismatch Reset

To maintain the integrity of the peripheral pin select control registers, they are constantly monitored with shadow registers in hardware. If an unexpected change in any of the registers occur (such as cell disturbances caused by ESD or other external events), a configuration mismatch Reset occurs.

The Configuration Mismatch Flag bit (CM) in the Reset Control register (RCON<9>) is set to indicate the configuration mismatch Reset. Refer to

Section 10.0 “I/O Ports” for more information on the

configuration mismatch Reset.

Note: The configuration mismatch feature and

associated reset flag is not available on all devices.

6.10 Illegal Condition Device Reset

An illegal condition device Reset occurs due to the following sources:

• Illegal Opcode Reset

• Uninitialized W Register Reset

• Security Reset

The Illegal Opcode or Uninitialized W Access Reset Flag bit (IOPUWR) in the Reset Control register (RCON<14>) is set to indicate the illegal condition device Reset.

6.10.1 ILLEGAL OPCODE RESET

A device Reset is generated if the device attempts to execute an illegal opcode value that is fetched from program memory.

The illegal opcode Reset function can prevent the device from executing program memory sections that are used to store constant data. To take advantage of the illegal opcode Reset, use only the lower 16 bits of

each program memory section to store the data values. The upper 8 bits should be programmed with 3Fh, which is an illegal opcode value.

6.10.2 UNINITIALIZED W REGISTER RESET

Any attempts to use the uninitialized W register as an address pointer will Reset the device. The W register array (with the exception of W15) is cleared during all resets and is considered uninitialized until written to.

6.10.3 SECURITY RESET

If a Program Flow Change (PFC) or Vector Flow Change (VFC) targets a restricted location in a protected segment (Boot and Secure Segment), that operation will cause a security Reset.

The PFC occurs when the Program Counter is reloaded as a result of a Call, Jump, Computed Jump, Return, Return from Subroutine, or other form of branch instruction.

The VFC occurs when the Program Counter is reloaded with an Interrupt or Trap vector.

Refer to Section 21.8 “Code Protection and

CodeGuard™ Security” for more information on

Security Reset.

6.11 Using the RCON Status Bits

The user application can read the Reset Control register (RCON) after any device Reset to determine the cause of the reset.

Note: The status bits in the RCON register

should be cleared after they are read so that the next RCON register value after a device Reset will be meaningful.

Table 6-3 provides a summary of the reset flag bit

operation.

TABLE 6-3: RESET FLAG BIT OPERATION

Flag Bit Set by: Cleared by:

TRAPR (RCON<15>) Trap conflict event POR,BOR

IOPWR (RCON<14>) Illegal opcode or uninitialized

W register access or Security Reset

CM (RCON<9>)

EXTR (RCON<7>) MCLR Reset POR

SWR (RCON<6>) RESET instruction POR,BOR

WDTO (RCON<4>) WDT time-out PWRSAV instruction,

SLEEP (RCON<3>) PWRSAV #SLEEP instruction POR,BOR

IDLE (RCON<2>) PWRSAV #IDLE instruction POR,BOR

BOR (RCON<1>) POR, BOR —

POR (RCON<0>) POR —

Note: All Reset flag bits can be set or cleared by user software.

Configuration Mismatch POR,BOR

POR,BOR

CLRWDT instruction, POR,BOR

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NOTES:

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7.0 INTERRUPT CONTROLLER

Note 1: This data sheet summarizes the features

of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section

32. “Interrupts (Part III)” (DS70214) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).

2: Some registers and associated bits

described in this section may not be available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register and bit information.

The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 CPU. It has the following features:

• Up to 8 processor exceptions and software traps

• 7 user-selectable priority levels

• Interrupt Vector Table (IVT) with up to 118 vectors

• A unique vector for each interrupt or exception source

• Fixed priority within a specified user priority level

• Alternate Interrupt Vector Table (AIVT) for debug support

• Fixed interrupt entry and return latencies

7.1 Interrupt Vector Table

The Interrupt Vector Table (IVT) is shown in Figure 7-1. The IVT resides in program memory, starting at location 000004h. The IVT contains 126 vectors consisting of 8 nonmaskable trap vectors plus up to 118 sources of interrupt. In general, each interrupt source has its own vector. Each interrupt vector contains a 24-bit-wide address. The value programmed into each interrupt vector location is the starting address of the associated Interrupt Service Routine (ISR).

Interrupt vectors are prioritized in terms of their natural priority. This priority is linked to their position in the vector table. Lower addresses generally have a higher natural priority. For example, the interrupt associated with vector 0 will take priority over interrupts at any other vector address.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices implement up to 26 unique interrupts and 4 nonmaskable traps. These are summarized in

Table 7-1 and Ta b le 7 -2 .

7.1.1 ALTERNATE INTERRUPT VECTOR TA BL E

The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 7-1. Access to the AIVT is provided by the ALTIVT control bit (INTCON2<15>). If the ALTIVT bit is set, all interrupt and exception processes use the alternate vectors instead of the default vectors. The alternate vectors are organized in the same manner as the default vectors.

The AIVT supports debugging by providing a means to switch between an application and a support environment without requiring the interrupt vectors to be reprogrammed. This feature also enables switching between applications for evaluation of different software algorithms at run time. If the AIVT is not needed, the AIVT should be programmed with the same addresses used in the IVT.

7.2 Reset Sequence

A device Reset is not a true exception because the interrupt controller is not involved in the Reset process. The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 device clears its registers in response to a Reset, which forces the PC to zero. The digital signal controller then begins program execution at location 0x000000. A GOTO instruction at the Reset address can redirect program execution to the appropriate start-up routine.

Note: Any unimplemented or unused vector

locations in the IVT and AIVT should be programmed with the address of a default interrupt handler routine that contains a RESET instruction.

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Reset – GOTO Instruction 0x000000

Reset – GOTO Address 0x000002

Reserved 0x000004

Oscillator Fail Trap Vector

Address Error Trap Vector

Stack Error Trap Vector

Math Error Trap Vector

Reserved Reserved

Reserved Interrupt Vector 0 0x000014 Interrupt Vector 1

~ ~

~ Interrupt Vector 52 0x00007C Interrupt Vector 53 0x00007E Interrupt Vector 54 0x000080

Interrupt Vector 116 0x0000FC Interrupt Vector 117 0x0000FE

Reserved

0x000100 Reserved 0x000102 Reserved

Oscillator Fail Trap Vector

Address Error Trap Vector

Stack Error Trap Vector

Math Error Trap Vector

Reserved Reserved Reserved

Interrupt Vector 0 0x000114 Interrupt Vector 1

~ ~

~ Interrupt Vector 52 0x00017C Interrupt Vector 53 0x00017E Interrupt Vector 54 0x000180

Interrupt Vector 116 Interrupt Vector 117 0x0001FE

Start of Code 0x000200

Decreasing Natural Order Priority

Interrupt Vector Table (IVT)

(1)

Alternate Interrupt Vector Table (AIVT)

(1)

Note 1: See Table 7-1 for the list of implemented interrupt vectors.

FIGURE 7-1: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 INTERRUPT VECTOR TABLE

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TABLE 7-1: INTERRUPT VECTORS

Vector

Number

8 0 0x000014 0x000114 INT0 – External Interrupt 0

9 1 0x000016 0x000116 IC1 – Input Capture 1 10 2 0x000018 0x000118 OC1 – Output Compare 1 11 3 0x00001A 0x00011A T1 – Timer1 12 4 0x00001C 0x00011C Reserved 13 5 0x00001E 0x00011E IC2 – Input Capture 2 14 6 0x000020 0x000120 OC2 – Output Compare 2 15 7 0x000022 0x000122 T2 – Timer2 16 8 0x000024 0x000124 T3 – Timer3 17 9 0x000026 0x000126 SPI1E – SPI1 Error 18 10 0x000028 0x000128 SPI1 – SPI1 Transfer Done 19 11 0x00002A 0x00012A U1RX – UART1 Receiver 20 12 0x00002C 0x00012C U1TX – UART1 Transmitter 21 13 0x00002E 0x00012E ADC1 – ADC1

22-23 14-15 0x000030-0x000032 0x000130-0x000132 Reserved

24 16 0x000034 0x000134 SI2C1 – I2C1 Slave Events 25 17 0x000036 0x000136 MI2C1 – I2C1 Master Events 26 18 0x000038 0x000138 Reserved 27 19 0x00003A 0x00013A Change Notification Interrupt 28 20 0x00003C 0x00013C INT1 – External Interrupt 1 29 21 0x00003E 0x00013E Reserved 30 22 0x000040 0x000140 IC7 – Input Capture 7 31 23 0x000042 0x000142 IC8 – Input Capture 8

32-36 24-28 0x000044-0x00004C 0x000144-0x00014C Reserved

37 29 0x00004E 0x00014E INT2 – External Interrupt 2

38-64 30-56 0x000050-0x000084 0x000150-0x000184 Reserved

65 57 0x000086 0x000186 PWM1 – PWM1 Period Match 66 58 0x000088 0x000188 QEI – Position Counter Compare

67-70 59-62 0x00008A-0x000090 0x00018A-0x000190 Reserved

71 63 0x000092 0x000192 FLTA1

72 64 0x000094 0x000194 Reserved 73 65 0x000096 0x000196 U1E – UART1 Error

74-80 66-72 0x000098-0x0000A4 0x000198-0x0001A4 Reserved

81 73 0x0000A6 0x0001A6 PWM2 – PWM2 Period Match 82 74 0x0000A8 0x0001A8

83-125 75-117 0x0000AA-0x0000FE 0x0001AA-0x0001FE Reserved

Interrupt

Request (IRQ)

Number

IVT Address AIVT Address Interrupt Source

– PWM1 Fault A

– PWM2 Fault A

FLTA2

TABLE 7-2: TRAP VECTORS

Vector Number IVT Address AIVT Address Trap Source

0 0x000004 0x000104 Reserved 1 0x000006 0x000106 Oscillator Failure 2 0x000008 0x000108 Address Error 3 0x00000A 0x00010A Stack Error 4 0x00000C 0x00010C Math Error 5 0x00000E 0x00010E Reserved 6 0x000010 0x000110 Reserved 7 0x000012 0x000112 Reserved

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7.3 Interrupt Resources

Note: In the event you are not able to access

the product page using the link above, enter this URL in your browser:

http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en530334

7.3.1 KEY RESOURCES

• Section 6. “Interrupts” (DS70184)

• Code Samples

• Application Notes

• Software Libraries

• Webinars

• All related dsPIC33F/PIC24H Family Reference Manuals Sections

• Development Tools

7.4 Interrupt Control and Status

Registers

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices implement a total of 22 registers for the interrupt controller:

• INTCON1

• INTCON2

•IFSx

•IECx

•IPCx

•INTTREG

7.4.1 INTCON1 AND INTCON2

Global interrupt control functions are controlled from INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable bit (NSTDIS) as well as the control and status flags for the processor trap sources. The INTCON2 register controls the external interrupt request signal behavior and the use of the Alternate Interrupt Vector Table.

7.4.2 IFSx

The IFS registers maintain all of the interrupt request flags. Each source of interrupt has a status bit, which is set by the respective peripherals or external signal and is cleared via software.

7.4.3 IECx

The IEC registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals.

7.4.4 IPCx

The IPC registers are used to set the interrupt priority level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels.

7.4.5 INTTREG

The INTTREG register contains the associated interrupt vector number and the new CPU interrupt priority level, which are latched into vector number (VECNUM<6:0>) and Interrupt level bit (ILR<3:0>) fields in the INTTREG register. The new interrupt priority level is the priority of the pending interrupt.

The interrupt sources are assigned to the IFSx, IECx and IPCx registers in the same sequence that they are listed in Ta bl e 7- 1 . For example, the INT0 (External Interrupt 0) is shown as having vector number 8 and a natural order priority of 0. Thus, the INT0IF bit is found in IFS0<0>, the INT0IE bit in IEC0<0>, and the INT0IP bits in the first position of IPC0 (IPC0<2:0>).

7.4.6 STATUS/CONTROL REGISTERS

Although they are not specifically part of the interrupt control hardware, two of the CPU Control registers contain bits that control interrupt functionality.

• The CPU STATUS register, SR, contains the IPL<2:0> bits (SR<7:5>). These bits indicate the current CPU interrupt priority level. The user can change the current CPU priority level by writing to the IPL bits.

• The CORCON register contains the IPL3 bit which, together with IPL<2:0>, also indicates the current CPU priority level. IPL3 is a read-only bit so that trap events cannot be masked by the user software.

All Interrupt registers are described in Register 7-1 through Register 7-24 in the following pages.

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(1)

R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R -0 R/W-0

OA OB SA SB OAB SAB DA DC

bit 15 bit 8

R/W-0

IPL2

(3)

(2)

R/W-0

IPL1

(2)

(3)

R/W-0

IPL0

(2)

(3)

R-0 R/W-0 R/W-0 R/W-0 R/W-0

RA N OV Z C

bit 7 bit 0

Legend:

C = Clear only bit R = Readable bit U = Unimplemented bit, read as ‘0’

S = Set only bit W = Writable bit -n = Value at POR

‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits

(2)

Note 1: For complete register details, see Register 3-1: “SR: CPU STATUS Register”.

2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority

Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3> = 1.

3: The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15>) = 1.

(1)

U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0

— — —USEDT DL<2:0>

bit 15 bit 8

R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0

SATA SATB SATDW ACCSAT IPL3

(2)

PSV RND IF

bit 7 bit 0

Legend: C = Clear only bit

R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set

0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’

bit 3 IPL3: CPU Interrupt Priority Level Status bit 3

(2)

1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less

Note 1: For complete register details, see Register 3-2: “CORCON: CORE Control Register”.

2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.

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R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE

bit 15 bit 8

R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0

SFTACERR DIV0ERR

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 NSTDIS: Interrupt Nesting Disable bit

1 = Interrupt nesting is disabled 0 = Interrupt nesting is enabled

bit 14 OVAERR: Accumulator A Overflow Trap Flag bit

1 = Trap was caused by overflow of Accumulator A 0 = Trap was not caused by overflow of Accumulator A

bit 13 OVBERR: Accumulator B Overflow Trap Flag bit

1 = Trap was caused by overflow of Accumulator B 0 = Trap was not caused by overflow of Accumulator B

bit 12 COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit

1 = Trap was caused by catastrophic overflow of Accumulator A 0 = Trap was not caused by catastrophic overflow of Accumulator A

bit 11 COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit

1 = Trap was caused by catastrophic overflow of Accumulator B 0 = Trap was not caused by catastrophic overflow of Accumulator B

bit 10 OVATE: Accumulator A Overflow Trap Enable bit

1 = Trap overflow of Accumulator A 0 = Trap disabled

bit 9 OVBTE: Accumulator B Overflow Trap Enable bit

1 = Trap overflow of Accumulator B 0 = Trap disabled

bit 8 COVTE: Catastrophic Overflow Trap Enable bit

1 = Trap on catastrophic overflow of Accumulator A or B enabled 0 = Trap disabled

bit 7 SFTACERR: Shift Accumulator Error Status bit

1 = Math error trap was caused by an invalid accumulator shift 0 = Math error trap was not caused by an invalid accumulator shift

bit 6 DIV0ERR: Arithmetic Error Status bit

1 = Math error trap was caused by a divide by zero 0 = Math error trap was not caused by a divide by zero

bit 5 Unimplemented: Read as ‘0’

bit 4 MATHERR: Arithmetic Error Status bit

1 = Math error trap has occurred 0 = Math error trap has not occurred

bit 3 ADDRERR: Address Error Trap Status bit

1 = Address error trap has occurred 0 = Address error trap has not occurred

— MATHERR ADDRERR STKERR OSCFAIL —

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bit 2 STKERR: Stack Error Trap Status bit

1 = Stack error trap has occurred 0 = Stack error trap has not occurred

bit 1 OSCFAIL: Oscillator Failure Trap Status bit

1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred

bit 0 Unimplemented: Read as ‘0’

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REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2

R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0

ALTIVT DISI

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — INT2EP INT1EP INT0EP

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit

1 = Use alternate vector table 0 = Use standard (default) vector table

bit 14 DISI: DISI Instruction Status bit

1 = DISI instruction is active 0 = DISI instruction is not active

bit 13-3 Unimplemented: Read as ‘0’

bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit

1 = Interrupt on negative edge 0 = Interrupt on positive edge

bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit

1 = Interrupt on negative edge 0 = Interrupt on positive edge

bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit

1 = Interrupt on negative edge 0 = Interrupt on positive edge

— — — — — —

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U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF

bit 15 bit 8

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

T2IF OC2IF IC2IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13 AD1IF: ADC1 Conversion Complete Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 12 U1TXIF: UART1 Transmitter Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 11 U1RXIF: UART1 Receiver Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 10 SPI1IF: SPI1 Event Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 9 SPI1EIF: SPI1 Fault Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 8 T3IF: Timer3 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 7 T2IF: Timer2 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 6 OC2IF: Output Compare Channel 2 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 5 IC2IF: Input Capture Channel 2 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 4 Unimplemented: Read as ‘0’

bit 3 T1IF: Timer1 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

— T1IF OC1IF IC1IF INT0IF

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bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 0 INT0IF: External Interrupt 0 Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

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REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1

U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

— —INT2IF— — — — —

bit 15 bit 8

R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0

IC8IF IC7IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13 INT2IF: External Interrupt 2 Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 12-8 Unimplemented: Read as ‘0’

bit 7 IC8IF: Input Capture Channel 8 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 6 IC7IF: Input Capture Channel 7 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 5 Unimplemented: Read as ‘0’

bit 4 INT1IF: External Interrupt 1 Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 3 CNIF: Input Change Notification Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 2 Unimplemented: Read as ‘0’

bit 1 MI2C1IF: I2C1 Master Events Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

— INT1IF CNIF — MI2C1IF SI2C1IF

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REGISTER 7-7: IFS3: INTERRUPT FLAG STATUS REGISTER 3

R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0

FLTA1IF

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 FLTA1IF: PWM1 Fault A Interrupt Flag Status bit

bit 14-11 Unimplemented: Read as ‘0’

bit 10 QEIIF: QEI Event Interrupt Flag Status bit

bit 9 PWM1IF: PWM1 Interrupt Flag Status bit

bit 8-0 Unimplemented: Read as ‘0’

— — — — QEIIF PWM1IF —

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

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REGISTER 7-8: IFS4: INTERRUPT FLAG STATUS REGISTER 4

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0

— — — — — FLTA2IF PWM2IF —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0

— — — — — —U1EIF—

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-11 Unimplemented: Read as ‘0’

bit 10 FLTA2IF: PWM2 Fault A Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 9 PWM2IF: PWM2 Error Interrupt Enable bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 8-2 Unimplemented: Read as ‘0’

bit 1 U1EIF: UART1 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 0 Unimplemented: Read as ‘0’

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U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE

bit 15 bit 8

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

T2IE OC2IE IC2IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13 AD1IE: ADC1 Conversion Complete Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 12 U1TXIE: UART1 Transmitter Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 11 U1RXIE: UART1 Receiver Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 10 SPI1IE: SPI1 Event Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 9 SPI1EIE: SPI1 Event Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 8 T3IE: Timer3 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 7 T2IE: Timer2 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 6 OC2IE: Output Compare Channel 2 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 5 IC2IE: Input Capture Channel 2 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 4 Unimplemented: Read as ‘0’

bit 3 T1IE: Timer1 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

— T1IE OC1IE IC1IE INT0IE

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bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 0 INT0IE: External Interrupt 0 Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

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REGISTER 7-10: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1

U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

— —INT2IE— — — — —

bit 15 bit 8

R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0

IC8IE IC7IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13 INT2IE: External Interrupt 2 Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 12-8 Unimplemented: Read as ‘0’

bit 7 IC8IE: Input Capture Channel 8 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 6 IC7IE: Input Capture Channel 7 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 5 Unimplemented: Read as ‘0’

bit 4 INT1IE: External Interrupt 1 Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 3 CNIE: Input Change Notification Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 2 Unimplemented: Read as ‘0’

bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

— INT1IE CNIE —MI2C1IESI2C1IE

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REGISTER 7-11: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3

R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0

FLTA1IE

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 FLTA1IE: PWM1 Fault A Interrupt Enable bit

bit 14-11 Unimplemented: Read as ‘0’

bit 10 QEIIE: QEI Event Interrupt Enable bit

bit 9 PWM1IE: PWM1 Error Interrupt Enable bit

bit 8-0 Unimplemented: Read as ‘0’

— — — — QEIIE PWM1IE —

1 = Interrupt request enabled 0 = Interrupt request not enabled

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REGISTER 7-12: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0

— — — — — FLA2IE PWM2IE —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0

— — — — — —U1EIE—

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-11 Unimplemented: Read as ‘0’

bit 10 FLA2IE: PWM2 Fault A Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 9 PWM2IE: PWM2 Error Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 8-2 Unimplemented: Read as ‘0’

bit 1 U1EIE: UART1 Error Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 0 Unimplemented: Read as ‘0’

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REGISTER 7-13: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— T1IP<2:0> —OC1IP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

—IC1IP<2:0>— INT0IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

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REGISTER 7-14: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— T2IP<2:0> —OC2IP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

—IC2IP<2:0>— — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3-0 Unimplemented: Read as ‘0’

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REGISTER 7-15: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— U1RXIP<2:0> — SPI1IP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— SPI1EIP<2:0> — T3IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 SPI1IP<2:0>: SPI1 Event Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 SPI1EIP<2:0>: SPI1 Error Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

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REGISTER 7-16: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

—AD1IP<2:0>— U1TXIP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-7 Unimplemented: Read as ‘0’

bit 6-4 AD1IP<2:0>: ADC1 Conversion Complete Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

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REGISTER 7-17: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— CNIP<2:0> — — — —

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— MI2C1IP<2:0> — SI2C1IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 CNIP<2:0>: Change Notification Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 11-7 Unimplemented: Read as ‘0’

bit 6-4 MI2C1IP<2:0>: I2C1 Master Events Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

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REGISTER 7-18: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

—IC8IP<2:0>— IC7IP<2:0>

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0

— — — — — INT1IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 IC8IP<2:0>: Input Capture Channel 8 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 IC7IP<2:0>: Input Capture Channel 7 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 7-3 Unimplemented: Read as ‘0’

bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

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REGISTER 7-19: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— INT2IP<2:0> — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-7 Unimplemented: Read as ‘0’

bit 6-4 INT2IP<2:0>: External Interrupt 2 Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3-0 Unimplemented: Read as ‘0’

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REGISTER 7-20: IPC14: INTERRUPT PRIORITY CONTROL REGISTER 14

U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0

— — — — —QEIIP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— PWM1IP<2:0> — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-12 Unimplemented: Read as ‘0’

bit 10-8 QEIIP<2:0>: QEI Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 PWM1IP<2:0>: PWM1 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3-0 Unimplemented: Read as ‘0’

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REGISTER 7-21: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

—FLTA1IP<2:0>— — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 FLTA1IP<2:0>: PWM1 Fault A Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 11-0 Unimplemented: Read as ‘0’

REGISTER 7-22: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

—U1EIP<2:0>— — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-7 Unimplemented: Read as ‘0’

bit 6-4 U1EIP<2:0>: UART1 Error Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3-0 Unimplemented: Read as ‘0’

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REGISTER 7-23: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — FLTA2IP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— PWM2IP<2:0> — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-11 Unimplemented: Read as ‘0’

bit 8-10 FLTA2IP<2:0>: PWM2 Fault A Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 PWM2IP<2:0>: PWM2 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3-0 Unimplemented: Read as ‘0’

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REGISTER 7-24: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER

U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0

— — — —ILR<3:0>

bit 15 bit 8

U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

— VECNUM<6:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-12 Unimplemented: Read as ‘0’

bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits

1111 = CPU Interrupt Priority Level is 15

•

0001 = CPU Interrupt Priority Level is 1 0000 = CPU Interrupt Priority Level is 0

bit 7 Unimplemented: Read as ‘0’

bit 6-0 VECNUM<6:0>: Vector Number of Pending Interrupt bits

0111111 = Interrupt Vector pending is number 135

•

0000001 = Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8

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7.5 Interrupt Setup Procedures

7.5.1 INITIALIZATION

To configure an interrupt source at initialization:

1. Set the NSTDIS bit (INTCON1<15>) if nested interrupts are not desired.

2. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source. If multiple priority levels are not desired, the IPCx register control bits for all enabled interrupt sources can be programmed to the same non-zero value.

Note: At a device Reset, the IPCx registers are

initialized such that all user interrupt sources are assigned to priority level 4.

3. Clear the interrupt flag status bit associated with the peripheral in the associated IFSx register.

4. Enable the interrupt source by setting the interrupt enable control bit associated with the source in the appropriate IECx register.

7.5.2 INTERRUPT SERVICE ROUTINE

The method used to declare an Interrupt Service Routine (ISR) and initialize the IVT with the correct vector address depends on the programming language (C or assembler) and the language development tool suite used to develop the application.

In general, the user application must clear the interrupt flag in the appropriate IFSx register for the source of interrupt that the ISR handles. Otherwise, program will re-enter the ISR immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level.

7.5.3 TRAP SERVICE ROUTINE

A Trap Service Routine (TSR) is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR.

7.5.4 INTERRUPT DISABLE

All user interrupts can be disabled using this procedure:

1. Push the current SR value onto the software stack using the PUSH instruction.

2. Force the CPU to priority level 7 by inclusive ORing the value OEh with SRL.

To enable user interrupts, the POP instruction can be used to restore the previous SR value.

Note: Only user interrupts with a priority level of

7 or lower can be disabled. Trap sources (level 8-level 15) cannot be disabled.

The DISI instruction provides a convenient way to disable interrupts of priority levels 1-6 for a fixed period of time. Level 7 interrupt sources are not disabled by the DISI instruction.

Microchip PIC33FJ32MC202, PIC33FJ32MC204, PIC33FJ16MC304 Specifications

Specifications and Main Features

Frequently Asked Questions

User Manual

1.0 DEVICE OVERVIEW

FIGURE 1-1: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 BLOCK DIAGRAM

2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT DIGITAL SIGNAL CONTROLLERS

2.1 Basic Connection Requirements

2.2 Decoupling Capacitors

2.4 Master Clear (MCLR) Pin

2.5 ICSP Pins

2.6 External Oscillator Pins

2.7 Oscillator Value Conditions on Device Start-up

2.8 Configuration of Analog and Digital Pins During ICSP Operations

2.9 Unused I/Os

3.0 CPU

3.1 Data Addressing Overview

3.2 DSP Engine Overview

3.3 Special MCU Features

FIGURE 3-1: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 CPU CORE BLOCK DIAGRAM

FIGURE 3-2: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 PROGRAMMER’S MODEL

3.4 CPU Resources

3.5 CPU Control Registers

REGISTER 3-2: CORCON: CORE CONTROL REGISTER

3.6 Arithmetic Logic Unit (ALU)

3.7 DSP Engine

FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM

4.0 MEMORY ORGANIZATION

4.1 Program Address Space

FIGURE 4-2: PROGRAM MEMORY ORGANIZATION

4.2 Data Address Space

4.3 Program Memory Resources

4.4 Special Function Register Maps

TABLE 4-2: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ32MC202

TABLE 4-3: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ32MC204 and dsPIC33FJ16MC304

TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP

TABLE 4-5: TIMER REGISTER MAP

TABLE 4-6: INPUT CAPTURE REGISTER MAP

TABLE 4-7: OUTPUT COMPARE REGISTER MAP

TABLE 4-8: 6-OUTPUT PWM1 REGISTER MAP

TABLE 4-9: 2-OUTPUT PWM2 REGISTER MAP

TABLE 4-10: QEI1 REGISTER MAP

TABLE 4-11: I2C1 REGISTER MAP

TABLE 4-12: UART1 REGISTER MAP

TABLE 4-13: SPI1 REGISTER MAP

TABLE 4-14: ADC1 REGISTER MAP FOR dsPIC33FJ32MC202

TABLE 4-15: ADC1 REGISTER MAP FOR dsPIC33FJ32MC204 AND dsPIC33FJ16MC304

TABLE 4-16: PERIPHERAL PIN SELECT INPUT REGISTER MAP

TABLE 4-17: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ32MC202

TABLE 4-18: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ32MC204 AND dsPIC33FJ16MC304

TABLE 4-19: PORTA REGISTER MAP FOR dsPIC33FJ32MC202

TABLE 4-20: PORTA REGISTER MAP FOR dsPIC33FJ32MC204 AND dsPIC33FJ16MC304

TABLE 4-21: PORTB REGISTER MAP

TABLE 4-22: PORTC REGISTER MAP FOR dsPIC33FJ32MC204 AND dsPIC33FJ16MC304

TABLE 4-23: SYSTEM CONTROL REGISTER MAP

TABLE 4-24: NVM REGISTER MAP

TABLE 4-25: PMD REGISTER MAP

FIGURE 4-4: CALL STACK FRAME

4.5 Instruction Addressing Modes

TABLE 4-26: FUNDAMENTAL ADDRESSING MODES SUPPORTED

4.6 Modulo Addressing

FIGURE 4-5: MODULO ADDRESSING OPERATION EXAMPLE

4.7 Bit-Reversed Addressing

FIGURE 4-6: BIT-REVERSED ADDRESS EXAMPLE

TABLE 4-27: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)

TABLE 4-28: PROGRAM SPACE ADDRESS CONSTRUCTION

FIGURE 4-7: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

FIGURE 4-8: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS

FIGURE 4-9: PROGRAM SPACE VISIBILITY OPERATION

5.0 FLASH PROGRAM MEMORY

FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS

5.2 RTSP Operation

5.3 Programming Operations

EQUATION 5-1: PROGRAMMING TIME

5.4 Flash Memory Resources

5.5 Control Registers

REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER

REGISTER 5-2: NVMKEY: NONVOLATILE MEMORY KEY REGISTER

EXAMPLE 5-1: ERASING A PROGRAM MEMORY PAGE

EXAMPLE 5-2: LOADING THE WRITE BUFFERS