MICROCHIP PIC24HJXXXGPX06, PIC24HJXXXGPX08, PIC24HJXXXGPX10 DATA SHEET
PIC24HJXXXGPX06/X08/X10
Data Sheet
High-Performance,
16-Bit Microcontrollers
© 2009 Microchip Technology Inc. DS70175H
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K
EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, rfPIC, SmartShunt and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP,
PICkit, PICDEM, PICDEM.net, PICtail, PIC
32
logo, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select
Mode, Total Endurance, TSHARC, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
®
MCUs and dsPIC® DSCs, KEELOQ
®
code hopping
DS70175H-page ii © 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
High-Performance, 16-Bit Microcontrollers
Operating Range:
• Up to 40 MIPS operation (at 3.0-3.6V):
- Industrial temperature range
(-40°C to +85°C)
High-Performance CPU:
• Modified Harvard architecture
• C compiler optimized instruction set
• 16-bit wide data path
• 24-bit wide instructions
• Linear program memory addressing up to 4M
instruction words
• Linear data memory addressing up to 64 Kbytes
• 71 base instructions: mostly 1 word/1 cycle
• Sixteen 16-bit General Purpose Registers
• Flexible and powerful Indirect Addressing modes
• Software stack
• 16 x 16 multiply operations
• 32/16 and 16/16 divide operations
• Up to ±16-bit data shifts
Direct Memory Access (DMA):
• 8-channel hardware DMA
• 2 Kbytes dual ported DMA buffer area
(DMA RAM) to store data transferred via DMA:
- Allows data transfer between RAM and a
peripheral while CPU is executing code
(no cycle stealing)
• Most peripherals support DMA
Interrupt Controller:
• 5-cycle latency
• Up to 61 available interrupt sources
• Up to five external interrupts
• Seven programmable priority levels
• FIve processor exceptions
On-Chip Flash and SRAM:
• Flash program memory, up to 256 Kbytes
• Data SRAM, up to 16 Kbytes (includes 2 Kbytes
of DMA RAM)
System Management:
• Flexible clock options:
- External, crystal, resonator, internal RC
- Fully integrated PLL
- Extremely low jitter PLL
• Power-up Timer
• Oscillator Start-up Timer/Stabilizer
• Watchdog Timer with its own RC oscillator
• Fail-Safe Clock Monitor
• Reset by multiple sources
Power Management:
• On-chip 2.5V voltage regulator
• Switch between clock sources in real time
• Idle, Sleep and Doze modes with fast wake-up
Timers/Capture/Compare/PWM:
• Timer/Counters, up to nine 16-bit timers:
- Can pair up to make four 32-bit timers
- One timer runs as Real-Time Clock with
external 32.768 kHz oscillator
- Programmable prescaler
• Input Capture (up to eight channels):
- Capture on up, down or both edges
- 16-bit capture input functions
- 4-deep FIFO on each capture
• Output Compare (up to eight channels):
- Single or Dual 16-Bit Compare mode
- 16-bit Glitchless PWM mode
Digital I/O:
• Up to 85 programmable digital I/O pins
• Wake-up/Interrupt-on-Change on up to 24 pins
• Output pins can drive from 3.0V to 3.6V
• All digital input pins are 5V tolerant
• 4 mA sink on all I/O pins
© 2009 Microchip Technology Inc. DS70175H-page 1
PIC24HJXXXGPX06/X08/X10
Communication Modules:
• 3-wire SPI (up to two modules):
- Framing supports I/O interface to simple
codecs
- Supports 8-bit and 16-bit data
- Supports all serial clock formats and
sampling modes
2
C™ (up to two modules):
•I
- Full Multi-Master Slave mode support
- 7-bit and 10-bit addressing
- Bus collision detection and arbitration
- Integrated signal conditioning
- Slave address masking
• UART (up to two modules):
- Interrupt on address bit detect
- Interrupt on UART error
- Wake-up on Start bit from Sleep mode
- 4-character TX and RX FIFO buffers
- LIN bus support
®
-IrDA
- High-Speed Baud mode
- Hardware Flow Control with CTS and RTS
• Enhanced CAN (ECAN™ module) 2.0B active
(up to two modules):
- Up to eight transmit and up to 32 receive buffers
- 16 receive filters and 3 masks
- Loopback, Listen Only and Listen All
- Wake-up on CAN message
- Automatic processing of Remote
- FIFO mode using DMA
- DeviceNet™ addressing support
encoding and decoding in hardware
Messages modes for diagnostics and bus
monitoring
Transmission Requests
Analog-to-Digital Converters:
• Up to two Analog-to-Digital Converter (ADC)
modules in a device
• 10-bit, 1.1 Msps or 12-bit, 500 ksps conversion:
- Two, four, or eight simultaneous samples
- Up to 32 input channels with auto-scanning
- Conversion start can be manual or
synchronized with one of four trigger sources
- Conversion possible in Sleep mode
- ±1 LSb max integral nonlinearity
- ±1 LSb max differential nonlinearity
CMOS Flash Technology:
• Low-power, high-speed Flash technology
• Fully static design
• 3.3V (±10%) operating voltage
• Industrial temperature
• Low-power consumption
Packaging:
• 100-pin TQFP (14x14x1 mm and 12x12x1 mm)
• 64-pin TQFP (10x10x1 mm)
Note: See the device variant tables for exact
peripheral features per device.
DS70175H-page 2 © 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
PIC24H PRODUCT FAMILIES
The PIC24H Family of devices is ideal for a wide variety of 16-bit MCU embedded applications. The device
names, pin counts, memory sizes and peripheral availability of each device are listed below, followed by their
pinout diagrams.
PIC24H Family Controllers
Program
Device Pins
PIC24HJ64GP206 64 64 8 8 9 8 8 0 1 ADC,
PIC24HJ64GP210 100 64 8 8 9 8 8 0 1 ADC,
PIC24HJ64GP506 64 64 8 8 9 8 8 0 1 ADC,
PIC24HJ64GP510 100 64 8 8 9 8 8 0 1 ADC,
PIC24HJ128GP206 64 128 8 8 9 8 8 0 1 ADC,
PIC24HJ128GP210 100 128 8 8 9 8 8 0 1 ADC,
PIC24HJ128GP506 64 128 8 8 9 8 8 0 1 ADC,
PIC24HJ128GP510 100 128 8 8 9 8 8 0 1 ADC,
PIC24HJ128GP306 64 128 16 8 9 8 8 0 1 ADC,
PIC24HJ128GP310 100 128 16 8 9 8 8 0 1 ADC,
PIC24HJ256GP206 64 256 16 8 9 8 8 0 1 ADC,
PIC24HJ256GP210 100 256 16 8 9 8 8 0 1 ADC,
PIC24HJ256GP610 100 256 16 8 9 8 8 0 2 ADC,
Note 1: RAM size is inclusive of 2 Kbytes DMA RAM.
2: Maximum I/O pin count includes pins shared by the peripheral functions.
Flash
Memory (KB)
(KB)
(1)
RAM
Codec
Interface
Input Capture
Std. PWM
Output Compare
18 ch
32 ch
18 ch
32 ch
18 ch
32 ch
18 ch
32 ch
18 ch
32 ch
18 ch
32 ch
32 ch
Timer 16-bit
DMA Channels
(2)
C™
SPI
2
ADC
UART
221 053 PT
2 2 2 0 85 PF, PT
222 153 PT
2 2 2 1 85 PF, PT
222 053 PT
2 2 2 0 85 PF, PT
222 153 PT
2 2 2 1 85 PF, PT
222 053 PT
2 2 2 0 85 PF, PT
222 053 PT
2 2 2 0 85 PF, PT
2 2 2 2 85 PF, PT
CAN
I
Packages
I/O Pins (Max)
© 2009 Microchip Technology Inc. DS70175H-page 3
PIC24HJXXXGPX06/X08/X10
64-Pin TQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
36
35
34
33
32
31
30
29
28
27
26
646362616059585756
14
15
16
171819202122232425
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/RD0
IC4/INT4/RD11
IC2/U1CTS
/INT2/RD9
IC1/INT1/RD8
V
SS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
V
DD
SCL1/RG2
U1RTS
/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
VSS
VDD
AN3/CN5/RB3
AN2/SS1
/CN4/RB2
PGEC3/AN1/V
REF-/CN3/RB1
PGED3/AN0/V
REF+/CN2/RB0
OC8/CN16/RD7
RG13
RG12
RG14
V
CAP/VDDCORE
RG1
RF1
RG0
OC2/RD1
OC3/RD2
PGEC1/AN6/OCFA/RB6
PGED1/AN7/RB7
AVDD
AVSS
U2CTS/AN8/RB8
AN9/RB9
TMS/AN10/RB10
TDO/AN11/RB11
V
SS
VDD
TCK/AN12/RB12
TDI/AN13/RB13
U2RTS
/AN14/RB14
AN15/OCFB/CN12/RB15
U2TX/SCL2/CN18/RF5
U2RX/SDA2/CN17/RF4
SDA1/RG3
43
42
41
40
39
38
37
44
48
47
46
504951
545352
55
45
SS2
/CN11/RG9
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
IC3/INT3/RD10
VDD
RF0
OC4/RD3
OC7/CN15/RD6
OC6/IC6/CN14/RD5
OC5/IC5/CN13/RD4
PIC24HJ64GP206
PIC24HJ128GP206
PIC24HJ256GP206
Note: The PIC24HJ64GP206 device does not have the SCL2 and SDA2 pins.
= Pins are up to 5V tolerant
Pin Diagrams
DS70175H-page 4 © 2009 Microchip Technology Inc.
Pin Diagrams (Continued)
64-Pin TQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
36
35
34
33
32
31
30
29
28
27
26
646362616059585756
14
15
16
171819202122232425
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/RD0
IC4/INT4/RD11
IC2/U1CTS
/INT2/RD9
IC1/INT1/RD8
V
SS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
V
DD
SCL1/RG2
U1RTS
/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
VSS
VDD
AN3/CN5/RB3
AN2/SS1
/CN4/RB2
PGEC3/AN1/V
REF-/CN3/RB1
PGED3/AN0/V
REF+/CN2/RB0
OC8/CN16/RD7
RG13
RG12
RG14
V
CAP/VDDCORE
RG1
RF1
RG0
OC2/RD1
OC3/RD2
PGEC1/AN6/OCFA/RB6
PGED1/AN7/RB7
AV
DD
AVSS
U2CTS/AN8/RB8
AN9/RB9
TMS/AN10/RB10
TDO/AN11/RB11
V
SS
VDD
TCK/AN12/RB12
TDI/AN13/RB13
U2RTS
/AN14/RB14
AN15/OCFB/CN12/RB15
U2TX/SCL2/CN18/RF5
U2RX/SDA2/CN17/RF4
SDA1/RG3
43
42
41
40
39
38
37
44
48
47
46
504951
545352
55
45
SS2
/CN11/RG9
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
IC3/INT3/RD10
VDD
RF0
OC4/RD3
OC7/CN15/RD6
OC6/IC6/CN14/RD5
OC5/IC5/CN13/RD4
PIC24HJ128GP306
= Pins are up to 5V tolerant
PIC24HJXXXGPX06/X08/X10
© 2009 Microchip Technology Inc. DS70175H-page 5
PIC24HJXXXGPX06/X08/X10
64-Pin TQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
36
35
34
33
32
31
30
29
28
27
26
646362616059585756
14
15
16
171819202122232425
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/RD0
IC4/INT4/RD11
IC2/U1CTS
/INT2/RD9
IC1/INT1/RD8
V
SS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
V
DD
SCL1/RG2
U1RTS
/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
VSS
VDD
AN3/CN5/RB3
AN2/SS1
/CN4/RB2
PGEC3/AN1/V
REF-/CN3/RB1
PGED3/AN0/V
REF+/CN2/RB0
OC8/CN16/RD7
RG13
RG12
RG14
V
CAP/VDDCORE
RG1
C1TX/RF1
RG0
OC2/RD1
OC3/RD2
PGEC1/AN6/OCFA/RB6
PGED1/AN7/RB7
AVDD
AVSS
U2CTS/AN8/RB8
AN9/RB9
TMS/AN10/RB10
TDO/AN11/RB11
V
SS
VDD
TCK/AN12/RB12
TDI/AN13/RB13
U2RTS
/AN14/RB14
AN15/OCFB/CN12/RB15
U2TX/SCL2/CN18/RF5
U2RX/SDA2/CN17/RF4
SDA1/RG3
43
42
41
40
39
38
37
44
48
47
46
504951
545352
55
45
SS2
/CN11/RG9
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
IC3/INT3/RD10
VDD
C1RX/RF0
OC4/RD3
OC7/CN15/RD6
OC6/IC6/CN14/RD5
OC5/IC5/CN13/RD4
PIC24HJ64GP506
PIC24HJ128GP506
= Pins are up to 5V tolerant
Pin Diagrams (Continued)
DS70175H-page 6 © 2009 Microchip Technology Inc.
Pin Diagrams (Continued)
9294939190898887868584838281807978
20
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
65
64
63
62
61
60
59
26
56
45
44
43
42
41
40
39
2829303132333435363738
17
18
19
21
22
95
1
76
77
72
71
70
69
68
67
66
75
74
73
58
57
24
23
25
969897
99
27
4647484950
55
54
53
52
51
OC6/CN14/RD5
OC5/CN13/RD4
IC6/CN19/RD13
IC5/RD12
OC4/RD3
OC3/RD2
OC2/RD1
AN23/CN23/RA7
AN22/CN22/RA6
AN26/RE2
RG13
RG12
RG14
AN25/RE1
AN24/RE0
RG0
AN28/RE4
AN27/RE3
RF0
V
CAP
/V
DDCORE
PGED2/SOSCI/CN1/RC13
OC1/RD0
IC3/RD10
IC2/RD9
IC1/RD8
IC4/RD11
SDA2/RA3
SCL2/RA2
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
V
DD
SCL1/RG2
SCK1/INT0/RF6
SDI1/RF7
SDO1/RF8
SDA1/RG3
U1RX/RF2
U1TX/RF3
V
SS
PGEC2/SOSCO/T1CK/CN0/RC14
V
REF
+/RA10
V
REF
-/RA9
AV
DD
AV
SS
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
V
DD
U2CTS/RF12
U2RTS
/RF13
IC7/U1CTS
/CN20/RD14
IC8/U1RTS
/CN21/RD15
V
DD
V
SS
PGEC1/AN6/OCFA/RB6
PGED1PGED1/AN7/RB7
U2TX/CN18/RF5
U2RX/CN17/RF4
AN29/RE5
AN30/RE6
AN31/RE7
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
SCK2/CN8/RG6
V
DD
TMS/RA0
AN20/INT1/RA12
AN21/INT2/RA13
AN5/CN7/RB5
AN4/CN6/RB4
AN3/CN5/RB3
AN2/SS1
/CN4/RB2
SDI2/CN9/RG7
SDO2/CN10/RG8
PGEC3/AN1/CN3/RB1
PGED3/AN0/CN2/RB0
RG15
V
DD
SS2/CN11/RG9
MCLR
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
RG1
RF1
OC8/CN16/RD7
OC7/CN15/RD6
TDO/RA5
INT4/RA15
INT3/RA14
V
SS
V
SS
V
SS
V
DD
TDI/RA4
TCK/RA1
100-Pin TQFP
PIC24HJ64GP210
PIC24HJ128GP210
100
PIC24HJ128GP310
PIC24HJ256GP210
= Pins are up to 5V tolerant
PIC24HJXXXGPX06/X08/X10
© 2009 Microchip Technology Inc. DS70175H-page 7
PIC24HJXXXGPX06/X08/X10
929493
91908988878685848382818079
78
20
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
65
64
63
62
61
60
59
26
56
45
44
43
42
41
40
39
2829303132333435363738
17
18
19
21
22
95
1
76
77
72
71
70
69
68
67
66
75
74
73
58
57
24
23
25
969897
99
27
4647484950
55
54
53
52
51
OC6/CN14/RD5
OC5/CN13/RD4
IC6/CN19/RD13
IC5/RD12
OC4/RD3
OC3/RD2
OC2/RD1
AN23/CN23/RA7
AN22/CN22/RA6
AN26/RE2
RG13
RG12
RG14
AN25/RE1
AN24/RE0
RG0
AN28/RE4
AN27/RE3
C1RX/RF0
V
CAP
/V
DDCORE
PGED2/SOSCI/CN1/RC13
OC1/RD0
IC3/RD10
IC2/RD9
IC1/RD8
IC4/RD11
SDA2/RA3
SCL2/RA2
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
V
DD
SCL1/RG2
SCK1/INT0/RF6
SDI1/RF7
SDO1/RF8
SDA1/RG3
U1RX/RF2
U1TX/RF3
V
SS
PGEC2/SOSCO/T1CK/CN0/RC14
V
REF
+/RA10
V
REF
-/RA9
AV
DD
AV
SS
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
V
DD
U2CTS/RF12
U2RTS
/RF13
IC7/U1CTS
/CN20/RD14
IC8/U1RTS
/CN21/RD15
V
DD
V
SS
PGEC1/AN6/OCFA/RB6
PGED1/AN7/RB7
U2TX/CN18/RF5
U2RX/CN17/RF4
AN29/RE5
AN30/RE6
AN31/RE7
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
SCK2/CN8/RG6
V
DD
TMS/RA0
AN20/INT1/RA12
AN21/INT2/RA13
AN5/CN7/RB5
AN4/CN6/RB4
AN3/CN5/RB3
AN2/SS1
/CN4/RB2
SDI2/CN9/RG7
SDO2/CN10/RG8
PGEC3/AN1/CN3/RB1
PGED3/AN0/CN2/RB0
RG15
V
DD
SS2/CN11/RG9
MCLR
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
RG1
C1TX/RF1
OC8/CN16/RD7
OC7/CN15/RD6
TDO/RA5
INT4/RA15
INT3/RA14
V
SS
V
SS
V
SS
V
DD
TDI/RA4
TCK/RA1
100-Pin TQFP
PIC24HJ64GP510
100
PIC24HJ128GP510
= Pins are up to 5V tolerant
Pin Diagrams (Continued)
DS70175H-page 8 © 2009 Microchip Technology Inc.
Pin Diagrams (Continued)
9294939190898887868584838281807978
20
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
65
64
63
62
61
60
59
26
56
45
44
43
42
41
40
39
2829303132333435363738
17
18
19
21
22
95
1
76
77
72
71
70
69
68
67
66
75
74
73
58
57
24
23
25
969897
99
27
4647484950
55
54
53
52
51
OC6/CN14/RD5
OC5/CN13/RD4
IC6/CN19/RD13
IC5/RD12
OC4/RD3
OC3/RD2
OC2/RD1
AN23/CN23/RA7
AN22/CN22/RA6
AN26/RE2
RG13
RG12
RG14
AN25/RE1
AN24/RE0
C2RX/RG0
AN28/RE4
AN27/RE3
C1RX/RF0
V
CAP
/V
DDCORE
PGED2/SOSCI/CN1/RC13
OC1/RD0
IC3/RD10
IC2/RD9
IC1/RD8
IC4/RD11
SDA2/RA3
SCL2/RA2
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
V
DD
SCL1/RG2
SCK1/INT0/RF6
SDI1/RF7
SDO1/RF8
SDA1/RG3
U1RX/RF2
U1TX/RF3
V
SS
PGEC2/SOSCO/T1CK/CN0/RC14
V
REF
+/RA10
V
REF
-/RA9
AV
DD
AV
SS
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
V
DD
U2CTS/RF12
U2RTS
/RF13
IC7/U1CTS
/CN20/RD14
IC8/U1RTS
/CN21/RD15
V
DD
V
SS
PGEC1/AN6/OCFA/RB6
PGED1/AN7/RB7
U2TX/CN18/RF5
U2RX/CN17/RF4
AN29/RE5
AN30/RE6
AN31/RE7
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
SCK2/CN8/RG6
V
DD
TMS/RA0
AN20/INT1/RA12
AN21/INT2/RA13
AN5/CN7/RB5
AN4/CN6/RB4
AN3/CN5/RB3
AN2/SS1
/CN4/RB2
SDI2/CN9/RG7
SDO2/CN10/RG8
PGEC3/AN1/CN3/RB1
PGED3/AN0/CN2/RB0
RG15
V
DD
SS2/CN11/RG9
MCLR
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
C2TX/RG1
C1TX/RF1
OC8/CN16/RD7
OC7/CN15/RD6
TDO/RA5
INT4/RA15
INT3/RA14
V
SS
V
SS
V
SS
V
DD
TDI/RA4
TCK/RA1
100-Pin TQFP
100
PIC24HJ256GP610
= Pins are up to 5V tolerant
PIC24HJXXXGPX06/X08/X10
© 2009 Microchip Technology Inc. DS70175H-page 9
PIC24HJXXXGPX06/X08/X10
Table of Contents
PIC24H Product Families....................................................................................................................................................................... 3
1.0 Device Overview ........................................................................................................................................................................ 11
2.0 Guidelines for Getting Started with 16-Bit Microcontrollers........................................................................................................ 15
3.0 CPU............................................................................................................................................................................................ 19
4.0 Memory Organization ................................................................................................................................................................. 25
5.0 Flash Program Memory.............................................................................................................................................................. 55
6.0 Reset ......................................................................................................................................................................................... 61
7.0 Interrupt Controller ..................................................................................................................................................................... 65
8.0 Direct Memory Access (DMA) .................................................................................................................................................. 109
9.0 Oscillator Configuration ............................................................................................................................................................ 119
10.0 Power-Saving Features ............................................................................................................................................................ 129
11.0 I/O Ports ................................................................................................................................................................................... 137
12.0 Timer1 ...................................................................................................................................................................................... 139
13.0 Timer2/3, Timer4/5, Timer6/7 and Timer8/9 ............................................................................................................................ 141
14.0 Input Capture............................................................................................................................................................................ 147
15.0 Output Compare ....................................................................................................................................................................... 149
16.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 153
17.0 Inter-Integrated Circuit™ (I
18.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 167
19.0 Enhanced CAN (ECAN™) Module ........................................................................................................................................... 173
20.0 10-Bit/12-Bit Analog-to-Digital Converter (ADC) ...................................................................................................................... 199
21.0 Special Features ...................................................................................................................................................................... 211
22.0 Instruction Set Summary .......................................................................................................................................................... 219
23.0 Development Support............................................................................................................................................................... 227
24.0 Electrical Characteristics .......................................................................................................................................................... 231
25.0 Packaging Information.............................................................................................................................................................. 267
Appendix A: Revision History............................................................................................................................................................. 275
Index ................................................................................................................................................................................................. 281
The Microchip Web Site ..................................................................................................................................................................... 285
Customer Change Notification Service .............................................................................................................................................. 285
Customer Support .............................................................................................................................................................................. 285
Reader Response .............................................................................................................................................................................. 286
Product Identification System............................................................................................................................................................. 287
2
C™).............................................................................................................................................. 159
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DS70175H-page 10 © 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
1.0 DEVICE OVERVIEW
Note: This data sheet summarizes the features
of the PIC24HJXXXGPX06/X08/X10 family of devices. However, it is not intended
to be a comprehensive reference source.
To complement the information in this data
sheet, refer to the latest family reference
sections of the “PIC24H Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
This document contains device specific information for
the following devices:
• PIC24HJ64GP206
• PIC24HJ64GP210
• PIC24HJ64GP506
• PIC24HJ64GP510
• PIC24HJ128GP206
• PIC24HJ128GP210
• PIC24HJ128GP506
• PIC24HJ128GP510
• PIC24HJ128GP306
• PIC24HJ128GP310
• PIC24HJ256GP206
• PIC24HJ256GP210
• PIC24HJ256GP610
The PIC24HJXXXGPX06/X08/X10 device family
includes devices with different pin counts (64 and 100
pins), different program memory sizes (64 Kbytes, 128
Kbytes and 256 Kbytes) and different RAM sizes (8
Kbytes and 16 Kbytes).
This makes these families suitable for a wide variety of
high-performance digital signal control applications.
The devices are pin compatible with the dsPIC33F family of devices, and also share a very high degree of
compatibility with the dsPIC30F family devices. This
allows easy migration between device families as may
be necessitated by the specific functionality, computational resource and system cost requirements of the
application.
The PIC24HJXXXGPX06/X08/X10 device family
employs a powerful 16-bit architecture, ideal for
applications that rely on high-speed, repetitive
computations, as well as control.
The 17 x 17 multiplier, hardware support for division
operations, multi-bit data shifter, a large array of 16-bit
working registers and a wide variety of data addressing
modes, together provide the
PIC24HJXXXGPX06/X08/X10 Central Processing Unit
(CPU) with extensive mathematical processing
capability. Flexible and deterministic interrupt handling,
coupled with a powerful array of peripherals, renders
the PIC24HJXXXGPX06/X08/X10 devices suitable for
control applications. Further, Direct Memory Access
(DMA) enables overhead-free transfer of data between
several peripherals and a dedicated DMA RAM.
Reliable, field programmable Flash program memory
ensures scalability of applications that use
PIC24HJXXXGPX06/X08/X10 devices.
Figure 1-1 shows a general block diagram of the
various core and peripheral modules in the
PIC24HJXXXGPX06/X08/X10 family of devices, while
Table 1-1 lists the functions of the various pins shown
in the pinout diagrams.
© 2009 Microchip Technology Inc. DS70175H-page 11
16
OSC1/CLKI
OSC2/CLKO
V
DD, VSS
Timing
Generation
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Precision
Reference
Band Gap
FRC/LPRC
Oscillators
Regulator
Voltage
VCAP/VDDCORE
UART1,2
ECAN1,2
IC1-8
OC/
SPI1,2
I2C1,2
PORTA
Note: Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins
and features present on each device.
PWM1-8
CN1-23
Instruction
Decode and
Control
PCH PCL
16
Program Counter
16-bit ALU
23
23
24
23
Instruction Reg
PCU
16 x 16
W Register Array
ROM Latch
16
EA MUX
16
8
Interrupt
Controller
PSV and Table
Data Access
Control Block
Stack
Control
Logic
Loop
Control
Logic
Address Latch
Program Memory
Data Latch
Literal Data
16
16
16
16
Data Latch
Address
Latch
16
X RAM
Data Bus
17 x 17 Multiplier
Divide Support
16
DMA
RAM
DMA
Controller
Control Signals
to Various Blocks
ADC1,2
Timers
PORTB
PORTC
PORTD
PORTE
PORTF
PORTG
Address Generator Units
1-9
PIC24HJXXXGPX06/X08/X10
FIGURE 1-1: PIC24HJXXXGPX06/X08/X10 GENERAL BLOCK DIAGRAM
DS70175H-page 12 © 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
TABLE 1-1: PINOUT I/O DESCRIPTIONS
Pin Name
AN0-AN31 I Analog Analog input channels.
AV
DD P P Positive supply for analog modules. This pin must be connected at all times.
AVSS P P Ground reference for analog modules.
CLKI
CLKO
CN0-CN23 I ST Input change notification inputs.
C1RX
C1TX
C2RX
C2TX
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
IC1-IC8 I ST Capture inputs 1 through 8.
INT0
INT1
INT2
INT3
INT4
MCLR
OCFA
OCFB
OC1-OC8
OSC1
OSC2
RA0-RA7
RA9-RA10
RA12-RA15
RB0-RB15 I/O ST PORTB is a bidirectional I/O port.
RC1-RC4
RC12-RC15
RD0-RD15 I/O ST PORTD is a bidirectional I/O port.
RE0-RE7 I/O ST PORTE is a bidirectional I/O port.
RF0-RF8
RF12-RF13
RG0-RG3
RG6-RG9
RG12-RG15
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
Pin
Type
I
O
I
O
I
O
I/O
I
I/O
I
I/O
I
I
I
I
I
I
I/P ST Master Clear (Reset) input. This pin is an active-low Reset to the device.
I
I
O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O ST PORTF is a bidirectional I/O port.
I/O
I/O
I/O
Buffer
Typ e
ST/CMOS—External clock source input. Always associated with OSC1 pin function.
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes. Always associated
with OSC2 pin function.
Can be software programmed for internal weak pull-ups on all inputs.
ST
—
ST
—
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
—
ST/CMOS—Oscillator crystal input. ST buffer when configured in RC mode; CMOS
ST
ST
ST
ST
ST
ST
ST
ST
ECAN1 bus receive pin.
ECAN1 bus transmit pin.
ECAN2 bus receive pin.
ECAN2 bus transmit pin.
Data I/O pin for programming/debugging communication channel 1.
Clock input pin for programming/debugging communication channel 1.
Data I/O pin for programming/debugging communication channel 2.
Clock input pin for programming/debugging communication channel 2.
Data I/O pin for programming/debugging communication channel 3.
Clock input pin for programming/debugging communication channel 3.
External interrupt 0.
External interrupt 1.
External interrupt 2.
External interrupt 3.
External interrupt 4.
Compare Fault A input (for Compare Channels 1, 2, 3 and 4).
Compare Fault B input (for Compare Channels 5, 6, 7 and 8).
Compare outputs 1 through 8.
otherwise.
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes.
PORTA is a bidirectional I/O port.
PORTC is a bidirectional I/O port.
PORTG is a bidirectional I/O port.
Description
© 2009 Microchip Technology Inc. DS70175H-page 13
PIC24HJXXXGPX06/X08/X10
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
SCK1
SDI1
SDO1
SS1
SCK2
SDI2
SDO2
SS2
SCL1
SDA1
SCL2
SDA2
SOSCI
SOSCO
TMS
TCK
TDI
TDO
T1CK
T2CK
T3CK
T4CK
T5CK
T6CK
T7CK
T8CK
T9CK
U1CTS
U1RTS
U1RX
U1TX
U2CTS
U2RTS
U2RX
U2TX
DD P — Positive supply for peripheral logic and I/O pins.
V
V
CAP/VDDCORE P — CPU logic filter capacitor connection.
VSS P — Ground reference for logic and I/O pins.
V
REF+ I Analog Analog voltage reference (high) input.
V
REF- I Analog Analog voltage reference (low) input.
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
Pin
Type
I/O
I
O
I/O
I/O
I
O
I/O
I/O
I/O
I/O
I/O
I
O
I
I
I
O
I
I
I
I
I
I
I
I
I
I
O
I
O
I
O
I
O
Buffer
Typ e
ST
ST
—
ST
ST
ST
—
ST
ST
ST
ST
ST
ST/CMOS—32.768 kHz low-power oscillator crystal input; CMOS otherwise.
ST
ST
ST
—
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
—
ST
—
ST
—
ST
—
Synchronous serial clock input/output for SPI1.
SPI1 data in.
SPI1 data out.
SPI1 slave synchronization or frame pulse I/O.
Synchronous serial clock input/output for SPI2.
SPI2 data in.
SPI2 data out.
SPI2 slave synchronization or frame pulse I/O.
Synchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
Synchronous serial clock input/output for I2C2.
Synchronous serial data input/output for I2C2.
32.768 kHz low-power oscillator crystal output.
JTAG Test mode select pin.
JTAG test clock input pin.
JTAG test data input pin.
JTAG test data output pin.
Timer1 external clock input.
Timer2 external clock input.
Timer3 external clock input.
Timer4 external clock input.
Timer5 external clock input.
Timer6 external clock input.
Timer7 external clock input.
Timer8 external clock input.
Timer9 external clock input.
UART1 clear to send.
UART1 ready to send.
UART1 receive.
UART1 transmit.
UART2 clear to send.
UART2 ready to send.
UART2 receive.
UART2 transmit.
Description
DS70175H-page 14 © 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT MICROCONTROLLERS
Note: This data sheet summarizes the features
of the PIC24HJXXXGPX06/X08/X10
family of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the “PIC24H Family
Reference Manual”, which is available
from the Microchip website
(www.microchip.com).
2.1 Basic Connection Requirements
Getting started with the PIC24HJXXXGPX06/X08/X10
family of 16-bit Microcontrollers (MCUs) requires
attention to a minimal set of device pin connections
before proceeding with development. The following is a
list of pin names, which must always be connected:
DD and VSS pins
• All V
(see Section 2.2 “Decoupling Capacitors”)
• All AV
•V
•MCLR
• PGECx/PGEDx pins used for In-Circuit Serial
• OSC1 and OSC2 pins when external oscillator
Additionally, the following pins may be required:
•V
DD and AVSS pins (regardless if ADC module
is not used)
(see Section 2.2 “Decoupling Capacitors”)
CAP/VDDCORE
(see Section 2.3 “Capacitor on Internal Voltage
Regulator (VCAP/VDDCORE)”)
pin
(see Section 2.4 “Master Clear (MCLR) Pin”)
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
source is used
(see Section 2.6 “External Oscillator Pins”)
REF+/VREF- pins used when external voltage
reference for ADC module is implemented
Note: The AVDD and AVSS pins must be
connected independent of the ADC
voltage reference source.
2.2 Decoupling Capacitors
The use of decoupling capacitors on every pair of
power supply pins, such as V
AVSS is required.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: Recommendation
of 0.1 µF (100 nF), 10-20V. This capacitor should
be a low-ESR and have resonance frequency in
the range of 20 MHz and higher. It is
recommended that ceramic capacitors be used.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within
one-quarter inch (6 mm) in length.
• Handling high frequency noise: If the board is
experiencing high frequency noise, upward of
tens of MHz, add a second ceramic-type capacitor
in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible.
For example, 0.1 µF in parallel with 0.001 µF.
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum thereby reducing PCB track inductance.
DD, VSS, AVDD and
© 2009 Microchip Technology Inc. DS70175H-page 15
PIC24HJXXXGPX06/X08/X10
PIC24H
VDD
VSS
VDD
VSS
VSS
VDD
AVDD
AVSS
VDD
VSS
0.1 µF
Ceramic
0.1 µF
Ceramic
0.1 µF
Ceramic
0.1 µF
Ceramic
C
R
V
DD
MCLR
0.1 µF
Ceramic
VCAP/VDDCORE
10 Ω
R1
Note 1: R ≤ 10 kΩ is recommended. A suggested
starting value is 10 kΩ. Ensure that the
MCLR
pin VIH and VIL specifications are met.
2: R1 ≤ 470Ω will limit any current flowing into
MCLR
from the external capacitor C, in the
event of MCLR
pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR
pin
V
IH and VIL specifications are met.
C
R1
R
V
DD
MCLR
PIC24H
JP
FIGURE 2-1: RECOMMENDED
MINIMUM CONNECTION
2.2.1 TANK CAPACITORS
On boards with power traces running longer than six
inches in length, it is suggested to use a tank capacitor
for integrated circuits including MCUs to supply a local
power source. The value of the tank capacitor should
be determined based on the trace resistance that connects the power supply source to the device, and the
maximum current drawn by the device in the application. In other words, select the tank capacitor so that it
meets the acceptable voltage sag at the device. Typical
values range from 4.7 µF to 47 µF.
2.4 Master Clear (MCLR) Pin
The MCLR pin provides for two specific device
functions:
• Device Reset
• Device programming and debugging
During device programming and debugging, the
resistance and capacitance that can be added to the
pin must be considered. Device programmers and
debuggers drive the MCLR
specific voltage levels (VIH and VIL) and fast signal
transitions must not be adversely affected. Therefore,
specific values of R and C will need to be adjusted
based on the application and PCB requirements.
For example, as shown in Figure 2-2, it is
recommended that the capacitor C, be isolated from
the MCLR
pin during programming and debugging
operations.
Place the components shown in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR
FIGURE 2-2: EXAMPLE OF MCLR PIN
CONNECTIONS
pin. Consequently,
pin.
2.3 Capacitor on Internal Voltage
Regulator (V
A low-ESR (< 5 Ohms) capacitor is required on the
CAP/VDDCORE pin, which is used to stabilize the
V
voltage regulator output voltage. The V
pin must not be connected to VDD, and must have a
capacitor between 4.7 µF and 10 µF, 16V connected to
ground. The type can be ceramic or tantalum. Refer to
Section 24.0 “Electrical Characteristics” for
additional information.
The placement of this capacitor should be close to the
CAP/VDDCORE. It is recommended that the trace
V
length not exceed one-quarter inch (6 mm). Refer to
Section 21.2 “On-Chip Voltage Regulator” for
details.
DS70175H-page 16 © 2009 Microchip Technology Inc.
CAP/VDDCORE)
CAP/VDDCORE
PIC24HJXXXGPX06/X08/X10
13
Main Oscillator
Guard Ring
Guard Trace
Secondary
Oscillator
14
15
16
17
18
19
20
2.5 ICSP Pins
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length
between the ICSP connector and the ICSP pins on the
device as short as possible. If the ICSP connector is
expected to experience an ESD event, a series resistor
is recommended, with the value in the range of a few
tens of Ohms, not to exceed 100 Ohms.
Pull-up resistors, series diodes, and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communications to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits and pin input voltage high
IH) and input low (VIL) requirements.
(V
Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to
MPLAB
ICE™.
For more information on ICD 2, ICD 3 and REAL ICE
connection requirements, refer to the following
documents that are available on the Microchip website.
• “MPLAB
• “Using MPLAB
• “MPLAB
• “Using MPLAB
• “MPLAB
• “MPLAB
• “Using MPLAB
®
ICD 2, MPLAB ICD 3, or MPLAB REAL
®
ICD 2 In-Circuit Debugger User’s
Guide” DS51331
®
®
ICD 2” (poster) DS51265
ICD 2 Design Advisory” DS51566
®
ICD 3 In-Circuit Debugger”
(poster) DS51765
®
ICD 3 Design Advisory” DS51764
®
REAL ICE™ In-Circuit Emulator User’s
Guide” DS51616
®
REAL ICE™” (poster) DS51749
2.6 External Oscillator Pins
Many MCUs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator (refer to Section 9.0 “Oscillator
Configuration” for details).
The oscillator circuit should be placed on the same
side of the board as the device. Also, place the
oscillator circuit close to the respective oscillator pins,
not exceeding one-half inch (12 mm) distance
between them. The load capacitors should be placed
next to the oscillator itself, on the same side of the
board. Use a grounded copper pour around the
oscillator circuit to isolate them from surrounding
circuits. The grounded copper pour should be routed
directly to the MCU ground. Do not run any signal
traces or power traces inside the ground pour. Also, if
using a two-sided board, avoid any traces on the
other side of the board where the crystal is placed. A
suggested layout is shown in Figure 2-3.
FIGURE 2-3: SUGGESTED PLACEMENT
OF THE OSCILLATOR
CIRCUIT
© 2009 Microchip Technology Inc. DS70175H-page 17
PIC24HJXXXGPX06/X08/X10
2.7 Oscillator Value Conditions on Device Start-up
If the PLL of the target device is enabled and
configured for the device start-up oscillator, the
maximum oscillator source frequency must be limited
to 4 MHz < F
start-up conditions. This means that if the external
oscillator frequency is outside this range, the
application must start-up in the FRC mode first. The
default PLL settings after a POR with an oscillator
frequency outside this range will violate the device
operating speed.
Once the device powers up, the application firmware
can initialize the PLL SFRs, CLKDIV and PLLDBF to a
suitable value, and then perform a clock switch to the
Oscillator + PLL clock source. Note that clock switching
must be enabled in the device Configuration word.
2.8 Configuration of Analog and
IN < 8 MHz to comply with device PLL
Digital Pins During ICSP
Operations
If MPLAB ICD 2, ICD 3 or REAL ICE is selected as a
debugger, it automatically initializes all of the A/D input
pins (ANx) as “digital” pins, by setting all bits in the
AD1PCFGL register.
The bits in this register that correspond to the A/D pins
that are initialized by MPLAB ICD 2, ICD 3, or REAL
ICE, must not be cleared by the user application
firmware; otherwise, communication errors will result
between the debugger and the device.
If your application needs to use certain A/D pins as
analog input pins during the debug session, the user
application must clear the corresponding bits in the
AD1PCFGL register during initialization of the ADC
module.
When MPLAB ICD 2, ICD 3 or REAL ICE is used as a
programmer, the user application firmware must
correctly configure the AD1PCFGL register. Automatic
initialization of this register is only done during
debugger operation. Failure to correctly configure the
register(s) will result in all A/D pins being recognized as
analog input pins, resulting in the port value being read
as a logic ‘0’, which may affect user application
functionality.
2.9 Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic-low state.
Alternatively, connect a 1k to 10k resistor to V
unused pins and drive the output to logic low.
DS70175H-page 18 © 2009 Microchip Technology Inc.
SS on
PIC24HJXXXGPX06/X08/X10
3.0 CPU
Note: This data sheet summarizes the features
of the PIC24HJXXXGPX06/X08/X10 family of devices. However, it is not intended
to be a comprehensive reference source.
To complement the information in this data
sheet, refer to the “PIC24H Family Refer-
ence Manual”, Section 2. “CPU”
(DS70245), which is available from the
Microchip website (www.microchip.com).
The PIC24HJXXXGPX06/X08/X10 CPU module has a
16-bit (data) modified Harvard architecture with an
enhanced instruction set and addressing modes. The
CPU has a 24-bit instruction word with a variable length
opcode field. The Program Counter (PC) is 23 bits wide
and addresses up to 4M x 24 bits of user program
memory space. The actual amount of program memory
implemented varies by device. A single-cycle instruction
prefetch mechanism is used to help maintain throughput
and provides predictable execution. All instructions
execute in a single cycle, with the exception of
instructions that change the program flow, the double
word move (MOV.D) instruction and the table instructions.
Overhead-free, single-cycle program loop constructs are
supported using the REPEAT instruction, which is
interruptible at any point.
The PIC24HJXXXGPX06/X08/X10 devices have
sixteen, 16-bit working registers in the programmer’s
model. Each of the working registers can serve as a data,
address or address offset register. The 16th working
register (W15) operates as a software Stack Pointer (SP)
for interrupts and calls.
The PIC24HJXXXGPX06/X08/X10 instruction set
includes many addressing modes and is designed for
optimum C compiler efficiency. For most instructions,
the PIC24HJXXXGPX06/X08/X10 is capable of
executing a data (or program data) memory read, a
working register (data) read, a data memory write and
a program (instruction) memory read per instruction
cycle. As a result, three parameter instructions can be
supported, allowing A + B = C operations to be
executed in a single cycle.
A block diagram of the CPU is shown in Figure 3-1,
and the programmer’s model for the
PIC24HJXXXGPX06/X08/X10 is shown in Figure 3-2.
3.1 Data Addressing Overview
The data space can be linearly addressed as 32K words
or 64 Kbytes using an Address Generation Unit (AGU).
The upper 32 Kbytes of the data space memory map can
optionally be mapped into program space at any 16K program word boundary defined by the 8-bit Program Space
Visibility Page (PSVPAG) register. The program to data
space mapping feature lets any instruction access program space as if it were data space.
The data space also includes 2 Kbytes of DMA RAM,
which is primarily used for DMA data transfers, but may
be used as general purpose RAM.
3.2 Special MCU Features
The PIC24HJXXXGPX06/X08/X10 features a 17-bit by
17-bit, single-cycle multiplier. The multiplier can
perform signed, unsigned and mixed-sign
multiplication. Using a 17-bit by 17-bit multiplier for
16-bit by 16-bit multiplication makes mixed-sign
multiplication possible.
The PIC24HJXXXGPX06/X08/X10 supports 16/16 and
32/16 integer divide operations. All divide instructions
are iterative operations. They must be executed within
a REPEAT loop, resulting in a total execution time of 19
instruction cycles. The divide operation can be
interrupted during any of those 19 cycles without loss
of data.
A multi-bit data shifter is used to perform up to a 16-bit,
left or right shift in a single cycle.
© 2009 Microchip Technology Inc. DS70175H-page 19
PIC24HJXXXGPX06/X08/X10
Instruction
Decode and
Control
PCH PCL
Program Counter
16-bit ALU
24
23
Instruction Reg
PCU
16 x 16
W Register Array
ROM Latch
EA MUX
Interrupt
Controller
Stac k
Control
Logic
Loop
Control
Logic
Control Signals
to Various Blocks
Literal Data
16
16
16
To Peripheral Modules
Data Latch
Address
Latch
16
X RAM
Address Generator Units
X Data Bus
DMA
Controller
DMA
RAM
17 x 17
Divide Support
16
16
23
23
16
8
PSV and Table
Data Access
Control Block
16
16
16
Program Memory
Data Latch
Address Latch
Multiplier
FIGURE 3-1: PIC24HJXXXGPX06/X08/X10 CPU CORE BLOCK DIAGRAM
DS70175H-page 20 © 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
PC22
PC0
7
0
D0D15
Program Counter
Data Table Page Address
STATUS Register
Working Registers
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14/Frame Pointer
W15/Stack Pointer
7
0
Program Space Visibility Page Address
Z
0
— — ——
RCOUNT
15
0
REPEAT Loop Counter
IPL2 IPL1
SPLIM
Stack Pointer Limit Register
SRL
PUSH.S Shadow
DO Shadow
——
15
0
Core Configuration Register
Legend
CORCON
— DC
RA
N
TBLPAG
PSVPAG
IPL0 OV
W0/WREG
SRH
C
FIGURE 3-2: PIC24HJXXXGPX06/X08/X10 PROGRAMMER’S MODEL
3.3 CPU Control Registers
© 2009 Microchip Technology Inc. DS70175H-page 21
PIC24HJXXXGPX06/X08/X10
REGISTER 3-1: SR: CPU STATUS REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — —DC
bit 15 bit 8
(1)
R/W-0
IPL<2:0>
bit 7 bit 0
Legend:
C = Clear only bit R = Readable bit U = Unimplemented bit, read as ‘0’
S = Set only bit W = Writable bit -n = Value at POR
‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-9 Unimplemented: Read as ‘0’
bit 8 DC: MCU ALU Half Carry/Borrow
1 = A carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized data)
0 = No carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized
bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits
111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
bit 4 RA: REPEAT Loop Active bit
1 = REPEAT loop in progress
0 = REPEAT loop not in progress
bit 3 N: MCU ALU Negative bit
1 = Result was negative
0 = Result was non-negative (zero or positive)
bit 2 OV: MCU ALU Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the magnitude which
causes the sign bit to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 1 Z: MCU ALU Zero bit
1 = An operation which affects the Z bit has set it at some time in the past
0 = The most recent operation which affects the Z bit has cleared it (i.e., a non-zero result)
bit 0 C: MCU ALU Carry/Borrow
1 = A carry-out from the Most Significant bit (MSb) of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
(2)
R/W-0
(2)
of the result occurred
data) of the result occurred
R/W-0
(2)
R-0 R/W-0 R/W-0 R/W-0 R/W-0
RA N OV Z C
bit
(2)
bit
Note 1: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
2: The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>).
DS70175H-page 22 © 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
REGISTER 3-2: CORCON: CORE CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R/C-0 R/W-0 U-0 U-0
— — — —IPL3
bit 7 bit 0
Legend: C = Clear only bit
R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set
0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’
bit 15-4 Unimplemented: Read as ‘0’
bit 3 IPL3: CPU Interrupt Priority Level Status bit 3
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
bit 2 PSV: Program Space Visibility in Data Space Enable bit
1 = Program space visible in data space
0 = Program space not visible in data space
bit 1-0 Unimplemented: Read as ‘0’
Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.
(1)
(1)
PSV — —
© 2009 Microchip Technology Inc. DS70175H-page 23
PIC24HJXXXGPX06/X08/X10
3.4 Arithmetic Logic Unit (ALU)
The PIC24HJXXXGPX06/X08/X10 ALU is 16 bits wide
and is capable of addition, subtraction, bit shifts and
logic operations. Unless otherwise mentioned,
arithmetic operations are 2’s complement in nature.
Depending on the operation, the ALU may affect the
values of the Carry (C), Zero (Z), Negative (N),
Overflow (OV) and Digit Carry (DC) Status bits in the
SR register. The C and DC Status bits operate as
and Digit Borrow bits, respectively, for
Borrow
subtraction operations.
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from
the ALU can be written to the W register array or a data
memory location.
Refer to the “dsPIC30F/33F Programmer’s Reference
Manual” (DS70157) for information on the SR bits
affected by each instruction.
The PIC24HJXXXGPX06/X08/X10 CPU incorporates
hardware support for both multiplication and division.
This includes a dedicated hardware multiplier and
support hardware for 16-bit divisor division.
3.4.1 MULTIPLIER
Using the high-speed 17-bit x 17-bit multiplier, the ALU
supports unsigned, signed or mixed-sign operation in
several multiplication modes:
1. 16-bit x 16-bit signed
2. 16-bit x 16-bit unsigned
3. 16-bit signed x 5-bit (literal) unsigned
4. 16-bit unsigned x 16-bit unsigned
5. 16-bit unsigned x 5-bit (literal) unsigned
6. 16-bit unsigned x 16-bit signed
7. 8-bit unsigned x 8-bit unsigned
3.4.2 DIVIDER
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
1. 32-bit signed/16-bit signed divide
2. 32-bit unsigned/16-bit unsigned divide
3. 16-bit signed/16-bit signed divide
4. 16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0
and the remainder in W1. Sixteen-bit signed and
unsigned DIV instructions can specify any W register
for both the 16-bit divisor (Wn) and any W register
(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.
The divide algorithm takes one cycle per bit of divisor,
so both 32-bit/16-bit and 16-bit/16-bit instructions take
the same number of cycles to execute.
3.4.3 MULTI-BIT DATA SHIFTER
The multi-bit data shifter is capable of performing up to
16-bit arithmetic or logic right shifts, or up to 16-bit left
shifts in a single cycle. The source can be either a
working register or a memory location.
The shifter requires a signed binary value to determine
both the magnitude (number of bits) and direction of the
shift operation. A positive value shifts the operand right.
A negative value shifts the operand left. A value of ‘0’
does not modify the operand.
DS70175H-page 24 © 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
Reset Address
0x000000
0x0000FE
0x000002
0x000100
Device Configuration
User Program
Flash Memory
0x00AC00
0x00ABFE
(22K instructions)
0x800000
0xF80000
Registers
0xF80017
0xF80010
DEVID (2)
0xFEFFFE
0xFF0000
0xFFFFFE
0xF7FFFE
Unimplemented
(Read ‘0’s)
GOTO Instruction
0x000004
Reserved
0x7FFFFE
Reserved
0x000200
0x0001FE
0x000104
Alternate Vector Table
Reserved
Interrupt Vector Table
Reset Address
Device Configuration
Registers
DEVID (2)
Unimplemented
(Read ‘0’s)
GOTO
Instruction
Reserved
Reserved
Alternate Vector Table
Reserved
Interrupt Vector Table
Reset Address
Device Configuration
User Program
Flash Memory
(88K instructions)
Registers
DEVID (2)
GOTO Instruction
Reserved
Reserved
Alternate Vector Table
Reserved
Interrupt Vector Table
PIC24HJ64XXXXX PIC24HJ128XXXXX PIC24HJ256XXXXX
Configuration Memory Space
User Memory Space
0x015800
0x0157FE
User Program
(44K instructions)
Flash Memory
(Read ‘0’s)
Unimplemented
0x02AC00
0x02ABFE
4.0 MEMORY ORGANIZATION
Note: This data sheet summarizes the features
of the PIC24HJXXXGPX06/X08/X10 family of devices. However, it is not intended
to be a comprehensive reference source.
To complement the information in this data
sheet, refer to the “PIC24H Family Refer-
ence Manual”, Section 3. “Data Memory”
(DS70237), which is available from the
Microchip website (www.microchip.com).
The PIC24HJXXXGPX06/X08/X10 architecture features separate program and data memory spaces and
buses. This architecture also allows the direct access
of program memory from the data space during code
execution.
FIGURE 4-1: PROGRAM MEMORY MAP FOR PIC24HJXXXGPX06/X08/X10 FAMILY DEVICES
4.1 Program Address Space
The program address memory space of the
PIC24HJXXXGPX06/X08/X10 devices is 4M instructions.
The space is addressable by a 24-bit value derived from
either the 23-bit Program Counter (PC) during program
execution, or from table operation or data space remapping as described in Section 4.4 “Interfacing Program
and Data Memory Spaces”.
User access to the program memory space is restricted
to the lower half of the address range (0x000000 to
0x7FFFFF). The exception is the use of TBLRD/TBLWT
operations, which use TBLPAG<7> to permit access to
the Configuration bits and Device ID sections of the
configuration memory space.
Memory maps for the PIC24HJXXXGPX06/X08/X10
family of devices are shown in Figure 4-1.
© 2009 Microchip Technology Inc. DS70175H-page 25
PIC24HJXXXGPX06/X08/X10
0816
PC Address
0x000000
0x000002
0x000004
0x000006
23
00000000
00000000
00000000
00000000
Program Memory
‘Phantom’ Byte
(read as ‘0’)
least significant word
most significant word
Instruction Width
0x000001
0x000003
0x000005
0x000007
msw
Address (lsw Address)
4.1.1 PROGRAM MEMORY ORGANIZATION
The program memory space is organized in wordaddressable blocks. Although it is treated as 24 bits
wide, it is more appropriate to think of each address of
the program memory as a lower and upper word, with
the upper byte of the upper word being unimplemented.
The lower word always has an even address, while the
upper word has an odd address (Figure 4-2).
Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or
decremented by two during code execution. This
arrangement also provides compatibility with data
memory space addressing and makes it possible to
access data in the program memory space.
4.1.2 INTERRUPT AND TRAP VECTORS
All PIC24HJXXXGPX06/X08/X10 devices reserve the
addresses between 0x00000 and 0x000200 for hardcoded program execution vectors. A hardware Reset
vector is provided to redirect code execution from the
default value of the PC on device Reset to the actual
start of code. A GOTO instruction is programmed by the
user at 0x000000, with the actual address for the start
of code at 0x000002.
PIC24HJXXXGPX06/X08/X10 devices also have two
interrupt vector tables, located from 0x000004 to
0x0000FF and 0x000100 to 0x0001FF. These vector
tables allow each of the many device interrupt sources
to be handled by separate Interrupt Service Routines
(ISRs). A more detailed discussion of the interrupt vector tables is provided in Section 7.1 “Interrupt Vector
Table”.
FIGURE 4-2: PROGRAM MEMORY ORGANIZATION
DS70175H-page 26 © 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
4.2 Data Address Space
The PIC24HJXXXGPX06/X08/X10 CPU has a separate 16-bit wide data memory space. The data space is
accessed using separate Address Generation Units
(AGUs) for read and write operations. Data memory
maps of devices with different RAM sizes are shown in
Figure 4-3 and Figure 4-4.
All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to bytes within the data space.
This arrangement gives a data space address range of
64 Kbytes or 32K words. The lower half of the data
memory space (that is, when EA<15> = 0) is used for
implemented memory addresses, while the upper half
(EA<15> = 1) is reserved for the Program Space
Visibility area (see Section 4.4.3 “Reading Data from
Program Memory Using Program Space Visibility”).
PIC24HJXXXGPX06/X08/X10 devices implement up
to 16 Kbytes of data memory. Should an EA point to a
location outside of this area, an all-zero word or byte
will be returned.
4.2.1 DATA SPACE WIDTH
The data memory space is organized in byte addressable, 16-bit wide blocks. Data is aligned in data
memory and registers as 16-bit words, but all data
space EAs resolve to bytes. The Least Significant
Bytes of each word have even addresses, while the
Most Significant Bytes have odd addresses.
4.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT
To maintain backward compatibility with PIC
devices and improve data space memory usage
efficiency, the PIC24HJXXXGPX06/X08/X10 instruction set supports both word and byte operations. As a
consequence of byte accessibility, all effective address
calculations are internally scaled to step through wordaligned memory. For example, the core recognizes that
Post-Modified Register Indirect Addressing mode
[Ws++] will result in a value of Ws + 1 for byte
operations and Ws + 2 for word operations.
Data byte reads will read the complete word that
contains the byte, using the Least Significant bit (LSb)
of any EA to determine which byte to select. The
selected byte is placed onto the Least Significant Byte
(LSB) of the data path. That is, data memory and registers are organized as two parallel byte-wide entities
with shared (word) address decode but separate write
lines. Data byte writes only write to the corresponding
side of the array or register which matches the byte
address.
®
MCU
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error
trap is generated. If the error occurred on a read, the
instruction underway is completed; if it occurred on a
write, the instruction will be executed but the write does
not occur. In either case, a trap is then executed, allowing the system and/or user to examine the machine
state prior to execution of the address Fault.
All byte loads into any W register are loaded into the
Least Significant Byte. The Most Significant Byte
(MSB) is not modified.
A sign-extend instruction (SE) is provided to allow
users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, users
can clear the Most Significant Byte of any W register by
executing a zero-extend (ZE) instruction on the
appropriate address.
4.2.3 SFR SPACE
The first 2 Kbytes of the Near Data Space, from 0x0000
to 0x07FF, is primarily occupied by Special Function
Registers (SFRs). These are used by the
PIC24HJXXXGPX06/X08/X10 core and peripheral
modules for controlling the operation of the device.
SFRs are distributed among the modules that they
control, and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’. A complete listing of implemented
SFRs, including their addresses, is shown in Table 4-1
through Table 4-33.
Note: The actual set of peripheral features and
interrupts varies by the device. Please
refer to the corresponding device tables
and pinout diagrams for device-specific
information.
4.2.4 NEAR DATA SPACE
The 8-Kbyte area between 0x0000 and 0x1FFF is
referred to as the Near Data Space. Locations in this
space are directly addressable via a 13-bit absolute
address field within all memory direct instructions.
Additionally, the whole data space is addressable using
MOV instructions, which support Memory Direct
Addressing mode with a 16-bit address field, or by
using Indirect Addressing mode using a working
register as an Address Pointer.
© 2009 Microchip Technology Inc. DS70175H-page 27
PIC24HJXXXGPX06/X08/X10
0x0000
0x07FE
0xFFFE
LSB
Address
16 bits
LSBMSB
MSB
Address
0x0001
0x07FF
0xFFFF
Optionally
Mapped
into Program
Memory
0x27FF 0x27FE
0x0801
0x0800
2 Kbyte
SFR Space
8 Kbyte
SRAM Space
0x8001
0x8000
0x28000x2801
0x1FFE
0x2000
0x1FFF
0x2001
Space
Data
Near
8 Kbyte
SFR Space
X Data
Unimplemented (X)
DMA RAM
X Data RAM (X)
FIGURE 4-3: DATA MEMORY MAP FOR PIC24HJXXXGPX06/X08/X10 DEVICES WITH 8 KBS RAM
DS70175H-page 28 © 2009 Microchip Technology Inc.
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