MICROCHIP PIC24H Technical data

PIC24H

Family Overview

High-Performance 16-Bit

Microcontrollers

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such ac t s allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of M icrochip’s prod ucts as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICD EM, Select Mode, Smart Serial, SmartTel, Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

8-bit MCUs, KEELOQ

code hopping

PIC24H

PIC24H High-Performance 16-Bit MCU Overview

Operating Range

• DC – 40 MIPS ( 40 M IPS @ 3. 0-3 .6 V, -40° to +8 5°C)

• Industrial temperature range (-40° to +85°C)

High-Performance DSC CPU

• Modified Harvard architecture

• C compiler optimized instruction set

• 16-bit wide data path

• 24-bit wide instructions

• Linear program memory addressing up to 4M

instruction words

• Linear data m emory addressing up to 64 Kbytes

• 74 base instructions: mostly 1 word/1 cycle

• Sixteen 16-bit general-purpose registers

• Flexible and powerful addressing modes

• Software stack

• 16 x 16 integer multiply operations

• 32/16 and 16/16 divide operations

• Single-cycle multiply

• Up to ± 16-bit shifts

Direct Memory Access (DMA)

• 8-channel hardware DMA

• Allows data transfer between RAM and a

peripheral while CPU is executing code (no cycle stealing)

• 2 KB of dual-porte d DM A bu f fe r area (DMA RAM)

to store data transferred via DMA

• Most peripherals support DMA

Interrupt Controller

• 5-cycle latency

• 118 interrupt vectors

• Up to 61 available interrupt sources, up to 5 external interrupts

• 7 programmable priority level s

• 5 processor exceptions

Digital I/O

• Up to 85 programmable digital I/O pins

• Wake-up/Interrupt-on-Change on up to 24 pins

• Output pins can drive from 3.0V to 3.6V

• All digital input pins are 5V tolerant

• 4 mA sink and source on all I/O pins

On-Chip Flash and SRAM

• Flash program memory, up to 256 Kbytes

• Data SRAM (up to 30 Kbytes):

- Includes 2 KB of DMA RA M

System Management

• Flexible clock options:

- External, crystal, resonator, internal RC

- Fully integrated P LL

- Extremely low jitter PLL

• Power-up timer

• Oscillator Start-up Timer/Stabilizer

• Watchdog timer with its own RC oscillator

• Fail-Safe Clock Mo nito r

• Reset by multiple sources

Power Management

• On-chip 2.5V voltage regulator

• Switch between clock sources in real time

• Idle, Sleep and Doze modes with fast wake-up

PIC24H

Timers/Capture/Compare/PWM

• Timer/Counters: up to nine 16-bit timers:

- Can pair up to make four 32-bit timers

- 1 timer runs as Real-Time Clock with external 32 kHz oscill ator

- Programmable prescaler

• Input Capture (up to 8 channels):

- Capture on up, down or both edges

- 16-bit capture input functions

- 4-deep FIFO on each capture

• Output Compare (up to 8 channels):

- Single or Dual 16-Bit Compare mode

- 16-Bit Glitchless PWM mode

Communication Modules

• 3-wire SPI™ (up to 2 modules):

- Framing supports I/O interface to simple codecs

- Supports 8-bit and 16-bit data

- Supports all serial clock formats and sampling modes

- 8-word FIFO buffers

C™ (up to 2 modules):

•I

- Full Multi-Master Slave mode s upport

- 7-bit and 10-bit addressing

- Bus collision detection and arbitration

- Integrated signal conditioning

-Address masking

• UART (up to 2 modules):

- Interrupt-on-address bit detect

- Wake-up-on-Start bit from Sleep mode

- 4-character TX and RX FIFO buffers

- LIN bus support

-IrDA

- High-Speed Baud mode

• Enhanced CAN 2.0B active (up to 2 modules):

- Up to 8 transmit and up to 32 receive buffers

- 16 receive filters and 3 masks

- Loopback, Listen Only and Listen All

- Wake-up on CAN message

- FIFO mode using DMA

encoding and decoding in hardware

Messages modes for diagnostics and bus monitoring

Analog-to-Digit al Converters (ADC)

• Up to two 10-bit or 12-bit ADC modules in a device

• 10-bit 2.2 Msps or 12-bit 1 Msps conversion:

- 2, 4 or 8 simultaneous samples

- Up to 32 input channels with auto-scanning

- Conversion start can be manual or

synchronized with 1 of 4 trigger sources

- Conversion possible in Sleep mode

- ±1 LSB max integral nonlinearity

- ±1 LSB max differential nonlinearity

CMOS Flash T echnology

• Low-power, high-speed Flash technology

• Fully static design

• 3.3V (+/- 10%) operating voltage

• Industrial temperature

• Low-power consumption

Packaging:

• 100-pin TQ FP (14x14x1 mm and 12x12x 1 mm)

• 64-pin TQFP (10x10x1 mm) Note: See Table 1-1 for exact peripheral

features per device.

1.0 PIC24H PRODUCT FAMILIES

1.1 General-Purpose Family

The PIC24H General-purpose Family (Table 1-1) is ideal for a wide variety of 16-bit MCU embedded applications. The variants with codec interfaces are well-suited for audio applications.

TABLE 1-1: PIC24H GENERAL-PURPOSE FAMILY VARIANTS

PIC24H

(2)

Device Pins

24HJ64GP206 64 64 8 8 9 8 8 0 1 ADC,

24HJ64GP210 100 64 8 8 9 8 8 0 1 ADC,

24HJ64GP506 64 64 8 8 9 8 8 0 1 ADC,

24HJ64GP510 100 64 8 8 9 8 8 0 1 ADC,

24HJ128GP206 64 128 8 8 9 8 8 0 1 ADC,

24HJ128GP210 100 128 8 8 9 8 8 0 1 ADC,

24HJ128GP506 64 128 8 8 9 8 8 0 1 ADC,

24HJ128GP510 100 128 8 8 9 8 8 0 1 ADC,

24HJ128GP306 64 128 16 8 9 8 8 0 1 ADC,

24HJ128GP310 100 128 16 8 9 8 8 0 1 ADC,

24HJ256GP206 64 256 16 8 9 8 8 0 1 ADC,

24HJ256GP210 100 256 16 8 9 8 8 0 1 ADC,

24HJ256GP610 100 256 16 8 9 8 8 0 2 ADC,

Note 1: RAM size is inclusive of 2 KB DMA RAM.

2: Maximum I/O pin count includes pins shared by the peripheral functions.

Program Flash

Memory (KB)

(1)

RAM

(KB)

Interface

18 ch

32 ch

18 ch

32 ch

18 ch

32 ch

18 ch

32 ch

18 ch

32 ch

18 ch

32 ch

ADC

Codec

Timer 16-bit

DMA Channels

Input Capture

Std. PWM

Output Compare

CAN

Packages

I/O Pins (Max)

C™

SPI™

UART

2 2 1 0 53 PT

2 2 2 0 85 PT

222153 PF, PT

222185 PT

2 2 2 0 53 PT

2 2 2 0 85 PF, PT

222153 PT

222185 PT

2 2 2 0 53 PF, PT

2 2 2 0 85 PT

222053 PT

222085 PF, PT

2 2 2 2 85 PF, PT

PIC24H

PRODUCT IDENTIFICATION SYSTEM

24 HJ 256 GP6 10 T I / PT - XXX

PIC

Microchip Trademark Architecture Flash Memory Family

Program Memory Size (KB) Product Group Pin Count Tape and Reel Flag (if applicable) Temperature Range Package Pattern

Architecture 24 = 16-bit Microcontroller

Flash Memory Family HJ = Flash program memory, 3.3V, high-speed

Program Memory Size 64 = 64 Kbytes

Product Group GP2 = General Purpose family

128 = 128 Kbytes 256 = 256 Kbytes

GP3 = Gene ra l Purp ose fami ly GP5 = Gene ra l Purp ose fami ly GP6 = Gene ra l Purp ose fami ly

Examples:

a) dsPIC24HJ64GP610I/PT:

General Purpose dsPIC24H, 64 KB program memory, 100-pin, Industrial temp., TQFP package.

b) dsPIC24HJ64GP206I/PT-ES:

Motor Control dsPIC24H, 64 KB program memory, 64-pin, Industrial temp., TQFP package, Engineering Sample.

Tape & Reel T = Applicable

Pin Count 06 = 64-pin

Temperature Range I = -40°C to +85°C (Industrial)

Package PT = 10x10 or 12x12 mm TQFP (Thin Quad Flatpack)

Pattern Three-digit QTP, SQTP, Code or Special Requirements

Blank = Not applicable

10 = 100-pin

PF = 14x14 mm TQFP (Thin Quad Flatpack)

(blank otherwise) ES = Engineering Sample

PIC24H

2.0 PIC24H DEVICE FAMILY OVERVIEW

The PIC24H device family employs a powerful 16-bit microcontroller (MCU). The res ulti ng CPU fun cti ona lity is ideal for applications that rely on high-speed, repetitive comput at ion s, as well as contro l.

Flexible and deterministic interrupt handling, coupled with a powerful array of peripherals, renders the PIC24H devices suitable for control applications.

FIGURE 2-1: PIC24H DEVICE BLOCK DIAGRAM

X-Data Bus <16-bit>

Shifter

Divide Control

Legend:

MCU/DSP X-Data Path Address Path

17 x 17 Multiplier

W Register

Array

16 x 16

Memory Mapped

16-bit ALU

Program Flash

Memory Data

Access

Program Counter

<23 bits>

Instruction

Prefetch & Decode

STATUS Register

Further, Direct Memory Access (DMA) enables overhead-free transfer of data between several peripherals and a dedicated DMA RAM. Reliable, field programmable Flash program memory ensures scalability of applications that use PIC24H devices.

Figure 2-1 shows a sample device block diagram typical of the PIC24H product family.

Data SRAM

up to

28 Kbytes

Flash

Program

Memory

up to

256 Kbytes

Dual Port

RAM

2 Kbytes

I/O Ports

Peripherals

DMA

Controller

AGU

PIC24H

3.0 CPU ARCHITECTURE

3.1 Overview

The PIC24H C P U mo du l e has a 1 6 -bi t ( data ) mo dif i ed Harvard architecture with an enhanced instruction set. The CPU has a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M x 24 bits of user program memory spac e. The actual amou nt of program memory implemented, as illustrated in Figure 3-1, varies from one device to another. A single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a single cycle, with the exception of instructions that change the program flow, the double word move (MOV.D) instruction and the table instructions. Overhead-free program loop constructs are supported using the REPEAT instruction, which is interruptible at any point.

The PIC24H devices have sixteen 16-bit working registers in the programmer’s model. Each of the working registers can serve as a data, address or address offset register. The 16th working register (W15) operates as a software Stack Pointer (SP) for interrupts and calls.

The PIC24H instruction set includes many addressing modes and is designed for optimum C compiler efficiency.

3.1.1 DATA MEMORY OVERVIEW

The data space can be addressed as 32K words or 64 Kbytes . Reads and w rites are per formed usin g an Address Generation Unit (AGU), which accesses the entire memory map as one linear data space.

PIC24H

3.1.2 ADDRESSING MODES OVERVIEW

The CPU supports Inherent (no operand), Relative, Literal, Memory Direct, Register Direct and Register Indirect Addressing modes. Each instruction is associated with a predefined addressing mode group depending upon its functional requirements. As many as 6 addressing modes are supported for each instruction.

For most instructions, the PIC24H is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three parameter instructions can be supported, allowing A + B = C operations to be executed in a single cycle.

3.1.3 SPECIAL MCU FEATURES

The PIC24H features a 17-bit by 17-bit, single-cycle multiplier. The multiplier can perform signed, unsigned and mixed-sign multiplication. Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication allows you to perform mixed-sign multiplication.

The PIC24H supports 16/16 and 32/16 divide operations, both fractional and integer. All divide instructions are iterative operations. They must be executed within a REPEAT loop, resulting in a total execution time of 19 instruction cycles. The divide operation can be interrupted during any of those 19 cycles without loss of data.

A 40-bit data shifter is used to perform up to a 16-bit left or right shift in a single cycle.

3.1.5 FEATURES TO ENHANCE COMPILER EFFICIENCY

The CPU architecture possesses several features that lead to a more efficient (code size and speed) C compiler.

1. For most instructions, three-parameter instruc-

tions can be supported, allowing A + B = C operations to be executed in a single cycle.

2. Instruction addressing modes are extremely

flexible to meet compiler needs.

3. The working re gister array consis ts of 16 x 16-b it

registers, each of which can act as data, address or offse t registers. One w orking regist er (W15) operates as the software Stack Pointer for interrupts and calls.

4. Linear indirect access of all data space is

possible, plus the memory direct address range is up to 8 Kbytes. This capability, together with the addition of 16-bit direct address MOV-based instructions, has provided a contiguous linear addressing space.

5. Linear indirect access of 32K word (64 Kbyte)

pages within program space is possible, using any working register via new table read and write instructions.

6. Part of dat a sp a ce c an be mapped into program

space, allowi ng const ant dat a to be acc essed as if it were in data space.

3.1.4 INTERRUPT OVER VIE W

The PIC24H has a vectored exception scheme with up to 5 sources of non-maskable traps and 67 interrupt sources. Each interrup t source can be assign ed to one of seven priority levels.

PIC24H

3.2 Programmer’s Model

The programmer’s model, shown in Figure 3-2, consists of 16 x 16-bit working registers (W0 through W15), STATUS reg ister (SR), Dat a Table Page register (TBLPAG), Program Space Visibility Page register (PSVPAG), REPEAT count register (RCOUNT) and Program Counter (PC). The working registers can act as data, addres s or offset registers. A ll registers are memory mapped. W0 is the W register for all instructions that perform file register addressing.

Some of these registers have a shadow register associated with them (see the legend in Figure 3-2). The shadow register is used as a temporary holding register and can tran sfe r it s co ntents to or from its host register upon some event occurring in a single cycle. None of the shadow registers are accessible directly.

When a byte operation is performed on a working register, only the Least Significant Byte (LSB) of the target register is affected. However, a benefit of memory mapped working registers is that both the Least and Most Significant Bytes (MSBs) can be manipulated through byte-wide data memory space accesses.

W15 is the dedicated software Stack Pointer (SP). It is automatically modified by exception processing and subroutine calls and returns. However, W15 can be referenced by any instruction in the same manner as all other W registers. This simplifies the reading, writing and manipulation of the Stack Pointer (e.g., creating stack frames).

W14 has been dedica ted as a Stack Frame Pointer, as defined by the LNK and ULNK instructions. However, W14 can be referenced by any instruction in the same manner as all other W registers.

The Stack Pointer always points to the first available free word and grows from lower addresses towards higher addresses. It pre-decrements for stack pops (reads) and post-increments for stack pushes (writes).

FIGURE 3-2: PROGRAMMER’S MODEL

PIC24H

DIV and MUL Result Registers

015

W0/WREG

W1 W2 W3 W4 W5

W6 W7

W9 W10 W11 W12 W13

W14/Frame Pointer W15*/Stack Pointer

SPLIM* Stack Pointer Limit Register

Legend:

Working Registers

*W15 and SPLIM not shadowed

PUSH.S Shadow

TABPAG

TBLPAG

PSVPAG

— — — —

SRH

— —

Data Table Page Address

Program Space Visibility Page Address

RCOUNT

CORCON

—DC

IPL2 IPL1

IPL0 OV

SRL

Program Counter

REPEAT Loop Counter

Core Configuration Register

STATUS Register

PIC24H

3.3 Data Address Sp ace

The data space is accessed as one unified linear address range (for MCU instructions). The data space is accessed using the Address Generat ion Unit (AG U). All Effective Addre sses (EAs) are 16 b its wide and poi nt to bytes within the data space. Therefore, the data space address range is 64 Kbytes or 32K words, though the implemented memory locations vary from one device to another.

3.3.1 DMA RAM

Every PIC24H device contains 2 Kbytes of DMA RAM located at the end of Y data space. Memo ry locations in the DMA RAM space are accessible simultaneously by the CPU and the DMA Controller module. DMA RAM is utilized by the DMA Controller to store data to be transferred to various peripherals using DMA, as well as data transferred from various peripherals using DMA.

When the CPU and the DMA Controller attempt to concurrently write to the same DMA RAM location, the hardware ensures tha t the C PU is giv en prec edenc e in accessing the DMA RAM location. Therefore, the DMA RAM provides a reliable means of transferring DMA data without ever having to stall the CPU.

3.3.2 DATA SPACE WIDTH

The core data width is 16 bits. All internal registers are organized as 16 -bit wide word s. Dat a space memory is organized in byte addressable, 16-bit wide blocks. Figure 3-3 depicts a sam ple data space memo ry map for the PIC24H device with 16 Kbytes of RAM.

3.3.3 DATA ALIGNMENT

To help maintain backward compatibility with PICmicro memory usage efficiency, the PIC24H instruction set supports both word and byte operations. Data is aligned in data memory and registers as words, but all data space EAs resolv e to byt es. Data b yte rea ds will read the complete word which contains the byte, using the Least Significant bit (LSb) of any EA to determine which byte to select.

As a consequence of t his byte accessib ility , all Effec tive Address calculations are internally scaled. For example, the core would recognize that Post-Modified Register Indi rect Ad dressin g mode, [Ws+ +], wil l result in a value of Ws + 1 for byt e op erations and Ws + 2 for word operations.

All word accesses m ust be al igned to an even a ddress. Misaligned word data fetches are not supported. Should a misaligned read or write be attempted, a trap will then be ex ec ut e d, al l ow in g t he sys tem an d/ o r use r to examine the machine state prior to execution of the address Fault.

MCU devices and improve data space

FIGURE 3-3: SAMPLE DATA SPACE MEMORY MAP

PIC24H

2-Kbyte SFR Space

8-Kbyte Data Space

Most Significant Byte

Address

0x0001

0x07FF

0x0801

0x1FFF 0x1FFE

0x3FFF

0x4001

0x47FF 0x47FE

0x4801 0x4800

16 Bits

LSBMSB

SFR Space

Data RAM

DMA RAM

Unimplemented

Least Significant Byte

Address

0x0000

0x07FE 0x0800

0x3FFE 0x4000

0x8001 0x8000

Optionally Mapped into Program Memory

0xFFFF

Note: This data memory map is for the largest memory PIC24H devic e. Data memory map s for other de vices

may vary.

0xFFFE

PIC24H

4.0 DIRECT MEMORY ACCESS

Direct Memory Access (DMA) is a very efficient mechanism of copying data between peripheral SFRs (e.g., UART Receive register, Input Capture 1 buffer) and buffers or variables stored in RAM with minimal CPU intervention. The DMA Controller can automatically copy entire blocks of data, without the user software havin g to read or w rite peripheral Special Function Registers (SFRs) every time a peripheral interrupt occurs. To exploit the DMA capability, the corresponding user buffers or variables must be located in DMA RAM space.

The DMA Controller features eight identical data transfer channels, each with its own set of control and status registers. The UART, SPI, DCI, Input Capture, Output Compare, ECAN™ technology and ADC modules can utilize DMA. Each DMA channel can be configured to copy data either from buffers stored in DMA RAM to peripheral SFRs o r fro m periph eral SF Rs to buffers in DMA RAM.

Each channel support s the fol low i ng feat ures :

• Word or byte-sized data transfers

• Transfers from peripheral to DMA RAM or DMA RAM to peripheral

• Indirect addressing of DMA RA M loc ation s with or without automatic post-increment

• Peripheral Indirect Addressing – In some peripherals, the DMA RAM read/write addresses may be partially derived from the peripheral

• One-Shot Block Transfers – Terminating DMA transfer after one block transfer

• Continuous Block Transfers – Reloading DMA RAM buffer start address aft er every block transfer is complete

• Ping-Pong Mode – Switching between two DMA RAM start addresses between successive block transfers, thereby filling two buffers alternately

• Automatic or manual initiation of block transfers

• Each channel can select from 32 possible sources of data sources or destinations

For each DMA channel, a DMA interrupt request is generated when a block transfer is complete. Alternatively , an interrupt can be ge nerated when half of the block has been filled. Additionally, a DMA error trap is generated in either of the following Fault conditions:

• DMA RAM data write collision between the CPU and a peripheral

• Peripheral SFR data wri te collision between the CPU and the DMA Controller

FIGURE 4-1: TOP LEVEL SYSTEM ARCHITECTURE USING A DEDICATED TRANSACTION BUS

DMA

Ready

Peripheral 3

DMA

Ready

Peripheral 2

SRAM

SRAM X-Bus

CPU

DMA RAM

PORT 1

PORT 2

CPU Peripheral DS Bus

Non-DMA

Ready

Peripheral

DMA

Ready

Peripheral 1

PIC24H

5.0 EXCEPTION PROCESSING

The PIC24H has four pro cessor ex ception s (trap s) and up to 61 sources o f interrupt s, whi ch must be arbitrate d based on a pr iority sche me.

The processor core is responsible for reading the Interrupt Vector Table (IVT) and transferring the address contained in the interrupt vector to the Program Counter.

The Interrupt Vector Table (IVT) and Alternate In terrupt Vector Table (AIVT) are placed near the beginning of program memory (0x000004) for ease of debugging.

The interrupt controller hardware pre-processes the interrupts before they are presented to the CPU. The interrupts and traps are enabled, prioritized and controlled using centralized Special Function Registers.

Each individual interrupt source has its own vector address and can be individ ually enabled and prioritized in user software. Each interrupt source a lso has it s own status flag. This indepe ndent control and monitoring of the interrupt eliminates the need to poll various status flags to determine the interrupt source

Table 5-1 contains information about the interrupt vector.

Certain interrupts have specialized control bits for features like edge or level triggered interrupts, interrupton-change, etc. Control of these features remains within the peripheral m od ul e, which generates the interr upt.

The special DISI instruction ca n be used to disable the processing of interru pt s of pri orit ies 6 and lowe r for a certain number of instruction cycles, during which the DISI bit remains set.

TABLE 5-1: INTERRUPT VECTORS

Vector

Number

8 0x000014 0x000114 INT0 – External Interrupt 0

9 0x000016 0x000116 IC1 – Input Compare 1 10 0x000018 0x000118 OC1 – Output Compare 1 11 0x00001A 0x00011A T1 – Timer1 12 0x00001C 0x00011C DMA0 – DMA Channel 0 13 0x00001E 0x00011E IC2 – Input Capture 2 14 0x000020 0x000120 OC2 – Output Compare 2 15 0x000022 0x000122 T2 – Timer2 16 0x000024 0x000124 T3 – Timer3 17 0x000026 0x000126 SPI1E – SPI1 Error 18 0x000028 0x000128 SPI1 – SPI1 Transfer Done 19 0x00002A 0x00012A U1RX – UART1 Receiver 20 0x00002C 0x00012C U1TX – UART1 Transmitter 21 0x00002E 0x00012E ADC1 – ADC 1 22 0x000030 0x000130 DMA1 – DMA Channel 1 23 0x000032 0x000132 Reserved 24 0x000034 0x000134 I2C1S – I2C1 Slave Event 25 0x000036 0x000136 I2C1M – I2C1 Master Event 26 0x000038 0x000138 Reserved 27 0x00003A 0x00013A Change Notification Interrupt 28 0x00003C 0x00013C INT1 – External Interrupt 1 29 0x00003E 0x00013E ADC2 – ADC 2 30 0x000040 0x000140 IC7 – Input Capture 7 31 0x000042 0x000142 IC8 – Input Capture 8 32 0x000044 0x000144 DMA2 – DMA Channel 2 33 0x000046 0x000146 OC3 – Output Compare 3 34 0x000048 0x000148 OC4 – Output Compare 4 35 0x00004A 0x00014A T4 – Timer4 36 0x00004C 0x00014C T5 – Timer5 37 0x00004E 0x00014E INT2 – External Interrupt 2 38 0x000050 0x000150 U2RX – UART2 Receiver 39 0x000052 0x000152 U2TX – UART2 Transmitter

IVT Address AIVT Address Interrupt Source

PIC24H

TABLE 5-1: INTERRUPT VECTORS (CONTINUED)

Vector

Number

40 0x000054 0x000154 SPI2E – SPI2 Error 41 0x000056 0x000156 SPI1 – SPI1 Transfer Done 42 0x000058 0x000158 C1RX – ECAN1 Receive Data Ready 43 0x00005A 0x00015A C1 – ECAN1 Event 44 0x00005C 0x00015C DMA3 – DMA Channel 3 45 0x00005E 0x00015E IC3 – Input Capture 3 46 0x000060 0x000160 IC4 – Input Capture 4 47 0x000062 0x000162 IC5 – Input Capture 5 48 0x000064 0x000164 IC6 – Input Capture 6 49 0x000066 0x000166 OC5 – Output Compare 5 50 0x000068 0x000168 OC6 – Output Compare 6 51 0x00006A 0x00016A OC7 – Output Compare 7 52 0x00006C 0x00016C OC8 – Output Compare 8 53 0x00006E 0x00016E Reserved 54 0x000070 0x000170 DMA4 – DMA Channel 4 55 0x000072 0x000172 T6 – Timer6 56 0x000074 0x000174 T7 – Timer7 57 0x000076 0x000176 I2C2S – I2C2 Slave Event 58 0x000078 0x000178 I2C2M – I2C2 Master Event 59 0x00007A 0x00017A T8 – Timer8 60 0x00007C 0x00017C T9 – Timer9 61 0x00007E 0x00017E INT3 – External Interrupt 3 62 0x000080 0x000180 INT4 – External Interrupt 4 63 0x000082 0x000182 C2RX – ECAN2 Receive Data Ready 64 0x000084 0x000184 C2 – ECAN2 Event

65-68 0x000086-0x00008C 0x000186-0x00018C Reserved

69 0x00008E 0x00018E DMA5 – DMA Channel 5

70-72 0x000090-0x000094 0x000190-0x000194 Reserved

73 0x000096 0x000196 U1E – UART1 Error 74 0x000098 0x000198 U2E – UART2 Error 75 0x00009A 0x00019A Reserved 76 0x00009C 0x00019C DMA6 – DMA Channel 6 77 0x00009E 0x00019E DMA7 – DMA Channel 7 78 0x0000A0 0x0001A0 C1TX – ECAN1 Transmit Data Request 79 0x0000A2 0x0001A2 C2TX – ECAN2 Transmit Data Request

80-125 0x0000A4-

IVT Address AIVT Address Interrupt Source

0x0000FE

0x0001A4-

0x0001FE

Reserved

PIC24H

5.1 Interrupt Priority

Each interrupt source can be user-assigned to one of 8 priority levels, 0 through 7. Levels 7 and 1 represent the highest and lowest maskable priorities, respectively. A priority level of 0 disables the interrupt.

Since more than one interrupt request source may be assigned to a user-specified priority level, a means is provided to assign priority within a given level. This method is called “Natural Order Priority”.

The Natural Order Priori ty of an interrup t is nu merica lly identical to its vector number. The Natural Order Priority scheme has 0 as the highe st pri orit y and 74 as the lowest priority.

The ability for the user to assign every interrupt to one of eight priority levels implies that the user can assign a very high overall priority level to an interrupt with a low Natural Order Priority, thereby providing much flexibility in designing applications that use a large number of peripherals.

5.2 Interrupt Nesting

Interrupts, by default, are nestable. Any ISR that is in progress may be interrupted by another source of interrupt with a higher user-assigned priority level. Interrupt nesting may be optionally disabled by setting the NSTDIS control bit (INTCON1<15>). When the NSTDIS control bit is se t, all interrupts in progress will force the CPU priority to level 7 by setting IPL<2:0> = 111. This action will effectively mask all other sources of interrupt until a RETFIE instruction is executed. When interrupt nesting is disabled, the user-assigned in terrupt priority levels will have no effect, except to resolve conflicts between simultaneous pending interrupts.

The IPL<2:0> bits become read-only when interrupt nesting is disabled. This prevents the user software from settin g IPL<2:0> to a lower va lue, which would effectively re-enable interrupt nesting.

5.3 Traps

Traps can be considered as non-maskable, nestable interrupts that adhere to a fixed priority structure. Traps are intended to provide the user a means to correct erroneous operation during debug and when operating within the application. If the user does not intend to ta ke corrective ac tion in the even t of a trap error condition, these vectors must be loaded with the address of a software routi ne th at w il l reset the device. Otherwise, the trap vector is programmed with the address of a service routine that will correct the trap condition.

The PIC24H has five implemented sources of non-maskable traps:

• Oscillator Failure Trap

• Address Error Trap

• Stack Error Trap

• Math Error Trap

• DMA Error Trap Many of these trap conditions can only be detected

when they happen. Consequently, the instruction that caused the trap is allowed to complete before exception processing begins. Therefore, the user may have to correct the action of the instruction that caused the trap.

Each trap s ource h as a fixe d priori ty as de fined by its position in the IVT. An oscillator failure trap has the highest priority, while an arithmetic error trap has the lowest priority.

Table 5-2 contains information about the trap vector.

5.4 Generating a Software Interrupt

Any available interrupt can be manually generated by user software (even if the corresponding peripheral is disabled), simply by enabling the interrupt and then setting the interrupt flag bit when required.

TABLE 5-2: TRAP VECTORS

Vector Number IVT Address AIVT Address Trap Source

0 0x000004 0x000084 Reserved 1 0x000006 0x000086 Oscillator Failure 2 0x000008 0x000088 Address Error 3 0x0 000 0A 0x00008A Stack Error 4 0x00000C 0x00008C Math Error 5 0x00000E 0x00008E DMA Error Trap 6 0x000010 0x000090 Reserved 7 0x000012 0x000092 Reserved

PIC24H

6.0 SYSTEM INTEGRATION

System managemen t servic es provided by the PI C24H device family include:

• Control of clock options and oscillators

• Power-on Reset

• Oscillator Start-up Timer/Stabilizer

• Watchdog Timer with RC oscillator

• Fail-Safe Clock Monitor

• Reset by multiple sources

6.1 Clock Options and Oscillators

There are 7 clock options provided by the PIC24H:

• FRC Oscillator

• FRC Oscillator with PLL

• Primary (XT, HS or EC) Oscillator

• Primary Oscillator with PLL

• Secondary (LP) Oscillator

• LPRC Oscillator The FRC (Fast RC) inte rnal osci llator runs at a nom inal

frequency of 7.37 MHz. The user s oftware can tune th e FRC frequency. User software can specify a factor by which this clock frequency is scaled.

The primary oscillator can use one of the following as its clock source:

1. XT (Cryst al): Cryst als and c eramic re sonators i n the range of 3 MHz to 10 MHz. The crystal is connected to the OSC1 and OSC2 pins.

2. HS (High-Speed Crystal): Crystals in the range of 10 MHz to 40 MHz. The crysta l is conn ected to the OSC1 and OSC2 pins.

3. EC (External Clock): External clock signal in the range of 0.8 MHz to 64 MHz. The extern al cloc k signal is directly applied to the OSC1 pin.

The secondary (LP) os cillator is design ed for low power and uses a 32 kHz cryst al or ceramic resonator . The LP oscillator uses the SOSCI and SOSCO pins.

The LPRC (Low-Power RC) internal oscIllator runs at a nominal frequency of 32.768 kHz. Another scaled reference clock is used by the Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM).

The clock signals generated by the FRC and primary oscillators can be optionally applied to an on-chip Phase Locked Loop (PLL) to provide a wide range of output frequencies for device operation. The input to the PLL can be in the range of 1.6 MH z to 16 MHz, and the PLL Phase Detector Input Divider, PLL Multiplier Ratio and PLL Voltage Controlled Osc illato r (VCO) ca n be individually conf igured b y user so ftware to genera te output frequencies in the range of 25 MHz to 160 MHz.

The output of the oscillator (or the output of the PLL if a PLL mode has been selected) is divided by 2 to generate the device instruction clock (F

CY). FCY

defines the operating speed of the device, and speeds up to 40 MHz are supported by the PIC24H architecture.

The PIC24H oscillator system provides:

• Various external and internal oscillator options as clock sources

• An on-chip PLL to scale the internal operating frequency to the required system clock frequency

• The internal FRC oscillator can also be used with the PLL, thereby allowing full-speed operation without any external clock generation hardware

• Clock switching between various clock sources

• Programmable clock postscaler f or s ystem po w er savings

• A Fail-Safe Clock Monitor (FSCM) that detects clock failure and takes fail-safe measures

• A Clock Control register (OSCCON)

• Nonvolatile Configuration bits for main oscillator selection.

A simplified block diagram of the oscillator system is shown in Figure 6-1.

+ 40 hidden pages

MICROCHIP PIC24H Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

PIC24H

1.0 PIC24H PRODUCT FAMILIES

1.1 General-Purpose Family

TABLE 1-1: PIC24H GENERAL-PURPOSE FAMILY VARIANTS

2: Maximum I/O pin count includes pins shared by the peripheral functions.

2.0 PIC24H DEVICE FAMILY OVERVIEW

FIGURE 2-1: PIC24H DEVICE BLOCK DIAGRAM

3.0 CPU ARCHITECTURE

3.1 Overview

3.1.1 DATA MEMORY OVERVIEW

3.1.2 ADDRESSING MODES OVERVIEW

3.1.3 SPECIAL MCU FEATURES

3.1.5 FEATURES TO ENHANCE COMPILER EFFICIENCY

3.1.4 INTERRUPT OVER VIE W

3.2 Programmer’s Model

FIGURE 3-2: PROGRAMMER’S MODEL

3.3 Data Address Sp ace

3.3.1 DMA RAM

3.3.2 DATA SPACE WIDTH

3.3.3 DATA ALIGNMENT

FIGURE 3-3: SAMPLE DATA SPACE MEMORY MAP

4.0 DIRECT MEMORY ACCESS

5.0 EXCEPTION PROCESSING

5.1 Interrupt Priority

5.2 Interrupt Nesting

5.3 Traps

5.4 Generating a Software Interrupt

TABLE 5-2: TRAP VECTORS

6.0 SYSTEM INTEGRATION

6.1 Clock Options and Oscillators