MICROCHIP PIC24H DATA SHEET

PIC24H Family

Data Sheet

High-Performance, 16-bit

Microcontrollers

© 2006 Microchip Technology Inc. Advance Information DS70175A

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WAR­RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and
its use. Use of Microchip devices in life support and/or safety
applications is entirely at the buyer’s risk, and the buyer agrees
to defend, indemnify and hold harmless Microchip from any and
all damages, claims, suits, or expenses resulting from such
use. No licenses are conveyed, implicitly or otherwise, under
any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K

EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Linear Active Thermistor,
MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM,
PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo,
PowerMate, PowerTool, Real ICE, rfLAB, rfPICDEM, Select
Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,
WiperLock and Zena are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2006, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

®

8-bit MCUs, KEELOQ

®

code hopping

DS70175A-page ii Advance Information © 2006 Microchip Technology Inc.

PIC24H

High-Performance, 16-bit Microcontrollers

Operating Range

• DC – 40 MIPS (40 MIPS @ 3.0-3.6V,

-40°C to +85°C)

• Industrial temperature range (-40°C to +85°C)

High-Performance DSC CPU

• Modified Harvard architecture

• C compiler optimized instruction set

• 16-bit wide data path

• 24-bit wide instructions

• Linear program memory addressing up to 4M

instruction words

• Linear data memory addressing up to 64 Kbytes

• 72 base instructions: mostly 1 word/1 cycle

• Sixteen 16-bit General Purpose Registers

• Flexible and powerful Indirect Addressing modes

• Software stack

• 16 x 16 multiply operations

• 32/16 and 16/16 divide operations

• Up to ±16-bit data shifts

Direct Memory Access (DMA)

• 8-channel hardware DMA:

• 2 Kbytes dual ported DMA buffer area

(DMA RAM) to store data transferred via DMA:

- Allows data transfer between RAM and a
peripheral while CPU is executing code
(no cycle stealing)

• Most peripherals support DMA

Interrupt Controller

• 5-cycle latency

• 118 interrupt vectors

• Up to 61 available interrupt sources:

• Up to 5 external interrupts

• 7 programmable priority levels

• 5 processor exceptions

On-Chip Flash and SRAM

• Flash program memory, up to 256 Kbytes

• Data SRAM, up to 16 Kbytes (includes 2 Kbytes
of DMA RAM):

System Management

• Flexible clock options:

- External, crystal, resonator, internal RC

- Fully integrated PLL

- Extremely low jitter PLL

• Power-up Timer

• Oscillator Start-up Timer/Stabilizer

• Watchdog Timer with its own RC oscillator

• Fail-Safe Clock Monitor

• Reset by multiple sources

Power Management

• On-chip 2.5V voltage regulator

• Switch between clock sources in real time

• Idle, Sleep and Doze modes with fast wake-up

Timers/Capture/Compare/PWM

• Timer/Counters, up to nine 16-bit timers:

- Can pair up to make four 32-bit timers

- 1 timer runs as Real-Time Clock with external

32.768 kHz oscillator

- Programmable prescaler

• Input Capture (up to 8 channels):

- Capture on up, down or both edges

- 16-bit capture input functions

- 4-deep FIFO on each capture

• Output Compare (up to 8 channels):

- Single or Dual 16-Bit Compare mode

- 16-bit Glitchless PWM mode

Digital I/O

• Up to 85 programmable digital I/O pins

• Wake-up/Interrupt-on-Change on up to 24 pins

• Output pins can drive from 3.0V to 3.6V

• All digital input pins are 5V tolerant

• 4 mA sink on all I/O pins

© 2006 Microchip Technology Inc. Advance Information DS70175A-page 1

PIC24H

Communication Modules

• 3-wire SPI (up to 2 modules):

- Framing supports I/O interface to simple
codecs

- Supports 8-bit and 16-bit data

- Supports all serial clock formats and
sampling modes

2

•I

C™ (up to 2 modules):

- Full Multi-Master Slave mode support

- 7-bit and 10-bit addressing

- Bus collision detection and arbitration

- Integrated signal conditioning

- Slave address masking

• UART (up to 2 modules):

- Interrupt on address bit detect

- Interrupt on UART error

- Wake-up on Start bit from Sleep mode

- 4-character TX and RX FIFO buffers

- LIN bus support

®

-IrDA

- High-Speed Baud mode

- Hardware Flow Control with CTS and RTS

• Enhanced CAN (ECAN™) 2.0B active
(up to 2 modules):

- Up to 8 transmit and up to 32 receive buffers

- 16 receive filters and 3 masks

- Loopback, Listen Only and Listen All

- Wake-up on CAN message

- Automatic processing of Remote

- FIFO mode using DMA

encoding and decoding in hardware

Messages modes for diagnostics and bus
monitoring

Transmission Requests

Analog-to-Digital Converters

• Up to two A/D modules in a device

• 10-bit, 2.2 Msps or 12-bit, 1 Msps conversion:

- 2, 4 or 8 simultaneous samples

- Up to 32 input channels with auto-scanning

- Conversion start can be manual or
synchronized with 1 of 4 trigger sources

- Conversion possible in Sleep mode

- ±1 LSB max integral nonlinearity

- ±1 LSB max differential nonlinearity

CMOS Flash Technology

• Low-power, high-speed Flash technology

• Fully static design

• 3.3V (±10%) operating voltage

• Industrial temperature

• Low-power consumption

Packaging:

• 100-pin TQFP (14x14x1 mm and 12x12x1 mm):

• 64-pin TQFP (10x10x1 mm)

Note: See the device variant tables for exact

peripheral features per device.

DS70175A-page 2 Advance Information © 2006 Microchip Technology Inc.

PIC24H PRODUCT FAMILIES

The PIC24H General Purpose Family is ideal for a wide
variety of 16-bit MCU embedded applications. The
device names, pin counts, memory sizes and periph­eral availability of each family are listed below, followed
by their pinout diagrams.

PIC24H General Purpose Family Variants

Program

Device Pins

PIC24HJ64GP206 64 64 8 8 9 8 8 0 1 ADC,

PIC24HJ64GP210 100 64 8 8 9 8 8 0 1 ADC,

PIC24HJ64GP506 64 64 8 8 9 8 8 0 1 ADC,

PIC24HJ64GP510 100 64 8 8 9 8 8 0 1 ADC,

PIC24HJ128GP206 64 128 8 8 9 8 8 0 1 ADC,

PIC24HJ128GP210 100 128 8 8 9 8 8 0 1 ADC,

PIC24HJ128GP506 64 128 8 8 9 8 8 0 1 ADC,

PIC24HJ128GP510 100 128 8 8 9 8 8 0 1 ADC,

PIC24HJ128GP306 64 128 16 8 9 8 8 0 1 ADC,

PIC24HJ128GP310 100 128 16 8 9 8 8 0 1 ADC,

PIC24HJ256GP206 64 256 16 8 9 8 8 0 1 ADC,

PIC24HJ256GP210 100 256 16 8 9 8 8 0 1 ADC,

PIC24HJ256GP610 100 256 16 8 9 8 8 0 2 ADC,

Note 1: RAM size is inclusive of 2 Kbytes DMA RAM.

2: Maximum I/O pin count includes pins shared by the peripheral functions.

Flash

Memory (KB)

(KB)

(1)

RAM

Codec

Interface

Timer 16-bit

DMA Channels

Std. PWM

Input Capture

Output Compare

18 ch

32 ch

18 ch

32 ch

18 ch

32 ch

18 ch

32 ch

18 ch

32 ch

18 ch

32 ch

32 ch

PIC24H

(2)

C™

SPI

2

ADC

UART

2 2 1 0 53 PT

2 2 2 0 85 PF, PT

222 153 PT

222 185 PF, PT

2 2 2 0 53 PT

2 2 2 0 85 PF, PT

222 153 PT

222 185 PF, PT

2 2 2 0 53 PT

2 2 2 0 85 PF, PT

222 053 PT

222 085 PF, PT

2 2 2 2 85 PF, PT

CAN

I

I/O Pins (Max)

Packages

© 2006 Microchip Technology Inc. Advance Information DS70175A-page 3

PIC24H

Pin Diagrams

64-Pin TQFP

DDCORE

RG13

RG12

RG14

RG1

RF1

RG0

OC8/CN16/RD7

V

VDD

RF0

OC7/CN15/RD6

OC6/IC6/CN14/RD5

OC5/IC5/CN13/RD4

OC4/RD3

OC3/RD2

OC2/RD1

AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2

SDO2/CN10/RG8

/T5CK/CN11/RG9

SS2

AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4

PGC3/EMUC3/AN1/V

PGD3/EMUD3/AN0/V

AN2/SS1

RG15

SCK2/CN8/RG6

SDI2/CN9/RG7

MCLR

VSS
VDD

AN3/CN5/RB3

/CN4/RB2

REF-/CN3/RB1

REF+/CN2/RB0

646362616059585756

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

PIC24HJ64GP206
PIC24HJ128GP206
PIC24HJ256GP206

171819202122232425

DD

AVSS

AV

U2CTS/AN8/RB8

PGD1/EMUD1/AN7/RB7

PGC1/EMUC1/AN6/OCFA/RB6

AN9/RB9

545352

55

27

26

SS

V

VDD

TDO/AN11/RB11

TMS/AN10/RB10

TCK/AN12/RB12

504951

48

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14

47

PGD2/EMUD2/SOSCI/T4CK/CN1/RC13

46

OC1/RD0
IC4/INT4/RD11

45
44

IC3/INT3/RD10
IC2/U1CTS/INT2/RD9

43

IC1/INT1/RD8

42

V

41

SS

40

OSC2/CLKO/RC15

39

OSC1/CLKIN/RC12

38

V

DD

37

SCL1/RG2

36

SDA1/RG3

35

U1RTS/SCK1/INT0/RF6

34

U1RX/SDI1/RF2

33

U1TX/SDO1/RF3

32

31

30

29

28

TDI/AN13/RB13

U2TX/CN18/RF5

U2RX/CN17/RF4

U2RTS/AN14/RB14

AN15/OCFB/CN12/RB15

Note: The PIC24HJ64GP206 device does not have the SCL2 and SDA2 pins.

DS70175A-page 4 Advance Information © 2006 Microchip Technology Inc.

Pin Diagrams (Continued)

64-Pin TQFP

PIC24H

DDCORE

RG13

RG12

RG14

RG1

RF1

RG0

OC8/CN16/RD7

V

VDD

RF0

OC7/CN15/RD6

OC6/IC6/CN14/RD5

OC5/IC5/CN13/RD4

OC4/RD3

OC3/RD2

OC2/RD1

AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2

SDO2/CN10/RG8

/T5CK/CN11/RG9

SS2

AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4

PGC3/EMUC3/AN1/V

PGD3/EMUD3/AN0/V

AN2/SS1

RG15

SCK2/CN8/RG6

SDI2/CN9/RG7

MCLR

VSS

VDD

AN3/CN5/RB3

/CN4/RB2

REF-/CN3/RB1

REF+/CN2/RB0

646362616059585756

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

PIC24HJ128GP306

171819202122232425

DD

AVSS

AV

U2CTS/AN8/RB8

PGD1/EMUD1/AN7/RB7

PGC1/EMUC1/AN6/OCFA/RB6

AN9/RB9

545352

55

27

26

SS

V

VDD

TDO/AN11/RB11

TMS/AN10/RB10

TCK/AN12/RB12

504951

48

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14

47

PGD2/EMUD2/SOSCI/T4CK/CN1/RC13

46

OC1/RD0
IC4/INT4/RD11

45
44

IC3/INT3/RD10
IC2/U1CTS/INT2/RD9

43

IC1/INT1/RD8

42

V

41

SS

40

OSC2/CLKO/RC15

39

OSC1/CLKIN/RC12

38

V

DD

37

SCL1/RG2

36

SDA1/RG3

35

U1RTS/SCK1/INT0/RF6

34

U1RX/SDI1/RF2

33

U1TX/SDO1/RF3

32

31

30

29

28

TDI/AN13/RB13

U2RTS/AN14/RB14

U2TX/SCL2/CN18/RF5

U2RX/SDA2/CN17/RF4

AN15/OCFB/CN12/RB15

© 2006 Microchip Technology Inc. Advance Information DS70175A-page 5

PIC24H

Pin Diagrams (Continued)

64-Pin TQFP

DDCORE

CSDO/RG13

CSDI/RG12

CSCK/RG14

RG1

C1TX/RF1

RG0

OC8/CN16/RD7

V

VDD

C1RX/RF0

OC7/CN15/RD6

OC6/IC6/CN14/RD5

OC5/IC5/CN13/RD4

OC4/RD3

OC3/RD2

OC2/RD1

AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2

SDO2/CN10/RG8

/T5CK/CN11/RG9

SS2

AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4

PGC3/EMUC3/AN1/V

PGD3/EMUD3/AN0/V

AN2/SS1

COFS/RG15

SCK2/CN8/RG6

SDI2/CN9/RG7

MCLR

VSS

VDD

AN3/CN5/RB3

/CN4/RB2

REF-/CN3/RB1

REF+/CN2/RB0

646362616059585756

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

PIC24HJ64GP506
PIC24HJ128GP506

171819202122232425

DD

AVSS

AV

U2CTS/AN8/RB8

PGD1/EMUD1/AN7/RB7

PGC1/EMUC1/AN6/OCFA/RB6

AN9/RB9

545352

55

27

26

SS

V

VDD

TDO/AN11/RB11

TMS/AN10/RB10

TCK/AN12/RB12

504951

48

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14

47

PGD2/EMUD2/SOSCI/T4CK/CN1/RC13

46

OC1/RD0

45

IC4/INT4/RD11

44

IC3/INT3/RD10

43

IC2/U1CTS/INT2/RD9

42

IC1/INT1/RD8

41

V

SS

40

OSC2/CLKO/RC15

39

OSC1/CLKIN/RC12

38

V

DD

37

SCL1/RG2

36

SDA1/RG3

35

U1RTS/SCK1/INT0/RF6

34

U1RX/SDI1/RF2

33

U1TX/SDO1/RF3

32

31

30

29

28

TDI/AN13/RB13

U2RTS/AN14/RB14

U2TX/SCL2/CN18/RF5

U2RX/SDA2/CN17/RF4

AN15/OCFB/CN12/RB15

DS70175A-page 6 Advance Information © 2006 Microchip Technology Inc.

Pin Diagrams (Continued)

100-Pin TQFP

AN28/RE4

AN27/RE3

99

100

RG15

AN29/RE5

AN30/RE6

AN16/T2CK/T7CK/RC1

AN17/T3CK/T6CK/RC2

AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4

PGC3/EMUC3/AN1/CN3/RB1

PGD3/EMUD3/AN0/CN2/RB0

AN31/RE7

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

SS2/CN11/RG9

TMS/RA0

AN20/INT1/RE8
AN21/INT2/RE9

AN5/CN7/RB5
AN4/CN6/RB4

AN3/CN5/RB3

/CN4/RB2

AN2/SS1

1

V

2

DD

3

4

5

6

7

8

9

10

11

12

13

14

V

SS

15

V

DD

16

17

18

19

20

21

22

23
24

25

AN26/RE2

PIC24H

DDCORE

AN23/CN23/RA7

RG13

RG12

RG14

95

969897

AN22/CN22/RA6

AN25/RE1

AN24/RE0

RG0

9294939190898887868584838281807978

DD

RF0

V

RG1

RF1

PIC24HJ64GP210
PIC24HJ128GP210
PIC24HJ128GP310
PIC24HJ256GP210

OC6/CN14/RD5

OC5/CN13/RD4

IC6/CN19/RD13

IC5/RD12

OC4/RD3

OC3/RD2

V

OC8/CN16/RD7

OC7/CN15/RD6

OC2/RD1

76

77

V

SS

75

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14

74

PGD2/EMUD2/SOSCI/CN1 /RC13

73

OC1/RD0

72

IC4/RD11

71

IC3/RD10

70

IC2/RD9

69

IC1/RD8

68

INT4/RA15

67

INT3/RA14

66

V

SS

65

OSC2/CLKO/RC15

64

OSC1/CLKIN/RC12

63

DD

V

62

TDO/RA5

61

TDI/RA4

60

SDA2/RA3

59

SCL2/RA2

58

SCL1/RG2

57

SDA1/RG3

56

SCK1/INT0/RF6

55

SDI1/RF7

54

SDO1/RF8

53

U1RX/RF2

52

U1TX/RF3

51

26

2829303132333435363738

27

SS

DD

AV

AV

-/RA9
+/RA10

REF

V

PGD1/EMUD1/AN7/RB7

PGC1/EMUC1/AN6/OCFA/RB6

AN8/RB8

REF

V

AN9/RB9

AN10/RB10

41

40

39

SS

DD

V

V

TCK/RA1

AN11/RB11

AN12/RB12

U2RTS/RF13

U2CTS/RF12

42

AN13/RB13

43

AN14/RB14

44

AN15/OCFB/CN12/RB15

45

4647484950

SS

DD

V

V

IC7/U1CTS/CN20/RD14

U2TX/CN18/RF5

U2RX/CN17/RF4

IC8/U1RTS/CN21/RD15

© 2006 Microchip Technology Inc. Advance Information DS70175A-page 7

PIC24H

Pin Diagrams (Continued)

100-Pin TQFP

AN28/RE4

AN27/RE3

99

100

RG15

AN29/RE5
AN30/RE6
AN31/RE7

AN16/T2CK/T7CK/RC1

AN17/T3CK/T6CK/RC2

AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

SS2/CN11/RG9

TMS/RA0

AN20/INT1/RE8
AN21/INT2/RE9

AN5/CN7/RB5

AN4/CN6/RB4

AN3/CN5/RB3

/CN4/RB2

AN2/SS1

PGC3/EMUC3/AN1/CN3/RB1

PGD3/EMUD3/AN0/CN2/RB0

1

2

DD

V

3

4

5

6

7

8
9

10

11

12

13

14

SS

V

15

16

DD

V

17

18

19

20

21

22

23

24

25

AN26/RE2

RG1

DD

C1RX/RF0

C1TX/RF1

V

AN23/CN23/RA7

RG13

RG12

RG14

95

969897

AN22/CN22/RA6

AN25/RE1

AN24/RE0

RG0

929493

91908988878685848382818079

PIC24HJ64GP510

PIC24HJ128GP510

OC6/CN14/RD5

OC5/CN13/RD4

IC6/CN19/RD13

IC5/RD12

OC4/RD3

OC3/RD2

V

OC8/CN16/RD7

OC7/CN15/RD6

OC2/RD1

78

76

77

75

V

SS

PGC2/EMUC2/SOSCO/T1CK/CN0/ RC14

74

73

PGD2/EMUD2/SOSCI/CN1/RC13
OC1/RD0

72

IC4/RD11

71

IC3/RD10

70

IC2/RD9

69

IC1/RD8

68

INT4/RA15

67

66

INT3/RA14

V

SS

65

OSC2/CLKO/RC15

64

OSC1/CLKIN/RC12

63

DD

V

62

TDO/RA5

61

TDI/RA4

60

SDA2/RA3

59

SCL2/RA2

58

SCL1/RG2

57

SDA1/RG3

56

SCK1/INT0/RF6

55

SDI1/RF7

54

SDO1/RF8

53

U1RX/RF2

52

51

U1TX/RF3

DDCORE

26

2829303132333435363738

27

SS

DD

AV

AV

-/RA9
+/RA10

REF

V

PGD1/EMUD1/AN7/RB7

PGC1/EMUC1/AN6/OCFA/RB6

AN8/RB8

REF

V

AN9/RB9

AN10/RB10

41

40

39

SS

DD

V

V

TCK/RA1

AN11/RB11

AN12/RB12

U2RTS/RF13

U2CTS/RF12

42

AN13/RB13

43

AN14/RB14

44

AN15/OCFB/CN12/RB15

45

4647484950

SS

DD

V

V

IC7/U1CTS/CN20/RD14

U2TX/CN18/RF5

U2RX/CN17/RF4

IC8/U1RTS/CN21/RD15

DS70175A-page 8 Advance Information © 2006 Microchip Technology Inc.

Pin Diagrams (Continued)

100-Pin TQFP

AN28/RE4

AN27/RE3

99

100

RG15

AN29/RE5

AN30/RE6

AN16/T2CK/T7CK/RC1

AN17/T3CK/T6CK/RC2

AN18/T4CK/T9CK/RC3

AN19/T5CK/T8CK/RC4

PGC3/EMUC3/AN1/CN3/RB1

PGD3/EMUD3/AN0/CN2/RB0

AN31/RE7

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

SS2/CN11/RG9

TMS/RA0

AN20/INT1/RE8
AN21/INT2/RE9

AN5/CN7/RB5
AN4/CN6/RB4

AN3/CN5/RB3

AN2/SS1

/CN4/RB2

1

DD

V

2

3

4

5

6

7

8

9

10

11

12

13

14

V

SS

15

V

DD

16

17

18

19

20

21

22

23

24

25

AN26/RE2

PIC24H

DDCORE

C2TX/RG1

DD

C1RX/RF0

V

C1TX/RF1

AN23/CN23/RA7

RG13

RG12

RG14

95

969897

AN22/CN22/RA6

AN25/RE1

AN24/RE0

C2RX/RG0

9294939190898887868584838281807978

PIC24HJ256GP610

OC6/CN14/RD5

OC5/CN13/RD4

IC6/CN19/RD13

IC5/RD12

OC4/RD3

OC3/RD2

V

OC8/CN16/RD7

OC7/CN15/RD6

OC2/RD1

76

77

75

V

SS

74

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
PGD2/EMUD2/SOSCI/CN1/RC13

73

OC1/RD0

72

IC4/RD11

71

IC3/RD10

70

IC2/RD9

69

68

IC1/RD8
INT4/RA15

67

66

INT3/RA14

V

SS

65

OSC2/CLKO/RC15

64

OSC1/CLKIN/RC12

63

V

DD

62

61

TDO/RA5

TDI/RA4

60

SDA2/RA3

59

SCL2/RA2

58

SCL1/RG2

57

SDA1/RG3

56

SCK1/INT0/RF6

55

SDI1/RF7

54

SDO1/RF8

53

U1RX/RF2

52

51

U1TX/RF3

26

2829303132333435363738

27

SS

DD

AV

AV

-/RA9
+/RA10

REF

V

PGD1/EMUD1/AN7/RB7

PGC1/EMUC1/AN6/OCFA/RB6

AN8/RB8

REF

V

AN9/RB9

41

40

39

SS

DD

V

V

TCK/RA1

AN11/RB11

AN10/RB10

AN12/RB12

U2RTS/RF13

U2CTS/RF12

45

44

43

42

AN13/RB13

AN14/RB14

4647484950

SS

DD

V

V

AN15/OCFB/CN12/RB15

U2TX/CN18/RF5

U2RX/CN17/RF4

IC8/U1RTS/ CN21/ RD15

IC7/U1CTS/CN20/RD14

© 2006 Microchip Technology Inc. Advance Information DS70175A-page 9

PIC24H

Table of Contents

1.0 Device Overview ........................................................................................................................................................................ 13

2.0 CPU............................................................................................................................................................................................ 17

3.0 Memory Organization ................................................................................................................................................................. 25

4.0 Flash Program Memory .............................................................................................................................................................. 55

5.0 Resets ....................................................................................................................................................................................... 61

6.0 Interrupt Controller ..................................................................................................................................................................... 65

7.0 Direct Memory Access (DMA) .................................................................................................................................................. 109

8.0 Oscillator Configuration............................................................................................................................................................ 123

9.0 Power-Saving Features............................................................................................................................................................ 131

10.0 I/O Ports ................................................................................................................................................................................... 133

11.0 Timer1 ...................................................................................................................................................................................... 135

12.0 Timer2/3, Timer4/5, Timer6/7 and Timer8/9 ............................................................................................................................ 137

13.0 Input Capture............................................................................................................................................................................ 143

14.0 Output Compare....................................................................................................................................................................... 145

15.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 149

16.0 Inter-Integrated Circuit (I

17.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 167

18.0 Enhanced CAN Module ............................................................................................................................................................ 175

19.0 10-bit/12-bit A/D Converter....................................................................................................................................................... 205

20.0 Special Features ...................................................................................................................................................................... 217

21.0 Instruction Set Summary .......................................................................................................................................................... 223

22.0 Development Support............................................................................................................................................................... 231

23.0 Electrical Characteristics .......................................................................................................................................................... 235

24.0 Packaging Information.............................................................................................................................................................. 269

Appendix A: Revision History............................................................................................................................................................. 273

Index ................................................................................................................................................................................................. 275

The Microchip Web Site..................................................................................................................................................................... 279

Customer Change Notification Service .............................................................................................................................................. 279

Customer Support .............................................................................................................................................................................. 279

Reader Response .............................................................................................................................................................................. 280

Product Identification System............................................................................................................................................................. 281

2

C) ..................................................................................................................................................... 157

DS70175A-page 10 Advance Information © 2006 Microchip Technology Inc.

PIC24H

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at [e-mail] or fax the Reader Response Form in the back of this data sheet to [phone]. We
welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

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© 2006 Microchip Technology Inc. Advance Information DS70175A-page 11

PIC24H

NOTES:

DS70175A-page 12 Advance Information © 2006 Microchip Technology Inc.

PIC24H

1.0 DEVICE OVERVIEW

Note: This data sheet summarizes the features

of this group of PIC24H devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “dsPIC30F
Family Reference Manual” (DS70046).

This document contains device specific information for
the following devices:

• PIC24HJ64GP206

• PIC24HJ64GP210

• PIC24HJ64GP506

• PIC24HJ64GP510

• PIC24HJ128GP206

• PIC24HJ128GP210

• PIC24HJ128GP506

• PIC24HJ128GP510

• PIC24HJ128GP306

• PIC24HJ128GP310

• PIC24HJ256GP206

• PIC24HJ256GP210

• PIC24HJ256GP610

The PIC24H device family includes devices with differ­ent pin counts (64 and 100 pins), different program
memory sizes (64 Kbytes, 128 Kbytes and 256 Kbytes)
and different RAM sizes (8 Kbytes and 16 Kbytes).

This makes these families suitable for a wide variety of
high-performance digital signal control application. The
devices are pin compatible with the PIC24H family of
devices, and also share a very high degree of compat­ibility with the dsPIC30F family devices. This allows
easy migration between device families as may be
necessitated by the specific functionality, computa­tional resource and system cost requirements of the
application.

The PIC24H device family employs a powerful 16-bit
architecture, ideal for applications that rely on
high-speed, repetitive computations, as well as control.

The 17 x 17 multiplier, hardware support for division
operations, multi-bit data shifter, a large array of 16-bit
working registers and a wide variety of data addressing
modes, together provide the PIC24H Central
Processing Unit (CPU) with extensive mathematical
processing capability. Flexible and deterministic
interrupt handling, coupled with a powerful array of
peripherals, renders the PIC24H devices suitable for

control applications. Further, Direct Memory Access
(DMA) enables overhead-free transfer of data between
several peripherals and a dedicated DMA RAM.
Reliable, field programmable Flash program memory
ensures scalability of applications that use PIC24H
devices.

Figure 1-1 shows a general block diagram of the
various core and peripheral modules in the PIC24H
family of devices, while Table 1-1 lists the functions of
the various pins shown in the pinout diagrams.

© 2006 Microchip Technology Inc. Advance Information DS70175A-page 13

PIC24H

FIGURE 1-1: PIC24H GENERAL BLOCK DIAGRAM

PSV & Table
Data Access

Control Block

23

Address Latch

Program Memory

Data Latch

OSC2/CLKO

OSC1/CLKI

Interrupt

Controller

23

Timing

Generation

FRC/LPRC

Oscillators

Precision
Band Gap
Reference

Voltag e

Regulator

23

Control

Address Bus

Control Signals
to Various Blocks

8

PCH PCL

PCU
Program Counter

Stack

Logic

Loop

Control

Logic

24

Instruction

Decode &

Control

Power-up

Time r

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Time r

Brown-out

Reset

16

Data Bus

16

Data Latch

X RAM

Address

Latch

16

Address Generator Units

ROM Latch

Instruction Reg

17 x 17 Multiplier

Divide Support

16

W Register Array

EA MUX

16

Literal Data

16 x 16

16-bit ALU

Controller

16

16

DMA

RAM

DMA

16

16

16

PORTA

PORTB

PORTC

PORTD

PORTE

PORTF

PORTG

VDDCORE/VCAP

Timers

1-9

IC1-8

DD, VSS

V

ADC1,2

PWM1-8

OC/

MCLR

ECAN1,2

CN1-23

UART1,2

SPI1,2

I2C1,2

Note: Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins

and features present on each device.

DS70175A-page 14 Advance Information © 2006 Microchip Technology Inc.

TABLE 1-1: PINOUT I/O DESCRIPTIONS

Pin Name

AN0-AN31 I Analog Analog input channels.

AV

DD P P Positive supply for analog modules.

SS P P Ground reference for analog modules.

AV

CLKI
CLKO

CN0-CN23 I ST Input change notification inputs.

C1RX
C1TX
C2RX
C2TX

PGD1/EMUD1
PGC1/EMUC1
PGD2/EMUD2
PGC2/EMUC2
PGD3/EMUD3
PGC3/EMUC3

IC1-IC8 I ST Capture inputs 1 through 8.

INT0
INT1
INT2
INT3
INT4

MCLR

OCFA
OCFB
OC1-OC8

OSC1
OSC2

RA0-RA7
RA9-RA10
RA12-RA15

RB0-RB15 I/O ST PORTB is a bidirectional I/O port.

RC1-RC4
RC12-RC15

RD0-RD15 I/O ST PORTD is a bidirectional I/O port.

RE0-RE9 I/O ST PORTE is a bidirectional I/O port.

RF0-RF8
RF12-RF13

RG0-RG3
RG6-RG9
RG12-RG15

Legend: CMOS = CMOS compatible input or output; Analog = Analog input

Pin

Typ e

I

O

I

O

I

O

I/O

I

I/O

I

I/O

I

I
I
I
I
I

I/P ST Master Clear (Reset) input. This pin is an active-low Reset to the device.

I
I

O

I

I/O

I/O
I/O
I/O

I/O
I/O

I/O ST PORTF is a bidirectional I/O port.

I/O
I/O
I/O

ST = Schmitt Trigger input with CMOS levels; O = Output; I = Input; P = Power

Buffer

Type

ST/CMOS—External clock source input. Always associated with OSC1 pin function.

ST

—

ST

—

ST
ST
ST
ST
ST
ST

ST
ST
ST
ST
ST

ST
ST

—

ST/CMOS—Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise.

ST
ST
ST

ST
ST

ST
ST
ST

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode.

Optionally functions as CLKO in RC and EC modes. Always associated with OSC2
pin function.

Can be software programmed for internal weak pull-ups on all inputs.

ECAN1 bus receive pin.
ECAN1 bus transmit pin.
ECAN2 bus receive pin.
ECAN2 bus transmit pin.

Data I/O pin for programming/debugging communication channel 1.
Clock input pin for programming/debugging communication channel 1.
Data I/O pin for programming/debugging communication channel 2.
Clock input pin for programming/debugging communication channel 2.
Data I/O pin for programming/debugging communication channel 3.
Clock input pin for programming/debugging communication channel 3.

External interrupt 0.
External interrupt 1.
External interrupt 2.
External interrupt 3.
External interrupt 4.

Compare Fault A input (for Compare Channels 1, 2, 3 and 4).
Compare Fault B input (for Compare Channels 5, 6, 7 and 8).
Compare outputs 1 through 8.

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode.
Optionally functions as CLKO in RC and EC modes.

PORTA is a bidirectional I/O port.

PORTC is a bidirectional I/O port.

PORTG is a bidirectional I/O port.

PIC24H

Description

© 2006 Microchip Technology Inc. Advance Information DS70175A-page 15

PIC24H

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

SCK1
SDI1
SDO1
SS1
SCK2
SDI2
SDO2
SS2

SCL1
SDA1
SCL2
SDA2

SOSCI
SOSCO

TMS
TCK
TDI
TDO

T1CK
T2CK
T3CK
T4CK
T5CK
T6CK
T7CK
T8CK
T9CK

U1CTS
U1RTS
U1RX
U1TX
U2CTS
U2RTS
U2RX
U2TX

V

DD P — Positive supply for peripheral logic and I/O pins.

DDCORE P — CPU logic filter capacitor connection.

V

VSS P — Ground reference for logic and I/O pins.

REF+ I Analog Analog voltage reference (high) input.

V

VREF- I Analog Analog voltage reference (low) input.

Legend: CMOS = CMOS compatible input or output; Analog = Analog input

Pin

Typ e

I/O

I

O
I/O
I/O

I

O
I/O

I/O
I/O
I/O
I/O

I

O

I
I
I

O

I
I
I
I
I
I
I
I
I

I

O

I

O

I

O

I

O

ST = Schmitt Trigger input with CMOS levels; O = Output; I = Input; P = Power

Buffer

Type

ST
ST

—
ST
ST
ST

—
ST

ST
ST
ST
ST

ST/CMOS—32.768 kHz low-power oscillator crystal input; CMOS otherwise.

ST
ST
ST

—

ST
ST
ST
ST
ST
ST
ST
ST
ST

ST

—
ST

—
ST

—
ST

—

Synchronous serial clock input/output for SPI1.
SPI1 data in.
SPI1 data out.
SPI1 slave synchronization or frame pulse I/O.
Synchronous serial clock input/output for SPI2.
SPI2 data in.
SPI2 data out.
SPI2 slave synchronization or frame pulse I/O.

Synchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
Synchronous serial clock input/output for I2C2.
Synchronous serial data input/output for I2C2.

32.768 kHz low-power oscillator crystal output.

JTAG Test mode select pin.
JTAG test clock input pin.
JTAG test data input pin.
JTAG test data output pin.

Timer1 external clock input.
Timer2 external clock input.
Timer3 external clock input.
Timer4 external clock input.
Timer5 external clock input.
Timer6 external clock input.
Timer7 external clock input.
Timer8 external clock input.
Timer9 external clock input.

UART1 clear to send.
UART1 ready to send.
UART1 receive.
UART1 transmit.
UART2 clear to send.
UART2 ready to send.
UART2 receive.
UART2 transmit.

Description

DS70175A-page 16 Advance Information © 2006 Microchip Technology Inc.

PIC24H

2.0 CPU

Note: This data sheet summarizes the features

of this group of PIC24H devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “dsPIC30F
Family Reference Manual” (DS70046).

The PIC24H CPU module has a 16-bit (data) modified
Harvard architecture with an enhanced instruction set
and addressing modes. The CPU has a 24-bit instruction
word with a variable length opcode field. The Program
Counter (PC) is 23 bits wide and addresses up to 4M x
24 bits of user program memory space. The actual
amount of program memory implemented varies by
device. A single-cycle instruction prefetch mechanism is
used to help maintain throughput and provides
predictable execution. All instructions execute in a single
cycle, with the exception of instructions that change the
program flow, the double word move (MOV.D) instruction
and the table instructions. Overhead-free single-cycle
program loop constructs are supported using the
REPEAT instruction, which is interruptible at any point.

The PIC24H devices have sixteen, 16-bit working
registers in the programmer’s model. Each of the working
registers can serve as a data, address or address offset
register. The 16th working register (W15) operates as a
software Stack Pointer (SP) for interrupts and calls.

The PIC24H instruction set includes many addressing
modes and is designed for optimum C compiler
efficiency. For most instructions, the PIC24H is capable
of executing a data (or program data) memory read, a
working register (data) read, a data memory write and
a program (instruction) memory read per instruction
cycle. As a result, three parameter instructions can be
supported, allowing A + B = C operations to be
executed in a single cycle.

A block diagram of the CPU is shown in Figure 2-1,
and the programmer’s model for the PIC24H is shown
in Figure 2-2.

2.2 Special MCU Features

The PIC24H features a 17-bit by 17-bit, single-cycle
multiplier. The multiplier can perform signed, unsigned
and mixed-sign multiplication. Using a 17-bit by 17-bit
multiplier for 16-bit by 16-bit multiplication makes
mixed-sign multiplication possible.

The PIC24H supports 16/16 and 32/16 integer divide
operations. All divide instructions are iterative
operations. They must be executed within a REPEAT
loop, resulting in a total execution time of 19 instruction
cycles. The divide operation can be interrupted during
any of those 19 cycles without loss of data.

A multi-bit data shifter is used to perform up to a 16-bit,
left or right shift in a single cycle.

2.1 Data Addressing Overview

The data space can be linearly addressed as 32K words
or 64 Kbytes using an Address Generation Unit (AGU).
The upper 32 Kbytes of the data space memory map can
optionally be mapped into program space at any 16K pro­gram word boundary defined by the 8-bit Program Space
Visibility Page (PSVPAG) register. The program to data
space mapping feature lets any instruction access pro­gram space as if it were data space.

The data space also includes 2 Kbytes of DMA RAM,
which is primarily used for DMA data transfers, but may
be used as general purpose RAM.

© 2006 Microchip Technology Inc. Advance Information DS70175A-page 17

PIC24H

FIGURE 2-1: PIC24H CPU CORE BLOCK DIAGRAM

PSV & Table
Data Access
Control Block

Interrupt

Controller

23

23

Address Latch

Program Memory

Data Latch

23

8

PCH PCL

PCU

Program Counter

Stac k

Control

Logic

Address Bus

24

Instruction

Decode &

Control

Control Signals

to Various Blocks

16

Loop

Control

Logic

X Data Bus

16

Data Latch

X RAM

Address

Latch

Address Generator Units

ROM Latch

Instruction Reg

17 x 17
Multiplier

Divide Support

16

16

EA MUX

16

16

Literal Data

16 x 16

W Register Array

Controller

16

DMA

RAM

DMA

16

16

16-bit ALU

16

To Peripheral Modules

DS70175A-page 18 Advance Information © 2006 Microchip Technology Inc.

FIGURE 2-2: PIC24H PROGRAMMER’S MODEL

W0/WREG

W1

W2

W3

W4

W5

W6

W7

W8

W9

W10

W11

W12

W13

W14/Frame Pointer

W15/Stack Pointer

PIC24H

D0D15

PUSH.S Shadow

DO Shadow

Legend

Working Registers

PC22

7

TBLPAG

7

PSVPAG

— — ——

SRH

0

0

— —

SPLIM

Data Table Page Address

Program Space Visibility Page Address

15

RCOUNT

15

CORCON

— DC

IPL2 IPL1

IPL0 OV

RA

SRL

PC0

N

Stack Pointer Limit Register

Program Counter

0

0

REPEAT Loop Counter

0

Core Configuration Register

C

Z

STATUS Register

© 2006 Microchip Technology Inc. Advance Information DS70175A-page 19

PIC24H

2.3 CPU Control Registers

REGISTER 2-1: SR: CPU STATUS REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — —DC

bit 15 bit 8

(1)

R/W-0

IPL<2:0>

bit 7 bit 0

Legend:

C = Clear only bit R = Readable bit U = Unimplemented bit, read as ‘0’

S = Set only bit W = Writable bit -n = Value at POR

‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-9 Unimplemented: Read as ‘0’

bit 8 DC: MCU ALU Half Carry/Borrow

1 = A carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized data)

0 = No carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized

bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits

111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)

bit 4 RA: REPEAT Loop Active bit

1 = REPEAT loop in progress
0 = REPEAT loop not in progress

bit 3 N: MCU ALU Negative bit

1 = Result was negative
0 = Result was non-negative (zero or positive)

bit 2 OV: MCU ALU Overflow bit

This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the magnitude which
causes the sign bit to change state.

1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred

bit 1 Z: MCU ALU Zero bit

1 = An operation which effects the Z bit has set it at some time in the past
0 = The most recent operation which effects the Z bit has cleared it (i.e., a non-zero result)

Note 1: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority

Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.

2: The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>).

(2)

R/W-0

(2)

of the result occurred

data) of the result occurred

R/W-0

(2)

R-0 R/W-0 R/W-0 R/W-0 R/W-0

RA N OV Z C

bit

(2)

DS70175A-page 20 Advance Information © 2006 Microchip Technology Inc.

PIC24H

REGISTER 2-1: SR: CPU STATUS REGISTER (CONTINUED)

bit 0 C: MCU ALU Carry/Borrow bit

1 = A carry-out from the Most Significant bit (MSb) of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred

Note 1: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority

Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.

2: The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>).

© 2006 Microchip Technology Inc. Advance Information DS70175A-page 21

PIC24H

REGISTER 2-2: CORCON: CORE CONTROL REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0

— — — —IPL3

bit 7 bit 0

Legend: C = Clear only bit

R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set

0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’

bit 15-4 Unimplemented: Read as ‘0’

bit 3 IPL3: CPU Interrupt Priority Level Status bit 3

1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less

bit 2 PSV: Program Space Visibility in Data Space Enable bit

1 = Program space visible in data space
0 = Program space not visible in data space

bit 1-0 Unimplemented: Read as ‘0’

Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.

(2)

(1)

PSV — —

DS70175A-page 22 Advance Information © 2006 Microchip Technology Inc.

PIC24H

2.4 Arithmetic Logic Unit (ALU)

The PIC24H ALU is 16 bits wide and is capable of addi­tion, subtraction, bit shifts and logic operations. Unless
otherwise mentioned, arithmetic operations are 2’s
complement in nature. Depending on the operation, the
ALU may affect the values of the Carry (C), Zero (Z),
Negative (N), Overflow (OV) and Digit Carry (DC) Sta­tus bits in the SR register. The C and DC Status bits
operate as Borrow
for subtraction operations.

The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W reg­ister array, or data memory, depending on the address­ing mode of the instruction. Likewise, output data from
the ALU can be written to the W register array or a data
memory location.

Refer to the “dsPIC30F/33F Programmer’s Reference
Manual” (DS70157) for information on the SR bits
affected by each instruction.

The PIC24H CPU incorporates hardware support for
both multiplication and division. This includes a dedi­cated hardware multiplier and support hardware for
16-bit-divisor division.

and Digit Borrow bits, respectively,

2.4.3 MULTI-BIT DATA SHIFTER

The multi-bit data shifter is capable of performing up to
16-bit arithmetic or logic right shifts, or up to 16-bit left
shifts in a single cycle. The source can be either a
working register or a memory location.

The shifter requires a signed binary value to determine
both the magnitude (number of bits) and direction of the
shift operation. A positive value shifts the operand right.
A negative value shifts the operand left. A value of ‘0’
does not modify the operand.

2.4.1 MULTIPLIER

Using the high-speed 17-bit x 17-bit multiplier, the ALU
supports unsigned, signed or mixed-sign operation in
several multiplication modes:

1. 16-bit x 16-bit signed

2. 16-bit x 16-bit unsigned

3. 16-bit signed x 5-bit (literal) unsigned

4. 16-bit unsigned x 16-bit unsigned

5. 16-bit unsigned x 5-bit (literal) unsigned

6. 16-bit unsigned x 16-bit signed

7. 8-bit unsigned x 8-bit unsigned

2.4.2 DIVIDER

The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:

1. 32-bit signed/16-bit signed divide

2. 32-bit unsigned/16-bit unsigned divide

3. 16-bit signed/16-bit signed divide

4. 16-bit unsigned/16-bit unsigned divide

The quotient for all divide instructions ends up in W0
and the remainder in W1. Sixteen-bit signed and
unsigned DIV instructions can specify any W register
for both the 16-bit divisor (Wn) and any W register
(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.
The divide algorithm takes one cycle per bit of divisor,
so both 32-bit/16-bit and 16-bit/16-bit instructions take
the same number of cycles to execute.

© 2006 Microchip Technology Inc. Advance Information DS70175A-page 23

PIC24H

NOTES:

DS70175A-page 24 Advance Information © 2006 Microchip Technology Inc.

PIC24H

3.0 MEMORY ORGANIZATION

Note: This data sheet summarizes the features

of this group of PIC24H devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “dsPIC30F
Family Reference Manual” (DS70046).

The PIC24H architecture features separate program
and data memory spaces and buses. This architecture
also allows the direct access of program memory from
the data space during code execution.

3.1 Program Address Space

The program address memory space of the PIC24H
devices is 4M instructions. The space is addressable by a
24-bit value derived from either the 23-bit Program Counter
(PC) during program execution, or from table operation
or data space remapping as described in Section 3.4
“Interfacing Program and Data Memory Spaces”.

User access to the program memory space is restricted
to the lower half of the address range (0x000000 to
0x7FFFFF). The exception is the use of TBLRD/TBLWT
operations, which use TBLPAG<7> to permit access to
the Configuration bits and Device ID sections of the
configuration memory space.

Memory maps for the PIC24H family of devices are
shown in Figure 3-1.

FIGURE 3-1: PROGRAM MEMORY MAP FOR PIC24H FAMILY DEVICES

PIC24HJ64XXXXX PIC24HJ128XXXXX PIC24HJ256XXXXX

GOTO Instruction

Reset Address

Interrupt Vector Table

Reserved

Alternate Vector Table

User Program

Flash Memory

(22K instructions)

Instruction

GOTO

Reset Address

Interrupt Vector Table

Reserved

Alternate Vector Table

User Program
Flash Memory

(44K instructions)

GOTO Instruction

Reset Address

Interrupt Vector Table

Reserved

Alternate Vector Table

User Program
Flash Memory

(88K instructions)

0x000000
0x000002

0x000004

0x0000FE
0x000100
0x000104
0x0001FE
0x000200

0x00ABFE
0x00AC00

0x0157FE
0x015800

User Memory Space

Unimplemented

Device Configuration

Configuration Memory Space

(Read ‘0’s)

Reserved

Registers

Reserved

DEVID (2)

Unimplemented

(Read ‘0’s)

Reserved

Device Configuration

Registers

Reserved

DEVID (2)

Unimplemented

(Read ‘0’s)

Reserved

Device Configuration

Registers

Reserved

DEVID (2)

0x02ABFE
0x02AC00

0x7FFFFE
0x800000

0xF7FFFE
0xF80000

0xF8000E
0xF80010

0xFEFFFE
0xFF0000

0xFFFFFE

© 2006 Microchip Technology Inc. Advance Information DS70175A-page 25

PIC24H

3.1.1 PROGRAM MEMORY ORGANIZATION

The program memory space is organized in
word-addressable blocks. Although it is treated as
24 bits wide, it is more appropriate to think of each
address of the program memory as a lower and upper
word, with the upper byte of the upper word being
unimplemented. The lower word always has an even
address, while the upper word has an odd address
(Figure 3-2).

Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or
decremented by two during code execution. This
arrangement also provides compatibility with data
memory space addressing and makes it possible to
access data in the program memory space.

3.1.2 INTERRUPT AND TRAP VECTORS

All PIC24H devices reserve the addresses between
0x00000 and 0x000200 for hard-coded program exe­cution vectors. A hardware Reset vector is provided to
redirect code execution from the default value of the
PC on device Reset to the actual start of code. A GOTO
instruction is programmed by the user at 0x000000,
with the actual address for the start of code at
0x000002.

PIC24H devices also have two interrupt vector tables,
located from 0x000004 to 0x0000FF and 0x000100 to
0x0001FF. These vector tables allow each of the many
device interrupt sources to be handled by separate
Interrupt Service Routines (ISRs). A more detailed dis­cussion of the interrupt vector tables is provided in

Section 6.1 “Interrupt Vector Table”.

FIGURE 3-2: PROGRAM MEMORY ORGANIZATION

msw

Address (lsw Address)

0x000001
0x000003
0x000005
0x000007

most significant word

23

00000000

00000000

00000000

00000000

least significant word

PC Address

0816

0x000000
0x000002
0x000004
0x000006

Program Memory

‘Phantom’ Byte

(read as ‘0’)

Instruction Width

DS70175A-page 26 Advance Information © 2006 Microchip Technology Inc.

PIC24H

3.2 Data Address Space

The PIC24H CPU has a separate 16-bit wide data
memory space. The data space is accessed using sep­arate Address Generation Units (AGUs) for read and
write operations. Data memory maps of devices with
different RAM sizes are shown in Figure 3-3 and
Figure 3-4.

All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to bytes within the data space.
This arrangement gives a data space address range of
64 Kbytes or 32K words. The lower half of the data
memory space (that is, when EA<15> = 0) is used for
implemented memory addresses, while the upper half
(EA<15> = 1) is reserved for the Program Space
Visibility area (see Section 3.4.3 “Reading Data From
Program Memory Using Program Space Visibility”).

PIC24H devices implement up to 16 Kbytes of data
memory. Should an EA point to a location outside of
this area, an all-zero word or byte will be returned.

3.2.1 DATA SPACE WIDTH

The data memory space is organized in byte address­able, 16-bit wide blocks. Data is aligned in data
memory and registers as 16-bit words, but all data
space EAs resolve to bytes. The Least Significant
Bytes of each word have even addresses, while the
Most Significant Bytes have odd addresses.

3.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT

To maintain backward compatibility with PICmicro
devices and improve data space memory usage
efficiency, the PIC24H instruction set supports both
word and byte operations. As a consequence of byte
accessibility, all effective address calculations are inter­nally scaled to step through word-aligned memory. For
example, the core recognizes that Post-Modified
Register Indirect Addressing mode [Ws++] will result in
a value of Ws + 1 for byte operations and Ws + 2 for
word operations.

Data byte reads will read the complete word that
contains the byte, using the Least Significant bit (LSb)
of any EA to determine which byte to select. The
selected byte is placed onto the Least Significant Byte
(LSB) of the data path. That is, data memory and reg­isters are organized as two parallel byte-wide entities
with shared (word) address decode but separate write
lines. Data byte writes only write to the corresponding
side of the array or register which matches the byte
address.

All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word opera­tions, or translating from 8-bit MCU code. If a mis­aligned read or write is attempted, an address error
trap is generated. If the error occurred on a read, the
instruction underway is completed; if it occurred on a
write, the instruction will be executed but the write does
not occur. In either case, a trap is then executed, allow­ing the system and/or user to examine the machine
state prior to execution of the address Fault.

All byte loads into any W register are loaded into the
Least Significant Byte. The Most Significant Byte is not
modified.

A sign-extend instruction (SE) is provided to allow
users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, users
can clear the Most Significant Byte (MSB) of any W
register by executing a zero-extend (ZE) instruction on
the appropriate address.

3.2.3 SFR SPACE

The first 2 Kbytes of the Near Data Space, from 0x0000
to 0x07FF, is primarily occupied by Special Function
Registers (SFRs). These are used by the PIC24H core
and peripheral modules for controlling the operation of
the device.

SFRs are distributed among the modules that they
control, and are generally grouped together by module.
Much of the SFR space contains unused addresses;

®

these are read as ‘0’. A complete listing of implemented
SFRs, including their addresses, is shown in Table 3-1
through Table 3-31.

Note: The actual set of peripheral features and

interrupts varies by the device. Please
refer to the corresponding device tables
and pinout diagrams for device-specific
information.

3.2.4 NEAR DATA SPACE

The 8-Kbyte area between 0x0000 and 0x1FFF is
referred to as the Near Data Space. Locations in this
space are directly addressable via a 13-bit absolute
address field within all memory direct instructions.
Additionally, the whole data space is addressable using
MOV instructions, which support Memory Direct
Addressing mode with a 16-bit address field, or by
using Indirect Addressing mode using a working
register as an Address Pointer.

© 2006 Microchip Technology Inc. Advance Information DS70175A-page 27

PIC24H

FIGURE 3-3: DATA MEMORY MAP FOR PIC24H DEVICES WITH 8 KBYTES RAM

2-Kbyte
SFR Space

8-Kbyte

SRAM Space

MSB

Address

0x0001

0x07FF

0x0801

0x1FFF

0x2001

0x27FF 0x27FE

0x8001

16 bits

LSBMSB

SFR Space

X Data RAM (X)

DMA RAM

LSB

Address

0x0000

0x07FE
0x0800

0x1FFE
0x2000

0x28000x2801

0x8000

8-Kbyte
Near
Data
Space

Optionally
Mapped
into Program
Memory

0xFFFF

X Data

Unimplemented (X)

0xFFFE

DS70175A-page 28 Advance Information © 2006 Microchip Technology Inc.