MICROCHIP PIC24H DATA SHEET

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PIC24H Family

Data Sheet

High-Performance, 16-bit

Microcontrollers

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, Real ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and Zena are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

8-bit MCUs, KEELOQ

code hopping

PIC24H

High-Performance, 16-bit Microcontrollers

Operating Range

• DC – 40 MIPS (40 MIPS @ 3.0-3.6V,

-40°C to +85°C)

• Industrial temperature range (-40°C to +85°C)

High-Performance DSC CPU

• Modified Harvard architecture

• C compiler optimized instruction set

• 16-bit wide data path

• 24-bit wide instructions

• Linear program memory addressing up to 4M

instruction words

• Linear data memory addressing up to 64 Kbytes

• 72 base instructions: mostly 1 word/1 cycle

• Sixteen 16-bit General Purpose Registers

• Flexible and powerful Indirect Addressing modes

• Software stack

• 16 x 16 multiply operations

• 32/16 and 16/16 divide operations

• Up to ±16-bit data shifts

Direct Memory Access (DMA)

• 8-channel hardware DMA:

• 2 Kbytes dual ported DMA buffer area

(DMA RAM) to store data transferred via DMA:

- Allows data transfer between RAM and a peripheral while CPU is executing code (no cycle stealing)

• Most peripherals support DMA

Interrupt Controller

• 5-cycle latency

• 118 interrupt vectors

• Up to 61 available interrupt sources:

• Up to 5 external interrupts

• 7 programmable priority levels

• 5 processor exceptions

On-Chip Flash and SRAM

• Flash program memory, up to 256 Kbytes

• Data SRAM, up to 16 Kbytes (includes 2 Kbytes of DMA RAM):

System Management

• Flexible clock options:

- External, crystal, resonator, internal RC

- Fully integrated PLL

- Extremely low jitter PLL

• Power-up Timer

• Oscillator Start-up Timer/Stabilizer

• Watchdog Timer with its own RC oscillator

• Fail-Safe Clock Monitor

• Reset by multiple sources

Power Management

• On-chip 2.5V voltage regulator

• Switch between clock sources in real time

• Idle, Sleep and Doze modes with fast wake-up

Timers/Capture/Compare/PWM

• Timer/Counters, up to nine 16-bit timers:

- Can pair up to make four 32-bit timers

- 1 timer runs as Real-Time Clock with external

32.768 kHz oscillator

- Programmable prescaler

• Input Capture (up to 8 channels):

- Capture on up, down or both edges

- 16-bit capture input functions

- 4-deep FIFO on each capture

• Output Compare (up to 8 channels):

- Single or Dual 16-Bit Compare mode

- 16-bit Glitchless PWM mode

Digital I/O

• Up to 85 programmable digital I/O pins

• Wake-up/Interrupt-on-Change on up to 24 pins

• Output pins can drive from 3.0V to 3.6V

• All digital input pins are 5V tolerant

• 4 mA sink on all I/O pins

PIC24H

Communication Modules

• 3-wire SPI (up to 2 modules):

- Framing supports I/O interface to simple codecs

- Supports 8-bit and 16-bit data

- Supports all serial clock formats and sampling modes

•I

C™ (up to 2 modules):

- Full Multi-Master Slave mode support

- 7-bit and 10-bit addressing

- Bus collision detection and arbitration

- Integrated signal conditioning

- Slave address masking

• UART (up to 2 modules):

- Interrupt on address bit detect

- Interrupt on UART error

- Wake-up on Start bit from Sleep mode

- 4-character TX and RX FIFO buffers

- LIN bus support

-IrDA

- High-Speed Baud mode

- Hardware Flow Control with CTS and RTS

• Enhanced CAN (ECAN™) 2.0B active (up to 2 modules):

- Up to 8 transmit and up to 32 receive buffers

- 16 receive filters and 3 masks

- Loopback, Listen Only and Listen All

- Wake-up on CAN message

- Automatic processing of Remote

- FIFO mode using DMA

encoding and decoding in hardware

Messages modes for diagnostics and bus monitoring

Transmission Requests

Analog-to-Digital Converters

• Up to two A/D modules in a device

• 10-bit, 2.2 Msps or 12-bit, 1 Msps conversion:

- 2, 4 or 8 simultaneous samples

- Up to 32 input channels with auto-scanning

- Conversion start can be manual or synchronized with 1 of 4 trigger sources

- Conversion possible in Sleep mode

- ±1 LSB max integral nonlinearity

- ±1 LSB max differential nonlinearity

CMOS Flash Technology

• Low-power, high-speed Flash technology

• Fully static design

• 3.3V (±10%) operating voltage

• Industrial temperature

• Low-power consumption

Packaging:

• 100-pin TQFP (14x14x1 mm and 12x12x1 mm):

• 64-pin TQFP (10x10x1 mm)

Note: See the device variant tables for exact

peripheral features per device.

PIC24H PRODUCT FAMILIES

The PIC24H General Purpose Family is ideal for a wide variety of 16-bit MCU embedded applications. The device names, pin counts, memory sizes and peripheral availability of each family are listed below, followed by their pinout diagrams.

PIC24H General Purpose Family Variants

Program

Device Pins

PIC24HJ64GP206 64 64 8 8 9 8 8 0 1 ADC,

PIC24HJ64GP210 100 64 8 8 9 8 8 0 1 ADC,

PIC24HJ64GP506 64 64 8 8 9 8 8 0 1 ADC,

PIC24HJ64GP510 100 64 8 8 9 8 8 0 1 ADC,

PIC24HJ128GP206 64 128 8 8 9 8 8 0 1 ADC,

PIC24HJ128GP210 100 128 8 8 9 8 8 0 1 ADC,

PIC24HJ128GP506 64 128 8 8 9 8 8 0 1 ADC,

PIC24HJ128GP510 100 128 8 8 9 8 8 0 1 ADC,

PIC24HJ128GP306 64 128 16 8 9 8 8 0 1 ADC,

PIC24HJ128GP310 100 128 16 8 9 8 8 0 1 ADC,

PIC24HJ256GP206 64 256 16 8 9 8 8 0 1 ADC,

PIC24HJ256GP210 100 256 16 8 9 8 8 0 1 ADC,

PIC24HJ256GP610 100 256 16 8 9 8 8 0 2 ADC,

Note 1: RAM size is inclusive of 2 Kbytes DMA RAM.

2: Maximum I/O pin count includes pins shared by the peripheral functions.

Flash

Memory (KB)

(KB)

(1)

RAM

Codec

Interface

Timer 16-bit

DMA Channels

Std. PWM

Input Capture

Output Compare

18 ch

32 ch

18 ch

32 ch

18 ch

32 ch

18 ch

32 ch

18 ch

32 ch

18 ch

32 ch

PIC24H

(2)

C™

SPI

ADC

UART

2 2 1 0 53 PT

2 2 2 0 85 PF, PT

222 153 PT

222 185 PF, PT

2 2 2 0 53 PT

2 2 2 0 85 PF, PT

222 153 PT

222 185 PF, PT

2 2 2 0 53 PT

2 2 2 0 85 PF, PT

222 053 PT

222 085 PF, PT

2 2 2 2 85 PF, PT

CAN

I/O Pins (Max)

Packages

PIC24H

Pin Diagrams

64-Pin TQFP

DDCORE

RG13

RG12

RG14

RG1

RF1

RG0

OC8/CN16/RD7

VDD

RF0

OC7/CN15/RD6

OC6/IC6/CN14/RD5

OC5/IC5/CN13/RD4

OC4/RD3

OC3/RD2

OC2/RD1

AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2

SDO2/CN10/RG8

/T5CK/CN11/RG9

SS2

AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4

PGC3/EMUC3/AN1/V

PGD3/EMUD3/AN0/V

AN2/SS1

RG15

SCK2/CN8/RG6

SDI2/CN9/RG7

MCLR

VSS VDD

AN3/CN5/RB3

/CN4/RB2

REF-/CN3/RB1

REF+/CN2/RB0

646362616059585756

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

PIC24HJ64GP206 PIC24HJ128GP206 PIC24HJ256GP206

171819202122232425

AVSS

U2CTS/AN8/RB8

PGD1/EMUD1/AN7/RB7

PGC1/EMUC1/AN6/OCFA/RB6

AN9/RB9

545352

VDD

TDO/AN11/RB11

TMS/AN10/RB10

TCK/AN12/RB12

504951

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14

PGD2/EMUD2/SOSCI/T4CK/CN1/RC13

OC1/RD0 IC4/INT4/RD11

45 44

IC3/INT3/RD10 IC2/U1CTS/INT2/RD9

IC1/INT1/RD8

OSC2/CLKO/RC15

OSC1/CLKIN/RC12

SCL1/RG2

SDA1/RG3

U1RTS/SCK1/INT0/RF6

U1RX/SDI1/RF2

U1TX/SDO1/RF3

TDI/AN13/RB13

U2TX/CN18/RF5

U2RX/CN17/RF4

U2RTS/AN14/RB14

AN15/OCFB/CN12/RB15

Note: The PIC24HJ64GP206 device does not have the SCL2 and SDA2 pins.

Pin Diagrams (Continued)

64-Pin TQFP

PIC24H

DDCORE

RG13

RG12

RG14

RG1

RF1

RG0

OC8/CN16/RD7

VDD

RF0

OC7/CN15/RD6

OC6/IC6/CN14/RD5

OC5/IC5/CN13/RD4

OC4/RD3

OC3/RD2

OC2/RD1

AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2

SDO2/CN10/RG8

/T5CK/CN11/RG9

SS2

AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4

PGC3/EMUC3/AN1/V

PGD3/EMUD3/AN0/V

AN2/SS1

RG15

SCK2/CN8/RG6

SDI2/CN9/RG7

MCLR

VSS

VDD

AN3/CN5/RB3

/CN4/RB2

REF-/CN3/RB1

REF+/CN2/RB0

646362616059585756

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

PIC24HJ128GP306

171819202122232425

AVSS

U2CTS/AN8/RB8

PGD1/EMUD1/AN7/RB7

PGC1/EMUC1/AN6/OCFA/RB6

AN9/RB9

545352

VDD

TDO/AN11/RB11

TMS/AN10/RB10

TCK/AN12/RB12

504951

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14

PGD2/EMUD2/SOSCI/T4CK/CN1/RC13

OC1/RD0 IC4/INT4/RD11

45 44

IC3/INT3/RD10 IC2/U1CTS/INT2/RD9

IC1/INT1/RD8

OSC2/CLKO/RC15

OSC1/CLKIN/RC12

SCL1/RG2

SDA1/RG3

U1RTS/SCK1/INT0/RF6

U1RX/SDI1/RF2

U1TX/SDO1/RF3

TDI/AN13/RB13

U2RTS/AN14/RB14

U2TX/SCL2/CN18/RF5

U2RX/SDA2/CN17/RF4

AN15/OCFB/CN12/RB15

PIC24H

Pin Diagrams (Continued)

64-Pin TQFP

DDCORE

CSDO/RG13

CSDI/RG12

CSCK/RG14

RG1

C1TX/RF1

RG0

OC8/CN16/RD7

VDD

C1RX/RF0

OC7/CN15/RD6

OC6/IC6/CN14/RD5

OC5/IC5/CN13/RD4

OC4/RD3

OC3/RD2

OC2/RD1

AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2

SDO2/CN10/RG8

/T5CK/CN11/RG9

SS2

AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4

PGC3/EMUC3/AN1/V

PGD3/EMUD3/AN0/V

AN2/SS1

COFS/RG15

SCK2/CN8/RG6

SDI2/CN9/RG7

MCLR

VSS

VDD

AN3/CN5/RB3

/CN4/RB2

REF-/CN3/RB1

REF+/CN2/RB0

646362616059585756

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

PIC24HJ64GP506 PIC24HJ128GP506

171819202122232425

AVSS

U2CTS/AN8/RB8

PGD1/EMUD1/AN7/RB7

PGC1/EMUC1/AN6/OCFA/RB6

AN9/RB9

545352

VDD

TDO/AN11/RB11

TMS/AN10/RB10

TCK/AN12/RB12

504951

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14

PGD2/EMUD2/SOSCI/T4CK/CN1/RC13

OC1/RD0

IC4/INT4/RD11

IC3/INT3/RD10

IC2/U1CTS/INT2/RD9

IC1/INT1/RD8

OSC2/CLKO/RC15

OSC1/CLKIN/RC12

SCL1/RG2

SDA1/RG3

U1RTS/SCK1/INT0/RF6

U1RX/SDI1/RF2

U1TX/SDO1/RF3

TDI/AN13/RB13

U2RTS/AN14/RB14

U2TX/SCL2/CN18/RF5

U2RX/SDA2/CN17/RF4

AN15/OCFB/CN12/RB15

Pin Diagrams (Continued)

100-Pin TQFP

AN28/RE4

AN27/RE3

100

RG15

AN29/RE5

AN30/RE6

AN16/T2CK/T7CK/RC1

AN17/T3CK/T6CK/RC2

AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4

PGC3/EMUC3/AN1/CN3/RB1

PGD3/EMUD3/AN0/CN2/RB0

AN31/RE7

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

SS2/CN11/RG9

TMS/RA0

AN20/INT1/RE8 AN21/INT2/RE9

AN5/CN7/RB5 AN4/CN6/RB4

AN3/CN5/RB3

/CN4/RB2

AN2/SS1

23 24

AN26/RE2

PIC24H

DDCORE

AN23/CN23/RA7

RG13

RG12

RG14

969897

AN22/CN22/RA6

AN25/RE1

AN24/RE0

RG0

9294939190898887868584838281807978

RF0

RG1

RF1

PIC24HJ64GP210 PIC24HJ128GP210 PIC24HJ128GP310 PIC24HJ256GP210

OC6/CN14/RD5

OC5/CN13/RD4

IC6/CN19/RD13

IC5/RD12

OC4/RD3

OC3/RD2

OC8/CN16/RD7

OC7/CN15/RD6

OC2/RD1

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14

PGD2/EMUD2/SOSCI/CN1 /RC13

OC1/RD0

IC4/RD11

IC3/RD10

IC2/RD9

IC1/RD8

INT4/RA15

INT3/RA14

OSC2/CLKO/RC15

OSC1/CLKIN/RC12

TDO/RA5

TDI/RA4

SDA2/RA3

SCL2/RA2

SCL1/RG2

SDA1/RG3

SCK1/INT0/RF6

SDI1/RF7

SDO1/RF8

U1RX/RF2

U1TX/RF3

2829303132333435363738

-/RA9 +/RA10

REF

PGD1/EMUD1/AN7/RB7

PGC1/EMUC1/AN6/OCFA/RB6

AN8/RB8

REF

AN9/RB9

AN10/RB10

TCK/RA1

AN11/RB11

AN12/RB12

U2RTS/RF13

U2CTS/RF12

AN13/RB13

AN14/RB14

AN15/OCFB/CN12/RB15

4647484950

IC7/U1CTS/CN20/RD14

U2TX/CN18/RF5

U2RX/CN17/RF4

IC8/U1RTS/CN21/RD15

PIC24H

Pin Diagrams (Continued)

100-Pin TQFP

AN28/RE4

AN27/RE3

100

RG15

AN29/RE5 AN30/RE6 AN31/RE7

AN16/T2CK/T7CK/RC1

AN17/T3CK/T6CK/RC2

AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

SS2/CN11/RG9

TMS/RA0

AN20/INT1/RE8 AN21/INT2/RE9

AN5/CN7/RB5

AN4/CN6/RB4

AN3/CN5/RB3

/CN4/RB2

AN2/SS1

PGC3/EMUC3/AN1/CN3/RB1

PGD3/EMUD3/AN0/CN2/RB0

8 9

AN26/RE2

RG1

C1RX/RF0

C1TX/RF1

AN23/CN23/RA7

RG13

RG12

RG14

969897

AN22/CN22/RA6

AN25/RE1

AN24/RE0

RG0

929493

91908988878685848382818079

PIC24HJ64GP510

PIC24HJ128GP510

OC6/CN14/RD5

OC5/CN13/RD4

IC6/CN19/RD13

IC5/RD12

OC4/RD3

OC3/RD2

OC8/CN16/RD7

OC7/CN15/RD6

OC2/RD1

PGC2/EMUC2/SOSCO/T1CK/CN0/ RC14

PGD2/EMUD2/SOSCI/CN1/RC13 OC1/RD0

IC4/RD11

IC3/RD10

IC2/RD9

IC1/RD8

INT4/RA15

INT3/RA14

OSC2/CLKO/RC15

OSC1/CLKIN/RC12

TDO/RA5

TDI/RA4

SDA2/RA3

SCL2/RA2

SCL1/RG2

SDA1/RG3

SCK1/INT0/RF6

SDI1/RF7

SDO1/RF8

U1RX/RF2

U1TX/RF3

DDCORE

2829303132333435363738

-/RA9 +/RA10

REF

PGD1/EMUD1/AN7/RB7

PGC1/EMUC1/AN6/OCFA/RB6

AN8/RB8

REF

AN9/RB9

AN10/RB10

TCK/RA1

AN11/RB11

AN12/RB12

U2RTS/RF13

U2CTS/RF12

AN13/RB13

AN14/RB14

AN15/OCFB/CN12/RB15

4647484950

IC7/U1CTS/CN20/RD14

U2TX/CN18/RF5

U2RX/CN17/RF4

IC8/U1RTS/CN21/RD15

Pin Diagrams (Continued)

100-Pin TQFP

AN28/RE4

AN27/RE3

100

RG15

AN29/RE5

AN30/RE6

AN16/T2CK/T7CK/RC1

AN17/T3CK/T6CK/RC2

AN18/T4CK/T9CK/RC3

AN19/T5CK/T8CK/RC4

PGC3/EMUC3/AN1/CN3/RB1

PGD3/EMUD3/AN0/CN2/RB0

AN31/RE7

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

SS2/CN11/RG9

TMS/RA0

AN20/INT1/RE8 AN21/INT2/RE9

AN5/CN7/RB5 AN4/CN6/RB4

AN3/CN5/RB3

AN2/SS1

/CN4/RB2

AN26/RE2

PIC24H

DDCORE

C2TX/RG1

C1RX/RF0

C1TX/RF1

AN23/CN23/RA7

RG13

RG12

RG14

969897

AN22/CN22/RA6

AN25/RE1

AN24/RE0

C2RX/RG0

9294939190898887868584838281807978

PIC24HJ256GP610

OC6/CN14/RD5

OC5/CN13/RD4

IC6/CN19/RD13

IC5/RD12

OC4/RD3

OC3/RD2

OC8/CN16/RD7

OC7/CN15/RD6

OC2/RD1

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/CN1/RC13

OC1/RD0

IC4/RD11

IC3/RD10

IC2/RD9

IC1/RD8 INT4/RA15

INT3/RA14

OSC2/CLKO/RC15

OSC1/CLKIN/RC12

TDO/RA5

TDI/RA4

SDA2/RA3

SCL2/RA2

SCL1/RG2

SDA1/RG3

SCK1/INT0/RF6

SDI1/RF7

SDO1/RF8

U1RX/RF2

U1TX/RF3

2829303132333435363738

-/RA9 +/RA10

REF

PGD1/EMUD1/AN7/RB7

PGC1/EMUC1/AN6/OCFA/RB6

AN8/RB8

REF

AN9/RB9

TCK/RA1

AN11/RB11

AN10/RB10

AN12/RB12

U2RTS/RF13

U2CTS/RF12

AN13/RB13

AN14/RB14

4647484950

AN15/OCFB/CN12/RB15

U2TX/CN18/RF5

U2RX/CN17/RF4

IC8/U1RTS/ CN21/ RD15

IC7/U1CTS/CN20/RD14

PIC24H

Table of Contents

1.0 Device Overview ........................................................................................................................................................................ 13

2.0 CPU............................................................................................................................................................................................ 17

3.0 Memory Organization ................................................................................................................................................................. 25

4.0 Flash Program Memory .............................................................................................................................................................. 55

5.0 Resets ....................................................................................................................................................................................... 61

6.0 Interrupt Controller ..................................................................................................................................................................... 65

7.0 Direct Memory Access (DMA) .................................................................................................................................................. 109

8.0 Oscillator Configuration............................................................................................................................................................ 123

9.0 Power-Saving Features............................................................................................................................................................ 131

10.0 I/O Ports ................................................................................................................................................................................... 133

11.0 Timer1 ...................................................................................................................................................................................... 135

12.0 Timer2/3, Timer4/5, Timer6/7 and Timer8/9 ............................................................................................................................ 137

13.0 Input Capture............................................................................................................................................................................ 143

14.0 Output Compare....................................................................................................................................................................... 145

15.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 149

16.0 Inter-Integrated Circuit (I

17.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 167

18.0 Enhanced CAN Module ............................................................................................................................................................ 175

19.0 10-bit/12-bit A/D Converter....................................................................................................................................................... 205

20.0 Special Features ...................................................................................................................................................................... 217

21.0 Instruction Set Summary .......................................................................................................................................................... 223

22.0 Development Support............................................................................................................................................................... 231

23.0 Electrical Characteristics .......................................................................................................................................................... 235

24.0 Packaging Information.............................................................................................................................................................. 269

Appendix A: Revision History............................................................................................................................................................. 273

Index ................................................................................................................................................................................................. 275

The Microchip Web Site..................................................................................................................................................................... 279

Customer Change Notification Service .............................................................................................................................................. 279

Customer Support .............................................................................................................................................................................. 279

Reader Response .............................................................................................................................................................................. 280

Product Identification System............................................................................................................................................................. 281

C) ..................................................................................................................................................... 157

PIC24H

TO OUR VALUED CUSTOMERS

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Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

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Customer Notification System

PIC24H

NOTES:

PIC24H

1.0 DEVICE OVERVIEW

Note: This data sheet summarizes the features

of this group of PIC24H devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC30F Family Reference Manual” (DS70046).

This document contains device specific information for the following devices:

• PIC24HJ64GP206

• PIC24HJ64GP210

• PIC24HJ64GP506

• PIC24HJ64GP510

• PIC24HJ128GP206

• PIC24HJ128GP210

• PIC24HJ128GP506

• PIC24HJ128GP510

• PIC24HJ128GP306

• PIC24HJ128GP310

• PIC24HJ256GP206

• PIC24HJ256GP210

• PIC24HJ256GP610

The PIC24H device family includes devices with different pin counts (64 and 100 pins), different program memory sizes (64 Kbytes, 128 Kbytes and 256 Kbytes) and different RAM sizes (8 Kbytes and 16 Kbytes).

This makes these families suitable for a wide variety of high-performance digital signal control application. The devices are pin compatible with the PIC24H family of devices, and also share a very high degree of compatibility with the dsPIC30F family devices. This allows easy migration between device families as may be necessitated by the specific functionality, computational resource and system cost requirements of the application.

The PIC24H device family employs a powerful 16-bit architecture, ideal for applications that rely on high-speed, repetitive computations, as well as control.

The 17 x 17 multiplier, hardware support for division operations, multi-bit data shifter, a large array of 16-bit working registers and a wide variety of data addressing modes, together provide the PIC24H Central Processing Unit (CPU) with extensive mathematical processing capability. Flexible and deterministic interrupt handling, coupled with a powerful array of peripherals, renders the PIC24H devices suitable for

control applications. Further, Direct Memory Access (DMA) enables overhead-free transfer of data between several peripherals and a dedicated DMA RAM. Reliable, field programmable Flash program memory ensures scalability of applications that use PIC24H devices.

Figure 1-1 shows a general block diagram of the various core and peripheral modules in the PIC24H family of devices, while Table 1-1 lists the functions of the various pins shown in the pinout diagrams.

PIC24H

FIGURE 1-1: PIC24H GENERAL BLOCK DIAGRAM

PSV & Table Data Access

Control Block

Address Latch

Program Memory

Data Latch

OSC2/CLKO

OSC1/CLKI

Interrupt

Controller

Timing

Generation

FRC/LPRC

Oscillators

Precision Band Gap Reference

Voltag e

Regulator

Control

Address Bus

Control Signals to Various Blocks

PCH PCL

PCU Program Counter

Stack

Logic

Loop

Control

Logic

Instruction

Decode &

Control

Power-up

Time r

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Time r

Brown-out

Reset

Data Bus

Data Latch

X RAM

Address

Latch

Address Generator Units

ROM Latch

Instruction Reg

17 x 17 Multiplier

Divide Support

W Register Array

EA MUX

Literal Data

16 x 16

16-bit ALU

Controller

DMA

RAM

DMA

PORTA

PORTB

PORTC

PORTD

PORTE

PORTF

PORTG

VDDCORE/VCAP

Timers

1-9

IC1-8

DD, VSS

ADC1,2

PWM1-8

OC/

MCLR

ECAN1,2

CN1-23

UART1,2

SPI1,2

I2C1,2

Note: Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins

and features present on each device.

TABLE 1-1: PINOUT I/O DESCRIPTIONS

Pin Name

AN0-AN31 I Analog Analog input channels.

DD P P Positive supply for analog modules.

SS P P Ground reference for analog modules.

CLKI CLKO

CN0-CN23 I ST Input change notification inputs.

C1RX C1TX C2RX C2TX

PGD1/EMUD1 PGC1/EMUC1 PGD2/EMUD2 PGC2/EMUC2 PGD3/EMUD3 PGC3/EMUC3

IC1-IC8 I ST Capture inputs 1 through 8.

INT0 INT1 INT2 INT3 INT4

MCLR

OCFA OCFB OC1-OC8

OSC1 OSC2

RA0-RA7 RA9-RA10 RA12-RA15

RB0-RB15 I/O ST PORTB is a bidirectional I/O port.

RC1-RC4 RC12-RC15

RD0-RD15 I/O ST PORTD is a bidirectional I/O port.

RE0-RE9 I/O ST PORTE is a bidirectional I/O port.

RF0-RF8 RF12-RF13

RG0-RG3 RG6-RG9 RG12-RG15

Legend: CMOS = CMOS compatible input or output; Analog = Analog input

Typ e

I/O

I I I I I

I/P ST Master Clear (Reset) input. This pin is an active-low Reset to the device.

I I

I/O

I/O I/O I/O

I/O I/O

I/O ST PORTF is a bidirectional I/O port.

I/O I/O I/O

ST = Schmitt Trigger input with CMOS levels; O = Output; I = Input; P = Power

Buffer

Type

ST/CMOS—External clock source input. Always associated with OSC1 pin function.

—

ST ST ST ST ST ST

ST ST ST ST ST

ST ST

—

ST/CMOS—Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise.

ST ST ST

ST ST

ST ST ST

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode.

Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function.

Can be software programmed for internal weak pull-ups on all inputs.

ECAN1 bus receive pin. ECAN1 bus transmit pin. ECAN2 bus receive pin. ECAN2 bus transmit pin.

Data I/O pin for programming/debugging communication channel 1. Clock input pin for programming/debugging communication channel 1. Data I/O pin for programming/debugging communication channel 2. Clock input pin for programming/debugging communication channel 2. Data I/O pin for programming/debugging communication channel 3. Clock input pin for programming/debugging communication channel 3.

External interrupt 0. External interrupt 1. External interrupt 2. External interrupt 3. External interrupt 4.

Compare Fault A input (for Compare Channels 1, 2, 3 and 4). Compare Fault B input (for Compare Channels 5, 6, 7 and 8). Compare outputs 1 through 8.

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes.

PORTA is a bidirectional I/O port.

PORTC is a bidirectional I/O port.

PORTG is a bidirectional I/O port.

PIC24H

Description

PIC24H

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

SCK1 SDI1 SDO1 SS1 SCK2 SDI2 SDO2 SS2

SCL1 SDA1 SCL2 SDA2

SOSCI SOSCO

TMS TCK TDI TDO

T1CK T2CK T3CK T4CK T5CK T6CK T7CK T8CK T9CK

U1CTS U1RTS U1RX U1TX U2CTS U2RTS U2RX U2TX

DD P — Positive supply for peripheral logic and I/O pins.

DDCORE P — CPU logic filter capacitor connection.

VSS P — Ground reference for logic and I/O pins.

REF+ I Analog Analog voltage reference (high) input.

VREF- I Analog Analog voltage reference (low) input.

Legend: CMOS = CMOS compatible input or output; Analog = Analog input

Typ e

I/O

O I/O I/O

O I/O

I/O I/O I/O I/O

I I I

I I I I I I I I I

ST = Schmitt Trigger input with CMOS levels; O = Output; I = Input; P = Power

Buffer

Type

ST ST

— ST ST ST

— ST

ST ST ST ST

ST/CMOS—32.768 kHz low-power oscillator crystal input; CMOS otherwise.

ST ST ST

—

ST ST ST ST ST ST ST ST ST

— ST

—

Synchronous serial clock input/output for SPI1. SPI1 data in. SPI1 data out. SPI1 slave synchronization or frame pulse I/O. Synchronous serial clock input/output for SPI2. SPI2 data in. SPI2 data out. SPI2 slave synchronization or frame pulse I/O.

Synchronous serial clock input/output for I2C1. Synchronous serial data input/output for I2C1. Synchronous serial clock input/output for I2C2. Synchronous serial data input/output for I2C2.

32.768 kHz low-power oscillator crystal output.

JTAG Test mode select pin. JTAG test clock input pin. JTAG test data input pin. JTAG test data output pin.

Timer1 external clock input. Timer2 external clock input. Timer3 external clock input. Timer4 external clock input. Timer5 external clock input. Timer6 external clock input. Timer7 external clock input. Timer8 external clock input. Timer9 external clock input.

UART1 clear to send. UART1 ready to send. UART1 receive. UART1 transmit. UART2 clear to send. UART2 ready to send. UART2 receive. UART2 transmit.

Description

PIC24H

2.0 CPU

Note: This data sheet summarizes the features

The PIC24H CPU module has a 16-bit (data) modified Harvard architecture with an enhanced instruction set and addressing modes. The CPU has a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M x 24 bits of user program memory space. The actual amount of program memory implemented varies by device. A single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a single cycle, with the exception of instructions that change the program flow, the double word move (MOV.D) instruction and the table instructions. Overhead-free single-cycle program loop constructs are supported using the REPEAT instruction, which is interruptible at any point.

The PIC24H devices have sixteen, 16-bit working registers in the programmer’s model. Each of the working registers can serve as a data, address or address offset register. The 16th working register (W15) operates as a software Stack Pointer (SP) for interrupts and calls.

The PIC24H instruction set includes many addressing modes and is designed for optimum C compiler efficiency. For most instructions, the PIC24H is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three parameter instructions can be supported, allowing A + B = C operations to be executed in a single cycle.

A block diagram of the CPU is shown in Figure 2-1, and the programmer’s model for the PIC24H is shown in Figure 2-2.

2.2 Special MCU Features

The PIC24H features a 17-bit by 17-bit, single-cycle multiplier. The multiplier can perform signed, unsigned and mixed-sign multiplication. Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication makes mixed-sign multiplication possible.

The PIC24H supports 16/16 and 32/16 integer divide operations. All divide instructions are iterative operations. They must be executed within a REPEAT loop, resulting in a total execution time of 19 instruction cycles. The divide operation can be interrupted during any of those 19 cycles without loss of data.

A multi-bit data shifter is used to perform up to a 16-bit, left or right shift in a single cycle.

2.1 Data Addressing Overview

The data space can be linearly addressed as 32K words or 64 Kbytes using an Address Generation Unit (AGU). The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K program word boundary defined by the 8-bit Program Space Visibility Page (PSVPAG) register. The program to data space mapping feature lets any instruction access program space as if it were data space.

The data space also includes 2 Kbytes of DMA RAM, which is primarily used for DMA data transfers, but may be used as general purpose RAM.

PIC24H

FIGURE 2-1: PIC24H CPU CORE BLOCK DIAGRAM

PSV & Table Data Access Control Block

Interrupt

Controller

Address Latch

Program Memory

Data Latch

PCH PCL

PCU

Program Counter

Stac k

Control

Logic

Address Bus

Instruction

Decode &

Control

Control Signals

to Various Blocks

Loop

Control

Logic

X Data Bus

Data Latch

X RAM

Address

Latch

Address Generator Units

ROM Latch

Instruction Reg

17 x 17 Multiplier

Divide Support

EA MUX

Literal Data

16 x 16

W Register Array

Controller

DMA

RAM

DMA

16-bit ALU

To Peripheral Modules

FIGURE 2-2: PIC24H PROGRAMMER’S MODEL

W0/WREG

W10

W11

W12

W13

W14/Frame Pointer

W15/Stack Pointer

PIC24H

D0D15

PUSH.S Shadow

DO Shadow

Legend

Working Registers

PC22

TBLPAG

PSVPAG

— — ——

SRH

— —

SPLIM

Data Table Page Address

Program Space Visibility Page Address

RCOUNT

CORCON

— DC

IPL2 IPL1

IPL0 OV

SRL

PC0

Stack Pointer Limit Register

Program Counter

REPEAT Loop Counter

Core Configuration Register

STATUS Register

PIC24H

2.3 CPU Control Registers

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — —DC

bit 15 bit 8

(1)

R/W-0

IPL<2:0>

bit 7 bit 0

Legend:

C = Clear only bit R = Readable bit U = Unimplemented bit, read as ‘0’

S = Set only bit W = Writable bit -n = Value at POR

‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-9 Unimplemented: Read as ‘0’

bit 8 DC: MCU ALU Half Carry/Borrow

1 = A carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized data)

0 = No carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized

bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits

111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8)

bit 4 RA: REPEAT Loop Active bit

1 = REPEAT loop in progress 0 = REPEAT loop not in progress

bit 3 N: MCU ALU Negative bit

1 = Result was negative 0 = Result was non-negative (zero or positive)

bit 2 OV: MCU ALU Overflow bit

This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the magnitude which causes the sign bit to change state.

1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred

bit 1 Z: MCU ALU Zero bit

1 = An operation which effects the Z bit has set it at some time in the past 0 = The most recent operation which effects the Z bit has cleared it (i.e., a non-zero result)

Note 1: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority

Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3> = 1.

2: The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>).

(2)

R/W-0

(2)

of the result occurred

data) of the result occurred

R/W-0

(2)

R-0 R/W-0 R/W-0 R/W-0 R/W-0

RA N OV Z C

bit

(2)

PIC24H

bit 0 C: MCU ALU Carry/Borrow bit

1 = A carry-out from the Most Significant bit (MSb) of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred

Note 1: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority

Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3> = 1.

2: The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>).

PIC24H

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0

— — — —IPL3

bit 7 bit 0

Legend: C = Clear only bit

R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set

0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’

bit 15-4 Unimplemented: Read as ‘0’

bit 3 IPL3: CPU Interrupt Priority Level Status bit 3

1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less

bit 2 PSV: Program Space Visibility in Data Space Enable bit

1 = Program space visible in data space 0 = Program space not visible in data space

bit 1-0 Unimplemented: Read as ‘0’

Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.

(2)

(1)

PSV — —

PIC24H

2.4 Arithmetic Logic Unit (ALU)

The PIC24H ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU may affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register. The C and DC Status bits operate as Borrow for subtraction operations.

The ALU can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location.

Refer to the “dsPIC30F/33F Programmer’s Reference Manual” (DS70157) for information on the SR bits affected by each instruction.

The PIC24H CPU incorporates hardware support for both multiplication and division. This includes a dedicated hardware multiplier and support hardware for 16-bit-divisor division.

and Digit Borrow bits, respectively,

2.4.3 MULTI-BIT DATA SHIFTER

The multi-bit data shifter is capable of performing up to 16-bit arithmetic or logic right shifts, or up to 16-bit left shifts in a single cycle. The source can be either a working register or a memory location.

The shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. A positive value shifts the operand right. A negative value shifts the operand left. A value of ‘0’ does not modify the operand.

2.4.1 MULTIPLIER

Using the high-speed 17-bit x 17-bit multiplier, the ALU supports unsigned, signed or mixed-sign operation in several multiplication modes:

1. 16-bit x 16-bit signed

2. 16-bit x 16-bit unsigned

3. 16-bit signed x 5-bit (literal) unsigned

4. 16-bit unsigned x 16-bit unsigned

5. 16-bit unsigned x 5-bit (literal) unsigned

6. 16-bit unsigned x 16-bit signed

7. 8-bit unsigned x 8-bit unsigned

2.4.2 DIVIDER

The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes:

1. 32-bit signed/16-bit signed divide

2. 32-bit unsigned/16-bit unsigned divide

3. 16-bit signed/16-bit signed divide

4. 16-bit unsigned/16-bit unsigned divide

The quotient for all divide instructions ends up in W0 and the remainder in W1. Sixteen-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn) and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute.

PIC24H

NOTES:

PIC24H

3.0 MEMORY ORGANIZATION

Note: This data sheet summarizes the features

The PIC24H architecture features separate program and data memory spaces and buses. This architecture also allows the direct access of program memory from the data space during code execution.

3.1 Program Address Space

The program address memory space of the PIC24H devices is 4M instructions. The space is addressable by a 24-bit value derived from either the 23-bit Program Counter (PC) during program execution, or from table operation or data space remapping as described in Section 3.4 “Interfacing Program and Data Memory Spaces”.

User access to the program memory space is restricted to the lower half of the address range (0x000000 to 0x7FFFFF). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG<7> to permit access to the Configuration bits and Device ID sections of the configuration memory space.

Memory maps for the PIC24H family of devices are shown in Figure 3-1.

FIGURE 3-1: PROGRAM MEMORY MAP FOR PIC24H FAMILY DEVICES

PIC24HJ64XXXXX PIC24HJ128XXXXX PIC24HJ256XXXXX

GOTO Instruction

Reset Address

Interrupt Vector Table

Reserved

Alternate Vector Table

User Program

Flash Memory

(22K instructions)

Instruction

GOTO

Reset Address

Interrupt Vector Table

Reserved

Alternate Vector Table

User Program Flash Memory

(44K instructions)

GOTO Instruction

Reset Address

Interrupt Vector Table

Reserved

Alternate Vector Table

User Program Flash Memory

(88K instructions)

0x000000 0x000002

0x000004

0x0000FE 0x000100 0x000104 0x0001FE 0x000200

0x00ABFE 0x00AC00

0x0157FE 0x015800

User Memory Space

Unimplemented

Device Configuration

Configuration Memory Space

(Read ‘0’s)

Reserved

Registers

Reserved

DEVID (2)

Unimplemented

(Read ‘0’s)

Reserved

Device Configuration

Registers

Reserved

DEVID (2)

Unimplemented

(Read ‘0’s)

Reserved

Device Configuration

Registers

Reserved

DEVID (2)

0x02ABFE 0x02AC00

0x7FFFFE 0x800000

0xF7FFFE 0xF80000

0xF8000E 0xF80010

0xFEFFFE 0xFF0000

0xFFFFFE

PIC24H

3.1.1 PROGRAM MEMORY ORGANIZATION

The program memory space is organized in word-addressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. The lower word always has an even address, while the upper word has an odd address (Figure 3-2).

Program memory addresses are always word-aligned on the lower word, and addresses are incremented or decremented by two during code execution. This arrangement also provides compatibility with data memory space addressing and makes it possible to access data in the program memory space.

3.1.2 INTERRUPT AND TRAP VECTORS

All PIC24H devices reserve the addresses between 0x00000 and 0x000200 for hard-coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user at 0x000000, with the actual address for the start of code at 0x000002.

PIC24H devices also have two interrupt vector tables, located from 0x000004 to 0x0000FF and 0x000100 to 0x0001FF. These vector tables allow each of the many device interrupt sources to be handled by separate Interrupt Service Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in

Section 6.1 “Interrupt Vector Table”.

FIGURE 3-2: PROGRAM MEMORY ORGANIZATION

msw

Address (lsw Address)

0x000001 0x000003 0x000005 0x000007

most significant word

00000000

least significant word

PC Address

0816

0x000000 0x000002 0x000004 0x000006

Program Memory

‘Phantom’ Byte

(read as ‘0’)

Instruction Width

PIC24H

3.2 Data Address Space

The PIC24H CPU has a separate 16-bit wide data memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and write operations. Data memory maps of devices with different RAM sizes are shown in Figure 3-3 and Figure 3-4.

All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space. This arrangement gives a data space address range of 64 Kbytes or 32K words. The lower half of the data memory space (that is, when EA<15> = 0) is used for implemented memory addresses, while the upper half (EA<15> = 1) is reserved for the Program Space Visibility area (see Section 3.4.3 “Reading Data From Program Memory Using Program Space Visibility”).

PIC24H devices implement up to 16 Kbytes of data memory. Should an EA point to a location outside of this area, an all-zero word or byte will be returned.

3.2.1 DATA SPACE WIDTH

The data memory space is organized in byte addressable, 16-bit wide blocks. Data is aligned in data memory and registers as 16-bit words, but all data space EAs resolve to bytes. The Least Significant Bytes of each word have even addresses, while the Most Significant Bytes have odd addresses.

3.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT

To maintain backward compatibility with PICmicro devices and improve data space memory usage efficiency, the PIC24H instruction set supports both word and byte operations. As a consequence of byte accessibility, all effective address calculations are internally scaled to step through word-aligned memory. For example, the core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] will result in a value of Ws + 1 for byte operations and Ws + 2 for word operations.

Data byte reads will read the complete word that contains the byte, using the Least Significant bit (LSb) of any EA to determine which byte to select. The selected byte is placed onto the Least Significant Byte (LSB) of the data path. That is, data memory and registers are organized as two parallel byte-wide entities with shared (word) address decode but separate write lines. Data byte writes only write to the corresponding side of the array or register which matches the byte address.

All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error trap is generated. If the error occurred on a read, the instruction underway is completed; if it occurred on a write, the instruction will be executed but the write does not occur. In either case, a trap is then executed, allowing the system and/or user to examine the machine state prior to execution of the address Fault.

All byte loads into any W register are loaded into the Least Significant Byte. The Most Significant Byte is not modified.

A sign-extend instruction (SE) is provided to allow users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, users can clear the Most Significant Byte (MSB) of any W register by executing a zero-extend (ZE) instruction on the appropriate address.

3.2.3 SFR SPACE

The first 2 Kbytes of the Near Data Space, from 0x0000 to 0x07FF, is primarily occupied by Special Function Registers (SFRs). These are used by the PIC24H core and peripheral modules for controlling the operation of the device.

SFRs are distributed among the modules that they control, and are generally grouped together by module. Much of the SFR space contains unused addresses;

these are read as ‘0’. A complete listing of implemented SFRs, including their addresses, is shown in Table 3-1 through Table 3-31.

Note: The actual set of peripheral features and

interrupts varies by the device. Please refer to the corresponding device tables and pinout diagrams for device-specific information.

3.2.4 NEAR DATA SPACE

The 8-Kbyte area between 0x0000 and 0x1FFF is referred to as the Near Data Space. Locations in this space are directly addressable via a 13-bit absolute address field within all memory direct instructions. Additionally, the whole data space is addressable using MOV instructions, which support Memory Direct Addressing mode with a 16-bit address field, or by using Indirect Addressing mode using a working register as an Address Pointer.

PIC24H

FIGURE 3-3: DATA MEMORY MAP FOR PIC24H DEVICES WITH 8 KBYTES RAM

2-Kbyte SFR Space

8-Kbyte

SRAM Space

MSB

Address

0x0001

0x07FF

0x0801

0x1FFF

0x2001

0x27FF 0x27FE

0x8001

16 bits

LSBMSB

SFR Space

X Data RAM (X)

DMA RAM

LSB

Address

0x0000

0x07FE 0x0800

0x1FFE 0x2000

0x28000x2801

0x8000

8-Kbyte Near Data Space

Optionally Mapped into Program Memory

0xFFFF

X Data

Unimplemented (X)

0xFFFE

PIC24H

FIGURE 3-4: DATA MEMORY MAP FOR PIC24H DEVICES WITH 16 KBYTES RAM

2-Kbyte SFR Space

16-Kbyte SRAM Space

MSB

Address

0x0001

0x07FF 0x0801

0x1FFF

0x3FFF

0x4001

0x47FF 0x47FE

0x8001

16 bits

LSBMSB

SFR Space

X Data RAM (X)

DMA RAM

LSB

Address

0x0000

0x07FE 0x0800

0x1FFE

0x3FFE 0x4000

0x48000x4801

0x8000

8-Kbyte Near Data Space

Unimplemented (X)

Optionally Mapped into Program Memory

0xFFFF

3.2.5 DMA RAM

Every PIC24H device contains 2 Kbytes of dual ported DMA RAM located at the end of data space. Memory locations in the DMA RAM space are accessible simultaneously by the CPU and the DMA controller module. DMA RAM is utilized by the DMA controller to store data to be transferred to various peripherals using DMA, as well as data transferred from various

X Data

0xFFFE

peripherals using DMA. The DMA RAM can be accessed by the DMA controller without having to steal cycles from the CPU.

When the CPU and the DMA controller attempt to concurrently write to the same DMA RAM location, the hardware ensures that the CPU is given precedence in accessing the DMA RAM location. Therefore, the DMA RAM provides a reliable means of transferring DMA data without ever having to stall the CPU.

Note: DMA RAM can be used for general

purpose data storage if the DMA function is not required in an application.

PIC24H

All

0000

0800

xxxx

0000

xxxx

0000

Resets

xxxx

All

Resets

CN23IE CN22IE CN21IE CN20IE CN19IE CN18IE CN17IE CN16IE 0000

CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE 0000

— Disable Interrupts Counter

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

— — — — — — — —

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

Addr

SFR

Addr

SFR Name

WREG0 0000 Working Register 0

WREG1 0002 Working Register 1

WREG2 0004 Working Register 2

WREG3 0006 Working Register 3

WREG4 0008 Working Register 4

WREG5 000A Working Register 5

WREG6 000C Working Register 6

WREG7 000E Working Register 7

WREG8 0010 Working Register 8

WREG9 0012 Working Register 9

WREG10 0014 Working Register 10

WREG11 0016 Working Register 11

WREG12 0018 Working Register 12

WREG13 001A Working Register 13

WREG14 001C Working Register 14

WREG15 001E Working Register 15

SPLIM 0020 Stack Pointer Limit Register

PCL 002E Program Counter Low Word Register

PCH 0030 — — — — — — — — Program Counter High Byte Register

TBLPAG 0032 — — — — — — — — Table Page Address Pointer Register

PSVPAG 0034 — — — — — — — — Program Memory Visibility Page Address Pointer Register

RCOUNT 0036 Repeat Loop Counter Register

SR 0042 — — — — — — —DC IPL<2:0> RANOVZ C

CORCON 0044 — — — — — — — — — — — — IPL3 PSV — —

TABLE 3-1: CPU CORE REGISTERS MAP

DISICNT 0052 —

SFR

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Name

TABLE 3-2: CHANGE NOTIFICATION REGISTER MAP

CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000

— — — — — — — —

CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000

CNPU2 006A

CNEN2 0062

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24H

All

Resets

— 0000

— MI2C1IF SI2C1IF 0000

— MI2C1IE SI2C1IE 0000

— — — — — — — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

Addr

SFR

Name

INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL

TABLE 3-3: INTERRUPT CONTROLLER REGISTER MAP

INTCON2 0082 ALTIVT DISI

— DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF 0000

IFS0 0084

IFS1 0086 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF IC8IF IC7IF AD2IF INT1IF CNIF

— OC8IF OC7IF OC6IF OC5IF IC6IF IC5IF IC4IF IC3IF DMA3IF C1IF C1RXIF SPI2IF SPI2EIF 0000

IFS2 0088 T6IF DMA4IF

— —DMA5IF — — — — C2IF C2RXIF INT4IF INT3IF T9IF T8IF MI2C2IF SI2C2IF T7IF 0000

IFS3 008A

— — — — — — — — C2TXIF C1TXIF DMA7IF DMA6IF —U2EIFU1EIF— 0000

IFS4 008C

— DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE 0000

IEC0 0094

IEC1 0096 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE IC8IE IC7IE AD2IE INT1IE CNIE

— OC8IE OC7IE OC6IE OC5IE IC6IE IC5IE IC4IE IC3IE DMA3IE C1IE C1RXIE SPI2IE SPI2EIE 0000

IEC2 0098 T6IE DMA4IE

— —DMA5IE — — — — C2IE C2RXIE INT4IE INT3IE T9IE T8IE MI2C2IE SI2C2IE T7IE 0000

IEC3 009A

— — — — — — — — C2TXIE C1TXIE DMA7IE DMA6IE —U2EIEU1EIE— 0000

IEC4 009C

— T1IP<2:0> —OC1IP<2:0> —IC1IP<2:0>— INT0IP<2:0> 4444

IPC0 00A4

— T2IP<2:0> —OC2IP<2:0> —IC2IP<2:0>— DMA0IP<2:0> 4444

IPC1 00A6

— U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0> 4444

IPC2 00A8

— — — — — DMA1IP<2:0> — AD1IP<2:0> — U1TXIP<2:0> 0444

IPC3 00AA

— CNIP<2:0> — — — — — MI2C1IP<2:0> — SI2C1IP<2:0> 0044

IPC4 00AC

— IC8IP<2:0> —IC7IP<2:0> — AD2IP<2:0> — INT1IP<2:0> 4444

IPC5 00AE

— T4IP<2:0> —OC4IP<2:0> —OC3IP<2:0>— DMA2IP<2:0> 4444

IPC6 00B0

— U2TXIP<2:0> — U2RXIP<2:0> — INT2IP<2:0> — T5IP<2:0> 4444

IPC7 00B2

— C1IP<2:0> — C1RXIP<2:0> — SPI2IP<2:0> — SPI2EIP<2:0> 4444

IPC8 00B4

— IC5IP<2:0> —IC4IP<2:0> —IC3IP<2:0>— DMA3IP<2:0> 4444

IPC9 00B6

— OC7IP<2:0> —OC6IP<2:0>—OC5IP<2:0>—IC6IP<2:0>4444

IPC10 00B8

— T6IP<2:0> — DMA4IP<2:0> — — — — — OC8IP<2:0> 4404

IPC11 00BA

— T8IP<2:0> — MI2C2IP<2:0> — SI2C2IP<2:0> — T7IP<2:0> 4444

IPC12 00BC

IPC13 00BE — C2RXIP<2:0> — INT4IP<2:0> — INT3IP<2:0> — T9IP<2:0> 4444

— — — — — — — — — — — — — C2IP<2:0> 0004

IPC14 00C0

— — — — — — — — — DMA5IP<2:0> — — — — 0040

IPC15 00C2

— — — — — U2EIP<2:0> — U1EIP<2:0> — — — — 4440

IPC16 00C4

— C2TXIP<2:0> — C1TXIP<2:0> — DMA7IP<2:0> — DMA6IP<2:0> 4444

IPC17 00C6

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24H

All

xxxx

Resets

FFFF

0000

xxxx

FFFF

0000

xxxx

FFFF

0000

xxxx

FFFF

0000

xxxx

FFFF

0000

—

TSYNC TCS

—

TGATE TCKPS<1:0>

—

TCS

—

— —

TGATE TCKPS<1:0> T32

TGATE TCKPS<1:0>

—

TCS

—

— —

TGATE TCKPS<1:0> T32

TGATE TCKPS<1:0>

—

TCS

—

— —

TGATE TCKPS<1:0> T32

TGATE TCKPS<1:0>

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

Addr

SFR

Name

TABLE 3-4: TIMER REGISTER MAP

— — — — — —

TSIDL

—

TMR1 0100 Timer1 Register

PR1 0102 Period Regist er 1

T1CON 0104 TON

TMR2 0106 Timer2 Register

TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only)

TMR3 010A Timer3 Register

— — — — — —

TSIDL

—

PR2 010C Period Regist er 2

PR3 010E Period Register 3

T2CON 0110 TON

T3CON 0112 TON

TMR4 0114 Timer4 Register

TMR5HLD 0116 Timer5 Holding Register (for 32-bit operations only)

TMR5 0118 Timer5 Register

— — — — — —

TSIDL

—

PR4 011A Period Register 4

PR5 011C Period Regist er 5

T4CON 011E TON

T5CON 0120 TON

TMR6 0122 Timer6 Register

TMR7HLD 0124 Timer7 Holding Register (for 32-bit operations only)

TMR7 0126 Timer7 Register

PR6 0128 Period Regist er 6

PR7 012A Period Register 7

T6CON 012C TON —TSIDL— — — — — — TGATE TCKPS<1:0> T32 —TCS

T7CON 012E TON —TSIDL— — — — — — TGATE TCKPS<1:0> — —TCS

TMR8 0130 Timer8 Register

TMR9HLD 0132 Timer9 Holding Register (for 32-bit operations only)

TMR9 0134 Timer9 Register

— — — — — —

TSIDL

—

PR8 0136 Period Regist er 8

PR9 0138 Period Regist er 9

T8CON 013A TON

T9CON 013C TON

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24H

All

xxxx

Resets

0000

xxxx

0000

xxxx

0000

xxxx

0000

xxxx

0000

xxxx

0000

xxxx

0000

xxxx

0000

ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>

— — — — —

ICSIDL

— —

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

— —

SFR

Addr

SFR Name

IC1BUF 0140 Input 1 Capture Register

IC1CON 0142

IC2BUF 0144 Input 2 Capture Register

IC2CON 0146

IC3BUF 0148 Input 3 Capture Register

IC3CON 014A

IC4BUF 014C Input 4 Capture Register

IC4CON 014E

IC5BUF 0150 Input 5 Capture Register

IC5CON 0152

IC6BUF 0154 Input 6 Capture Register

IC6CON 0156

IC7BUF 0158 Input 7 Capture Register

IC7CON 015A

IC8BUF 015C Input 8 Capture Register

IC8CON 015E

TABLE 3-5: INPUT CAPTURE REGISTER MAP

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24H

All

xxxx

Resets

xxxx

0000

xxxx

0000

xxxx

0000

xxxx

0000

xxxx

0000

xxxx

0000

xxxx

0000

xxxx

0000

OCFLT OCTSEL OCM<2:0>

— — — — — — — —

OCFLT OCTSEL OCM<2:0>

— — — — — — — —

OCFLT OCTSEL OCM<2:0>

— — — — — — — —

OCFLT OCTSEL OCM<2:0>

— — — — — — — —

OCFLT OCTSEL OCM<2:0>

— — — — — — — —

OCFLT OCTSEL OCM<2:0>

— — — — — — — —

OCFLT OCTSEL OCM<2:0>

— — — — — — — —

OCFLT OCTSEL OCM<2:0>

— — — — — — — —

SFR

TABLE 3-6: OUTPUT COMPARE REGISTER MAP

OCSIDL

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Addr

SFR Name

— —

OC1RS 0180 Output Compare 1 Secondary Register

OC1R 0182 Output Compare 1 Register

OC1CON 0184

OCSIDL

— —

OC2RS 0186 Output Compare 2 Secondary Register

OC2R 0188 Output Compare 2 Register

OC2CON 018A

OCSIDL

— —

OC3RS 018C Output Compare 3 Secondary Register

OC3R 018E Output Compare 3 Register

OC3CON 0190

OCSIDL

— —

OC4RS 0192 Output Compare 4 Secondary Register

OC4R 0194 Output Compare 4 Register

OC4CON 0196

OCSIDL

— —

OC5RS 0198 Output Compare 5 Secondary Register

OC5R 019A Output Compare 5 Register

OC5CON 019C

OCSIDL

— —

OC6RS 019E Output Compare 6 Secondary Register

OC6R 01A0 Output Compare 6 Register

OC6CON 01A2

OCSIDL

— —

OC7RS 01A4 Output Compare 7 Secondary Register

OC7R 01A6 Output Compare 7 Register

OC7CON 01A8

OCSIDL

— —

OC8RS 01AA Output Compare 8 Secondary Register

OC8R 01AC Output Compare 8 Register

OC8CON 01AE

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24H

All

0000

00FF

0000

1000

0000

00FF

0000

1000

0000

Resets

0000

Resets

0000

SFR

TABLE 3-7: I2C1 REGISTER MAP

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Addr

SFR Name

I2C1RCV 0200 — — — — — — — — Receive Register

I2C1TRN 0202 — — — — — — — — Transmit Register

I2C1BRG 0204 — — — — — — — Baud Rate Generator Register

I2C1ON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN

I2C1STAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF

I2C1ADD 020A — — — — — — Address Register

I2C1MSK 020C — — — — — — Address Mask Register

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

SFR

TABLE 3-8: I2C2 REGISTER MAP

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR Name

Addr

I2C2RCV 0210 — — — — — — — — Receive Register

I2C2TRN 0212 — — — — — — — — Transmit Register

I2C2BRG 0214 — — — — — — — Baud Rate Generator Register

I2C2CON 0216 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN

I2C2STAT 0218 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF

I2C2ADD 021A — — — — — — Address Register

I2C2MSK 021C — — — — — — Address Mask Register

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24H

All

0000

0110

xxxx

0000

Resets

0000

All

0000

0110

xxxx

0000

Resets

0000

All

0000

Resets

0000

All

0000

Resets

0000

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

Addr

SFR Name

U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL

U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA

U1TXREG 0224 — — — — — — — UART Transmit Register

U1RXREG 0226 — — — — — — — UART Receive Register

U1BRG 0228 Baud Rate Generator Prescaler

TABLE 3-9: UART1 REGISTER MAP

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

Addr

SFR

Name

U2MODE 0230 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL

U2STA 0232 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA

U2TXREG 0234 — — — — — — — UART Transmit Register

U2RXREG 0236 — — — — — — — UART Receive Register

U2BRG 0238 Baud Rate Generator Prescaler

TABLE 3-10: UART2 REGISTER MAP

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

Addr

SFR

Name

SPI1STAT 0240 SPIEN — SPISIDL — — BUFELM<2:0> — SPIROV — — — — SPITBF SPIRBF

SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE<2:0> PPRE<1:0>

SPI1CON2 0244 FRMEN SPIFSD FRMPOL — — — — — — — — — — — FRMDLY ENHBUF

SPI1BUF 0248 SPI1 Transmit and Receive Buffer Register

TABLE 3-11: SPI1 REGISTER MAP

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

Addr

SFR Name

SPI2STAT 0260 SPIEN —SPISIDL— —BUFELM<2:0>— SPIROV — — — — SPITBF SPIRBF

SPI2CON1 0262 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE<2:0> PPRE<1:0>

SPI2CON2 0264 FRMEN SPIFSD FRMPOL — — — — — — — — — — — FRMDLY ENHBUF

SPI2BUF 0268 SPI2 Transmit and Receive Buffer Register

TABLE 3-12: SPI2 REGISTER MAP

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24H

All

Resets

All

Resets

ADC2BUF0 0340 ADC Data Buffer 0 xxxx

— ADSIDL ADDMABM — AD12B FORM<1:0> SSRC<2:0> — SIMSAM ASAM SAMP CONV 0000

AD2CON1 0360 ADON

— — CSCNA CHPS<1:0> BUFS — SMPI<3:0> BUFM ALTS 0000

AD2CON2 0362 VCFG<2:0>

— — — SAMC<4:0> ADRC — ADCS<5:0> 0000

AD2CON3 0364

— — — — — CH123NB<1:0> CH123SB — — — — — CH123NA<1:0> CH123SA 0000

AD2CHS123 0366

— — — CH0SB<3:0> CH0NA — — — CH0SA<3:0> 0000

AD2CHS0 0368 CH0NB

— — — — — — — — — — — — — — — — 0000

Reserved 036A

AD2PCFGL 036C PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000

— — — — — — — — — — — — — — — — 0000

Reserved 036E

AD2CSSL 0370 CSS15 CSS14 CSS13 CSS12 CSS11 CSS10 CSS9 CSS8 CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 0000

— — — — — — — — — — — — — DMABL<2:0> 0000

AD2CON4 0372

— — — — — — — — — — — — — — — — 0000

037E

Reserved 0374-

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

— — CSCNA CHPS<1:0> BUFS — SMPI<3:0> BUFM ALTS 0000

— ADSIDL ADDMABM — AD12B FORM<1:0> SSRC<2:0> — SIMSAM ASAM SAMP CONV 0000

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ADC1BUF0 0300 ADC Data Buffer 0 xxxx

AD1CON1 0320 ADON

TABLE 3-13: ADC1 REGISTER MAP

AD1CON2 0322 VCFG<2:0>

— — — SAMC<4:0> ADRC — ADCS<5:0> 0000

AD1CON3 0324

— — — — — CH123NB<1:0> CH123SB — — — — — CH123NA<1:0> CH123SA 0000

AD1CHS123 0326

— — CH0SB<4:0> CH0NA — — CH0SA<4:0> 0000

AD1CHS0 0328 CH0NB

AD1PCFGH 032A PCFG31 PCFG30 PCFG29 PCFG28 PCFG27 PCFG26 PCFG25 PCFG24 PCFG23 PCFG22 PCFG21 PCFG20 PCFG19 PCFG18 PCFG17 PCFG16 0000

AD1PCFGL 032C PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000

AD1CSSH 032E CSS31 CSS30 CSS29 CSS28 CSS27 CSS26 CSS25 CSS24 CSS23 CSS22 CSS21 CSS20 CSS19 CSS18 CSS17 CSS16 0000

AD1CSSL 0330 CSS15 CSS14 CSS13 CSS12 CSS11 CSS10 CSS9 CSS8 CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 0000

— — — — — — — — — — — — — DMABL<2:0> 0000

AD1CON4 0332

— — — — — — — — — — — — — — — — 0000

033E

Reserved 0334-

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TABLE 3-14: ADC2 REGISTER MAP

PIC24H

All

Resets

— — — — —AMODE<1:0> — —MODE<1:0>0000

— — — — — — — — IRQSEL<6:0> 0000

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TABLE 3-15: DMA REGISTER MAP

DMA0CON 0380 CHEN SIZE DIR HALF NULLW

DMA0REQ 0382 FORCE

DMA0STA 0384 STA<15:0> 0000

DMA0STB 0386 STB<15:0> 0000

DMA0PAD 0388 PAD<15:0> 0000

— — — — — — CNT<9:0> 0000

DMA0CNT 038A

— — — — —AMODE<1:0> — —MODE<1:0>0000

DMA1CON 038C CHEN SIZE DIR HALF NULLW

— — — — — — — — IRQSEL<6:0> 0000

DMA1STA 0390 STA<15:0> 0000

DMA1REQ 038E FORCE

DMA1STB 0392 STB<15:0> 0000

DMA1PAD 0394 PAD<15:0> 0000

— — — — — — CNT<9:0> 0000

DMA1CNT 0396

— — — — —AMODE<1:0> — —MODE<1:0>0000

DMA2CON 0398 CHEN SIZE DIR HALF NULLW

— — — — — — — — IRQSEL<6:0> 0000

DMA2REQ 039A FORCE

DMA2STA 039C STA<15:0> 0000

DMA2STB 039E STB<15:0> 0000

DMA2PAD 03A0 PAD<15:0> 0000

— — — — — — CNT<9:0> 0000

DMA2CNT 03A2

— — — — —AMODE<1:0> — —MODE<1:0>0000

DMA3CON 03A4 CHEN SIZE DIR HALF NULLW

— — — — — — — — IRQSEL<6:0> 0000

DMA3STA 03A8 STA<15:0> 0000

DMA3REQ 03A6 FORCE

DMA3STB 03AA STB<15:0> 0000

DMA3PAD 03AC PAD<15:0> 0000

— — — — — — CNT<9:0> 0000

DMA3CNT 03AE

— — — — —AMODE<1:0> — —MODE<1:0>0000

DMA4CON 03B0 CHEN SIZE DIR HALF NULLW

— — — — — — — — IRQSEL<6:0> 0000

DMA4STA 03B4 STA<15:0> 0000

DMA4REQ 03B2 FORCE

DMA4STB 03B6 STB<15:0> 0000

DMA4PAD 03B8 PAD<15:0> 0000

— — — — — — CNT<9:0> 0000

DMA4CNT 03BA

— — — — —AMODE<1:0> — —MODE<1:0>0000

DMA5CON 03BC CHEN SIZE DIR HALF NULLW

— — — — — — — — IRQSEL<6:0> 0000

DMA5REQ 03BE FORCE

DMA5STA 03C0 STA<15:0> 0000

DMA5STB 03C2 STB<15:0> 0000

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24H

All

Resets

All

Resets

0000

FSA<4:0>

— — — — —AMODE<1:0> — —MODE<1:0>0000

— — — — — — — — IRQSEL<6:0> 0000

— — — — — — CNT<9:0> 0000

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

DMA5PAD 03C4 PAD<15:0> 0000

TABLE 3-15: DMA REGISTER MAP (CONTINUED)

DMA5CNT 03C6

DMA6STA 03CC STA<15:0> 0000

DMA6STB 03CE STB<15:0> 0000

DMA6REQ 03CA FORCE

DMA6CON 03C8 CHEN SIZE DIR HALF NULLW

DMA6PAD 03D0 PAD<15:0> 0000

— — — — — — CNT<9:0> 0000

DMA6CNT 03D2

— — — — —AMODE<1:0> — —MODE<1:0>0000

DMA7CON 03D4 CHEN SIZE DIR HALF NULLW

— — — — — — — — IRQSEL<6:0> 0000

DMA7STA 03D8 STA<15:0> 0000

DMA7REQ 03D6 FORCE

DMA7STB 03DA STB<15:0> 0000

DMA7PAD 03DC PAD<15:0> 0000

— — — — — — CNT<9:0> 0000

DMA7CNT 03DE

DMACS0 03E0 PWCOL7 PWCOL6 PWCOL5 PWCOL4 PWCOL3 PWCOL2 PWCOL1 PWCOL0 XWCOL7 XWCOL6 XWCOL5 XWCOL4 XWCOL3 XWCOL2 XWCOL1 XWCOL0 0000

— — — — LSTCH<3:0> PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 0000

DMACS1 03E2

DSADR 03E4 DSADR<15:0> 0000

— — — — — — — —

— — CSIDL ABAT CANCKS REQOP<2:0> OPMODE<2:0> — CANCAP — —WIN0480

— — — — — — — — — — — DNCNT<4:0> 0000

— — —FILHIT<4:0> — ICODE<6:0> 0000

— — FBP<5:0> — — FNRB<5:0> 0000

— — TXBO TXBP RXBP TXWAR RXWAR EWARN IVRIF WAKIF ERRIF — FIFOIF RBOVIF RBIF TBIF 0000

— — — — — — — — IVRIE WAKIE ERRIE — FIFOIE RBOVIE RBIE TBIE 0000

— — — — — — — — SJW<1:0> BRP<5:0> 0000

— WAKFIL — — — SEG2PH<2:0> SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0> 0000

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TABLE 3-16: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0 OR 1

C1CTRL2 0402

C1VEC 0404

C1CTRL1 0400

C1FIFO 0408

C1INTF 040A

C1FCTRL 0406 DMABS<2:0>

C1INTE 040C

C1EC 040E TERRCNT<7:0> RERRCNT<7:0> 0000

C1FEN1 0414 FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 FLTEN10 FLTEN9 FLTEN8 FLTEN7 FLTEN6 FLTEN5 FLTEN4 FLTEN3 FLTEN2 FLTEN1 FLTEN0 0000

C1FMSKSEL1 0418 F7MSK<1:0> F6MSK<1:0> F5MSK<1:0> F4MSK<1:0> F3MSK<1:0> F2MSK<1:0> F1MSK<1:0> F0MSK<1:0> 0000

C1CFG2 0412

C1CFG1 0410

C1FMSKSEL2 041A F15MSK<1:0> F14MSK<1:0> F13MSK<1:0> F12MSK<1:0> F11MSK<1:0> F10MSK<1:0> F9MSK<1:0> F8MSK<1:0> 0000

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24H

All

Resets

RTREN0 TX0PRI<1:0> 0000

REQ0

ERR0

LARB0

RTREN2 TX2PRI<1:0> 0000

REQ2

ERR2

LARB2

RTREN4 TX4PRI<1:0> 0000

REQ4

ERR4

LARB4

RTREN6 TX6PRI<1:0> xxxx

REQ6

ERR6

LARB6

ABAT6

ABAT4

ABAT2

ABAT0

See definition when WIN = x

RTREN7 TX7PRI<1:0> TXEN6 TX

RTREN5 TX5PRI<1:0> TXEN4 TX

RTREN3 TX3PRI<1:0> TXEN2 TX

RTREN1 TX1PRI<1:0> TXEN0 TX

REQ1

ERR1

LARB1

ABT1

REQ3

ERR3

LARB3

ABT3

REQ5

ERR5

LARB5

ABT5

REQ7

ERR7

LARB7

ABT7

041E

0400-

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TABLE 3-17: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0

C1RXFUL1 0420 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 RXFUL8 RXFUL7 RXFUL6 RXFUL5 RXFUL4 RXFUL3 RXFUL2 RXFUL1 RXFUL0 0000

C1RXFUL2 0422 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16 0000

C1RXOVF1 0428 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 0000

C1RXOVF2 042A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000

C1TR23CON 0432 TXEN3 TX

C1TR01CON 0430 TXEN1 TX

C1TR67CON 0436 TXEN7 TX

C1TR45CON 0434 TXEN5 TX

C1RXD 0440 Recieved Data Word xxxx

C1TXD 0442 Transmit Data Word xxxx

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24H

All

Resets

—MIDE—EID<17:16>xxxx

—EXIDE—EID<17:16>xxxx

See definition when WIN = x

041E

0400-

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TABLE 3-18: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1

C1BUFPNT1 0420 F3BP<3:0> F2BP<3:0> F1BP<3:0> F0BP<3:0> 0000

C1BUFPNT2 0422 F7BP<3:0> F6BP<3:0> F5BP<3:0> F4BP<3:0> 0000

C1BUFPNT3 0424 F11BP<3:0> F10BP<3:0> F9BP<3:0> F8BP<3:0> 0000

C1BUFPNT4 0426 F15BP<3:0> F14BP<3:0> F13BP<3:0> F12BP<3:0> 0000

C1RXM0SID 0430 SID<10:3> SID<2:0>

C1RXM0EID 0432 EID<15:8> EID<7:0> xxxx

C1RXM1SID 0434 SID<10:3> SID<2:0>

C1RXM1EID 0436 EID<15:8> EID<7:0> xxxx

C1RXM2SID 0438 SID<10:3> SID<2:0>

C1RXM2EID 043A EID<15:8> EID<7:0> xxxx

C1RXF0SID 0440 SID<10:3> SID<2:0>

C1RXF0EID 0442 EID<15:8> EID<7:0> xxxx

C1RXF1SID 0444 SID<10:3> SID<2:0>

C1RXF1EID 0446 EID<15:8> EID<7:0> xxxx

C1RXF2SID 0448 SID<10:3> SID<2:0>

C1RXF2EID 044A EID<15:8> EID<7:0> xxxx

C1RXF3SID 044C SID<10:3> SID<2:0>

C1RXF3EID 044E EID<15:8> EID<7:0> xxxx

C1RXF4SID 0450 SID<10:3> SID<2:0>

C1RXF4EID 0452 EID<15:8> EID<7:0> xxxx

C1RXF5SID 0454 SID<10:3> SID<2:0>

C1RXF5EID 0456 EID<15:8> EID<7:0> xxxx

C1RXF6SID 0458 SID<10:3> SID<2:0>

C1RXF6EID 045A EID<15:8> EID<7:0> xxxx

C1RXF7SID 045C SID<10:3> SID<2:0>

C1RXF7EID 045E EID<15:8> EID<7:0> xxxx

C1RXF8SID 0460 SID<10:3> SID<2:0>

C1RXF8EID 0462 EID<15:8> EID<7:0> xxxx

C1RXF9SID 0464 SID<10:3> SID<2:0>

C1RXF9EID 0466 EID<15:8> EID<7:0> xxxx

C1RXF10SID 0468 SID<10:3> SID<2:0>

C1RXF10EID 046A EID<15:8> EID<7:0> xxxx

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24H

All

Resets

—EXIDE—EID<17:16>xxxx

Resets

0000

FSA<4:0>

— — — — — — — —

— — CSIDL ABAT CANCKS REQOP<2:0> OPMODE<2:0> — CANCAP — —WIN0480

— — — — — — — — — — — DNCNT<4:0> 0000

— — —FILHIT<4:0> — ICODE<6:0> 0000

— — FBP<5:0> — — FNRB<5:0> 0000

— — TXBO TXBP RXBP TXWAR RXWAR EWARN IVRIF WAKIF ERRIF — FIFOIF RBOVIF RBIF TBI F 0000

— — — — — — — — IVRIE WAKIE ERRIE — FIFOIE RBOVIE RBIE TBIE 0000

— — — — — — — — SJW<1:0> BRP<5:0> 0000

— WAKFIL — — — SEG2PH<2:0> SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0> 0000

TABLE 3-18: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 (CONTINUED)

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

C1RXF11SID 046C SID<10:3> SID<2:0> —EXIDE—EID<17:16>xxxx

C1RXF11EID 046E EID<15:8> EID<7:0> xxxx

C1RXF12SID 0470 SID<10:3> SID<2:0>

C1RXF12EID 0472 EID<15:8> EID<7:0> xxxx

C1RXF13SID 0474 SID<10:3> SID<2:0>

C1RXF13EID 0476 EID<15:8> EID<7:0> xxxx

C1RXF14SID 0478 SID<10:3> SID<2:0>

C1RXF14EID 047A EID<15:8> EID<7:0> xxxx

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

C1RXF15SID 047C SID<10:3> SID<2:0>

C1RXF15EID 047E EID<15:8> EID<7:0> xxxx

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TABLE 3-19: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 0 OR 1

C2CTRL1 0500

C2FCTRL 0506 DMABS<2:0>

C2VEC 0504

C2FIFO 0508

C2CTRL2 0502

C2INTF 050A

C2INTE 050C

C2EC 050E TERRCNT<7:0> RERRCNT<7:0> 0000

C2CFG2 0512

C2FEN1 0514 FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 FLTEN10 FLTEN9 FLTEN8 FLTEN7 FLTEN6 FLTEN5 FLTEN4 FLTEN3 FLTEN2 FLTEN1 FLTEN0 0000

C2FMSKSEL1 0518 F7MSK<1:0> F6MSK<1:0> F5MSK<1:0> F4MSK<1:0> F3MSK<1:0> F2MSK<1:0> F1MSK<1:0> F0MSK<1:0> 0000

C2FMSKSEL2 051A F15MSK<1:0> F14MSK<1:0> F13MSK<1:0> F12MSK<1:0> F11MSK<1:0> F10MSK<1:0> F9MSK<1:0> F8MSK<1:0> 0000

C2CFG1 0510

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24H

All

Resets

RTREN0 TX0PRI<1:0> 0000

REQ0

ERR0

LARB0

RTREN2 TX2PRI<1:0> 0000

REQ2

ERR2

LARB2

RTREN4 TX4PRI<1:0> 0000

REQ4

ERR4

LARB4

RTREN6 TX6PRI<1:0> xxxx

REQ6

ERR6

LARB6

All

Resets

—MIDE—EID<17:16>xxxx

— EXIDE —EID<17:16>xxxx

ABAT0

ABAT2

ABAT4

ABAT6

See definition when WIN = x

RTREN1 TX1PRI<1:0> TXEN0 TX

RTREN3 TX3PRI<1:0> TXEN2 TX

RTREN5 TX5PRI<1:0> TXEN4 TX

RTREN7 TX7PRI<1:0> TXEN6 TX

REQ1

ERR1

LARB1

ABAT1

REQ3

ERR3

LARB3

ABAT3

REQ5

ERR5

LARB5

ABAT5

REQ7

ERR7

LARB7

ABAT7

See definition when WIN = x

051E

0500-

051E

0500-

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TABLE 3-20: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 0

C2RXFUL1 0520 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 RXFUL8 RXFUL7 RXFUL6 RXFUL5 RXFUL4 RXFUL3 RXFUL2 RXFUL1 RXFUL0 0000

C2RXFUL2 0522 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16 0000

C2RXOVF1 0528 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF09 RXOVF08 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 0000

C2RXOVF2 052A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000

C2TR01CON 0530 TXEN1 TX

C2TR23CON 0532 TXEN3 TX

C2TR45CON 0534 TXEN5 TX

C2TR67CON 0536 TXEN7 TX

C2RXD 0540 Recieved Data Word xxxx

C2TXD 0542 Transmit Data Word xxxx

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TABLE 3-21: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 1

C2BUFPNT1 0520 F3BP<3:0> F2BP<3:0> F1BP<3:0> F0BP<3:0> 0000

C2BUFPNT2 0522 F7BP<3:0> F6BP<3:0> F5BP<3:0> F4BP<3:0> 0000

C2BUFPNT3 0524 F12BP<3:0> F10BP<3:0> F9BP<3:0> F8BP<3:0> 0000

C2BUFPNT4 0526 F15BP<3:0> F14BP<3:0> F13BP<3:0> F12BP<3:0> 0000

C2RXM0SID 0530 SID<10:3> SID<2:0>

C2RXM0EID 0532 EID<15:8> EID<7:0> xxxx

C2RXM1SID 0534 SID<10:3> SID<2:0>

C2RXM1EID 0536 EID<15:8> EID<7:0> xxxx

C2RXM2SID 0538 SID<10:3> SID<2:0>

C2RXM2EID 053A EID<15:8> EID<7:0> xxxx

C2RXF0SID 0540 SID<10:3> SID<2:0>

C2RXF0EID 0542 EID<15:8> EID<7:0> xxxx

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24H

All

Resets

— EXIDE —EID<17:16>xxxx

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TABLE 3-21: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 1 (CONTINUED)

C2RXF1SID 0544 SID<10:3> SID<2:0> — EXIDE —EID<17:16>xxxx

C2RXF1EID 0546 EID<15:8> EID<7:0> xxxx

C2RXF2SID 0548 SID<10:3> SID<2:0>

C2RXF2EID 054A EID<15:8> EID<7:0> xxxx

C2RXF3SID 054C SID<10:3> SID<2:0>

C2RXF3EID 054E EID<15:8> EID<7:0> xxxx

C2RXF4SID 0550 SID<10:3> SID<2:0>

C2RXF4EID 0552 EID<15:8> EID<7:0> xxxx

C2RXF5SID 0554 SID<10:3> SID<2:0>

C2RXF5EID 0556 EID<15:8> EID<7:0> xxxx

C2RXF6SID 0558 SID<10:3> SID<2:0>

C2RXF6EID 055A EID<15:8> EID<7:0> xxxx

C2RXF7SID 055C SID<10:3> SID<2:0>

C2RXF7EID 055E EID<15:8> EID<7:0> xxxx

C2RXF8SID 0560 SID<10:3> SID<2:0>

C2RXF8EID 0562 EID<15:8> EID<7:0> xxxx

C2RXF9SID 0564 SID<10:3> SID<2:0>

C2RXF9EID 0566 EID<15:8> EID<7:0> xxxx

C2RXF10SID 0568 SID<10:3> SID<2:0>

C2RXF10EID 056A EID<15:8> EID<7:0> xxxx

C2RXF11SID 056C SID<10:3> SID<2:0>

C2RXF11EID 056E EID<15:8> EID<7:0> xxxx

C2RXF12SID 0570 SID<10:3> SID<2:0>

C2RXF12EID 0572 EID<15:8> EID<7:0> xxxx

C2RXF13SID 0574 SID<10:3> SID<2:0>

C2RXF13EID 0576 EID<15:8> EID<7:0> xxxx

C2RXF14SID 0578 SID<10:3> SID<2:0>

C2RXF14EID 057A EID<15:8> EID<7:0> xxxx

C2RXF15SID 057C SID<10:3> SID<2:0>

C2RXF15EID 057E EID<15:8> EID<7:0> xxxx

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24H

All

D6C0

xxxx

Resets

xxxx

All

FFFF

xxxx

Resets

xxxx

All

F01E

xxxx

Resets

xxxx

RC4 RC3 RC2 RC1 —

LATC4 LATC3 LATC2 LATC1 —

TRISC4 TRISC3 TRISC2 TRISC1 —

All

FFFF

xxxx

Resets

xxxx

RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0

LATD11 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0

TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0

(1)

RA15 RA14 RA13 RA12 — RA10 RA9 — RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0

LATA15 LATA14 LATA13 LATA12 — L ATA 10 LAT A9 — L ATA 7 LA TA6 LATA 5 L ATA4 L ATA3 L ATA2 LATA 1 L ATA0

TRISA15 TRISA14 TRISA13 TRISA12 — TRISA10 TRISA9 — TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TABLE 3-22: PORTA REGISTER MAP

TRISA 02C0

ODCA15 ODCA14 ODCA13 ODCA12 — — — — — — ODCA5 ODCA4 ODCA3 ODCA2 ODCA1 ODCA0

06C0

(2)

PORTA 02C2

LATA 02C4

ODCA

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.

(1)

Note 1: The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TRISB 02C6 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0

PORTB 02C8 RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0

LATB 02CA LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0

TABLE 3-23: PORTB REGISTER MAP

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.

(1)

Note 1: The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TRISC 02CC TRISC15 TRISC14 TRISC13 TRISC12 — — — — — — —

PORTC 02CE RC15 RC14 RC13 RC12 — — — — — — —

LATC 02D0 LATC15 LATC14 LATC13 LATC12 — — — — — — —

TABLE 3-24: PORTC REGISTER MAP

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.

(1)

RD15 RD14 RD13 RD12

LATD15 LATD14 LATD13 LATD12

TRISD15 TRISD14 TRISD13 TRISD12

Note 1: The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TABLE 3-25: PORTD REGISTER MAP

TRISD 02D2

ODCD15 ODCD14 ODCD13 ODCD12 ODCD11 ODCD10 ODCD9 ODCD8 ODCD7 ODCD6 ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 ODCD0

06D2

(2)

PORTD 02D4

LATD 02D6

ODCD

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.

Note 1: The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.

PIC24H

All

31FF

xxxx

03FF

xxxx

TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0

RE6 RE5 RE4 RE3 RE2 RE1 RE0

xxxx

LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0

TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0

Resets

xxxx

All

F3CF

xxxx

Resets

xxxx

(1)

TRISE8 TRISE7

RE8 RE7

LATE8 LATE7

TRISF8 TRISF7

— — —

(1)

TRISF13 TRISF12

ODCF8 ODCF7 ODCF6 ODCF5 ODCF4 ODCF3 ODCF2 ODCF1 ODCF0

ODCG9 ODCG8 ODCG7 ODCG6 — — ODCG3 ODCG2 ODCG1 ODCG0

— — — RF8 RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0

— — — LATF8 LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0

— — —

— —

(1)

RF13 RF12

LATF13 LATF12

ODCF13 ODCF12

RG15 RG14 RG13 RG12 — — RG9 RG8 RG7 RG6 — —RG3RG2RG1RG0

LATG15 LATG14 LATG13 LATG12 — —LATG9LATG8LATG7LATG6 — — LATG3 LATG2 LATG1 LATG0

TRISG15 TRISG14 TRISG13 TRISG12 — — TRISG9 TRISG8 TRISG7 TRISG6 — — TRISG3 TRISG2 TRISG1 TRISG0

06DE — —

ODCG15 ODCG14 ODCG13 ODCG12

06E4

(2)

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TRISE 02D8 — — — — — — TRISE9

PORTE 02DA — — — — — —RE9

LATE 02DC — — — — — —LATE9

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.

TABLE 3-26: PORTE REGISTER MAP

Note 1: The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets

TRISF 02DE — —

PORTF 02E0 — —

LATF 02E2 — —

ODCF

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.

TABLE 3-27: PORTF REGISTER MAP

Note 1: The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TABLE 3-28: PORTG REGISTER MAP

TRISG 02E4

(2)

PORTG 02E6

LATG 02E8

ODCG

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.

Note 1: The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.

PIC24H

All

(2)

(3)

(1)

xxxx

Resets

(3)

(1)

All

0000

Resets

All

Resets

I2C1MD U2MD U1MD SPI2MD SPI1MD C2MD C1MD AD1MD 0000

— — —

— — — — — — — — — —I2C2MDAD2MD0000

— — — — — — — — NVMKEY<7:0>

2: OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset.

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

RCON 0740 TRAPR IOPUWR — — — — — VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR

OSCCON 0742 —COSC<2:0>— NOSC<2:0> CLKLOCK —LOCK—CF— LPOSCEN OSWEN 0300

TABLE 3-29: SYSTEM CONTROL REGISTER MAP

CLKDIV 0744 ROI DOZE<2:0> DOZEN FRCDIV<2:0> PLLPOST<1:0> — PLLPRE<4::0> 0040

PLLFBD 0746 — — — — — — — PLLDIV<8:0> 0030

OSCTUN 0748 — — — — — — — — — — TUN<5:0> 0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: RCON register Reset values dependent on type of Reset.

TABLE 3-30: NVM REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

NVMCON 0760 WR WREN WRERR — — — — — — ERASE — —NVMOP<3:0>

NVMKEY 0766

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TABLE 3-31: PMD REGISTER MAP

PMD1 0770 T5MD T4MD T3MD T2MD T1MD

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PMD2 0772 IC8MD IC7MD IC6MD IC5MD IC4MD IC3MD IC2MD IC1MD OC8MD OC7MD OC6MD OC5MD OC4MD OC3MD OC2MD OC1MD 0000

PMD3 0774 T9MD T8MD T7MD T6MD

PIC24H

3.2.6 SOFTWARE STACK

In addition to its use as a working register, the W15 register in the PIC24H devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as shown in Figure 3-5. For a PC push during any CALL instruction, the MSB of the PC is zero-extended before the push, ensuring that the MSB is always clear.

Note: A PC push during exception processing

concatenates the SRL register to the MSB of the PC prior to the push.

The Stack Pointer Limit register (SPLIM) associated with the Stack Pointer sets an upper address boundary for the stack. SPLIM is uninitialized at Reset. As is the case for the Stack Pointer, SPLIM<0> is forced to ‘0’ because all stack operations must be word-aligned. Whenever an EA is generated using W15 as a source or destination pointer, the resulting address is compared with the value in SPLIM. If the contents of the Stack Pointer (W15) and the SPLIM register are equal and a push operation is performed, a stack error trap will not occur. The stack error trap will occur on a subsequent push operation. Thus, for example, if it is desirable to cause a stack error trap when the stack grows beyond address 0x2000 in RAM, initialize the SPLIM with the value 0x1FFE.

Similarly, a Stack Pointer underflow (stack error) trap is generated when the Stack Pointer address is found to be less than 0x0800. This prevents the stack from interfering with the Special Function Register (SFR) space.

A write to the SPLIM register should not be immediately followed by an indirect read operation using W15.

FIGURE 3-5: CALL STACK FRAME

0x0000

015

3.3 Instruction Addressing Modes

The addressing modes in Table 3-32 form the basis of the addressing modes optimized to support the specific features of individual instructions. The addressing modes provided in the MAC class of instructions are somewhat different from those in the other instruction types.

3.3.1 FILE REGISTER INSTRUCTIONS

Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (Near Data Space). Most file register instructions employ a working register, W0, which is denoted as WREG in these instructions. The destination is typically either the same file register or WREG (with the exception of the MUL instruction), which writes the result to a register or register pair. The MOV instruction allows additional flexibility and can access the entire data space.

3.3.2 MCU INSTRUCTIONS

The 3-operand MCU instructions are of the form:

Operand 3 = Operand 1 <function> Operand 2

where Operand 1 is always a working register (i.e., the addressing mode can only be register direct) which is referred to as Wb. Operand 2 can be a W register, fetched from data memory, or a 5-bit literal. The result location can be either a W register or a data memory location. The following addressing modes are supported by MCU instructions:

• Register Direct

• Register Indirect

• Register Indirect Post-Modified

• Register Indirect Pre-Modified

• 5-bit or 10-bit Literal

Note: Not all instructions support all the

addressing modes given above. Individual instructions may support different subsets of these addressing modes.

PC<15:0>

000000000

Higher Address

Stack Grows Towards

PC<22:16>

W15 (before CALL)

W15 (after CALL)

POP : [--W15] PUSH : [W15++]

PIC24H

TABLE 3-32: FUNDAMENTAL ADDRESSING MODES SUPPORTED

Addressing Mode Description

File Register Direct The address of the file register is specified explicitly.

decremented) by a constant value.

to form the EA.

3.3.3 MOVE INSTRUCTIONS

Move instructions provide a greater degree of addressing flexibility than other instructions. In addition to the Addressing modes supported by most MCU instructions, move instructions also support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode.

Note: For the MOV instructions, the Addressing

mode specified in the instruction can differ for the source and destination EA. However, the 4-bit Wb (Register Offset) field is shared between both source and destination (but typically only used by one).

In summary, the following Addressing modes are supported by move instructions:

• Register Direct

• Register Indirect

• Register Indirect Post-modified

• Register Indirect Pre-modified

• Register Indirect with Register Offset (Indexed)

• Register Indirect with Literal Offset

• 8-bit Literal

• 16-bit Literal

Note: Not all instructions support all the

Addressing modes given above. Individual instructions may support different subsets of these Addressing modes.

3.3.4 OTHER INSTRUCTIONS

Besides the various addressing modes outlined above, some instructions use literal constants of various sizes. For example, BRA (branch) instructions use 16-bit signed literals to specify the branch destination directly, whereas the DISI instruction uses a 14-bit unsigned literal field. In some instructions, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands.

3.4 Interfacing Program and Data Memory Spaces

The PIC24H architecture uses a 24-bit wide program space and a 16-bit wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces.

Aside from normal execution, the PIC24H architecture provides two methods by which program space can be accessed during operation:

• Using table instructions to access individual bytes

or words anywhere in the program space

• Remapping a portion of the program space into

the data space (Program Space Visibility)

Table instructions allow an application to read or write to small areas of the program memory. This capability makes the method ideal for accessing data tables that need to be updated from time to time. It also allows access to all bytes of the program word. The remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look ups from a large table of static data. It can only access the least significant word of the program word.

3.4.1 ADDRESSING PROGRAM SPACE

Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. The solution depends on the interface method to be used.

For table operations, the 8-bit Table Page register (TBLPAG) is used to define a 32K word region within the program space. This is concatenated with a 16-bit EA to arrive at a full 24-bit program space address. In this format, the Most Significant bit of TBLPAG is used to determine if the operation occurs in the user memory (TBLPAG<7> = 0) or the configuration memory (TBLPAG<7> = 1).

PIC24H

For remapping operations, the 8-bit Program Space Visibility register (PSVPAG) is used to define a 16K word page in the program space. When the Most Significant bit of the EA is ‘1’, PSVPAG is concatenated with the lower 15 bits of the EA to form a 23-bit program space address. Unlike table operations, this limits remapping operations strictly to the user memory area.

Table 3-33 and Figure 3-6 show how the program EA is created for table operations and remapping accesses from the data EA. Here, P<23:0> refers to a program space word, whereas D<15:0> refers to a data space word.

TABLE 3-33: PROGRAM SPACE ADDRESS CONSTRUCTION

Access Type

Instruction Access (Code Execution)

TBLRD/TBLWT

(Byte/Word Read/Write)

Program Space Visibility (Block Remap/Read)

Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of

the address is PSVPAG<0>.

Access

Space

User 0 PC<22:1> 0

User TBLPAG<7:0> Data EA<15:0>

Configuration TBLPAG<7:0> Data EA<15:0>

User 0 PSVPAG<7:0> Data EA<14:0>

<23> <22:16> <15> <14:1> <0>

0xx xxxx xxxx xxxx xxxx xxx0

0xxx xxxx xxxx xxxx xxxx xxxx

1xxx xxxx xxxx xxxx xxxx xxxx

0 xxxx xxxx xxx xxxx xxxx xxxx

Program Space Address

(1)

PIC24H

FIGURE 3-6: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

Program Counter

Table Operations

Program Space Visibility (Remapping)

(1)

(2)

User/Configuration

1/0

(1)

Space Select

TBLPAG

8 bits

Select

PSVPAG

8 bits

23 bits

24 bits

23 bits

16 bits

15 bits

0Program Counter

1/0

Byte Select

Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word

alignment of data in the program and data spaces.

2: Table operations are not required to be word-aligned. Table read operations are permitted

in the configuration memory space.

PIC24H

3.4.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS

The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data.

The PC is incremented by two for each successive 24-bit program word. This allows program memory addresses to directly map to data space addresses. Program memory can thus be regarded as two 16-bit word wide address spaces, residing side by side, each with the same address range. TBLRDL and TBLWTL access the space which contains the least significant data word and TBLRDH and TBLWTH access the space which contains the upper data byte.

Two table instructions are provided to move byte or word sized (16-bit) data to and from program space. Both function as either byte or word operations.

1. TBLRDL (Table Read Low): In Word mode, it

maps the lower word of the program space location (P<15:0>) to a data address (D<15:0>).

In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower byte is selected when it is ‘0’.

2. TBLRDH (Table Read High): In Word mode, it maps the entire upper word of a program address (P<23:16>) to a data address. Note that D<15:8>, the ‘phantom byte’, will always be ‘0’.

In Byte mode, it maps the upper or lower byte of the program word to D<7:0> of the data address, as above. Note that the data will always be ‘0’ when the upper ‘phantom’ byte is selected (Byte Select = 1).

In a similar fashion, two table instructions, TBLWTH and TBLWTL, are used to write individual bytes or words to a program space address. The details of their operation are explained in Section 4.0 “Flash Program Memory”.

For all table operations, the area of program memory space to be accessed is determined by the Table Page register (TBLPAG). TBLPAG covers the entire program memory space of the device, including user and configuration spaces. When TBLPAG<7> = 0, the table page is located in the user memory space. When TBLPAG<7> = 1, the page is located in configuration space.

FIGURE 3-7: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS

TBLPAG

23 15 0

0x000000

0x020000

0x030000

0x800000

Program Space

00000000

‘Phantom’ Byte

TBLRDH.B (Wn<0> = 0)

TBLRDL.B (Wn<0> = 1)

TBLRDL.B (Wn<0> = 0)

TBLRDL.W

The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in the user memory area.

081623

PIC24H

3.4.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY

The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This option provides transparent access of stored constant data from the data space without the need to use special instructions (i.e., TBLRDL/H).

Program space access through the data space occurs if the Most Significant bit of the data space EA is ‘1’ and program space visibility is enabled by setting the PSV bit in the Core Control register (CORCON<2>). The location of the program memory space to be mapped into the data space is determined by the Program Space Visibility Page register (PSVPAG). This 8-bit register defines any one of 256 possible pages of 16K words in program space. In effect, PSVPAG functions as the upper 8 bits of the program memory address, with the 15 bits of the EA functioning as the lower bits. Note that by incrementing the PC by 2 for each program memory word, the lower 15 bits of data space addresses directly map to the lower 15 bits in the corresponding program space addresses.

Data reads to this area add an additional cycle to the instruction being executed, since two program memory fetches are required.

Although each data space address, 8000h and higher, maps directly into a corresponding program memory address (see Figure 3-8), only the lower 16 bits of the

24-bit program word are used to contain the data. The upper 8 bits of any program space location used as data should be programmed with ‘1111 1111’ or ‘0000 0000’ to force a NOP. This prevents possible issues should the area of code ever be accidentally executed.

Note: PSV access is temporarily disabled during

table reads/writes.

For operations that use PSV and are executed outside a REPEAT loop, the MOV and MOV.D instructions require one instruction cycle in addition to the specified execution time. All other instructions require two instruction cycles in addition to the specified execution time.

For operations that use PSV, which are executed inside a REPEAT loop, there will be some instances that require two instruction cycles in addition to the specified execution time of the instruction:

• Execution in the first iteration

• Execution in the last iteration

• Execution prior to exiting the loop due to an interrupt

• Execution upon re-entering the loop after an interrupt is serviced

Any other iteration of the REPEAT loop will allow the instruction accessing data, using PSV, to execute in a single cycle.

FIGURE 3-8: PROGRAM SPACE VISIBILITY OPERATION

When CORCON<2> = 1 and EA<15> = 1:

Program Space

PSVPAG

The data in the page designated by PSVPAG is mapped into the upper half of the data memory space...

23 15 0

0x000000

0x010000

0x018000

0x800000

Data Space

PSV Area

0x0000

0x8000

0xFFFF

Data EA<14:0>

...while the lower 15 bits of the EA specify an exact address within the PSV area. This corresponds exactly to the same lower 15 bits of the actual program space address.

PIC24H

NOTES:

PIC24H

4.0 FLASH PROGRAM MEMORY

Note: This data sheet summarizes the features

The PIC24H devices contain internal Flash program memory for storing and executing application code. The memory is readable, writable and erasable during normal operation over the entire V

Flash memory can be programmed in two ways:

1. In-Circuit Serial Programming™ (ICSP™)

2. Run-Time Self-Programming (RTSP)

ICSP allows a PIC24H device to be serially programmed while in the end application circuit. This is simply done with two lines for programming clock and programming data (one of the alternate programming pin pairs: PGC1/PGD1, PGC2/PGD2 or PGC3/PGD3, and three other lines for power (V Master Clear (MCLR

). This allows customers to manufacture boards with unprogrammed devices and then program the digital signal controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed.

DD range.

DD), ground (VSS) and

RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user can write program memory data in blocks or ‘rows’ of 64 instructions (192 bytes) at a time, and erase program memory in blocks or ‘pages’ of 512 instructions (1536 bytes) at a time.

4.1 Table Instructions and Flash

Programming

Regardless of the method used, all programming of Flash memory is done with the table read and table write instructions. These allow direct read and write access to the program memory space from the data memory while the device is in normal operating mode. The 24-bit target address in the program memory is formed using bits<7:0> of the TBLPAG register and the Effective Address (EA) from a W register specified in the table instruction, as shown in Figure 4-1.

The TBLRDL and the TBLWTL instructions are used to read or write to bits<15:0> of program memory. TBLRDL and TBLWTL can access program memory in both Word and Byte modes.

The TBLRDH and TBLWTH instructions are used to read or write to bits<23:16> of program memory. TBLRDH and TBLWTH can also access program memory in Word or Byte mode.

FIGURE 4-1: ADDRESSING FOR TABLE REGISTERS

24 bits

Using Program Counter

Using Table Instruction

User/Configuration Space Select

1/0

TBLPAG Reg

8 bits

Program Counter

Working Reg EA

24-bit EA

16 bits

Byte Select

PIC24H

4.2 RTSP Operation

The PIC24H Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user to erase a page of memory, which consists of eight rows (512 instructions) at a time, and to program one row at a time. The 8-row erase pages and single row write rows are edge-aligned, from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively.

The program memory implements holding buffers that can contain 64 instructions of programming data. Prior to the actual programming operation, the write data must be loaded into the buffers in sequential order. The instruction words loaded must always be from a group of 64 boundary.

The basic sequence for RTSP programming is to set up a Table Pointer, then do a series of TBLWT instructions to load the buffers. Programming is performed by setting the control bits in the NVMCON register. A total of 64 TBLWTL and TBLWTH instructions are required to load the instructions.

All of the table write operations are single-word writes (two instruction cycles) because only the buffers are written. A programming cycle is required for programming each row.

4.3 Control Registers

There are two SFRs used to read and write the program Flash memory: NVMCON and NVMKEY.

The NVMCON register (Register 4-1) controls which blocks are to be erased, which memory type is to be programmed and the start of the programming cycle.

NVMKEY is a write-only register that is used for write protection. To start a programming or erase sequence, the user must consecutively write 55h and AAh to the NVMKEY register. Refer to Section 4.4 “Programming

Operations” for further details.

4.4 Programming Operations

A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. A programming operation is nominally 4 ms in duration and the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON<15>) starts the operation, and the WR bit is automatically cleared when the operation is finished.

PIC24H

REGISTER 4-1: NVMCOM: FLASH MEMORY CONTROL REGISTER

R/SO-0

(1)

WR WREN WRERR — — — — —

bit 15 bit 8

R/W-0

(1)

R/W-0

(1)

U-0 U-0 U-0 U-0 U-0

U-0 R/W-0

(1)

U-0 U-0 R/W-0

— ERASE — —NVMOP<3:0>

(1)

R/W-0

(1)

R/W-0

(2)

(1)

R/W-0

(1)

bit 7 bit 0

Legend: SO = Satiable only bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 WR: Write Control bit

1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is

cleared by hardware once operation is complete.

0 = Program or erase operation is complete and inactive

bit 14 WREN: Write Enable bit

1 = Enable Flash program/erase operations 0 = Inhibit Flash program/erase operations

bit 13 WRERR: Write Sequence Error Flag bit

1 = An improper program or erase sequence attempt or termination has occurred (bit is set

automatically on any set attempt of the WR bit)

0 = The program or erase operation completed normally

bit 12-7 Unimplemented: Read as ‘0’

bit 6 ERASE: Erase/Program Enable bit

1 = Perform the erase operation specified by NVMOP<3:0> on the next WR command 0 = Perform the program operation specified by NVMOP<3:0> on the next WR command

bit 5-4 Unimplemented: Read as ‘0’

(2)

bit 3-0 NVMOP<3:0>: NVM Operation Select bits

1111 = Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0) 0011 = Memory word program operation (ERASE = 0) or no operation (ERASE = 1) 0010 = Memory page erase operation (ERASE = 1) or no operation (ERASE = 0) 0001 = Memory row program operation (ERASE = 0) or no operation (ERASE = 1) 0000 = Program or erase a single Configuration register byte

Note 1: These bits can only be reset on POR.

2: All other combinations of NVMOP<3:0> are unimplemented.

PIC24H

4.4.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY

The user can program one row of program Flash memory at a time. To do this, it is necessary to erase the 8-row erase page that contains the desired row. The general process is:

1. Read eight rows of program memory

(512 instructions) and store in data RAM.

2. Update the program data in RAM with the

desired new data.

3. Erase the page (see Example 4-1):

a) Set the NVMOP bits (NVMCOM<3:0>) to

‘0010’ to configure for block erase. Set the ERASE (NVMCOM<6>) and WREN (NVMCOM<14>) bits.

b) Write the starting address of the page to be

erased into the TBLPAG and W registers.

c) Perform a dummy table write operation

(TBLWTL) to any address within the page

that needs to be erased. d) Write 0x55 to NVMKEY. e) Write 0xAA to NVMKEY. f) Set the WR bit (NVMCOM<15>). The erase

cycle begins and the CPU stalls for the dura-

tion of the erase cycle. When the erase is

done, the WR bit is cleared automatically.

4. Write the first 64 instructions from data RAM into the program memory buffers (see Example 4-2).

5. Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure

for row programming. Clear the ERASE bit

and set the WREN bit. b) Write 0x55 to NVMKEY. c) Write 0xAA to NVMKEY. d) Set the WR bit. The programming cycle

begins and the CPU stalls for the duration of

the write cycle. When the write to Flash mem-

ory is done, the WR bit is cleared

automatically.

6. Repeat steps 4 and 5, using the next available 64 instructions from the block in data RAM by incrementing the value in TBLPAG, until all 512 instructions are written back to Flash memory.

For protection against accidental operations, the write initiate sequence for NVMKEY must be used to allow any erase or program operation to proceed. After the programming command has been executed, the user must wait for the programming time until programming is complete. The two instructions following the start of the programming sequence should be NOPs, as shown in Example 4-3.

EXAMPLE 4-1: ERASING A PROGRAM MEMORY PAGE

; Set up NVMCON for block erase operation

MOV #0x4042, W0 ; MOV W0, NVMCON ; Initialize NVMCON

; Init pointer to row to be ERASED

Note: A program memory page erase operation

MOV #tblpage(PROG_ADDR), W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #tbloffset(PROG_ADDR), W0 ; Initialize in-page EA<15:0> pointer TBLWTL W0, [W0] ; Set base address of erase block DISI #5 ; Block all interrupts with priority <7

; for next 5 instructions MOV #0x55, W0 MOV W0, NVMKEY ; Write the 55 key MOV #0xAA, W1 ; MOV W1, NVMKEY ; Write the AA key BSET NVMCON, #WR ; Start the erase sequence NOP ; Insert two NOPs after the erase NOP ; command is asserted

is set up by performing a dummy table write (TBLWTL) operation to any address within the page. This methodology is different from the page erase operation on dsPIC30F devices in which the erase page was selected using a dedicated pair of registers (NVMADRU and NVMADR).

EXAMPLE 4-2: LOADING THE WRITE BUFFERS

; Set up NVMCON for row programming operations

; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled

; Perform the TBLWT instructions to write the latches ; 0th_program_word

; 1st_program_word

; 2nd_program_word

; 63rd_program_word

MOV #0x4001, W0 ; MOV W0, NVMCON ; Initialize NVMCON

MOV #0x0000, W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #0x6000, W0 ; An example program memory address

MOV #LOW_WORD_0, W2 ; MOV #HIGH_BYTE_0, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch

MOV #LOW_WORD_1, W2 ; MOV #HIGH_BYTE_1, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch

MOV #LOW_WORD_2, W2 ; MOV #HIGH_BYTE_2, W3 ; TBLWTL W2, TBLWTH W3,

•

MOV #LOW_WORD_31, W2 ; MOV #HIGH_BYTE_31, W3 ; TBLWTL W2, TBLWTH W3,

[W0] ; Write PM low word into program latch [W0++] ; Write PM high byte into program latch

PIC24H

EXAMPLE 4-3: INITIATING A PROGRAMMING SEQUENCE

DISI #5 ; Block all interrupts with priority <7

MOV #0x55, W0 MOV W0, NVMKEY ; Write the 55 key MOV #0xAA, W1 ; MOV W1, NVMKEY ; Write the AA key BSET NVMCON, #WR ; Start the erase sequence NOP ; Insert two NOPs after the NOP ; erase command is asserted

; for next 5 instructions

PIC24H

NOTES:

PIC24H

5.0 RESETS

Note: This data sheet summarizes the features

The Reset module combines all Reset sources and controls the device Master Reset Signal, SYSRST following is a list of device Reset sources:

• POR: Power-on Reset

•MCLR

: Master Clear Pin Reset

•SWR: RESET Instruction

• WDT: Watchdog Timer Reset

• TRAPR: Trap Conflict Reset

• IOPUWR: Illegal Opcode and Uninitialized W Register Reset

A simplified block diagram of the Reset module is shown in Figure 5-1.

Any active source of Reset will make the SYSRST nal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. Most registers are unaffected by a Reset; their status is unknown on POR and unchanged by all other Resets.

. The

sig-

Note: Refer to the specific peripheral or CPU

section of this manual for register Reset states.

All types of device Reset will set a corresponding status bit in the RCON register to indicate the type of Reset (see Register 5-1). A POR will clear all bits, except for the POR bit (RCON<0>), that are set. The user can set or clear any bit at any time during code execution. The RCON bits only serve as status bits. Setting a particular Reset status bit in software does not cause a device Reset to occur.

The RCON register also has other bits associated with the Watchdog Timer and device power-saving states. The function of these bits is discussed in other sections of this manual.

Note: The status bits in the RCON register

should be cleared after they are read so that the next RCON register value after a device Reset will be meaningful.

FIGURE 5-1: RESET SYSTEM BLOCK DIAGRAM

RESET Instruction

Glitch Filter

MCLR

WDT

Module

Sleep or Idle

VDD Rise

Detect

VDD

Internal

Regulator

Trap Conflict

Illegal Opcode

Uninitialized W Register

POR

BOR

SYSRST

PIC24H

R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0

TRAPR IOPUWR

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1

EXTR SWR SWDTEN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 TRAPR: Trap Reset Flag bit

1 = A Trap Conflict Reset has occurred 0 = A Trap Conflict Reset has not occurred

bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit

1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an

Address Pointer caused a Reset

0 = An illegal opcode or uninitialized W Reset has not occurred

bit 13-9 Unimplemented: Read as ‘0’

bit 8 VREGS: Voltage Regulator Standby During Sleep bit

1 = Voltage regulator goes into Standby mode during Sleep 0 = Voltage regulator is active during Sleep

bit 7 EXTR: External Reset (MCLR

1 = A Master Clear (pin) Reset has occurred 0 = A Master Clear (pin) Reset has not occurred

bit 6 SWR: Software Reset (Instruction) Flag bit

1 = A RESET instruction has been executed 0 = A RESET instruction has not been executed

bit 5 SWDTEN: Software Enable/Disable of WDT bit

1 = WDT is enabled 0 = WDT is disabled

bit 4 WDTO: Watchdog Timer Time-out Flag bit

1 = WDT time-out has occurred 0 = WDT time-out has not occurred

bit 3 SLEEP: Wake-up from Sleep Flag bit

1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode

bit 2 IDLE: Wake-up from Idle Flag bit

1 = Device was in Idle mode 0 = Device was not in Idle mode

bit 1 BOR: Brown-out Reset Flag bit

1 = A Brown-out Reset has occurred 0 = A Brown-out Reset has not occurred

— — — — —VREGS

(2)

WDTO SLEEP IDLE BOR POR

) Pin bit

(1)

(2)

Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not

cause a device Reset.

2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the

SWDTEN bit setting.

PIC24H

bit 0 POR: Power-on Reset Flag bit

1 = A Power-up Reset has occurred 0 = A Power-up Reset has not occurred

Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not

cause a device Reset.

2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the

SWDTEN bit setting.

(1)

TABLE 5-1: RESET FLAG BIT OPERATION

Flag Bit Setting Event Clearing Event

TRAPR (RCON<15>) Trap conflict event POR

IOPUWR (RCON<14>) Illegal opcode or uninitialized

W register access

EXTR (RCON<7>) MCLR

SWR (RCON<6>) RESET instruction POR

WDTO (RCON<4>) WDT time-out PWRSAV instruction, POR

SLEEP (RCON<3>) PWRSAV #SLEEP instruction POR

IDLE (RCON<2>) PWRSAV #IDLE instruction POR

BOR (RCON<1> BOR —

POR (RCON<0>) POR —

Note: All Reset flag bits may be set or cleared by the user software.

Reset POR

POR

5.1 Clock Source Selection at Reset

If clock switching is enabled, the system clock source at device Reset is chosen, as shown in Table 5-2. If clock switching is disabled, the system clock source is always selected according to the oscillator Configuration bits. Refer to Section 8.0 “Oscillator Configuration” for further details.

TABLE 5-2: OSCILLATOR SELECTION vs.

TYPE OF RESET (CLOCK SWITCHING ENABLED)

Reset Type Clock Source Determinant

POR Oscillator Configuration bits

BOR

MCLR

WDTR

SWR

(FNOSC<2:0>)

COSC Control bits (OSCCON<14:12>)

5.2 Device Reset Times

The Reset times for various types of device Reset are summarized in Table 5-3. The system Reset signal is released after the POR and PWRT delay times expire.

The time at which the device actually begins to execute code also depends on the system oscillator delays, which include the Oscillator Start-up Timer (OST) and the PLL lock time. The OST and PLL lock times occur in parallel with the applicable reset delay times.

The FSCM delay determines the time at which the FSCM begins to monitor the system clock source after the reset signal is released.

PIC24H

TABLE 5-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS

Reset Type Clock Source SYSRST

POR EC, FRC, LPRC T

ECPLL, FRCPLL T

XT, HS, SOSC T

POR

Delay

+ TSTARTUP + TRST ——1, 2, 3

+ TSTARTUP + TRST TLOCK TFSCM 1, 2, 3, 5, 6

+ TSTARTUP + TRST TOST TFSCM 1, 2, 3, 4, 6

System Clock

Delay

XTPLL, HSPLL TPOR + TSTARTUP + TRST TOST + TLOCK TFSCM 1, 2, 3, 4, 5, 6

MCLR

Any Clock TRST ——3

WDT Any Clock TRST ——3

Software Any clock T

RST ——3

Illegal Opcode Any Clock TRST ——3

Uninitialized W Any Clock TRST ——3

Trap Conflict Any Clock T

RST ——3

Note 1: TPOR = Power-on Reset delay (10 μs nominal).

2: TSTARTUP = Conditional POR delay of 20 μs nominal (if on-chip regulator is enabled) or 64 ms nominal

Power-up Timer delay (if regulator is disabled). T

STARTUP is also applied to all returns from powered-down

states, including waking from Sleep mode, only if the regulator is enabled.

RST = Internal state Reset time (20 μs nominal).

3: T 4: TOST = Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the

oscillator clock to the system.

LOCK = PLL lock time (20 μs nominal).

5: T 6: T

FSCM = Fail-Safe Clock Monitor delay (100 μs nominal).

FSCM Delay

Notes

5.2.1 POR AND LONG OSCILLATOR START-UP TIMES

The oscillator start-up circuitry and its associated delay timers are not linked to the device Reset delays that occur at power-up. Some crystal circuits (especially low-frequency crystals) have a relatively long start-up time. Therefore, one or more of the following conditions is possible after the reset signal is released:

• The oscillator circuit has not begun to oscillate.

• The Oscillator Start-up Timer has not expired (if a

crystal oscillator is used).

• The PLL has not achieved a lock (if PLL is used).

The device will not begin to execute code until a valid clock source has been released to the system. Therefore, the oscillator and PLL start-up delays must be considered when the Reset delay time must be known.

5.2.2 FAIL-SAFE CLOCK MONITOR (FSCM) AND DEVICE RESETS

If the FSCM is enabled, it begins to monitor the system clock source when the reset signal is released. If a valid clock source is not available at this time, the device automatically switches to the FRC oscillator and the user can switch to the desired crystal oscillator in the Trap Service Routine.

5.2.2.1 FSCM Delay for Crystal and PLL Clock Sources

When the system clock source is provided by a crystal oscillator and/or the PLL, a small delay, T

FSCM, is auto-

matically inserted after the POR and PWRT delay times. The FSCM does not begin to monitor the system clock source until this delay expires. The FSCM delay time is nominally 100 μs and provides additional time for the oscillator and/or PLL to stabilize. In most cases, the FSCM delay prevents an oscillator failure trap at a device Reset when the PWRT is disabled.

5.3 Special Function Register Reset

States

Most of the Special Function Registers (SFRs) associated with the CPU and peripherals are reset to a particular value at a device Reset. The SFRs are grouped by their peripheral or CPU function and their Reset values are specified in each section of this manual.

The Reset value for each SFR does not depend on the type of Reset, with the exception of two registers. The Reset value for the Reset Control register, RCON, depends on the type of device Reset. The Reset value for the Oscillator Control register, OSCCON, depends on the type of Reset and the programmed values of the oscillator Configuration bits in the FOSC Configuration register.

PIC24H

6.0 INTERRUPT CONTROLLER

Note: This data sheet summarizes the features

The PIC24H interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the PIC24H CPU. It has the following features:

• Up to 8 processor exceptions and software traps

• 7 user-selectable priority levels

• Interrupt Vector Table (IVT) with up to 118 vectors

• A unique vector for each interrupt or exception source

• Fixed priority within a specified user priority level

• Alternate Interrupt Vector Table (AIVT) for debug support

• Fixed interrupt entry and return latencies

6.1 Interrupt Vector Table

The Interrupt Vector Table (IVT) is shown in Figure 6-1. The IVT resides in program memory, starting at location 000004h. The IVT contains 126 vectors consisting of 8 nonmaskable trap vectors plus up to 118 sources of interrupt. In general, each interrupt source has its own vector. Each interrupt vector contains a 24-bit wide address. The value programmed into each interrupt vector location is the starting address of the associated Interrupt Service Routine (ISR).

Interrupts vectors are prioritized in terms of their natural priority; this priority is linked to their position in the vector table. All other things being equal, lower addresses have a higher natural priority. For example, the interrupt associated with vector 0 will take priority over interrupts at any other vector address.

PIC24H devices implement up to 61 unique interrupts and 5 nonmaskable traps. These are summarized in Table 6-1 and Table 6-2.

6.1.1 ALTERNATE VECTOR TABLE

The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 6-1. Access to the AIVT is provided by the ALTIVT control bit (INTCON2<15>). If the ALTIVT bit is set, all interrupt and exception processes use the alternate vectors instead of the default vectors. The alternate vectors are organized in the same manner as the default vectors.

The AIVT supports debugging by providing a means to switch between an application and a support environment without requiring the interrupt vectors to be reprogrammed. This feature also enables switching between applications for evaluation of different software algorithms at run time. If the AIVT is not needed, the AIVT should be programmed with the same addresses used in the IVT.

6.2 Reset Sequence

A device Reset is not a true exception because the interrupt controller is not involved in the Reset process. The PIC24H device clears its registers in response to a Reset which forces the PC to zero. The digital signal controller then begins program execution at location 0x000000. The user programs a GOTO instruction at the Reset address which redirects program execution to the appropriate start-up routine.

Note: Any unimplemented or unused vector

locations in the IVT and AIVT should be programmed with the address of a default interrupt handler routine that contains a RESET instruction.

PIC24H

FIGURE 6-1: PIC24H INTERRUPT VECTOR TABLE

Reset – GOTO Instruction 0x000000

Reset – GOTO Address 0x000002

Reserved 0x000004 Oscillator Fail Trap Vector Address Error Trap Vector

Stack Error Trap Vector

Math Error Trap Vector DMA Error Trap Vector

Reserved

Interrupt Vector 0 0x000014 Interrupt Vector 1

~ ~

Interrupt Vector 52 0x00007C Interrupt Vector 53 0x00007E Interrupt Vector 54 0x000080

Interrupt Vector 116 0x0000FC Interrupt Vector 117 0x0000FE

Oscillator Fail Trap Vector

Decreasing Natural Order Priority

Address Error Trap Vector

Stack Error Trap Vector

Math Error Trap Vector DMA Error Trap Vector

Interrupt Vector 52 0x00017C Interrupt Vector 53 0x00017E Interrupt Vector 54 0x000180

Interrupt Vector 116 Interrupt Vector 117 0x0001FE

~ ~ ~

Reserved

Reserved 0x000102

Reserved

Interrupt Vector 0 0x000114 Interrupt Vector 1

~ ~ ~

Start of Code 0x000200

0x000100

Interrupt Vector Table (IVT)

Alternate Interrupt Vector Table (AIVT)

(1)

Note 1: See Table 6-1 for the list of implemented interrupt vectors.

TABLE 6-1: INTERRUPT VECTORS

Vector

Number

8 0 0x000014 0x000114 INT0 – External Interrupt 0

9 1 0x000016 0x000116 IC1 – Input Compare 1 10 2 0x000018 0x000118 OC1 – Output Compare 1

11 3 0x00001A 0x00011A T1 – Timer1 12 4 0x00001C 0x00011C DMA0 – DMA Channel 0 13 5 0x00001E 0x00011E IC2 – Input Capture 2 14 6 0x000020 0x000120 OC2 – Output Compare 2 15 7 0x000022 0x000122 T2 – Timer2 16 8 0x000024 0x000124 T3 – Timer3

17 9 0x000026 0x000126 SPI1E – SPI1 Error 18 10 0x000028 0x000128 SPI1 – SPI1 Transfer Done 19 11 0x00002A 0x00012A U1RX – UART1 Receiver 20 12 0x00002C 0x00012C U1TX – UART1 Transmitter 21 13 0x00002E 0x00012E ADC1 – A/D Converter 1 22 14 0x000030 0x000130 DMA1 – DMA Channel 1

23 15 0x000032 0x000132 Reserved 24 16 0x000034 0x000134 SI2C1 – I2C1 Slave Events 25 17 0x000036 0x000136 MI2C1 – I2C1 Master Events 26 18 0x000038 0x000138 Reserved 27 19 0x00003A 0x00013A CN - Change Notification Interrupt

28 20 0x00003C 0x00013C INT1 – External Interrupt 1 29 21 0x00003E 0x00013E ADC2 – A/D Converter 2 30 22 0x000040 0x000140 IC7 – Input Capture 7 31 23 0x000042 0x000142 IC8 – Input Capture 8 32 24 0x000044 0x000144 DMA2 – DMA Channel 2 33 25 0x000046 0x000146 OC3 – Output Compare 3

34 26 0x000048 0x000148 OC4 – Output Compare 4 35 27 0x00004A 0x00014A T4 – Timer4 36 28 0x00004C 0x00014C T5 – Timer5 37 29 0x00004E 0x00014E INT2 – External Interrupt 2 38 30 0x000050 0x000150 U2RX – UART2 Receiver 39 31 0x000052 0x000152 U2TX – UART2 Transmitter

40 32 0x000054 0x000154 SPI2E – SPI2 Error 41 33 0x000056 0x000156 SPI1 – SPI1 Transfer Done 42 34 0x000058 0x000158 C1RX – ECAN1 Receive Data Ready 43 35 0x00005A 0x00015A C1 – ECAN1 Event 44 36 0x00005C 0x00015C DMA3 – DMA Channel 3 45 37 0x00005E 0x00015E IC3 – Input Capture 3

46 38 0x000060 0x000160 IC4 – Input Capture 4 47 39 0x000062 0x000162 IC5 – Input Capture 5 48 40 0x000064 0x000164 IC6 – Input Capture 6 49 41 0x000066 0x000166 OC5 – Output Compare 5 50 42 0x000068 0x000168 OC6 – Output Compare 6 51 43 0x00006A 0x00016A OC7 – Output Compare 7

52 44 0x00006C 0x00016C OC8 – Output Compare 8 53 45 0x00006E 0x00016E Reserved

Interrupt

Request (IRQ)

Number

IVT Address AIVT Address Interrupt Source

PIC24H

TABLE 6-1: INTERRUPT VECTORS (CONTINUED)

Vector

Number

54 46 0x000070 0x000170 DMA4 – DMA Channel 4

55 47 0x000072 0x000172 T6 – Timer6 56 48 0x000074 0x000174 T7 – Timer7 57 49 0x000076 0x000176 SI2C2 – I2C2 Slave Events 58 50 0x000078 0x000178 MI2C2 – I2C2 Master Events 59 51 0x00007A 0x00017A T8 – Timer8 60 52 0x00007C 0x00017C T9 – Timer9

61 53 0x00007E 0x00017E INT3 – External Interrupt 3 62 54 0x000080 0x000180 INT4 – External Interrupt 4 63 55 0x000082 0x000182 C2RX – ECAN2 Receive Data Ready 64 56 0x000084 0x000184 C2 – ECAN2 Event

65-68 57-60 0x000086-

69 61 0x00008E 0x00018E DMA5 – DMA Channel 5

70-72 62-64 0x000090-

73 65 0x000096 0x000196 U1E – UART1 Error 74 66 0x000098 0x000198 U2E – UART2 Error 75 67 0x00009A 0x00019A Reserved

76 68 0x00009C 0x00019C DMA6 – DMA Channel 6 77 69 0x00009E 0x00019E DMA7 – DMA Channel 7 78 70 0x0000A0 0x0001A0 C1TX – ECAN1 Transmit Data Request 79 71 0x0000A2 0x0001A2 C2TX – ECAN2 Transmit Data Request

80-125 72-117 0x0000A4-

Interrupt

Request (IRQ)

Number

IVT Address AIVT Address Interrupt Source

0x00008C

0x000094

0x0000FE

0x0001860x00018C

0x000190-

0x000194

0x0001A4-

0x0001FE

Reserved

TABLE 6-2: TRAP VECTORS

Vector Number IVT Address AIVT Address Trap Source

0 0x000004 0x000084 Reserved

1 0x000006 0x000086 Oscillator Failure

2 0x000008 0x000088 Address Error

3 0x00000A 0x00008A Stack Error

4 0x00000C 0x00008C Math Error

5 0x00000E 0x00008E DMA Error Trap

6 0x000010 0x000090 Reserved

7 0x000012 0x000092 Reserved

PIC24H

6.3 Interrupt Control and Status Registers

PIC24H devices implement a total of 30 registers for the interrupt controller:

• INTCON1

• INTCON2

• IFS0 through IFS4

• IEC0 through IEC4

• IPC0 through IPC17

Global interrupt control functions are controlled from INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit as well as the control and status flags for the processor trap sources. The INTCON2 register controls the external interrupt request signal behavior and the use of the Alternate Interrupt Vector Table.

The IFS registers maintain all of the interrupt request flags. Each source of interrupt has a Status bit, which is set by the respective peripherals or external signal and is cleared via software.

The IEC registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals.

The IPC registers are used to set the interrupt priority level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels.

The interrupt sources are assigned to the IFSx, IECx and IPCx registers in the same sequence that they are listed in Table 6-1. For example, the INT0 (External Interrupt 0) is shown as having vector number 8 and a natural order priority of 0. Thus, the INT0IF bit is found in IFS0<0>, the INT0IE bit in IEC0<0>, and the INT0IP bits in the first position of IPC0 (IPC0<2:0>).

Although they are not specifically part of the interrupt control hardware, two of the CPU Control registers contain bits that control interrupt functionality. The CPU STATUS register, SR, contains the IPL<2:0> bits (SR<7:5>). These bits indicate the current CPU interrupt priority level. The user can change the current CPU priority level by writing to the IPL bits.

The CORCON register contains the IPL3 bit which, together with IPL<2:0>, also indicates the current CPU priority level. IPL3 is a read-only bit so that trap events cannot be masked by the user software.

All Interrupt registers are described in Register 6-1,

SR: CPU STATUS Register IPC17: Interrupt Priority Control Register 17, in the

following pages.

(1)

through Register 6-32,

PIC24H

(1)

R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R -0 R/W-0

OA OB SA SB OAB SAB DA DC

bit 15 bit 8

R/W-0

IPL2

(3)

(2)

R/W-0

IPL1

(2)

(3)

R/W-0

IPL0

(2)

(3)

R-0 R/W-0 R/W-0 R/W-0 R/W-0

RA N OV Z C

bit 7 bit 0

Legend:

C = Clear only bit R = Readable bit U = Unimplemented bit, read as ‘0’

S = Set only bit W = Writable bit -n = Value at POR

‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits

(2)

Note 1: For complete register details, see Register 2-1, SR: CPU STATUS Register.

2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority

Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3> = 1.

3: The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15>) = 1.

(1)

U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0

— — — US EDT DL<2:0>

bit 15 bit 8

R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0

SATA SATB SATDW ACCSAT IPL3

(2)

PSV RND IF

bit 7 bit 0

Legend: C = Clear only bit

R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set

0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’

bit 3 IPL3: CPU Interrupt Priority Level Status bit 3

(2)

1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less

Note 1: For complete register details, see Register 2-2, CORCON: CORE Control Register.

2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.

PIC24H

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0

SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 NSTDIS: Interrupt Nesting Disable bit

1 = Interrupt nesting is disabled 0 = Interrupt nesting is enabled

bit 14 OVAERR: Accumulator A Overflow Trap Flag bit

1 = Trap was caused by overflow of Accumulator A 0 = Trap was not caused by overflow of Accumulator A

bit 13 OVBERR: Accumulator B Overflow Trap Flag bit

1 = Trap was caused by overflow of Accumulator B 0 = Trap was not caused by overflow of Accumulator B

bit 12 COVAERR: Accumulator A Catastrophic Overflow Trap Enable bit

1 = Trap was caused by catastrophic overflow of Accumulator A 0 = Trap was not caused by catastrophic overflow of Accumulator A

bit 11 COVBERR: Accumulator B Catastrophic Overflow Trap Enable bit

1 = Trap was caused by catastrophic overflow of Accumulator B 0 = Trap was not caused by catastrophic overflow of Accumulator B

bit 10 OVATE: Accumulator A Overflow Trap Enable bit

1 = Trap overflow of Accumulator A 0 = Trap disabled

bit 9 OVBTE: Accumulator B Overflow Trap Enable bit

1 = Trap overflow of Accumulator B 0 = Trap disabled

bit 8 COVTE: Catastrophic Overflow Trap Enable bit

1 = Trap on catastrophic overflow of Accumulator A or B enabled 0 = Trap disabled

bit 7 SFTACERR: Shift Accumulator Error Status bit

1 = Math error trap was caused by an invalid accumulator shift 0 = Math error trap was not caused by an invalid accumulator shift

bit 6 DIV0ERR: Arithmetic Error Status bit

1 = Math error trap was caused by a divide by zero 0 = Math error trap was not caused by a divide by zero

bit 5 DMACERR: DMA Controller Error Status bit

1 = DMA controller error trap has occurred 0 = DMA controller error trap has not occurred

bit 4 MATHERR: Arithmetic Error Status bit

1 = Math error trap has occurred 0 = Math error trap has not occurred

—

PIC24H

bit 3 ADDRERR: Address Error Trap Status bit

1 = Address error trap has occurred 0 = Address error trap has not occurred

bit 2 STKERR: Stack Error Trap Status bit

1 = Stack error trap has occurred 0 = Stack error trap has not occurred

bit 1 OSCFAIL: Oscillator Failure Trap Status bit

1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred

bit 0 Unimplemented: Read as ‘0’

PIC24H

R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0

ALTIVT DISI

bit 15 bit 8

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — INT4EP INT3EP INT2EP INT1EP INT0EP

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit

1 = Use alternate vector table 0 = Use standard (default) vector table

bit 14 DISI: DISI Instruction Status bit

1 = DISI instruction is active 0 = DISI instruction is not active

bit 13-5 Unimplemented: Read as ‘0’

bit 4 INT4EP: External Interrupt 4 Edge Detect Polarity Select bit

1 = Interrupt on negative edge 0 = Interrupt on positive edge

bit 3 INT3EP: External Interrupt 3 Edge Detect Polarity Select bit

1 = Interrupt on negative edge 0 = Interrupt on positive edge

bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit

1 = Interrupt on negative edge 0 = Interrupt on positive edge

bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit

1 = Interrupt on negative edge 0 = Interrupt on positive edge

bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit

1 = Interrupt on negative edge 0 = Interrupt on positive edge

— — — — — —

PIC24H

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

T2IF OC2IF IC2IF DMA01IF T1IF OC1IF IC1IF INT0IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14 DMA1IF: DMA Channel 1 Data Transfer Complete Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 13 AD1IF: ADC1 Conversion Complete Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 12 U1TXIF: UART1 Transmitter Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 11 U1RXIF: UART1 Receiver Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 10 SPI1IF: SPI1 Event Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 9 SPI1EIF: SPI1 Fault Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 8 T3IF: Timer3 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 7 T2IF: Timer2 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 6 OC2IF: Output Compare Channel 2 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 5 IC2IF: Input Capture Channel 2 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 4 DMA0IF: DMA Channel 0 Data Transfer Complete Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 3 T1IF: Timer1 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 0 INT0IF: External Interrupt 0 Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

PIC24H

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA21IF

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IC8IF IC7IF AD2IF INT1IF CNIF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 U2TXIF: UART2 Transmitter Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 14 U2RXIF: UART2 Receiver Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 13 INT2IF: External Interrupt 2 Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 12 T5IF: Timer5 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 11 T4IF: Timer4 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 10 OC4IF: Output Compare Channel 4 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 9 OC3IF: Output Compare Channel 3 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 8 DMA2IF: DMA Channel 2 Data Transfer Complete Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 7 IC8IF: Input Capture Channel 8 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 6 IC7IF: Input Capture Channel 7 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 5 AD2IF: ADC2 Conversion Complete Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 4 INT1IF: External Interrupt 1 Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

— MI2C1IF SI2C1IF

bit 3 CNIF: Input Change Notification Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 2 Unimplemented: Read as ‘0’

bit 1 MI2C1IF: I2C1 Master Events Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

PIC24H

R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

T6IF DMA4IF

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IC5IF IC4IF IC3IF DMA3IF C1IF C1RXIF SPI2IF SPI2EIF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 T6IF: Timer6 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 14 DMA4IF: DMA Channel 4 Data Transfer Complete Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 13 Unimplemented: Read as ‘0’

bit 12 OC8IF: Output Compare Channel 8 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 11 OC7IF: Output Compare Channel 7 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 10 OC6IF: Output Compare Channel 6 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 9 OC5IF: Output Compare Channel 5 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 8 IC6IF: Input Capture Channel 6 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 7 IC5IF: Input Capture Channel 5 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 6 IC4IF: Input Capture Channel 4 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 5 IC3IF: Input Capture Channel 3 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 4 DMA3IF: DMA Channel 3 Data Transfer Complete Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

— OC8IF OC7IF OC6IF OC5IF IC6IF

bit 3 C1IF: ECAN1 Event Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 2 C1RXIF: ECAN1 Receive Data Ready Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 1 SPI2IF: SPI2 Event Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 0 SPI2EIF: SPI2 Error Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

PIC24H

U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0

— —DMA5IF— — — —C2IF

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

C2RXIF INT4IF INT3IF T9IF T8IF MI2C2IF SI2C2IF T7IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13 DMA5IF: DMA Channel 5 Data Transfer Complete Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 12-9 Unimplemented: Read as ‘0’

bit 8 C2IF: ECAN2 Event Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 7 C2RXIF: ECAN2 Receive Data Ready Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 6 INT4IF: External Interrupt 4 Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 5 INT3IF: External Interrupt 3 Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 4 T9IF: Timer9 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 3 T8IF: Timer8 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 2 MI2C2IF: I2C2 Master Events Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 1 SI2C2IF: I2C2 Slave Events Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 0 T7IF: Timer7 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

PIC24H

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0

C2TXIF C1TXIF DMA7IF DMA6IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-8 Unimplemented: Read as ‘0’

bit 7 C2TXIF: ECAN2 Transmit Data Request Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 6 C1TXIF: ECAN1 Transmit Data Request Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 5 DMA7IF: DMA Channel 7 Data Transfer Complete Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 4 DMA6IF: DMA Channel 6 Data Transfer Complete Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 3 Unimplemented: Read as ‘0’

bit 2 U2EIF: UART2 Error Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 1 U1EIF: UART1 Error Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 0 Unimplemented: Read as ‘0’

—U2EIFU1EIF—

PIC24H

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14 DMA1IE: DMA Channel 1 Data Transfer Complete Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 13 AD1IE: ADC1 Conversion Complete Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 12 U1TXIE: UART1 Transmitter Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 11 U1RXIE: UART1 Receiver Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 10 SPI1IE: SPI1 Event Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 9 SPI1EIE: SPI1 Error Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 8 T3IE: Timer3 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 7 T2IE: Timer2 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 6 OC2IE: Output Compare Channel 2 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 5 IC2IE: Input Capture Channel 2 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 4 DMA0IE: DMA Channel 0 Data Transfer Complete Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 3 T1IE: Timer1 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

PIC24H

bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 0 INT0IE: External Interrupt 0 Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

PIC24H

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IC8IE IC7IE AD2IE INT1IE CNIE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 U2TXIE: UART2 Transmitter Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 14 U2RXIE: UART2 Receiver Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 13 INT2IE: External Interrupt 2 Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 12 T5IE: Timer5 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 11 T4IE: Timer4 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 10 OC4IE: Output Compare Channel 4 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 9 OC3IE: Output Compare Channel 3 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 8 DMA2IE: DMA Channel 2 Data Transfer Complete Interrupt Enable bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 7 IC8IE: Input Capture Channel 8 Interrupt Enable bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 6 IC7IE: Input Capture Channel 7 Interrupt Enable bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 5 AD2IE: ADC2 Conversion Complete Interrupt Enable bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 4 INT1IE: External Interrupt 1 Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

— MI2C1IE SI2C1IE

PIC24H

bit 3 CNIE: Input Change Notification Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 2 Unimplemented: Read as ‘0’

bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

PIC24H

R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

T6IE DMA4IE — OC8IE OC7IE OC6IE OC5IE IC6IE

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IC5IE IC4IE IC3IE DMA3IE C1IE C1RXIE SPI2IE SPI2EIE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 T6IE: Timer6 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 14 DMA4IE: DMA Channel 4 Data Transfer Complete Interrupt Enable bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 13 Unimplemented: Read as ‘0’

bit 12 OC8IE: Output Compare Channel 8 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 11 OC7IE: Output Compare Channel 7 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 10 OC6IE: Output Compare Channel 6 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 9 OC5IE: Output Compare Channel 5 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 8 IC6IE: Input Capture Channel 6 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 7 IC5IE: Input Capture Channel 5 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 6 IC4IE: Input Capture Channel 4 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 5 IC3IE: Input Capture Channel 3 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 4 DMA3IE: DMA Channel 3 Data Transfer Complete Interrupt Enable bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 3 C1IE: ECAN1 Event Interrupt Enable bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

PIC24H

bit 2 C1RXIE: ECAN1 Receive Data Ready Interrupt Enable bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 1 SPI2IE: SPI2 Event Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 0 SPI2EIE: SPI2 Error Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

PIC24H

U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0

— —DMA5IE— — — —C2IE

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

C2RXIE INT4IE INT3IE T9IE T8IE MI2C2IE SI2C2IE T7IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13 DMA5IE: DMA Channel 5 Data Transfer Complete Interrupt Enable bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 12-9 Unimplemented: Read as ‘0’

bit 8 C2IE: ECAN2 Event Interrupt Enable bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 7 C2RXIE: ECAN2 Receive Data Ready Interrupt Enable bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 6 INT4IE: External Interrupt 4 Enable bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 5 INT3IE: External Interrupt 3 Enable bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 4 T9IE: Timer9 Interrupt Enable bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 3 T8IE: Timer8 Interrupt Enable bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 2 MI2C2IE: I2C2 Master Events Interrupt Enable bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 1 SI2C2IE: I2C2 Slave Events Interrupt Enable bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 0 T7IE: Timer7 Interrupt Enable bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

PIC24H

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0

C2TXIE C1TXIE DMA7IE DMA6IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-8 Unimplemented: Read as ‘0’

bit 7 C2TXIE: ECAN2 Transmit Data Request Interrupt Enable bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 6 C1TXIE: ECAN1 Transmit Data Request Interrupt Enable bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 5 DMA7IE: DMA Channel 7 Data Transfer Complete Enable Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 4 DMA6IE: DMA Channel 6 Data Transfer Complete Enable Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 3 Unimplemented: Read as ‘0’

bit 2 U2EIE: UART2 Error Interrupt Enable bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 1 U1EIE: UART1 Error Interrupt Enable bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 0 Unimplemented: Read as ‘0’

—U2EIEU1EIE—

PIC24H

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— T1IP<2:0> — OC1IP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— IC1IP<2:0> — INT0IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

PIC24H

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— T2IP<2:0> — OC2IP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— IC2IP<2:0> — DMA0IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 DMA0IP<2:0>: DMA Channel 0 Data Transfer Complete Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

PIC24H

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— U1RXIP<2:0> — SPI1IP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— SPI1EIP<2:0> — T3IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 SPI1IP<2:0>: SPI1 Event Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 SPI1EIP<2:0>: SPI1 Error Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

PIC24H

U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0

— — — — — DMA1IP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— AD1IP<2:0> — U1TXIP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-11 Unimplemented: Read as ‘0’

bit 10-8 DMA1IP<2:0>: DMA Channel 1 Data Transfer Complete Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 AD1IP<2:0>: ADC1 Conversion Complete Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

PIC24H

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

—CNIP<2:0>— — — —

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— MI2C1IP<2:0> — SI2C1IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 CNIP<2:0>: Change Notification Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 11-7 Unimplemented: Read as ‘0’

bit 6-4 MI2C1IP<2:0>: I2C1 Master Events Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

PIC24H

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— IC8IP<2:0> —IC7IP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— AD2IP<2:0> — INT1IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 IC8IP<2:0>: Input Capture Channel 8 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 IC7IP<2:0>: Input Capture Channel 7 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 AD2IP<2:0>: ADC2 Conversion Complete Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

PIC24H

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— T4IP<2:0> — OC4IP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

—OC3IP<2:0>— DMA2IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 T4IP<2:0>: Timer4 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 OC4IP<2:0>: Output Compare Channel 4 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 OC3IP<2:0>: Output Compare Channel 3 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 DMA2IP<2:0>: DMA Channel 2 Data Transfer Complete Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

PIC24H

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— U2TXIP<2:0> — U2RXIP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— INT2IP<2:0> — T5IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 U2RXIP<2:0>: UART2 Receiver Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 INT2IP<2:0>: External Interrupt 2 Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 T5IP<2:0>: Timer5 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

PIC24H

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— C1IP<2:0> — C1RXIP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— SPI2IP<2:0> — SPI2EIP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 C1IP<2:0>: ECAN1 Event Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 C1RXIP<2:0>: ECAN1 Receive Data Ready Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 SPI2IP<2:0>: SPI2 Event Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 SPI2EIP<2:0>: SPI2 Error Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

MICROCHIP PIC24H DATA SHEET

Specifications and Main Features

Frequently Asked Questions

User Manual

High-Performance, 16-bit Microcontrollers

1.0 DEVICE OVERVIEW

FIGURE 1-1: PIC24H GENERAL BLOCK DIAGRAM

2.0 CPU

2.2 Special MCU Features

2.1 Data Addressing Overview

FIGURE 2-1: PIC24H CPU CORE BLOCK DIAGRAM

FIGURE 2-2: PIC24H PROGRAMMER’S MODEL

2.3 CPU Control Registers

2.4 Arithmetic Logic Unit (ALU)

2.4.3 MULTI-BIT DATA SHIFTER

2.4.1 MULTIPLIER

2.4.2 DIVIDER

3.0 MEMORY ORGANIZATION

3.1 Program Address Space

FIGURE 3-1: PROGRAM MEMORY MAP FOR PIC24H FAMILY DEVICES

3.1.1 PROGRAM MEMORY ORGANIZATION

3.1.2 INTERRUPT AND TRAP VECTORS

FIGURE 3-2: PROGRAM MEMORY ORGANIZATION

3.2 Data Address Space

3.2.1 DATA SPACE WIDTH

3.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT

3.2.3 SFR SPACE

3.2.4 NEAR DATA SPACE

FIGURE 3-3: DATA MEMORY MAP FOR PIC24H DEVICES WITH 8 KBYTES RAM

FIGURE 3-4: DATA MEMORY MAP FOR PIC24H DEVICES WITH 16 KBYTES RAM

3.2.5 DMA RAM

TABLE 3-2: CHANGE NOTIFICATION REGISTER MAP

TABLE 3-5: INPUT CAPTURE REGISTER MAP

TABLE 3-6: OUTPUT COMPARE REGISTER MAP

TABLE 3-7: I2C1 REGISTER MAP

TABLE 3-8: I2C2 REGISTER MAP

TABLE 3-9: UART1 REGISTER MAP

TABLE 3-10: UART2 REGISTER MAP

TABLE 3-11: SPI1 REGISTER MAP

TABLE 3-13: ADC1 REGISTER MAP

TABLE 3-14: ADC2 REGISTER MAP

TABLE 3-16: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0 OR 1

TABLE 3-17: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0

TABLE 3-19: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 0 OR 1

TABLE 3-20: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 0

TABLE 3-29: SYSTEM CONTROL REGISTER MAP

TABLE 3-30: NVM REGISTER MAP

TABLE 3-31: PMD REGISTER MAP

3.2.6 SOFTWARE STACK

FIGURE 3-5: CALL STACK FRAME

3.3 Instruction Addressing Modes

3.3.1 FILE REGISTER INSTRUCTIONS

3.3.2 MCU INSTRUCTIONS

TABLE 3-32: FUNDAMENTAL ADDRESSING MODES SUPPORTED

3.3.3 MOVE INSTRUCTIONS

3.3.4 OTHER INSTRUCTIONS

3.4 Interfacing Program and Data Memory Spaces

3.4.1 ADDRESSING PROGRAM SPACE

TABLE 3-33: PROGRAM SPACE ADDRESS CONSTRUCTION

FIGURE 3-6: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

3.4.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS

FIGURE 3-7: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS

3.4.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY

FIGURE 3-8: PROGRAM SPACE VISIBILITY OPERATION

4.0 FLASH PROGRAM MEMORY

FIGURE 4-1: ADDRESSING FOR TABLE REGISTERS

4.2 RTSP Operation

4.3 Control Registers

4.4 Programming Operations

REGISTER 4-1: NVMCOM: FLASH MEMORY CONTROL REGISTER

4.4.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY

EXAMPLE 4-1: ERASING A PROGRAM MEMORY PAGE

EXAMPLE 4-2: LOADING THE WRITE BUFFERS

EXAMPLE 4-3: INITIATING A PROGRAMMING SEQUENCE

5.0 RESETS

FIGURE 5-1: RESET SYSTEM BLOCK DIAGRAM

TABLE 5-1: RESET FLAG BIT OPERATION

5.1 Clock Source Selection at Reset

5.2 Device Reset Times

TABLE 5-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS