MICROCHIP PIC24FJXXXGA1, PIC24FJXXXGB1 Technical data
PIC24FJXXXGA1/GB1
PIC24FJXXXGA1/GB1 Families Flash Programming
Specification
1.0 DEVICE OVERVIEW
This document defines the programming specification
for the PIC24FJXXXGA1/GB1 families of 16-bit
microcontroller devices. This programming specification
is required only for those developing programming
support for the PIC24FJXXXGA1/GB1 families.
Customers using only one of these devices should use
development tools that already provide support for
device programming.
This specification includes programming specifications
for the following devices:
• PIC24FJ256GA106 • PIC24FJ256GB106
• PIC24FJ256GA108 • PIC24FJ256GB108
• PIC24FJ256GA110 • PIC24FJ256GB110
• PIC24FJ192GA106 • PIC24FJ192GB106
• PIC24FJ192GA108 • PIC24FJ192GB108
• PIC24FJ192GA110 • PIC24FJ192GB110
• PIC24FJ128GA106 • PIC24FJ128GB106
• PIC24FJ128GA108 • PIC24FJ128GB108
• PIC24FJ128GA110 • PIC24FJ128GB110
• PIC24FJ64GB106 • PIC24FJ64GB108
• PIC24FJ64GB110
2.0 PROGRAMMING OVERVIEW OF THE PIC24FJXXXGA1/GB1 FAMILIES
There are two methods of programming the
PIC24FJXXXGA1/GB1 families of devices discussed
in this programming specification. They are:
• In-Circuit Serial Programming™ (ICSP™)
• Enhanced In-Circuit Serial Programming
(Enhanced ICSP)
The ICSP programming method is the most direct
method to program the device; however, it is also the
slower of the two methods. It provides native, low-level
programming capability to erase, program and verify
the chip.
The Enhanced In-Circuit Serial Programming
(Enhanced ICSP) protocol uses a faster method that
takes advantage of the programming executive, as
illustrated in Figure 2-1. The programming executive
provides all the necessary functionality to erase, program and verify the chip through a small command set.
The command set allows the programmer to program
the PIC24FJXXXGA1/GB1 devices without having to
deal with the low-level programming protocols of the
chip.
FIGURE 2-1: PROGRAMMING SYSTEM
PIC24FJXXXGA1/GB1
Programming
Executive
OVERVIEW FOR
ENHANCED ICSP™
On-Chip Memory
Programmer
This specification is divided into major sections that
describe the programming methods independently.
Section 4.0 “Device Programming – Enhanced
ICSP” describes the Run-Time Self-Programming
(RTSP) method. Section 3.0 “Device Programming –
ICSP” describes the In-Circuit Serial Programming
method.
© 2007 Microchip Technology Inc. DS39907A-page 1
PIC24FJXXXGA1/GB1
2.1 Power Requirements
All devices in the PIC24FJXXXGA1/GB1 families are
dual voltage supply designs: one supply for the core
and peripherals and another for the I/O pins. A regulator is provided on-chip to alleviate the need for two
external voltage supplies.
All PIC24FJXXXGA1/GB1 devices power their core
digital logic at a nominal 2.5V. To simplify system
design, all devices in the PIC24FJXXXGA1/GB1 families incorporate an on-chip regulator that allows the
device to run its core logic from V
DD.
The regulator provides power to the core from the other
VDD pins. A low-ESR capacitor (such as tantalum) must
be connected to the V
DDCORE pin (Table 2-1 and
Figure 2-2). This helps to maintain the stability of the
regulator. The specifications for core voltage and capacitance are listed in Section 7.0 “AC/DC Characteristics
and Timing Requirements”.
2.2 Program Memory Write/Erase Requirements
The Flash program memory on PIC24FJXXXGA1/GB1
devices has a specific write/erase requirement that
must be adhered to for proper device operation. The
rule is that any given word in memory must not be written more than twice before erasing the page in which it
is located. Thus, the easiest way to conform to this rule
is to write all the data in a programming block within
one write cycle. The programming methods specified in
this specification comply with this requirement.
Note: Writing to a location multiple times without
erasing is not recommended.
2.3 Pin Diagrams
FIGURE 2-2: CONNECTIONS FOR THE
ON-CHIP REGULATOR
Regulator Enabled (ENVREG tied to VDD):
3.3V
CEFC
(10
μF typ)
Regulator Disabled (ENVREG tied to ground):
(1)
2.5V
Regulator Disabled (VDD tied to VDDCORE):
2.5V
3.3V
(1)
PIC24FJXXXGA1/GB1
VDD
ENVREG
V
DDCORE/VCAP
VSS
(1)
PIC24FJXXXGA1/GB1
VDD
ENVREG
V
DDCORE/VCAP
VSS
PIC24FJXXXGA1/GB1
VDD
ENVREG
VDDCORE/VCAP
VSS
The pin diagrams for the PIC24FJXXXGA1/GB1 families are shown in the following figures. The pins that are
required for programming are listed in Table 2-1 and
are shown in bold letters in the figures. Refer to the
Note 1: These are typical operating voltages. Refer
Section 7.0 “AC/DC Characteristics and
to
Timing Requirements”
ranges of V
DD and VDDCORE.
for the full operating
appropriate device data sheet for complete pin
descriptions.
2.3.1 PGCx AND PGDx PIN PAIRS
All of the devices in the PIC24FJXXXGA1/GB1 families
have three separate pairs of programming pins,
labelled as PGEC1/PGED1, PGEC2/PGED2, and
PGEC3/PGED3. Any one of these pin pairs may be
used for device programming by either ICSP or
Enhanced ICSP. Unlike voltage supply and ground
pins, it is not necessary to connect all three pin pairs to
program the device. However, the programming
method must use both pins of the same pair.
DS39907A-page 2 © 2007 Microchip Technology Inc.
PIC24FJXXXGA1/GB1
TABLE 2-1: PIN DESCRIPTIONS (DURING PROGRAMMING)
Pin Name
Pin Name Pin Type Pin Description
MCLR MCLR P Programming Enable
ENVREG ENVREG I Enable for On-Chip Voltage Regulator
(1)
(1)
VDD P Power Supply
VSS PGround
DD and AVDD
V
VSS and AVSS
DDCORE VDDCORE P Regulated Power Supply for Core
V
PGECx PGCx I Programming Pin Pairs 1, 2 and 3: Serial Clock
PGEDx PGDX I/O Programming Pin Pairs 1, 2 and 3: Serial Data
Legend: I = Input, O = Output, P = Power
Note 1: All power supply and ground pins must be connected, including analog supplies (AVDD) and ground
(AV
SS).
FIGURE 2-3: PIN DIAGRAMS
64-Pin TQFP
During Programming
PGEC3/AN5/RP18/C1INA/CN7/RB5
PGED3/AN4/RP28/C1INB/CN6/RB4
PGEC1/AN1/RP1/V
PGED1/AN0/RP0/PMA6/V
REF-/CN3/RB1
REF+/
RE5
RE6
RE7
RG6
RG7
RG8
MCLR
RG9
VSS
V
DD
RB3
RB2
CN2/RB0
RE0
RE4
RE3
636261596058575654555352514950
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
171920
18
RF1
RE2
RE1
RF0
ENVREG
PIC24FJXXXGA106
2244242526272829303132
23
21
SS
RB8
RB9
AVDD
AV
RB11
RB10
CAP/VDDCORE
RD7
RD6
RD5
RD4
RD3
RD2
V
DD
VSS
V
RB12
RB13
RD1
48
RC14
47
RC13
46
RD0
45
RD11
RD10
43
RD9
42
RD8
41
VSS
40
RC15
39
RC12
38
V
DD
37
RG2
36
RG3
35
RF6
34
RF2
33
RF3
RF5
RF4
RB14
RB15
PGEC2/AN6/RP6/CN24/RB6
PGED2/AN7/RP7/CN25/RB7
© 2007 Microchip Technology Inc. DS39907A-page 3
PIC24FJXXXGA1/GB1
FIGURE 2-4: PIN DIAGRAMS (CONTINUED
80-Pin TQFP
RE2
RE4
RE3
RE1
RE0
DDCORE
RD5
RD4
RD13
RD12
RD3
RD2
RG0
RF0
VCAP/V
ENVREG
RG1
RF1
RD7
RD6
RD1
PGEC3/AN5/RP18/
PGED3/AN4/RP28/
PGEC1/AN1/RP1/CN3/RB1
PGED1/AN0/RP0/CN2/RB0
RE5
RE6
RE7
RC1
RC3
RG6
RG7
RG8
MCLR
RG9
VSS
V
DD
CN66/RE8
CN67/RE9
C1INA/CN7/RB5
C1INB/CN6/RB4
RB3
RB2
807978
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
232425
22
RA9
76
77
757473717270696866676564636162
PIC24FJXXXGA108
26
2829303132333435363738
27
SS
DD
RB8
RB9
AV
AV
RA10
DD
VSS
V
RB11
RB10
RB12
RB13
RC14
60
59
RC13
58
RD0
57
RD11
56
RD10
RD9
55
RD8
54
RA15
53
RA14
52
VSS
51
RC15
50
RC12
49
V
DD
48
RG2
47
RG3
46
RF6
45
RF7
44
RF8
43
RF2
42
RF3
41
40
39
RF5
RB14
RF4
RB15
RD15
RD14
PGEC2/AN6/RP6/CN24/RB6
PGED2/AN7/RP7/CN25/RB7
DS39907A-page 4 © 2007 Microchip Technology Inc.
FIGURE 2-5: PIN DIAGRAMS (CONTINUED)
100-Pin TQFP
RE2
RG13
RE4
RE3
99
100
DD
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SS
15
16
17
18
19
20
21
22
23
24
25
27
26
2829303132333435363738
RG15
V
RE5
RE6
RE7
RC1
RC2
RC3
RC4
RG6
RG7
RG8
MCLR
RG9
V
V
RA0
RE8
RE9
PGEC3/AN5/RP18/VBUSON/C1INA/CN7/RB5
PGED3/AN4/RP28/USBOEN/C1INB/CN6/RB4
RB3
RB2
PGEC1/AN1/RP1/CN3/RB1
PGED1/AN0/RP0/CN2/RB0
PIC24FJXXXGA1/GB1
CAP/VDDCORE
RA7
RG12
RG14
95
969897
RA6
RE1
RE0
9294939190898887868584838281807978
PIC24FJXXXGA110
RG1
RG0
RF1
ENVREG
RF0
40
39
V
RD7
RD6
RD5
RD4
RD13
RD12
RD3
RD2
RD1
76
77
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
4647484950
45
44
43
42
41
SS
V
RC14
RC13
RD0
RD11
RD10
RD9
RD8
RA15
RA14
VSS
RC15
RC12
V
DD
RA5
RA4
RA3
RA2
RG2
RG3
RF6
RF7
RF8
RF2
RF3
DD
RA9
PGEC2/AN6/RP6/CN24/RB6
PGED2/AN7/RP7/RCV/CN25/RB7
RB8
RB9
AVSS
AV
RA10
DD
VSS
V
RA1
RB11
RB10
RF12
RF13
RB12
SS
V
RB13
VDD
RB14
RB15
RF5
RF4
RD15
RD14
© 2007 Microchip Technology Inc. DS39907A-page 5
PIC24FJXXXGA1/GB1
FIGURE 2-6: PIN DIAGRAMS (CONTINUED)
64-Pin TQFP
RE4
64
1
RE5
2
RE6
RE7
3
RG6
4
RG7
5
RG8
6
MCLR
PGEC3/AN5/RP18/VBUSON/C1INA/CN7/RB5
PGED3/AN4/RP28/USBOEN/C1INB/CN6/RB4
PGEC1/AN1/RP1/V
PGED1/AN0/RP0/PMA6/V
REF-/CN3/RB1
REF+/
CN2/RB0
RG9
VSS
V
DD
RB3
RB2
7
8
9
10
11
12
13
14
15
16
17
CAP/VDDCORE
RD6
RD5
RD4
RE3
RE2
RE1
RF0
V
ENVREG
RE0
RF1
636261596058575654555352514950
RD7
RD3
PIC24FJXXXGB106
2244242526272829303132
192021
18
23
RD2
RD1
48
RC14
47
RC13
46
RD0
45
RD11
RD10
43
RD9
42
RD8
41
VSS
40
RC15
39
RC12
38
V
DD
37
D+/RG2
36
D-/RG3
35
V
USB
34
VBUS
33
RF3
SS
RB8
RB9
AV
AVDD
PGEC2/AN6/RP6/CN24/RB6
PGED2/AN7/RP7/RCV/CN25/RB7
DD
VSS
V
RB11
RB10
RB12
RB13
RF5
RF4
RB14
RB15
DS39907A-page 6 © 2007 Microchip Technology Inc.
FIGURE 2-7: PIN DIAGRAMS (CONTINUED)
80-Pin TQFP
RE2
RE4
RE3
PIC24FJXXXGA1/GB1
DDCORE
RD5
RD4
RD13
RD12
RD3
RD2
RE1
RE0
RG0
RF0
VCAP/V
ENVREG
RG1
RF1
RD7
RD6
RD1
PGEC3/AN5/RP18/VBUSON/
PGED3/AN4/RP28/USBOEN/
PGEC1/AN1/RP1/CN3/RB1
PGED1/AN0/RP0/CN2/RB0
RE5
RE6
RE7
RC1
RC3
RG6
RG7
RG8
MCLR
RG9
VSS
V
DD
CN66/RE8
CN67/RE9
C1INA/CN7/RB5
C1INB/CN6/RB4
RB3
RB2
807978
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
232425
22
RA9
76
77
757473717270696866676564636162
PIC24FJXXXGB108
26
2829303132333435363738
27
SS
DD
RB8
RB9
AV
AV
RA10
DD
VSS
V
RB11
RB10
RB12
RB13
RC14
60
59
RC13
58
RD0
57
RD11
56
RD10
RD9
55
RD8
54
RA15
53
RA14
52
VSS
51
RC15
50
RC12
49
V
DD
48
D+/RG2
47
D-/RG3
46
V
USB
45
VBUS
44
RF8
43
RF2
42
RF3
41
40
39
RF5
RB14
RF4
RB15
RD15
RD14
PGEC2/AN6/RP6/CN24/RB6
PGED2/AN7/RP7/RCV/CN25/RB7
© 2007 Microchip Technology Inc. DS39907A-page 7
PIC24FJXXXGA1/GB1
FIGURE 2-8: PIN DIAGRAMS (CONTINUED)
100-Pin TQFP
RE2
RG13
RG12
RE3
969897
99
2829303132333435363738
27
RG15
V
DD
RE5
RE6
RE7
RC1
RC2
RC3
RC4
RG6
RG7
RG8
MCLR
RG9
V
V
DD
RA0
RE8
PGEC3/AN5/RP18/VBUSON/C1INA/CN7/RB5
PGED3/AN4/RP28/USBOEN/C1INB/CN6/RB4
PGEC1/AN1/RP1/CN3/RB1
PGED1/AN0/RP0/CN2/RB0
RE9
RB3
RB2
RE4
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SS
15
16
17
18
19
20
21
22
23
24
25
26
CAP/VDDCORE
RG1
RA7
RG14
95
RA6
RE1
RE0
RG0
9294939190898887868584838281807978
V
RF1
RF0
ENVREG
RD7
PIC24FJXXXGB110
41
40
39
RD6
RD5
RD4
RD13
RD12
RD3
RD2
RD1
76
77
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
45
44
43
42
4647484950
SS
V
RC14
RC13
RD0
RD11
RD10
RD9
RD8
RA15
RA14
VSS
RC15
RC12
DD
V
RA5
RA4
RA3
RA2
D+/RG2
D-/RG3
V
USB
VBUS
RF8
RF2
RF3
SS
V
RB13
VDD
RB14
RB15
RF5
RF4
RD15
RD14
PGEC2/AN6/RP6/CN24/RB6
PGED2/AN7/RP7/RCV/CN25/RB7
RA9
DD
RB8
RB9
AVSS
AV
RA10
DD
VSS
V
RA1
RB11
RB10
RF12
RF13
RB12
DS39907A-page 8 © 2007 Microchip Technology Inc.
PIC24FJXXXGA1/GB1
2.4 Memory Map
The program memory map extends from 000000h to
FFFFFEh. Code storage is located at the base of the
memory map and supports up to 87K instruction words
(about 256 Kbytes). Table 2-2 shows the program
memory size and number of erase and program blocks
present in each device variant. Each erase block, or
page, contains 512 instructions, and each program
block, or row, contains 64 instructions.
Locations 800000h through 8007FEh are reserved for
executive code memory. This region stores the
programming executive and the debugging executive.
The programming executive is used for device programming and the debugging executive is used for
in-circuit debugging. This region of memory can not be
used to store user code.
The last three implemented program memory locations
are reserved for the Flash Configuration Words. In
PIC24FJXXXGB1 family devices, the last three locations are used for the Configuration Words; for
PIC24FJXXXGA1 devices, the last two locations are
used. The reserved addresses are shown in Table 2-2.
Locations FF0000h and FF0002h are reserved for the
Device ID registers. These bits can be used by the
programmer to identify what device type is being
programmed. They are described in Section 6.1
“Device ID”. The Device ID registers read out
normally, even after code protection is applied.
Figure 2-9 shows the memory map for the
PIC24FJXXXGA1/GB1 family variants.
TABLE 2-2: CODE MEMORY SIZE AND FLASH CONFIGURATION WORD LOCATIONS FOR
PIC24FJXXXGA1/GB1 DEVICES
User Memory
Device
PIC24FJ64GB1XX 00ABFEh (22K) 344 43 00ABFEh 00ABFCh 00ABFAh
PIC24FJ128GA1XX
PIC24FJ128GB1XX
PIC24FJ192GA1XX
PIC24FJ192GB1XX
PIC24FJ256GA1XX
PIC24FJ256GB1XX
Address Limit
(Instruction Words)
0157FEh (44K) 688 86 0157FEh 0157FCh 0157FAh
020BFEh (67K) 1048 131 020BFEh 020BFCh 020BFA
02ABFEh (87K) 1368 171 02ABFEh 02ABFCh 02ABFA
Write
Blocks
Erase
Blocks
Configuration Word Addresses
123
© 2007 Microchip Technology Inc. DS39907A-page 9
PIC24FJXXXGA1/GB1
FIGURE 2-9: PROGRAM MEMORY MAP
000000h
Space
User Memory
User Flash
Code Memory
Flash Configuration Words
Reserved
Executive Code Memory
(1024 x 24-bit)
Words
(8 x 24-bit)
(1)
0XXXF9h
0XXXFAh
0XXXFEh
0XXX00h
7FFFFEh
800000h
8007FAh
8007F0hDiagnostic and Calibration
800800h
(1)
(1)
(1)
(1)
Space
Reserved
Configuration Memory
FEFFFEh
Device ID
(2 x 16-bit)
Reserved
Note 1: The size and address boundaries for user Flash code memory are device dependent. See Table 2-2 for details.
DS39907A-page 10 © 2007 Microchip Technology Inc.
FF0000h
FF0002h
FF0004h
FFFFFEh
PIC24FJXXXGA1/GB1
3.0 DEVICE PROGRAMMING – ICSP
ICSP mode is a special programming protocol that
allows you to read and write to the memory of
PIC24FJXXXGA1/GB1 devices. The ICSP mode is the
most direct method used to program the device; note,
however, that Enhanced ICSP is faster. ICSP mode
also has the ability to read the contents of executive
memory to determine if the programming executive is
present. This capability is accomplished by applying
control codes and instructions, serially to the device,
using pins PGCx and PGDx.
In ICSP mode, the system clock is taken from the
PGCx pin, regardless of the device’s oscillator Configuration bits. All instructions are shifted serially into an
internal buffer, then loaded into the Instruction Register
(IR) and executed. No program fetching occurs from
internal memory. Instructions are fed in 24 bits at a
time. PGDx is used to shift data in and PGCx is used
as both the serial shift clock and the CPU execution
clock.
Note: During ICSP operation, the operating
frequency of PGCx must not exceed
10 MHz.
3.1 Overview of the Programming Process
Figure 3-1 shows the high-level overview of the
programming process. After entering ICSP mode, the
first action is to Chip Erase the device. Next, the code
memory is programmed, followed by the device
Configuration registers. Code memory (including the
Configuration registers) is then verified to ensure that
programming was successful. Then, program the
code-protect Configuration bits, if required.
FIGURE 3-1: HIGH-LEVEL ICSP™
PROGRAMMING FLOW
Start
Enter ICSP™
Perform Chip
Erase
Program Memory
Verify Program
Program Configuration Bits
Verify Configuration Bits
Exit ICSP
Done
3.2 ICSP Operation
Upon entry into ICSP mode, the CPU is Idle. Execution
of the CPU is governed by an internal state machine. A
4-bit control code is clocked in using PGCx and PGDx,
and this control code is used to command the CPU (see
Table 3-1).
The SIX control code is used to send instructions to the
CPU for execution, and the REGOUT control code is
used to read data out of the device via the VISI register.
TABLE 3-1: CPU CONTROL CODES IN
ICSP™ MODE
4-Bit
Control Code
0000b SIX Shift in 24-bit instruction
0001b REGOUT Shift out the VISI (0784h)
0010b-1111b N/A Reserved.
© 2007 Microchip Technology Inc. DS39907A-page 11
Mnemonic Description
and execute.
register.
PIC24FJXXXGA1/GB1
3.2.1 SIX SERIAL INSTRUCTION EXECUTION
The SIX control code allows execution of PIC24F family
assembly instructions. When the SIX code is received,
the CPU is suspended for 24 clock cycles, as the instruction is then clocked into the internal buffer. Once the
instruction is shifted in, the state machine allows it to be
executed over the next four PGC clock cycles. While the
received instruction is executed, the state machine
simultaneously shifts in the next 4-bit command (see
Figure 3-2).
FIGURE 3-2: SIX SERIAL EXECUTION
4 5
23 123 2324 1 2 3 4
16
PGCx
P3
P2
00
PGDx
0000
Execute PC – 1,
Fetch SIX
Control Code
78 9
Only for
Program
Memory Entry
P4
LSB X X X X X X X X X X X X X X MSB
P1A
P1B
Coming out of Reset, the first 4-bit control code is
always forced to SIX and a forced NOP instruction is
executed by the CPU. Five additional PGCx clocks are
needed on start-up, resulting in a 9-bit SIX command
instead of the normal 4-bit SIX command.
After the forced SIX is clocked in, ICSP operation
resumes as normal. That is, the next 24 clock cycles
load the first instruction word to the CPU.
Note: To account for this forced NOP, all example
P1
456 78 181920212217
24-Bit Instruction Fetch
PGDx = Input
code in this specification begins with a
NOP to ensure that no data is lost.
P4A
0000000
Execute 24-Bit
Instruction, Fetch
Next Control Code
3.2.1.1 Differences Between Execution of
SIX and Normal Instructions
There are some differences between executing instructions normally and using the SIX ICSP command. As a
result, the code examples in this specification may not
match those for performing the same functions during
normal device operation.
The important differences are:
• Two-word instructions require two SIX operations
to clock in all the necessary data.
Examples of two-word instructions are GOTO and
CALL.
• Two-cycle instructions require two SIX operations.
The first SIX operation shifts in the instruction and
begins to execute it. A second SIX operation – which
should shift in a NOP to avoid losing data – provides
the CPU clocks required to finish executing the
instruction.
Examples of two-cycle instructions are table read
and table write instructions.
• The CPU does not automatically stall to account
for pipeline changes.
A CPU stall occurs when an instruction modifies a
register that is used for Indirect Addressing by the
following instruction.
During normal operation, the CPU automatically
will force a NOP while the new data is read. When
using ICSP, there is no automatic stall, so any
indirect references to a recently modified
register should be preceded by a NOP.
For example, the instructions, MOV #0x0,W0 and
MOV [W0],W1, must have a NOP inserted
between them.
If a two-cycle instruction modifies a register that is
used indirectly, it will require two following NOPs: one
to execute the second half of the instruction and a
second to stall the CPU to correct the pipeline.
Instructions such as TBLWTL [W0++],[W1]
should be followed by two NOPs.
• The device Program Counter (PC) continues to
automatically increment during ICSP instruction
execution, even though the Flash memory is not
being used.
As a result, the PC may be incremented to point to
invalid memory locations. Invalid memory spaces
include unimplemented Flash addresses and the
vector space (locations 0x0 to 0x1FF).
If the PC points to these locations, the device will
reset, possibly interrupting the ICSP operation. To
prevent this, instructions should be periodically
executed to reset the PC to a safe space. The optimal method to accomplish this is to perform a
GOTO 0x200.
DS39907A-page 12 © 2007 Microchip Technology Inc.
PIC24FJXXXGA1/GB1
3.2.2 REGOUT SERIAL INSTRUCTION EXECUTION
The REGOUT control code allows for data to be
extracted from the device in ICSP mode. It is used to
clock the contents of the VISI register, out of the device,
over the PGDx pin. After the REGOUT control code is
received, the CPU is held Idle for 8 cycles. After these
8 cycles, an additional 16 cycles are required to clock the
data out (see Figure 3-3).
The REGOUT code is unique because the PGDx pin is
an input when the control code is transmitted to the
device. However, after the control code is processed,
the PGDx pin becomes an output as the VISI register is
shifted out.
FIGURE 3-3: REGOUT SERIAL EXECUTION
PGCx
PGDx
123 4 1 278
P4
1
0
0
123 1234
P5
1234
LSb
Note 1: After the contents of VISI are shifted out,
the PIC24FJXXXGA1/GB1 devices
maintain PGDx as an output until the first
rising edge of the next clock is received.
2: Data changes on the falling edge and
latches on the rising edge of PGCx. For
all data transmissions, the Least
Significant bit (LSb) is transmitted first.
456
11 13 15 161412
P4A
...
11100
MSb
141312
0000
Execute Previous Instruction,
Fetch REGOUT Control Code
PGDx = Input
CPU Held in Idle
Shift Out VISI Register<15:0>
PGDx = Output
No Execution Takes Place,
Fetch Next Control Code
PGDx = Input
© 2007 Microchip Technology Inc. DS39907A-page 13
PIC24FJXXXGA1/GB1
3.3 Entering ICSP Mode
As shown in Figure 3-4, entering ICSP Program/Verify
mode requires three steps:
1. MCLR
2. A 32-bit key sequence is clocked into PGDx.
3. MCLR
The programming voltage applied to MCLR is VIH,
which is essentially V
PIC24FJXXXGA1/GB1 devices. There is no minimum
time requirement for holding at VIH. After VIH is
removed, an interval of at least P18 must elapse before
presenting the key sequence on PGDx.
FIGURE 3-4: ENTERING ICSP™ MODE
MCLR
VDD
PGDx
PGCx
is briefly driven high, then low.
is then driven high within a specified
period of time and held.
DD in the case of
P6
P14
VIH
Program/Verify Entry Code = 4D434851h
0100 0 0
b31 b30 b29 b28 b27 b2 b1 b0b3
P18
1
P1A
P1B
...
The key sequence is a specific 32-bit pattern:
‘0100 1101 0100 0011 0100 1000 0101 0001’
(more easily remembered as 4D434851h in hexadecimal). The device will enter Program/Verify mode only
if the sequence is valid. The Most Significant bit (MSb) of
the most significant nibble must be shifted in first.
Once the key sequence is complete, V
applied to MCLR
and held at that level for as long as
IH must be
Program/Verify mode is to be maintained. An interval of
at least time, P19 and P7, must elapse before presenting data on PGDx. Signals appearing on PGCx before
P7 has elapsed will not be interpreted as valid.
On successful entry, the program memory can be
accessed and programmed in serial fashion. While in
ICSP mode, all unused I/Os are placed in the
high-impedance state.
P19
V
IH
0
1
P7
DS39907A-page 14 © 2007 Microchip Technology Inc.
PIC24FJXXXGA1/GB1
3.4 Flash Memory Programming in
ICSP Mode
3.4.1 PROGRAMMING OPERATIONS
Flash memory write and erase operations are controlled
by the NVMCON register. Programming is performed by
setting NVMCON to select the type of erase operation
(Table 3-2) or write operation (Table 3-3) and initiating
the programming by setting the WR control bit
(NVMCON<15>).
In ICSP mode, all programming operations are
self-timed. There is an internal delay between the user
setting the WR control bit and the automatic clearing of
the WR control bit when the programming operation
is complete. Please refer to Section 7.0 “AC/DC
Characteristics and Timing Requirements” for
information about the delays associated with various
programming operations.
TABLE 3-2: NVMCON ERASE
OPERATIONS
NVMCON
Value
404Fh Erase all code memory, executive
memory and Configuration registers
(does not erase Unit ID or Device ID
registers).
4042h Erase a page of code memory or
executive memory.
TABLE 3-3: NVMCON WRITE
NVMCON
Value
Erase Operation
OPERATIONS
Write Operation
3.5 Erasing Program Memory
The procedure for erasing program memory (all of code
memory, data memory, executive memory and
code-protect bits) consists of setting NVMCON to
404Fh and executing the programming cycle.
A Chip Erase can erase all of user memory or all of both
the user and configuration memory. A table write
instruction should be executed prior to performing the
Chip Erase to select which sections are erased.
When this table write instruction is executed:
• If the TBLPAG register points to user space (is
less than 0x80), the Chip Erase will erase only
user memory.
• If TBLPAG points to configuration space (is
greater than or equal to 0x80), the Chip Erase will
erase both user and configuration memory.
If configuration memory is erased, the internal
oscillator Calibration Word, located at 0x807FE,
will be erased. This location should be stored prior
to performing a whole Chip Erase and restored
afterward to prevent internal oscillators from
becoming uncalibrated.
Figure 3-5 shows the ICSP programming process for
performing a Chip Erase. This process includes the
ICSP command code, which must be transmitted (for
each instruction), Least Significant bit first, using the
PGCx and PGDx pins (see Figure 3-2).
Note: Program memory must be erased before
writing any data to program memory.
FIGURE 3-5: CHIP ERASE FLOW
Start
4003h Write a Configuration Word register.
4001h Program 1 row (64 instruction words) of
code memory or executive memory.
3.4.2 STARTING AND STOPPING A PROGRAMMING CYCLE
The WR bit (NVMCON<15>) is used to start an erase or
write cycle. Setting the WR bit initiates the programming
cycle.
All erase and write cycles are self-timed. The WR bit
should be polled to determine if the erase or write cycle
has been completed. Starting a programming cycle is
performed as follows:
BSET NVMCON, #WR
© 2007 Microchip Technology Inc. DS39907A-page 15
Write 404Fh to NVMCON SFR
Set the WR bit to Initiate Erase
Delay P11 + P10 Time
Done
PIC24FJXXXGA1/GB1
TABLE 3-4: SERIAL INSTRUCTION EXECUTION FOR CHIP ERASE
Command
(Binary)
Step 1: Exit the Reset vector.
0000
0000
0000
Step 2: Set the NVMCON to erase all program memory.
0000
0000
Step 3: Set TBLPAG and perform dummy table write to select what portions of memory are erased.
0000
0000
0000
0000
0000
0000
Step 4: Initiate the erase cycle.
0000
0000
0000
Step 5: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware.
0000
0000
0000
0000
0000
0001
0000
Data
(Hex)
000000
040200
000000
2404FA
883B0A
200000
880190
200000
BB0800
000000
000000
A8E761
000000
000000
040200
000000
803B02
883C22
000000
<VISI>
000000
Description
NOP
GOTO 0x200
NOP
MOV #0x404F, W10
MOV W10, NVMCON
MOV #<PAGEVAL>, W0
MOV W0, TBLPAG
MOV #0x0000, W0
TBLWTL W0,[W0]
NOP
NOP
BSET NVMCON, #WR
NOP
NOP
GOTO 0x200
NOP
MOV NVMCON, W2
MOV W2, VISI
NOP
Clock out contents of the VISI register.
NOP
DS39907A-page 16 © 2007 Microchip Technology Inc.
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