MICROCHIP PIC24FJ64GA004 DATA SHEET

PIC24FJ64GA004 Family

Data Sheet

28/44-Pin General Purpose,

16-Bit Flash Microcontrollers

© 2007 Microchip Technology Inc. Preliminary DS39881B

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K

EELOQ, KEELOQ logo, microID, MPLAB, PIC,

PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and
SmartShunt are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Linear Active Thermistor, Migratable
Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor
and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.

SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC
MCUs and dsPIC® DSCs, KEEL
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.

®

OQ

code hopping devices, Serial

DS39881B-page ii Preliminary © 2007 Microchip Technology Inc.

®

PIC24FJ64GA004 FAMILY

28/44-Pin General Purpose, 16-Bit Flash Microcont rollers

High-Performance CPU:

• Modified Harvard Architecture

• Up to 16 MIPS Operation @ 32 MHz

• 8 MHz Internal Oscillator with 4x PLL Option and

Multiple Divide Options

• 17-Bit by 17-Bit Single-Cycle Hardware Multiplier

• 32-Bit by 16-Bit Hardware Divider

• 16-Bit x 16-Bit Working Register Array

• C Compiler Optimized Instruction Set Architecture:

- 76 base instructions

- Flexible addressing modes

• Two Address Generation Units for Separate Read

and Write Addressing of Data Memory

Special Microcontroller Features:

• Operating Voltage Range of 2.0V to 3.6V

• 5.5V Tolerant Input (digital pins only)

• High-Current Sink/Source (18 mA/18 mA) on All I/O Pins

• Flash Program Memory:

- 10,000 erase/write

- 20-year data retention minimum

• Power Management modes:

- Sleep, Idle, Doze and Alternate Clock modes

- Operating current 650 μA/MIPS typical at 2.0V

- Sleep current 150 nA typical at 2.0V

• Fail-Safe Clock Monitor Operation:

- Detects clock failure and switches to on-chip,
low-power RC oscillator

• On-Chip, 2.5V Regulator with Tracking mode

• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)

• Flexible Watchdog Timer (WDT) with On-Chip,
Low-Power RC Oscillator for Reliable Operation

• In-Circuit Serial Programming™ (ICSP™) and
In-Circuit Debug (ICD) via 2 Pins

• JTAG Boundary Scan and Programming Support

Analog Features:

• 10-Bit, up to 13-Channel Analog-to-Digital Converter:

- 500 ksps conversion rate

- Conversion available during Sleep and Idle

• Dual Analog Comparators with Programmable
Input/Output Configuration

Peripheral Features:

• Peripheral Pin Select:

- Allows independent I/O mapping of many peripherals

- Up to 26 available pins (44-pin devices)

- Continuous hardware integrity checking and safety

interlocks prevent unintentional configuration changes

• 8-Bit Parallel Master/Slave Port (PMP/PSP):

- Up to 16-bit multiplexed addressing, with up to

11 dedicated address pins on 44-pin devices

- Programmable polarity on control lines

• Hardware Real-Time Clock/Calendar (RTCC):

- Provides clock, calendar and alarm functions

• Programmable Cyclic Redundancy Check (CRC)

• Two 3-Wire/4-Wire SPI modules (support 4 Frame
modes) with 8-Level FIFO Buffer

2

•Two I

• Two UART modules:

• Five 16-Bit Timers/Counters with Programmable Prescaler

• Five 16-Bit Capture Inputs

• Five 16-Bit Compare/PWM Outputs

• Configurable Open-Drain Outputs on Digital I/O Pins

• Up to 4 External Interrupt Sources

C™ modules support Multi-Master/Slave

mode and 7-Bit/10-Bit Addressing

- Supports RS-485, RS-232, and LIN 1.2

- On-chip hardware encoder/decoder for IrDA

- Auto-wake-up on Start bit

- Auto-Baud Detect

- 4-level deep FIFO buffer

®

Remappable Peripherals

PIC24FJ

Device

16GA002 28 16K 4K 16 5 5 5 2 2 2 10 2 Y Y

32GA002 28 32K 8K 16 5 5 5 2 2 2 10 2 Y Y

48GA002 28 48K 8K 16 5 5 5 2 2 2 10 2 Y Y

64GA002 28 64K 8K 16 5 5 5 2 2 2 10 2 Y Y

16GA004 44 16K 4K 26 5 5 5 2 2 2 13 2 Y Y

32GA004 44 32K 8K 26 5 5 5 2 2 2 13 2 Y Y

48GA004 44 48K 8K 26 5 5 5 2 2 2 13 2 Y Y

64GA004 44 64K 8K 26 5 5 5 2 2 2 13 2 Y Y

© 2007 Microchip Technology Inc. Preliminary DS39881B-page 1

Pins

Program

SRAM

(bytes)

Memory

(bytes)

Pins

Remappable

16-Bit

Timers

Input

Capture

PWM

Compare/

Output

®

IrDA

UART w/

C™

2

SPI

I

(ch)

10-Bit A/D

Comparators

JTAG

PMP/PSP

PIC24FJ64GA004 FAMILY

Pin Diagrams

28-Pin SPDIP, SSOP, SOIC

PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0

PGC1/EMUC1/AN3/C2IN+/RP1/CN5/RB1

AN4/C1IN-/RP2/SDA2/CN6/RB2

AN5/C1IN+/RP3/SCL2/CN7/RB3

OSCI/CLKI/CN30/RA2

OSCO/CLKO/CN29/PMA0/RA3

SOSCI/RP4/PMBE/CN1/RB4

SOSCO/T1CK/CN0/PMA1/RA4

PGD3/EMUD3/RP5/SDA1

28-Pin QFN

(1)

(1)

AN0/VREF+/CN2/RA0

AN1/V

MCLR

REF-/CN3/RA1

(2)

/CN27/x/RB5

VSS

VDD

DD

V

1
2
3
4
5
6
7

8
9
10
11
12
13
14

28

VSS

27

AN9/RP15/CN11/PMCS1/RB15

26

AN10/CV

25
24

23
22
21
20
19
18

PIC24FJXXGA002

17
16
15

REF/RTCC/RP14/CN12/PMWR/RB14

AN11/RP13/CN13/PMRD/RB13
AN12/RP12/CN14/PMD0/RB12
PGC2/EMUC2/TMS/RP11/CN15/PMD1/RB11
PGD2/EMUD2/TDI/RP10/CN16/PMD2/RB10
V

CAP/VDDCORE

DISVREG
TDO/RP9/SDA1/CN21/PMD3/RB9
TCK/RP8/SCL1/CN22/PMD4/RB8
RP7/INT0/CN23/PMD5/RB7
PGC3/EMUC3/RP6/SCL1

(2)

/CN24/PMD6/RB6

DD

V

VSS

12 13 14

/CN27/PMD7/RB5

/CN24/PMD6/RB6

(2)

(2)

PGD3/EMUD3/RP5/SDA1

PGC3/EMUC3/RP6/SCL1

REF/RTCC/RP14/CN12/PMWR/RB14

AN9/RP15/CN11/PMCS1/RB15

AN10/CV

22

232425262728

AN11/RP13/CN13/PMRD/RB13

21

AN12/RP12/CN14/PMD0/RB12

20

PGC2/EMUC2/TMS/RP11/CN15/PMD1/RB11

19
18

PGD2/EMUD2/TDI/RP10/CN16/PMD2/RB10
V

CAP/VDDCORE

17

DISVREG

16
15

TDO/RP9/SDA1/CN21/PMD3/RB9

RP7/INT0/CN23/PMD5/RB7

TCK/RP8/SCL1/CN22/PMD4/RB8

PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0

PGC1/EMUC1/AN3/C2IN+/RP1/CN5/RB1

AN4/C1IN-/RP2/SDA2/CN6/RB2

AN5/C1IN+/RP3/SCL2/CN7/RB3

V

OSCI/CLKI/CN30/RA2

OSCO/CLKO/CN29/PMA0/RA3

1
2
3

PIC24FJXXGA002

4

SS

5
6
7

8

REF-/CN3/RA1

AN1/V

9

SOSCI/RP4/PMBE/CN1/RB4

AN0/VREF+/CN2/RA0

10 11

SOSCO/T1CK/CN0/PMA1/RA4

MCLR

VDD

Legend: RPn represents remappable peripheral pins.
Note 1: RPn pins can be configured to function as any of the following peripherals: timers, UART, input capture, output

compare, PWM, comparator digital outputs and SPI. For more information, see Section 9.4 “Peripheral Pin
Select” and the specific peripheral sections.

2: Alternative multiplexing for SDA1 and SCL1 when I2C1SEL Configuration bit is cleared.

DS39881B-page 2 Preliminary © 2007 Microchip Technology Inc.

Pin Diagrams (Continued)

44-Pin QFN

RP9/SDA1/CN21/PMD3/RB9

RP22/CN18/PMA1/RC6
RP23/CN17/PMA0/RC7
RP24/CN20/PMA5/RC8
RP25/CN19/PMA6/RC9

PGD2/EMUD2/RP10/CN16/PMD2/RB10

PGC2/EMUC2/RP11/CN15/PMD1/RB11

AN12/RP12/CN14/PMD0/RB12

AN11/RP13/CN13/PMRD/RB13

DISVREG

V

CAP/VDDCORE

PIC24FJ64GA004 FAMILY

/CN27/PMD7/RB5

/CN24/PMD6/RB6

(2)

(2)

DD

PGD3/EMUD3/RP5/SDA1

V

RP7/INT0/CN23/PMD5/RB7

PGC3/EMUC3/RP6/SCL1

15

16

AVSS

VSSRP21/CN26/PMA3/RC5

39

17

RP8/SCL1/CN22/PMD4/RB8

4443424140

1
2
3
4
5

PIC24FJXXGA004

6
7
8
9
10
11

121314

DD

AV

TDI/PMA9/RA9

RP20/CN25/PMA4/RC4

RP19/CN28/PMBE/RC3

38

363435

37

1819202122

MCLR

SOSCO/T1CK/CN0/RA4

SOSCI/RP4/CN1/RB4

33

TDO/PMA8/RA8

32

OSCO/CLKO/CN29/RA3

31

OSCI/CLKI/CN30/RA2

30

VSS

29
28

V

DD

AN8/RP18/CN10/PMA2/RC2

27

AN7/RP17/CN9/RC1

26

AN6/RP16/CN8/RC0

25

AN5/C1IN+/RP3/SCL2/CN7/RB3

24
23

AN4/C1IN-/RP2/SDA2/CN6/RB2

REF-/CN3/RA1

TCK/PMA7/RA7

TMS/PMA10/RA10

AN9/RP15/CN11/PMCS1/RB15

REF/RTCC/RP14/CN12/PMWR/RB14

AN10/CV

REF+/CN2/RA0

AN0/V

AN1/V

PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0

PGC1/EMUC1/AN3/C2IN+/RP1/CN5/RB1

Legend: RPn represents remappable peripheral pins.
Note 1: RPn pins can be configured to function as any of the following peripherals: timers, UART, input capture, output

compare, PWM, comparator digital outputs and SPI. For more information, see Section 9.4 “Peripheral Pin
Select” and the specific peripheral sections.

2: Alternative multiplexing for SDA1 and SCL1 when I2C1SEL Configuration bit is cleared.

© 2007 Microchip Technology Inc. Preliminary DS39881B-page 3

PIC24FJ64GA004 FAMILY

Pin Diagrams (Continued)

44-Pin TQFP

4443424140

1
2
3
4
5

PIC24FJXXGA004

6
7
8
9
10
11

121314

15

16

38

39

37

1819202122

17

363435

33
32
31
30
29
28
27
26
25
24
23

DS39881B-page 4 Preliminary © 2007 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 7

2.0 CPU ........................................................................................................................................................................................... 17

3.0 Memory Organization................................................................................................................................................................. 23

4.0 Flash Program Memory.............................................................................................................................................................. 41

5.0 Resets ........................................................................................................................................................................................ 47

6.0 Interrupt Controller ..................................................................................................................................................................... 53

7.0 Oscillator Configuration.............................................................................................................................................................. 87

8.0 Power-Saving Features.............................................................................................................................................................. 95

9.0 I/O Ports ..................................................................................................................................................................................... 97

10.0 Timer1 ...................................................................................................................................................................................... 117

11.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 119

12.0 Input Capture............................................................................................................................................................................ 125

13.0 Output Compare....................................................................................................................................................................... 127

14.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 133

15.0 Inter-Integrated Circuit (I

16.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 153

17.0 Parallel Master Port (PMP)....................................................................................................................................................... 161

18.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 171

19.0 Programmable Cyclic Redundancy Check (CRC) Generator .................................................................................................. 181

20.0 10-bit High-Speed A/D Converter............................................................................................................................................. 185

21.0 Comparator Module.................................................................................................................................................................. 195

22.0 Comparator Voltage Reference................................................................................................................................................ 199

23.0 Special Features ...................................................................................................................................................................... 201

24.0 Development Support............................................................................................................................................................... 211

25.0 Instruction Set Summary.......................................................................................................................................................... 215

26.0 Electrical Characteristics.......................................................................................................................................................... 223

27.0 Packaging Information.............................................................................................................................................................. 237

Appendix A: Revision History............................................................................................................................................................. 245

Index ................................................................................................................................................................................................. 247

The Microchip Web Site..................................................................................................................................................................... 251

Customer Change Notification Service .............................................................................................................................................. 251

Customer Support .............................................................................................................................................................................. 251

Reader Response .............................................................................................................................................................................. 252

Product Identification System ............................................................................................................................................................ 253

2

C™) ................................................................................................................................................. 143

© 2007 Microchip Technology Inc. Preliminary DS39881B-page 5

PIC24FJ64GA004 FAMILY

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at [e-mail] or fax the Reader Response Form in the back of this data sheet to [phone]. We
welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page)

When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.

Customer Notification System

Register on our web site at www.microchip.com to receive the most current information on all of our products.

DS39881B-page 6 Preliminary © 2007 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

1.0 DEVICE OVERVIEW

This document contains device-specific information for
the following devices:

• PIC24FJ16GA002

• PIC24FJ32GA002

• PIC24FJ48GA002

• PIC24FJ64GA002

• PIC24FJ16GA004

• PIC24FJ32GA004

• PIC24FJ48GA004

• PIC24FJ64GA004

This family introduces a new line of Microchip devices:
a 16-bit microcontroller family with a broad peripheral
feature set and enhanced computational performance.
The PIC24FJ64GA004 family offers a new migration
option for those high-performance applications which
may be outgrowing their 8-bit platforms, but don’t
require the numerical processing power of a digital
signal processor.

1.1 Core Features

1.1.1 16-BIT ARCHITECTURE

Central to all PIC24F devices is the 16-bit modified
Harvard architecture, first introduced with Microchip’s
dsPIC® digital signal controllers. The PIC24F CPU core
offers a wide range of enhancements, such as:

• 16-bit data and 24-bit address paths with the
ability to move information between data and
memory spaces

• Linear addressing of up to 12 Mbytes (program
space) and 64 Kbytes (data)

• A 16-element working register array with built-in
software stack support

• A 17 x 17 hardware multiplier with support for
integer math

• Hardware support for 32 by 16-bit division

• An instruction set that supports multiple
addressing modes and is optimized for high-level
languages such as ‘C’

• Operational performance up to 16 MIPS

1.1.2 POWER-SAVING TECHNOLOGY

All of the devices in the PIC24FJ64GA004 family
incorporate a range of features that can significantly
reduce power consumption during operation. Key
items include:

• On-the-Fly Clock Switching: The device clock
can be changed under software control to the
Timer1 source or the internal, low-power RC
oscillator during operation, allowing the user to
incorporate power-saving ideas into their software
designs.

• Doze Mode Operation: When timing-sensitive
applications, such as serial communications,
require the uninterrupted operation of peripherals,
the CPU clock speed can be selectively reduced,
allowing incremental power savings without
missing a beat.

• Instruction-Based Power-Saving Modes: The
microcontroller can suspend all operations, or
selectively shut down its core while leaving its
peripherals active, with a single instruction in
software.

1.1.3 OSCILLATOR OPTIONS AND

FEATURES

All of the devices in the PIC24FJ64GA004 family offer
five different oscillator options, allowing users a range
of choices in developing application hardware. These
include:

• Two Crystal modes using crystals or ceramic
resonators.

• Two External Clock modes offering the option of a
divide-by-2 clock output.

• A Fast Internal Oscillator (FRC) with a nominal
8 MHz output, which can also be divided under
software control to provide clock speeds as low as
31 kHz.

• A Phase Lock Loop (PLL) frequency multiplier,
available to the external oscillator modes and the
FRC oscillator, which allows clock speeds of up to
32 MHz.

• A separate internal RC oscillator (LPRC) with a
fixed 31 kHz output, which provides a low-power
option for timing-insensitive applications.

The internal oscillator block also provides a stable
reference source for the Fail-Safe Clock Monitor. This
option constantly monitors the main clock source
against a reference signal provided by the internal
oscillator and enables the controller to switch to the
internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.

© 2007 Microchip Technology Inc. Preliminary DS39881B-page 7

PIC24FJ64GA004 FAMILY

1.1.4 EASY MIGRATION

Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve.

The consistent pinout scheme used throughout the
entire family also aids in migrating to the next larger
device. This is true when moving between devices with
the same pin count, or even jumping from 28-pin to
44-pin devices.

The PIC24F family is pin-compatible with devices in the
dsPIC33 family, and shares some compatibility with the
pinout schema for PIC18 and dsPIC30. This extends
the ability of applications to grow from the relatively
simple, to the powerful and complex, yet still selecting
a Microchip device.

1.2 Other Special Features

• Communications: The PIC24FJ64GA004 family
incorporates a range of serial communication
peripherals to handle a range of application
requirements. There are two independent I
modules that support both Master and Slave
modes of operation. Devices also have, through

peripheral pin select feature, two indepen-

the
dent UARTs with built-in IrDA encoder/decoders
and two SPI modules.

• Peripheral Pin Select: The peripheral pin select
feature allows most digital peripherals to be
mapped over a fixed set of digital I/O pins. Users
may independently map the input and/or output of
any one of the many digital peripherals to any one
of the I/O pins.

• Parallel Master/Enhanced Parallel Slave Port:
One of the general purpose I/O ports can be
reconfigured for enhanced parallel data communi­cations. In this mode, the port can be configured
for both master and slave operations, and
supports 8-bit and 16-bit data transfers with up to
16 external address lines in Master modes.

• Real-Time Clock/Calendar: This module
implements a full-featured clock and calendar with
alarm functions in hardware, freeing up timer
resources and program memory space for use of
the core application.

• 10-Bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period, as
well as faster sampling speeds.

2

C

1.3 Details on Individual Family Members

Devices in the PIC24FJ64GA004 family are available
in 28-pin and 44-pin packages. The general block
diagram for all devices is shown in Figure 1-1.

The devices are differentiated from each other in two
ways:

1. Flash program memory (64 Kbytes for

PIC24FJ64GA devices, 48 Kbytes for
PIC24FJ48GA devices, 32 Kbytes for
PIC24FJ32GA devices and 16 Kbytes for
PIC24FJ16GA devices).

2. Internal SRAM memory (4k for PIC24FJ16GA

devices, 8k for all other devices in the family).

3. Available I/O pins and ports (21 pins on 2 ports

for 28-pin devices and 35 pins on 3 ports for
44-pin devices).

All other features for devices in this family are identical.
These are summarized in Table 1-1.

A list of the pin features available on the
PIC24FJ64GA004 family devices, sorted by function, is
shown in Table 1-2. Note that this table shows the pin
location of individual peripheral features and not how
they are multiplexed on the same pin. This information
is provided in the pinout diagrams in the beginning of
the data sheet. Multiplexed features are sorted by the
priority given to a feature, with the highest priority
peripheral being listed first.

DS39881B-page 8 Preliminary © 2007 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ64GA004 FAMILY

Features

16GA002

Operating Frequency DC – 32 MHz

Program Memory (bytes) 16K 32K 48K 64K 16K 32K 48K 64K

Program Memory (instructions) 5,504 11,008 16,512 22,016 5,504 11,008 16,512 22,016

Data Memory (bytes) 4096 8192 4096 8192

Interrupt Sources
(soft vectors/NMI traps)

I/O Ports Ports A, B Ports A, B, C

Total I/O Pins 21 35

Timers:

Total Number (16-bit) 5

32-Bit (from paired 16-bit timers) 2

Input Capture Channels 5

Output Compare/PWM Channels 5

Input Change Notification Interrupt 21 30

Serial Communications:

UART 2

SPI (3-wire/4-wire) 2

I2C™ 2

Parallel Communications (PMP/PSP) Yes

JTAG Boundary Scan Yes

10-Bit Analog-to-Digital Module
(input channels)

Analog Comparators 2

Remappable Pins 16 26

Resets (and delays) POR, BOR, RESET Instruction, MCLR

REPEAT Instruction Hardware Traps, Configuration Word Mismatch

Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations

Packages 28-Pin SPDIP/SSOP/SOIC/QFN 44-Pin QFN/TQFP

Note 1: Peripherals are accessible through remappable pins.

32GA002

48GA002

10 13

(PWRT, OST, PLL Lock)

64GA002

43

(39/4)

16GA004

(1)

(1)

(1)

(1)

(1)

, WDT; Illegal Opcode,

32GA004

48GA004

64GA004

© 2007 Microchip Technology Inc. Preliminary DS39881B-page 9

PIC24FJ64GA004 FAMILY

FIGURE 1-1: PIC24FJ64GA004 FAMILY GENERAL BLOCK DIAGRAM

OSCO/CLKO

OSCI/CLKI

DISVREG

PSV & Table
Data Access

Control Block

Address Latch

Program Memory

Data Latch

Timing

Generation

FRC/LPRC

Oscillators

Precision
Band Gap
Reference

Volt ag e

Regulator

Interrupt

Controller

23

PCU

23

Program Counter
Stac k

Control

Logic

Address Bus

Instruction
Decode &

Control

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

BOR and

(2)

LVD

8

24

Control Signals

16

PCH PCL

Repeat
Control

Logic

Data Bus

16

Inst Latch

Inst Register

Divide

Support

17x17

Multiplier

16

Data Latch

Data RAM

Address

Latch

16

Read AGU
Write AGU

EA MUX

16

Literal Data

16 x 16

W Reg Array

16-Bit ALU

16

(1)

PORTA

RA0:RA9

16

PORTB

RB0:RB15

16

(1)

PORTC

RC0:RC9

(1)

RP

RP0:RP25

16

VDDCORE/VCAP

Timer1

IC1-5

Note 1: Not all pins or features are implemented on all device pinout configurations. See Table 1-2 for I/O port pin descriptions.

2: BOR functionality is provided when the on-board voltage regulator is enabled.
3: Peripheral I/Os are accessible through remappable pins.

V

V

DD,

SS

MCLR

(3)

Timer2/3

(3)

PWM/

OC1-5

(3)

Timer4/5

CN1-22

(3)

RTCC

SPI1/2

(3)

(1)

10-Bit

ADC

I2C1/2

Comparators

UART1/2

(3)

PMP/PSP

(3)

DS39881B-page 10 Preliminary © 2007 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS

Pin Number

Function

AN0 2 27 19 I ANA A/D Analog Inputs.

AN1 3 28 20 I ANA

AN2 4 1 21 I ANA

AN3 5 2 22 I ANA

AN4 6 3 23 I ANA

AN5 7 4 24 I ANA

AN6 — — 25 I ANA

AN7 — — 26 I ANA

AN8 — — 27 I ANA

AN9 26 23 15 I ANA

AN10 25 22 14 I ANA

AN11 24 21 11 I ANA

AN12 23 20 10 I ANA

DD — — 17 P — Positive Supply for Analog Modules.

AV

AV

SS — — 16 P — Ground Reference for Analog Modules.

C1IN- 6 3 23 I ANA Comparator 1 Negative Input.

C1IN+ 7 4 24 I ANA Comparator 1 Positive Input.

C2IN- 4 1 21 I ANA Comparator 2 Negative Input.

C2IN+ 5 2 22 I ANA Comparator 2 Positive Input.

CLKI 9 6 30 I ANA Main Clock Input Connection.

CLKO 10 7 31 O — System Clock Output.

Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer

Note 1: Alternative multiplexing for SDA1 and SCL1 when I2C1SEL Configuration bit is cleared.

28-Pin

SPDIP/

SSOP/SOIC

ANA = Analog level input/output I

28-Pin

QFN

44-Pin

QFN/TQFP

I/O

Input

Buffer

2

C™ = I2C/SMBus input buffer

Description

© 2007 Microchip Technology Inc. Preliminary DS39881B-page 11

PIC24FJ64GA004 FAMILY

TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin Number

Function

CN0 12 9 34 I ST Interrupt-on-Change Inputs.

CN1 11 8 33 I ST

CN2 2 27 19 I ST

CN3 3 28 20 I ST

CN4 4 1 21 I ST

CN5 5 2 22 I ST

CN6 6 3 23 I ST

CN7 7 4 24 I ST

CN8 — — 25 I ST

CN9 — — 26 I ST

CN10 — — 27 I ST

CN11 26 23 15 I ST

CN12 25 22 14 I ST

CN13 24 21 11 I ST

CN14 23 20 10 I ST

CN15 22 19 9 I ST

CN16 21 18 8 I ST

CN17 — — 3 I ST

CN18 — — 2 I ST

CN19 — — 5 I ST

CN20 — — 4 I ST

CN21 18 15 1 I ST

CN22 17 14 44 I ST

CN23 16 13 43 I ST

CN24 15 12 42 I ST

CN25 — — 37 I ST

CN26 — — 38 I ST

CN27 14 11 41 I ST

CN28 — — 36 I ST

CN29 10 7 31 I ST

CN30 9 6 30 I ST

REF 25 22 14 O ANA Comparator Voltage Reference Output.

CV

DISVREG 19 16 6 I ST Voltage Regulator Disable.

EMUC1 5 2 21 I/O ST In-Circuit Emulator Clock Input/Output.

EMUD1 4 1 22 I/O ST In-Circuit Emulator Data Input/Output.

EMUC2 22 19 9 I/O ST In-Circuit Emulator Clock Input/Output.

EMUD2 21 18 8 I/O ST In-Circuit Emulator Data Input/Output.

EMUC3 15 12 42 I/O ST In-Circuit Emulator Clock Input/Output.

EMUD3 14 11 41 I/O ST In-Circuit Emulator Data Input/Output.

INT0 16 13 43 I ST External Interrupt Input.

MCLR

Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer

Note 1: Alternative multiplexing for SDA1 and SCL1 when I2C1SEL Configuration bit is cleared.

28-Pin

SPDIP/

SSOP/SOIC

1 26 18 I ST Master Clear (device Reset) Input. This line is brought low

ANA = Analog level input/output I

28-Pin

QFN

44-Pin

QFN/TQFP

I/O

Input

Buffer

to cause a Reset.

2

C™ = I2C/SMBus input buffer

Description

DS39881B-page 12 Preliminary © 2007 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin Number

Function

OSCI 9 6 30 I ANA Main Oscillator Input Connection.

OSCO 10 7 31 O ANA Main Oscillator Output Connection.

PGC1 5 2 22 I/O ST In-Circuit Debugger and ICSP™ Programming Clock

PGD1 4 1 21 I/O ST In-Circuit Debugger and ICSP Programming Data.

PGC2 22 19 9 I/O ST In-Circuit Debugger and ICSP Programming Clock.

PGD2 21 18 8 I/O ST In-Circuit Debugger and ICSP Programming Data.

PGC3 14 12 42 I/O ST In-Circuit Debugger and ICSP Programming Clock.

PGD3 15 11 41 I/O ST In-Circuit Debugger and ICSP Programming Data.

PMA0 10 7 3 I/O ST Parallel Master Port Address Bit 0 Input (Buffered Slave

PMA1 12 9 2 I/O ST Parallel Master Port Address Bit 1 Input (Buffered Slave

PMA2 — — 27 O — Parallel Master Port Address (Demultiplexed Master

PMA3 — — 38 O —

PMA4 — — 37 O —

PMA5 — — 4 O —

PMA6 — — 5 O —

PMA7 — — 13 O —

PMA8 — — 32 O —

PMA9 — — 35 O —

PMA10 — — 12 O —

PMA11 — — — O —

PMA12 — — — O —

PMA13 — — — O —

PMBE 11 8 36 O — Parallel Master Port Byte Enable Strobe.

PMCS1 26 23 15 O — Parallel Master Port Chip Select 1 Strobe/Address Bit 14.

PMD0 23 20 10 I/O ST Parallel Master Port Data (Demultiplexed Master mode) or

PMD1 22 19 9 I/O ST

PMD2 21 18 8 I/O ST

PMD3 18 15 1 I/O ST

PMD4 17 14 44 I/O ST

PMD5 16 13 43 I/O ST

PMD6 15 12 42 I/O ST

PMD7 14 11 41 I/O ST

PMRD 24 21 11 O — Parallel Master Port Read Strobe.

PMWR 25 22 14 O — Parallel Master Port Write Strobe.

Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer

Note 1: Alternative multiplexing for SDA1 and SCL1 when I2C1SEL Configuration bit is cleared.

28-Pin

SPDIP/

SSOP/SOIC

ANA = Analog level input/output I

28-Pin

QFN

44-Pin

QFN/TQFP

I/O

Input

Buffer

modes) and Output (Master modes).

modes) and Output (Master modes).

modes).

Address/Data (Multiplexed Master modes).

2

C™ = I2C/SMBus input buffer

Description

© 2007 Microchip Technology Inc. Preliminary DS39881B-page 13

PIC24FJ64GA004 FAMILY

TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin Number

Function

RA0 2 27 19 I/O ST PORTA Digital I/O.

RA1 3 28 20 I/O ST

RA2 9 6 30 I/O ST

RA3 10 7 31 I/O ST

RA4 12 9 34 I/O ST

RA7 — — 13 I/O ST

RA8 — — 32 I/O ST

RA9 — — 35 I/O ST

RA10 — — 12 I/O ST

RB0 4 1 21 I/O ST PORTB Digital I/O.

RB1 5 2 22 I/O ST

RB2 6 3 23 I/O ST

RB3 7 4 24 I/O ST

RB4 11 8 33 I/O ST

RB5 14 11 41 I/O ST

RB6 15 12 42 I/O ST

RB7 16 13 43 I/O ST

RB8 17 14 44 I/O ST

RB9 18 15 1 I/O ST

RB10 21 18 8 I/O ST

RB11 22 19 9 I/O ST

RB12 23 20 10 I/O ST

RB13 24 21 11 I/O ST

RB14 25 22 14 I/O ST

RB15 26 23 15 I/O ST

RC0 — — 25 I/O ST PORTC Digital I/O.

RC1 — — 26 I/O ST

RC2 — — 27 I/O ST

RC3 — — 36 I/O ST

RC4 — — 37 I/O ST

RC5 — — 38 I/O ST

RC6 — — 2 I/O ST

RC7 — — 3 I/O ST

RC8 — — 4 I/O ST

RC9 — — 5 I/O ST

Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer

Note 1: Alternative multiplexing for SDA1 and SCL1 when I2C1SEL Configuration bit is cleared.

28-Pin

SPDIP/

SSOP/SOIC

ANA = Analog level input/output I

28-Pin

QFN

44-Pin

QFN/TQFP

I/O

Input

Buffer

2

C™ = I2C/SMBus input buffer

Description

DS39881B-page 14 Preliminary © 2007 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin Number

Function

RP0 4 1 21 I/O ST Remappable Peripheral.

RP1 5 2 22 I/O ST

RP2 6 3 23 I/O ST

RP3 7 4 24 I/O ST

RP4 11 8 33 I/O ST

RP5 14 11 41 I/O ST

RP6 15 12 42 I/O ST

RP7 16 13 43 I/O ST

RP8 17 14 44 I/O ST

RP9 18 15 1 I/O ST

RP10 21 18 8 I/O ST

RP11 22 19 9 I/O ST

RP12 23 20 10 I/O ST

RP13 24 21 11 I/O ST

RP14 25 22 14 I/O ST

RP15 26 23 15 I/O ST

RP16 — — 25 I/O ST

RP17 — — 26 I/O ST

RP18 — — 27 I/O ST

RP19 — — 36 I/O ST

RP20 — — 37 I/O ST

RP21 — — 38 I/O ST

RP22 — — 2 I/O ST

RP23 — — 3 I/O ST

RP24 — — 4 I/O ST

RP25 — — 5 I/O ST

RTCC 25 22 14 O — Real-Time Clock Alarm Output.

SCL1 17, 15

SCL2 7 4 I/O I

SDA1 18, 14

SDA2 6 3 I/O I

SOSCI 11 8 33 I ANA Secondary Oscillator/Timer1 Clock Input.

SOSCO 12 9 34 O ANA Secondary Oscillator/Timer1 Clock Output.

Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer

Note 1: Alternative multiplexing for SDA1 and SCL1 when I2C1SEL Configuration bit is cleared.

28-Pin

SPDIP/

SSOP/SOIC

(1)

(1)

ANA = Analog level input/output I

28-Pin

QFN

14, 12

15, 11

(1)

(1)

44-Pin

QFN/TQFP

(1)

44, 42

(1)

1, 41

Input

I/O

Buffer

I/O I2C I2C1 Synchronous Serial Clock Input/Output.

I/O I2C I2C1 Data Input/Output.

2

C I2C2 Synchronous Serial Clock Input/Output.

2

C I2C2 Data Input/Output.

2

C™ = I2C/SMBus input buffer

Description

© 2007 Microchip Technology Inc. Preliminary DS39881B-page 15

PIC24FJ64GA004 FAMILY

TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin Number

Function

T1CK 12 9 34 I ST Timer1 Clock.

TCK 17 14 13 I ST JTAG Test Clock/Programming Clock Input.

TDI 21 18 35 I ST JTAG Test Data/Programming Data Input.

TDO 18 15 32 O — JTAG Test Data Output.

TMS 22 19 12 I ST JTAG Test Mode Select Input.

DD 13, 28 10, 25 28, 40 P — Positive Supply for Peripheral Digital Logic and I/O Pins.

V

DDCAP 20 17 7 P — External Filter Capacitor Connection (regulator enabled).

V

V

DDCORE 20 17 7 P — Positive Supply for Microcontroller Core Logic (regulator

REF- 3 28 20 I ANA A/D and Comparator Reference Voltage (low) Input.

V

V

REF+ 2 27 19 I ANA A/D and Comparator Reference Voltage (high) Input.

SS 8, 27 5, 24 29, 39 P — Ground Reference for Logic and I/O Pins.

V

Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer

Note 1: Alternative multiplexing for SDA1 and SCL1 when I2C1SEL Configuration bit is cleared.

28-Pin

SPDIP/

SSOP/SOIC

ANA = Analog level input/output I

28-Pin

QFN

44-Pin

QFN/TQFP

I/O

Input

Buffer

disabled).

2

C™ = I2C/SMBus input buffer

Description

DS39881B-page 16 Preliminary © 2007 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

2.0 CPU

The PIC24F CPU has a 16-bit (data) modified Harvard
architecture with an enhanced instruction set and a
24-bit instruction word with a variable length opcode
field. The Program Counter (PC) is 23 bits wide and
addresses up to 4M instructions of user program
memory space. A single-cycle instruction prefetch
mechanism is used to help maintain throughput and pro­vides predictable execution. All instructions execute in a
single cycle, with the exception of instructions that
change the program flow, the double-word move
(MOV.D) instruction and the table instructions. Over­head-free program loop constructs are supported using
the REPEAT instructions, which are interruptible at any
point.

PIC24F devices have sixteen, 16-bit working registers
in the programmer’s model. Each of the working
registers can act as a data, address or address offset
register. The 16th working register (W15) operates as
a Software Stack Pointer for interrupts and calls.

The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K word boundary defined by the 8-bit Program Space
Visibility Page Address (PSVPAG) register. The program
to data space mapping feature lets any instruction
access program space as if it were data space.

The Instruction Set Architecture (ISA) has been
significantly enhanced beyond that of the PIC18, but
maintains an acceptable level of backward compatibil­ity. All PIC18 instructions and addressing modes are
supported, either directly, or through simple macros.
Many of the ISA enhancements have been driven by
compiler efficiency needs.

The core supports Inherent (no operand), Relative,
Literal, Memory Direct and three groups of addressing
modes. All modes support Register Direct and various
Register Indirect modes. Each group offers up to seven
addressing modes. Instructions are associated with
predefined addressing modes depending upon their
functional requirements.

For most instructions, the core is capable of executing
a data (or program data) memory read, a working reg-

© 2007 Microchip Technology Inc. Preliminary DS39881B-page 17

PIC24FJ64GA004 FAMILY

FIGURE 2-1: PIC24F CPU CORE BLOCK DIAGRAM

PSV & Table
Data Access

Control Block

Interrupt

Controller

8

23

23

23

PCU

Program Counter

Stac k

Control

Logic

16

PCH PCL

Loop

Control

Logic

Data Bus

16

16

Data Latch

Data RAM

Address

Latch

16

16

Address Latch

Program Memory

Data Latch

Address Bus

24

Instruction

Decode &

Control

Control Signals

to Various Blocks

ROM Latch

Instruction Reg

Hardware
Multiplier

Divide

Support

RAGU
WAGU

EA MUX

16

16

Literal Data

16 x 16

W Register Array

16-Bit ALU

16

16

To Peripheral Modules

DS39881B-page 18 Preliminary © 2007 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

TABLE 2-1: CPU CORE REGISTERS

Register(s) Name Description

W0 through W15 Working Register Array

PC 23-Bit Program Counter

SR ALU STATUS Register

SPLIM Stack Pointer Limit Value Register

TBLPAG Table Memory Page Address Register

PSVPAG Program Space Visibility Page Address Register

RCOUNT Repeat Loop Counter Register

CORCON CPU Control Register

FIGURE 2-2: PROGRAMMER’S MODEL

015

Divider Working Registers

Multiplier Registers

W0 (WREG)

W1

W2

W3

W4

W5

W6

W7

W8

W9

W10

W11

W12

W13

W14

W15

Frame Pointer

Stack Pointer

Working/Address
Registers

0

SPLIM

22

PC

7

TBLPAG

7

PSVPAG

15

RCOUNT

SRH

15

———————

15 0

————————————

Registers or bits shadowed for PUSH.S and POP.S instructions.

© 2007 Microchip Technology Inc. Preliminary DS39881B-page 19

DC

IPL

210

SRL

NOVZ C

RA

IPL3 PSV

0

0

0

0

0

0

0

——

Stack Pointer Limit
Value Register

Program Counter

Table Memory Page
Address Register

Program Space Visibility
Page Address Register

Repeat Loop Counter
Register

ALU STATUS Register (SR)

CPU Control Register (CORCON)

PIC24FJ64GA004 FAMILY

2.2 CPU Control Registers

REGISTER 2-1: SR: ALU STATUS REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — —DC

bit 15 bit 8

(1)

-0

R/W

(2)

IPL2

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-9 Unimplemented: Read as ‘0’

bit 8 DC: ALU Half Carry/Borrow bit

1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)

0 = No carry-out from the 4th or 8th low-order bit of the result has occurred

bit 7-5 IPL2:IPL0: CPU Interrupt Priority Level Status bits

111 = CPU interrupt priority level is 7 (15); user interrupts disabled.
110 = CPU interrupt priority level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU interrupt priority level is 4 (12)
011 = CPU interrupt priority level is 3 (11)
010 = CPU interrupt priority level is 2 (10)
001 = CPU interrupt priority level is 1 (9)
000 = CPU interrupt priority level is 0 (8)

bit 4 RA: REPEAT Loop Active bit

1 = REPEAT loop in progress
0 = REPEAT loop not in progress

bit 3 N: ALU Negative bit

1 = Result was negative
0 = Result was non-negative (zero or positive)

bit 2 OV: ALU Overflow bit

1 = Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation
0 = No overflow has occurred

bit 1 Z: ALU Zero bit

1 = An operation which effects the Z bit has set it at some time in the past
0 = The most recent operation which effects the Z bit has cleared it (i.e., a non-zero result)

bit 0 C: ALU Carry/Borrow

1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred

(1)

R/W-0

(2)

IPL1

of the result occurred

R/W-0

IPL0

bit

(2)

(1)

R-0 R/W-0 R/W-0 R/W-0 R/W-0

RA N OV Z C

(1,2)

Note 1: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.

2: The IPL Status bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority

Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1.

DS39881B-page 20 Preliminary © 2007 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

REGISTER 2-2: CORCON: CPU CONTROL REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 R/C-0 R/W

— — — —IPL3

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-4 Unimplemented: Read as ‘0’

bit 3 IPL3: CPU Interrupt Priority Level Status bit

1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less

bit 2 PSV: Program Space Visibility in Data Space Enable bit

1 = Program space visible in data space
0 = Program space not visible in data space

bit 1-0 Unimplemented: Read as ‘0’

Note 1: User interrupts are disabled when IPL3 = 1.

2.3 Arithmetic Logic Unit (ALU)

The PIC24F ALU is 16 bits wide and is capable of addi­tion, subtraction, bit shifts and logic operations. Unless
otherwise mentioned, arithmetic operations are 2’s
complement in nature. Depending on the operation, the
ALU may affect the values of the Carry (C), Zero (Z),
Negative (N), Overflow (OV) and Digit Carry (DC)
Status bits in the SR register. The C and DC Status bits
operate as Borrow
for subtraction operations.

The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array, or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.

and Digit Borrow bits, respectively,

(1)

(1)

The PIC24F CPU incorporates hardware support for
both multiplication and division. This includes a dedi­cated hardware multiplier and support hardware for
16-bit divisor division.

2.3.1 MULTIPLIER

The ALU contains a high-speed, 17-bit x 17-bit
multiplier. It supports unsigned, signed or mixed sign
operation in several multiplication modes:

1. 16-bit x 16-bit signed

2. 16-bit x 16-bit unsigned

3. 16-bit signed x 5-bit (literal) unsigned

4. 16-bit unsigned x 16-bit unsigned

5. 16-bit unsigned x 5-bit (literal) unsigned

6. 16-bit unsigned x 16-bit signed

7. 8-bit unsigned x 8-bit unsigned

-0 U-0 U-0

PSV — —

© 2007 Microchip Technology Inc. Preliminary DS39881B-page 21

PIC24FJ64GA004 FAMILY

2.3.2 DIVIDER

The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:

1. 32-bit signed/16-bit signed divide

2. 32-bit unsigned/16-bit unsigned divide

3. 16-bit signed/16-bit signed divide

4. 16-bit unsigned/16-bit unsigned divide

The quotient for all divide instructions ends up in W0
and the remainder in W1. Sixteen-bit signed and
unsigned DIV instructions can specify any W register
for both the 16-bit divisor (Wn), and any W register
(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.
The divide algorithm takes one cycle per bit of divisor,
so both 32-bit/16-bit and 16-bit/16-bit instructions take
the same number of cycles to execute.

2.3.3 MULTI-BIT SHIFT SUPPORT

The PIC24F ALU supports both single bit and
single-cycle, multi-bit arithmetic and logic shifts.
Multi-bit shifts are implemented using a shifter block,
capable of performing up to a 15-bit arithmetic right
shift, or up to a 15-bit left shift, in a single cycle. All
multi-bit shift instructions only support Register Direct
Addressing for both the operand source and result
destination.

A full summary of instructions that use the shift
operation is provided below in Table 2-2.

TABLE 2-2: INSTRUCTIONS THAT USE THE SINGLE AND MULTI-BIT SHIFT OPERATION

Instruction Description

ASR Arithmetic shift right source register by one or more bits.

SL Shift left source register by one or more bits.

LSR Logical shift right source register by one or more bits.

DS39881B-page 22 Preliminary © 2007 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

3.0 MEMORY ORGANIZATION

from either the 23-bit Program Counter (PC) during pro­gram execution, or from table operation or data space

As Harvard architecture devices, PIC24F micro­controllers feature separate program and data memory
spaces and busses. This architecture also allows the
direct access of program memory from the data space
during code execution.

3.1 Program Address Space

The program address memory space of
PIC24FJ64GA004 family devices is 4M instructions.
The space is addressable by a 24-bit value derived

remapping, as described in Section 3.3 “Interfacing
Program and Data Memory Spaces”.

User access to the program memory space is restricted
to the lower half of the address range (000000h to
7FFFFFh). The exception is the use of TBLRD/TBLWT
operations which use TBLPAG<7> to permit access to
the Configuration bits and device ID sections of the
configuration memory space.

Memory maps for the PIC24FJ64GA004 family of
devices are shown in Figure 3-1.

FIGURE 3-1: PROGRAM SPACE MEMORY MAP FOR PIC24FJ64GA004 FAMILY DEVICES

PIC24FJ16GA

GOTO Instruction

Reset Address

Interrupt Vector Table

Reserved

Alternate Vector Table

User Flash

Program Memory

(5.5K instructions)

Flash Config Words

PIC24FJ32GA

GOTO Instruction

Reset Address

Interrupt Vector Table

Reserved

Alternate Vector Table

User Flash

Program Memory

(11K instructions)

PIC24FJ48GA

GOTO Instruction

Reset Address

Interrupt Vector Table

Reserved

Alternate Vector Table

User Flash
Program Memory
(16K instructions)

PIC24FJ64GA

GOTO Instruction

Reset Address

Interrupt Vector Table

Reserved

Alternate Vector Table

User Flash
Program Memory
(22K instructions)

000000h
000002h
000004h

0000FEh
000100h
000104h

0001FEh
000200h

002BFEh
002C00h

User Memory Space

Unimplemented

Read ‘0’

Reserved

Device Config Registers

Reserved

Configuration Memory Space

DEVID (2)

Flash Config Words

Unimplemented

Read ‘0’

Reserved

Device Config Registers

Reserved

DEVID (2)

Flash Config Words

Unimplemented

Read ‘0’

Reserved

Device Config Registers

Reserved

DEVID (2)

Flash Config Words

Unimplemented

Read ‘0’

Reserved

Device Config Registers

Reserved

DEVID (2)

0057FEh
005800h

0083FEh
008400h

00ABFEh
00AC00h

7FFFFFh
800000h

F7FFFEh
F80000h

F8000Eh
F80010h

FEFFFEh
FF0000h

FFFFFFh

Note: Memory areas are not shown to scale.

© 2007 Microchip Technology Inc. Preliminary DS39881B-page 23

PIC24FJ64GA004 FAMILY

3.1.1 PROGRAM MEMORY ORGANIZATION

The program memory space is organized in
word-addressable blocks. Although it is treated as
24 bits wide, it is more appropriate to think of each
address of the program memory as a lower and upper
word, with the upper byte of the upper word being
unimplemented. The lower word always has an even
address, while the upper word has an odd address
(Figure 3-2).

Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or
decremented by two during code execution. This
arrangement also provides compatibility with data
memory space addressing and makes it possible to
access data in the program memory space.

3.1.2 HARD MEMORY VECTORS

All PIC24F devices reserve the addresses between
00000h and 000200h for hard coded program execu­tion vectors. A hardware Reset vector is provided to
redirect code execution from the default value of the
PC on device Reset to the actual start of code. A GOTO
instruction is programmed by the user at 000000h, with
the actual address for the start of code at 000002h.

PIC24F devices also have two interrupt vector tables,
located from 000004h to 0000FFh and 000100h to
0001FFh. These vector tables allow each of the many
device interrupt sources to be handled by separate
ISRs. A more detailed discussion of the interrupt vector
tables is provided in Section 6.1 “Interrupt Vector
Tabl e”.

3.1.3 FLASH CONFIGURATION WORDS

In PIC24FJ64GA004 family devices, the top two words
of on-chip program memory are reserved for configura­tion information. On device Reset, the configuration
information is copied into the appropriate Configuration
registers. The addresses of the Flash Configuration
Word for devices in the PIC24FJ64GA004 family are
shown in Table 3-1. Their location in the memory map
is shown with the other memory vectors in Figure 3-1.

The Configuration Words in program memory are a
compact format. The actual Configuration bits are
mapped in several different registers in the configuration
memory space. Their order in the Flash Configuration
Words do not reflect a corresponding arrangement in the
configuration space. Additional details on the device
Configuration Words are provided in Section 23.1

“Configuration Bits”.

TABLE 3-1: FLASH CONFIGURATION

WORDS FOR PIC24FJ64GA004
FAMILY DEVICES

Program

Device

PIC24FJ16GA 5.5

PIC24FJ32GA 11

PIC24FJ48GA 16

PIC24FJ64GA 22

Memory

(K words)

Configuration

Word

Addresses

002BFCh:

002BFEh

0057FCh:

0057FEh

0083FCh:

0083FEh

00ABFCh:

00ABFEh

FIGURE 3-2: PROGRAM MEMORY ORGANIZATION

msw

Address (lsw Address)

000001h
000003h
000005h
000007h

DS39881B-page 24 Preliminary © 2007 Microchip Technology Inc.

most significant word

23

00000000

00000000

00000000

00000000

Program Memory

‘Phantom’ Byte

(read as ‘0’)

least significant word

Instruction Width

PC Address

0816

000000h
000002h
000004h
000006h

PIC24FJ64GA004 FAMILY

3.2 Data Address Space

The PIC24F core has a separate, 16-bit wide data mem­ory space, addressable as a single linear range. The
data space is accessed using two Address Generation
Units (AGUs), one each for read and write operations.
The data space memory map is shown in Figure 3-3.

All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to bytes within the data space.
This gives a data space address range of 64 Kbytes or
32K words. The lower half of the data memory space
(that is, when EA<15> = 0) is used for implemented
memory addresses, while the upper half (EA<15> = 1) is
reserved for the program space visibility area (see

Section 3.3.3 “Reading Data from Program Memory
Using Program Space Visibility”).

PIC24FJ64GA family devices implement a total of
8 Kbytes of data memory. Should an EA point to a
location outside of this area, an all zero word or byte will
be returned.

3.2.1 DATA SPACE WIDTH

The data memory space is organized in
byte-addressable, 16-bit wide blocks. Data is aligned
in data memory and registers as 16-bit words, but all
data space EAs resolve to bytes. The Least Significant
Bytes of each word have even addresses, while the
Most Significant Bytes have odd addresses.

FIGURE 3-3: DATA SPACE MEMORY MAP FOR PIC24FJ64GA004 FAMILY DEVICES

LSB

Address

0000h

07FEh
0800h

1FFEh
2000h

27FEh
2800h

SFR

Space

Near

Data Space

(2)

Implemented

Data RAM

MSB

Address

0001h

07FFh

0801h

1FFFh

2001h

27FFh

2801h

LSBMSB

SFR Space

Data RAM

(2)

(1)

Unimplemented

Read as ‘0’

7FFFh

8001h

Program Space

Visibility Area

FFFFh

Note 1: Data memory areas are not shown to scale.

2: Upper memory limit for PIC24FJ16GAXXX devices is 17FFh.

7FFFh
8000h

FFFEh

© 2007 Microchip Technology Inc. Preliminary DS39881B-page 25

PIC24FJ64GA004 FAMILY

3.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT

To maintain backward compatibility with PIC
and improve data space memory usage efficiency, the
PIC24F instruction set supports both word and byte
operations. As a consequence of byte accessibility, all
effective address calculations are internally scaled to
step through word-aligned memory. For example, the
core recognizes that Post-Modified Register Indirect
Addressing mode [Ws++] will result in a value of Ws + 1
for byte operations and Ws + 2 for word operations.

Data byte reads will read the complete word which con­tains the byte, using the LSb of any EA to determine
which byte to select. The selected byte is placed onto
the LSB of the data path. That is, data memory and reg­isters are organized as two parallel, byte-wide entities
with shared (word) address decode but separate write
lines. Data byte writes only write to the corresponding
side of the array or register which matches the byte
address.

All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word opera­tions, or translating from 8-bit MCU code. If a
misaligned read or write is attempted, an address error
trap will be generated. If the error occurred on a read,
the instruction underway is completed; if it occurred on
a write, the instruction will be executed but the write will
not occur. In either case, a trap is then executed, allow­ing the system and/or user to examine the machine
state prior to execution of the address Fault.

All byte loads into any W register are loaded into the
Least Significant Byte. The Most Significant Byte is not
modified.

®

devices

A sign-extend instruction (SE) is provided to allow
users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, users
can clear the MSB of any W register by executing a
zero-extend (ZE) instruction on the appropriate
address.

Although most instructions are capable of operating on
word or byte data sizes, it should be noted that some
instructions operate only on words.

3.2.3 NEAR DATA SPACE

The 8-Kbyte area between 0000h and 1FFFh is
referred to as the near data space. Locations in this
space are directly addressable via a 13-bit absolute
address field within all memory direct instructions. The
remainder of the data space is addressable indirectly.
Additionally, the whole data space is addressable using
MOV instructions, which support Memory Direct
Addressing with a 16-bit address field.

3.2.4 SFR SPACE

The first 2 Kbytes of the near data space, from 0000h
to 07FFh, are primarily occupied with Special Function
Registers (SFRs). These are used by the PIC24F core
and peripheral modules for controlling the operation of
the device.

SFRs are distributed among the modules that they con­trol and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’. A diagram of the SFR space,
showing where SFRs are actually implemented, is
shown in Table 3-2. Each implemented area indicates
a 32-byte region where at least one address is imple­mented as an SFR. A complete listing of implemented
SFRs, including their addresses, is shown in Tables 3-3
through 3-24.

TABLE 3-2: IMPLEMENTED REGIONS OF SFR DATA SPACE

SFR Space Address

xx00 xx20 xx40 xx60 xx80 xxA0 xxC0 xxE0

000h Core ICN Interrupts

100h Timers Capture

2

200h I

300h A/D — — — — — —

400h

500h

600h PMP RTC/Comp CRC — PPS

700h

Legend: — = No implemented SFRs in this block

DS39881B-page 26 Preliminary © 2007 Microchip Technology Inc.

C™ UART SPI — — I/O

— — — — — — — —

— — — — — — — —

— — System NVM/PMD — — — —

— Compare — — —

—

PIC24FJ64GA004 FAMILY

All

All

0000

0000

0000

Resets

Resets

0000

CN16IE

CN16PUE

(1)

(1)

CN17IE

CN17PUE

(1)

(1)

CN18IE

CN18PUE

(1)

(1)

CN19IE

CN19PUE

(1)

(1)

— — — — — — — — Program Counter High Byte Register 0000

— — — — — — — — Table Memory Page Address Register 0000

— — — — — — — — Program Space Visibility Page Address Register 0000

— — — — — — — DC IPL2 IPL1 IPL0 RA N OV Z C 0000

— — — — — — — — — — — — IPL3 PSV — — 0000

— — Disable Interrupts Counter Register xxxx

CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE

CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE

(1)

(1)

CN24IE CN23IE CN22IE CN21IE CN20IE

CN8IE

(1)

CN9IE

(1)

CN24PUE CN23PUE CN22PUE CN21PUE CN20PUE

CN8PUE

(1)

(1)

(1)

CN25IE

CN9PUE

CN25PUE

(1)

(1)

(1)

CN27IE CN26IE

CN27PUE CN26PUE

(1)

(1)

CN30IE CN29IE CN28IE

CN30PUE CN29PUE CN28PUE

CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE

AddrBit 15Bit 14Bit 13Bit 12Bit 11Bit 10Bit 9Bit 8Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

File

Name

WREG0 0000 Working Register 0 0000

WREG1 0002 Working Register 1 0000

WREG2 0004 Working Register 2 0000

WREG3 0006 Working Register 3 0000

WREG4 0008 Working Register 4 0000

WREG5 000A Working Register 5 0000

WREG6 000C Working Register 6 0000

WREG7 000E Working Register 7 0000

WREG8 0010 Working Register 8 0000

WREG9 0012 Working Register 9 0000

WREG10 0014 Working Register 10 0000

WREG11 0016 Working Register 11 0000

WREG12 0018 Working Register 12 0000

WREG13 001A Working Register 13 0000

WREG14 001C Working Register 14 0000

WREG15 001E Working Register 15 0800

TABLE 3-3: CPU CORE REGISTERS MAP

SPLIM 0020 Stack Pointer Limit Value Register xxxx

PCL 002E Program Counter Low Byte Register 0000

TBLPAG 0032

PSVPAG 0034

PCH 0030

RCOUNT 0036 Repeat Loop Counter Register xxxx

CORCON 0044

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

DISICNT 0052

SR 0042

File

Name

CNEN1 0060

CNEN2 0062 —

CNPU1 0068

CNPU2 006A —

TABLE 3-4: ICN REGISTER MAP

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

© 2007 Microchip Technology Inc. Preliminary DS39881B-page 27

Note 1: Bits not available on 28-pin devices; read as ‘0’.

PIC24FJ64GA004 FAMILY

All

Resets

— — — — INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000

— — — — — — — — — — — INT2EP INT1EP INT0EP 0000

— — — — — — — — — — MATHERR ADDRERR STKERR OSCFAIL — 0000

— — AD1IF U1TXIF U1RXIF SPI1IF SPF1IF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF 0000

— —PMPIF— — —OC5IF— IC5IF IC4IF IC3IF — — — SPI2IF SPF2IF 0000

—RTCIF— — — — — — — — — — —MI2C2IFSI2C2IF— 0000

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

— — — — — — —LVDIF— — — — CRCIF U2ERIF U1ERIF — 0000

— — AD1IE U1TXIE U1RXIE SPI1IE SPF1IE T3IE T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE 0000

— — — — INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000

— —PMPIE— — —OC5IE— IC5IE IC4IE IC3IE — — — SPI2IE SPF2IE 0000

—RTCIE— — — — — — — — — — — MI2C2IE SI2C2IE — 0000

— — — — — — —LVDIE— — — — CRCIE U2ERIE U1ERIE — 0000

— T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 4444

— T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 — IC2IP2 IC2IP1 IC2IP0 — — — — 4444

— U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPF1IP2 SPF1IP1 SPF1IP0 — T3IP2 T3IP1 T3IP0 4444

— — — — — — — — — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0 4444

— CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 — MI2C1P2 MI2C1P1 MI2C1P0 — SI2C1P2 SI2C1P1 SI2C1P0 4444

— — — — — — — — — — — — — INT1IP2 INT1IP1 INT1IP0 4444

— T4IP2 T4IP1 T4IP0 — OC4IP2 OC4IP1 OC4IP0 — OC3IP2 OC3IP1 OC3IP0 — — — — 4444

— U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 — INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0 4444

— — — — — — — — — SPI2IP2 SPI2IP1 SPI2IP0 — SPF2IP2 SPF2IP1 SPF2IP0 4444

— IC5IP2 IC5IP1 IC5IP0 — IC4IP2 IC4IP1 IC4IP0 — IC3IP2 IC3IP1 IC3IP0 — — — — 4444

— — — — — — — — — OC5IP2 OC5IP1 OC5IP0 — — — — 4444

— — — — — — — — — PMPIP2 PMPIP1 PMPIP0 — — — — 4444

— — — — — MI2C2P2 MI2C2P1 MI2C2P0 — SI2C2P2 SI2C2P1 SI2C2P0 — — — — 4444

— — — — — RTCIP2RTCIP1RTCIP0 — — — — — — — — 4444

— CRCIP2 CRCIP1 CRCIP0 — U2ERIP2 U2ERIP1 U2ERIP0 — U1ERIP2 U1ERIP1 U1ERIP0 — — — — 4444

— — — — — — — — — — — — — LVDIP2 LVDIP1 LVDIP0 4444

File

Name

INTCON1 0080 NSTDIS

INTCON2 0082 ALTIVT DISI

IFS1 0086 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF

TABLE 3-5: INTERRUPT CONTROLLER REGISTER MAP

IFS0 0084

IFS4 008C

IEC0 0094

IFS3 008A

IFS2 0088

IEC1 0096 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE

IEC4 009C

IPC0 00A4

IEC3 009A

IEC2 0098

IPC2 00A8

IPC1 00A6

IPC3 00AA

IPC4 00AC

IPC7 00B2

IPC5 00AE

IPC6 00B0

IPC10 00B8

IPC11 00BA

IPC12 00BC

IPC15 00C2

IPC16 00C4

IPC8 00B4

IPC9 00B6

IPC18 00C8

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

DS39881B-page 28 Preliminary © 2007 Microchip Technology Inc.