MICROCHIP PIC24FJ128GA Technical data

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PIC24FJ128GA Family

Data Sheet

General Purpose,

16-Bit Flash Microcontrollers

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and Zena are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

8-bit MCUs, KEEL

code hopping

PIC24FJ128GA FAMILY

General Purpose, 16-bit Flash Microcontrollers

High-Performance CPU:

• Modified Harvard Architecture

• Up to 16 MIPS operation @ 32 MHz

• 8 MHz internal oscillator:

- 4x PLL option

- Multiple divide options

• 17-bit x 17-bit Single-Cycle Hardware

Fractional/Integer Multiplier

• 32-bit by 16-bit Hardware Divider

• 16 x 16-bit Working Register Array

• C compiler Optimized Instruction Set Architecture:

- 76 base instructions

- Flexible addressing modes

• Linear Program Memory Addressing up to 12 Mbytes

• Linear Data Memory Addressing up to 64 Kbytes

• Two Address Generation Units for separate Read

and Write Addressing of Data Memory

Special Microcontroller Features:

• Operating Voltage Range of 2.0V to 3.6V

• Flash Program Memory:

- 1000 erase/write cycles, typical

- Flash retention 20 years, typical

• Self-Reprogrammable under Software Control

• Selectable Power Management modes:

- Sleep, Idle and Alternate Clock modes

• Fail-Safe Clock Monitor operation:

- Detects clock failure and switches to on-chip, low-power RC oscillator

• On-Chip LDO Regulator

• JTAG Boundary Scan and Programming Support

• Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

• Flexible Watchdog Timer (WDT) with On-Chip, Low-Power RC Oscillator for reliable operation

• In-Circuit Serial Programming™ (ICSP™) and In-Circuit Emulation (ICE) via 2 pins

Analog Features:

• 10-bit, up to 16-channel Analog-to-Digital Converter (A/D):

- 500 ksps conversion rate

- Conversion available during Sleep and Idle

• Dual Analog Comparators with Programmable Input/Output Configuration

Peripheral Features:

• Two 3-wire/4-wire SPI modules, supporting 4 Frame modes with 4-level FIFO Buffer

•Two I2C™ modules support Multi-Master/Slave mode and 7-bit/10-bit Addressing

• Two UART modules:

- Supports RS-232, RS-485 and LIN 1.2

- Supports IrDA

- Auto-Wake-up on Start bit

- Auto-Baud Detect

- 4-level FIFO buffer

• Parallel Master Slave Port (PMP/PSP):

- Supports 8-bit or 16-bit data

- Supports 16 address lines

• Hardware Real-Time Clock/Calendar (RTCC):

- Provides clock, calendar and alarm functions

• Five 16-bit Timers/Counters with Programmable prescaler

• Five 16-bit Capture Inputs

• Five 16-bit Compare/PWM Outputs

• High-Current Sink/Source on select I/O pins: 18 mA/18 mA

• Configurable Open-Drain Output on Digital I/O pins

• Up to 5 External Interrupt Sources

with on-chip hardware endec

Program

Device Pins

PIC24FJ64GA006 64 64K 8K 5 5 5 2 2 2 16 2 Y Y

PIC24FJ96GA006 64 96K 8K 5 5 5 2 2 2 16 2 Y Y

PIC24FJ128GA006 64 128K 8K 5 5 5 2 2 2 16 2 Y Y

PIC24FJ64GA008 80 64K 8K 5 5 5 2 2 2 16 2 Y Y

PIC24FJ96GA008 80 96K 8K 5 5 5 2 2 2 16 2 Y Y

PIC24FJ128GA008 80 128K 8K 5 5 5 2 2 2 16 2 Y Y

PIC24FJ64GA010 100 64K 8K 5 5 5 2 2 2 16 2 Y Y

PIC24FJ96GA010 100 96K 8K 5 5 5 2 2 2 16 2 Y Y

PIC24FJ128GA010 100 128K 8K 5 5 5 2 2 2 16 2 Y Y

Memory

(Bytes)

SRAM

(Bytes)

Timers

16-bit

Input

Capture

Compare/

PWM Output

SPI I2C™

UART

10-bit

A/D (ch)

PMP/PSP

Comparators

JTAG

PIC24FJ128GA FAMILY

Pin Diagrams

64-Pin TQFP

PMD4/RE4

PMD3/RE3

PMD2/RE2

PMD1/RE1

PMD0/RE0

RF1

636261596058575654555352514950

3 4

5 6

8 9

10 11

14 15

PIC24FJXXGA006

PIC24FJXXXGA006

2244242526272829303132

192021

PMA5/SCK2/CN8/RG6

PMA4/SDI2/CN9/RG7

PMA3/SDO2/CN10/RG8

PMA2/SS2

C2IN-/AN2/SS1

PGC1/EMUC1/V

PGD1/EMUD1/PMA6/V

PMD5/RE5 PMD6/RE6 PMD7/RE7

MCLR

/CN11/RG9

VSS V

C1IN+/AN5/CN7/RB5

C1IN-/AN4/CN6/RB4

C2IN+/AN3/CN5/RB3

/CN4/RB2

REF-/AN1/CN3/RB1

REF+/AN0/CN2/RB0

RF0

ENVREG

CAP/VDDCORE

CN15/RD6

PMRD/CN14/RD5

PMWR/OC5/IC5/CN13/RD4

PMBE/OC4/RD3

OC3/RD2

CN16/RD7

OC2/RD1

SOSCO/T1CK/CN0/RC14

SOSCI/CN1/RC13

OC1/RD0 IC4/PMCS1/INT4/RD11

IC3/PMCS2/INT3/RD10

IC2/U1CTS

IC1/RTCC/INT1/RD8

Vss

OSC2/CLKO/RC15

OSC1/CLKI/RC12

SCL1/RG2

SDA1/RG3

U1RTS

U1RX/SDI1/RF2

U1TX/SDO1/RF3

//INT2/RD9

/BCLK1/SCK1/INT0/RF6

PGD2/EMUD2/AN7/RB7

PGC2/EMUC2/AN6/OCFA/RB6

AVDD

VSS

REF/AN10/RB10

/BCLK2/AN14/RB14

PMA7/C2OUT/AN9/RB9

TDO/PMA12/AN11/RB11

U2CTS/C1OUT/AN8/RB8

TMS/PMA13/CV

TDI/PMA10/AN13/RB13

TCK/PMA11/AN12/RB12

PMA8/U2TX/SCL2/CN18/RF5

PMA9/U2RX/SDA2/CN17/RF4

PMA0/AN15/OCFB/CN12/RB15

PMA1/U2RTS

Pin Diagrams (Continued)

80-Pin TQFP

PMD4/RE4

PMD3/RE3

PMD2/RE2

PMD1/RE1

PMD0/RE0

PIC24FJ128GA FAMILY

CAP/VDDCORE

PMRD/CN14/RD5

PMWR/OC5/CN13/RD4

CN19/RD13

IC5/RD12

PMBE/OC4/RD3

OC3/RD2

RG0

RG1

RF0

ENVREG

RF1

CN16/RD7

CN15/RD6

OC2/RD1

PMD5/RE5 PMD6/RE6 PMD7/RE7

T2CK/RC1 T4CK/RC3

PMA5/SCK2/CN8/RG6

PMA4/SDI2/CN9/RG7

PMA3/SDO2/CN10/RG8

MCLR

PMA2/SS2

C1IN+/AN5/CN7/RB5

C2IN+/AN3/CN5/RB3

C2IN-/AN2/SS1

PGC1/EMUC1/AN1/CN3/RB1

PGD1/EMUD1/AN0/CN2/RB0

/CN11/RG9

VSS

V TMS/INT1/RE8 TDO/INT2/RE9

C1IN-/AN4/CN6/RB4

/CN4/RB2

TCK/PMA11/AN12/RB12

/BCLK2/AN14/RB14

TDI/PMA10/AN13/RB13

PMA1/U2RTS

6564636162

/BCLK1/RD15

CN20/U1CTS/RD14

CN21/U1RTS

PMA0/AN15/OCFB/CN12/RB15

SOSCO/T1CK/CN0/RC14

SOSCI/CN1/RC13

OC1/RD0

IC4/PMCS1/RD11

IC3/PMCS2/RD10

IC2/RD9

IC1/RTCC/RD8

SDA2/INT4/RA15

SCL2/INT3/RA14

VSS

OSC2/CLKO/RC15

OSC1/CLKI/RC12

V 47 46

43 42

PMA8/U2TX/CN18/RF5

PMA9/U2RX/CN17/RF4

SCL1/RG2

SDA1/RG3

SCK1/INT0/RF6

SDI1/RF7

SDO1/RF8

U1RX/RF2

U1TX/RF3

807978

2 3 4 5 6 7 8 9 10 11 12

13 14 15 16 17 18 19 20

PGD2/EMUD2/AN7/RB7

PGC2/EMUC2/AN6/OCFA/RB6

7574737172

PIC24FJXXGA008

PIC24FJXXXGA008

232425

REF-/RA9

PMA7/V

PMA6/VREF+/RA10

U2CTS/C1OUT/AN8/RB8

7069686667

2829303132333435363738

VSS

REF/AN10/RB10

C2OUT/AN9/RB9

PMA12/AN11/RB11

PMA13/CV

PIC24FJ128GA FAMILY

Pin Diagrams (Continued))

100-Pin TQFP

RG1

RA6

RG0

RF1

RG15

V PMD5/RE5 PMD6/RE6 PMD7/RE7

T2CK/RC1 T3CK/RC2 T4CK/RC3

PMA5/SCK2/CN8/RG6

PMA4/SDI2/CN9/RG7

PMA3/SDO2/CN10/RG8

PMA2/SS2

C1IN+/AN5/CN7/RB5

C1IN-/AN4/CN6/RB4

C2IN+/AN3/CN5/RB3

C2IN-/AN2/SS1 PGC1/EMUC1/AN1/CN3/RB1 PGD1/EMUD1/AN0/CN2/RB0

T5CK/RC4

MCLR

/CN11/RG9

V TMS/RA0 INT1/RE8 INT2/RE9

/CN4/RB2

PMD2/RE2

RG13

PMD4/RE4

100

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

RG12

PMD3/RE3

969897

2829303132333435363738

RA7

RG14

PMD1/RE1

PMD0/RE0

9294939190898887868584838281807978

PIC24FJXXGA010

PIC24FJXXXGA010

ENVREG

RF0

CN15/RD6

PMRD/CN14/RD5

PMWR/OC5/CN13/RD4

CN19/RD13

IC5/RD12

PMBE/OC4/RD3

OC3/RD2

464748

OC2/RD1

SOSCO/T1CK/CN0/RC14

SOSCI/CN1/RC13

OC1/RD0

IC4/PMCS1/RD11

IC3/PMCS2/RD10

IC2/RD9

IC1/RTCC/RD8

INT4/RA15

INT3/RA14

VSS

OSC2/CLKO/RC15

OSC1/CLKI/RC12

TDO/RA5

TDI/RA4

SDA2/RA3

SCL2/RA2

SCL1/RG2

SDA1/RG3

SCK1/INT0/RF6

SDI1/RF7

SDO1/RF8

U1RX/RF2

U1TX/RF3

VCAP/VDDCORE

CN16/RD7

AVSS

REF-/RA9

PMA7/V

PGD2/EMUD2/AN7/RB7

PGC2/EMUC2/AN6/OCFA/RB6

C1OUT/AN8/RB8

PMA6/VREF+/RA10

C2OUT/AN9/RB9

REF/AN10/RB10

PMA13/CV

VSS

TCK/RA1

U2CTS/RF12

/BCLK2/RF13

PMA12/AN11/RB11

PMA11/AN12/RB12

PMA10/AN13/RB13

U2RTS

VSS

/RD14

/BCLK1/RD15

PMA1/AN14/RB14

CN20/U1CTS

PMA8/U2TX/CN18/RF5

PMA9/U2RX/CN17/RF4

CN21/U1RTS

PMA0/AN15/OCFB/CN12/RB15

PIC24FJ128GA FAMILY

1.0 Device Overview .......................................................................................................................................................................... 7

2.0 CPU............................................................................................................................................................................................ 19

3.0 Memory Organization ................................................................................................................................................................. 25

4.0 Flash Program Memory.............................................................................................................................................................. 45

5.0 Resets ........................................................................................................................................................................................ 51

6.0 Interrupt Controller ..................................................................................................................................................................... 57

7.0 Oscillator Configuration.............................................................................................................................................................. 91

8.0 Power-Saving Features .............................................................................................................................................................. 97

9.0 I/O Ports ..................................................................................................................................................................................... 99

10.0 Timer1 ...................................................................................................................................................................................... 101

11.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 103

12.0 Input Capture............................................................................................................................................................................ 109

13.0 Output Compare....................................................................................................................................................................... 111

14.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 115

15.0 Inter-Integrated Circuit (I

16.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 131

17.0 Parallel Master Port .................................................................................................................................................................. 139

18.0 Real-Time Clock and Calendar ................................................................................................................................................ 149

19.0 Programmable Cyclic Redundancy Check (CRC) Generator .................................................................................................. 161

20.0 10-bit High-Speed A/D Converter............................................................................................................................................. 165

21.0 Comparator Module.................................................................................................................................................................. 173

22.0 Comparator Voltage Reference................................................................................................................................................ 177

23.0 Special Features ...................................................................................................................................................................... 179

24.0 Instruction Set Summary .......................................................................................................................................................... 189

25.0 Development Support............................................................................................................................................................... 197

26.0 Electrical Characteristics .......................................................................................................................................................... 201

27.0 Packaging Information.............................................................................................................................................................. 213

Appendix A: Revision History............................................................................................................................................................. 219

Index ................................................................................................................................................................................................. 221

The Microchip Web Site..................................................................................................................................................................... 225

Customer Change Notification Service .............................................................................................................................................. 225

Customer Support .............................................................................................................................................................................. 225

Reader Response .............................................................................................................................................................................. 226

Product Identification System ............................................................................................................................................................ 227

C™) ................................................................................................................................................. 123

PIC24FJ128GA FAMILY

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

PIC24FJ128GA FAMILY

1.0 DEVICE OVERVIEW

This document contains device specific information for the following devices:

• PIC24FJ64GA006

• PIC24FJ64GA008

• PIC24FJ64GA010

• PIC24FJ96GA006

• PIC24FJ96GA008

• PIC24FJ96GA010

• PIC24FJ128GA006

• PIC24FJ128GA008

• PIC24FJ128GA010

This family introduces a new line of Microchip devices: a 16-bit RISC microcontroller family with a broad peripheral feature set and enhanced computational performance. The PIC24FJ128GA family offers a new migration option for those high-performance applications which may be outgrowing their 8-bit platforms, but don’t require the numerical processing power of a digital signal processor.

1.1 Core Features

1.1.1 16-BIT ARCHITECTURE

Central to all PIC24 devices is the 16-bit modified Harvard architecture, first introduced with Microchip’s dsPIC® digital signal controllers. The PIC24 CPU core offers a wide range of enhancements, such as:

• 16-bit data and 24-bit address paths, with the ability to move information between data and memory spaces

• Linear addressing of up to 8 Mbytes (program space) and 64 Kbytes (data)

• A 16-element working register array with built-in software stack support

• A 17 x 17 hardware multiplier with support for integer math

• Hardware support for 32 by 16-bit division

• An instruction set that supports multiple addressing modes and is optimized for high-level languages such as ‘C’

• Operational performance up to 16 MIPS

1.1.2 POWER-SAVING TECHNOLOGY

All of the devices in the PIC24FJ128GA family incorporate a range of features that can significantly reduce power consumption during operation. Key items include:

• On-the-Fly Clock Switching: The device clock can be changed under software control to the Timer1 source or the internal low-power RC oscillator during operation, allowing the user to incorporate power-saving ideas into their software designs.

• Doze Mode Operation: When timing-sensitive applications, such as serial communications, require the uninterrupted operation of peripherals, the CPU clock speed can be selectively reduced, allowing incremental power savings without missing a beat.

• Instruction-Based Power-Saving Modes: The microcontroller can suspend all operations, or selectively shut down its core while leaving its peripherals active, with a single instruction in software.

1.1.3 OSCILLATOR OPTIONS AND

FEATURES

All of the devices in the PIC24FJ128GA family offer five different oscillator options, allowing users a range of choices in developing application hardware. These include:

• Two Crystal modes, using crystals or ceramic resonators.

• Two External Clock modes, offering the option of a divide-by-2 clock output.

• A Fast Internal Oscillator (FRC) with a nominal 8 MHz output, which can also be divided under software control to provide clock speeds as low as 31 kHz.

• A Phase Lock Loop (PLL) frequency multiplier, available to the external oscillator modes and the FRC oscillator, which allows clock speeds of up to 32 MHz.

• A separate internal RC oscillator (LPRC) with a fixed 31 kHz output, which provides a low-power option for timing-insensitive applications.

The internal oscillator block also provides a stable reference source for the Fail-Safe Clock Monitor. This option constantly monitors the main clock source against a reference signal provided by the internal oscillator and enables the controller to switch to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown.

PIC24FJ128GA FAMILY

1.1.4 EASY MIGRATION

Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve.

The consistent pinout scheme used throughout the entire family also aids in migrating to the next larger device. This is true when moving between devices with the same pin count, or even jumping from 64-pin to 80-pin to 100-pin devices.

The PIC24 family is pin-compatible with devices in the dsPIC33 family, and shares some compatibility with the pinout schema for PIC18 and dsPIC30. This extends the ability of applications to grow from the relatively simple to the powerful and complex, yet still select a Microchip device.

1.2 Other Special Features

• Communications: The PIC24FJ128GA family incorporates a range of serial communication peripherals to handle a range of application requirements. All devices are equipped with two independent UARTs with built-in IrDA encoder/decoders. There are also two independent SPI modules, and two independent I modules that support both Master and Slave modes of operation.

• Parallel Master/Enhanced Parallel Slave Port: One of the general purpose I/O ports can be reconfigured for enhanced parallel data communications. In this mode, the port can be configured for both master and slave operations, and supports 8-bit and 16-bit data transfers with up to 16 external address lines in Master modes.

• Real-Time Clock/Calendar: This module implements a full-featured clock and calendar with alarm functions in hardware, freeing up timer resources and program memory space for use of the core application.

• 10-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period, as well as faster sampling speeds.

1.3 Details on Individual Family Members

Devices in the PIC24FJ128GA family are available in 64-pin, 80-pin and 100-pin packages. The general block diagram for all devices is shown in Figure 1-1.

The devices are differentiated from each other in two ways:

1. Flash program memory (64 Kbytes for

PIC24FJ64GA devices, 96 Kbytes for PIC24FJ96GA devices and 128 Kbytes for PIC24FJ128GA devices).

2. Available I/O pins and ports (53 pins on 6 ports

for 64-pin devices, 69 pins on 7 ports for 80-pin devices and 84 pins on 7 ports for 100-pin devices).

All other features for devices in this family are identical. These are summarized in Table 1-1.

A list of the pin features available on the PIC24FJ128GA family devices, sorted by function, is shown in Table 1-2. Note that this table shows the pin location of individual peripheral features and not how they are multiplexed on the same pin. This information is provided in the pinout diagrams in the beginning of the data sheet. Multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first.

PIC24FJ128GA FAMILY

TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ128GA FAMILY

Features

PIC24FJ64GA006

Operating Frequency DC – 32 MHz

Program Memory (Bytes) 64K 96K 128K 64K 96K 128K 64K 96K 128K

Program Memory (Instructions) 22,016 32,768 44,032 22,016 32,768 44,032 22,016 32,768 44,032

Data Memory (Bytes) 8192

Interrupt Sources (Soft Vectors/NMI Traps)

I/O Ports Ports B, C, D, E, F, G Ports A, B, C, D, E, F, G Ports A, B, C, D, E, F, G

Total I/O Pins 53 69 84

Timers:

Total number (16-bit) 5

32-bit (from paired 16-bit timers) 2

Input Capture Channels 5

Output Compare/PWM Channels

Input Change Notification Interrupt

Serial Communications:

Enhanced UART 2

SPI (3-wire/4-wire) 2

C™ 2

Parallel Communications (PMP/PSP)

JTAG Boundary Scan Yes

10-bit Analog-to-Digital Module (input channels)

Analog Comparators 2

Resets (and Delays) POR, BOR, RESET Instruction, MCLR

Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations

Packages 64-pin TQFP 80-pin TQFP 100-pin TQFP

PIC24FJ96GA006

19 22

PIC24FJ128GA006

Repeat Hardware Traps, (PWRT, OST, PLL Lock)

PIC24FJ64GA008

PIC24FJ96GA008

(39/4)

Yes

PIC24FJ128GA008

, WDT; Illegal Opcode,

PIC24FJ64GA010

PIC24FJ96GA010

PIC24FJ128GA010

PIC24FJ128GA FAMILY

FIGURE 1-1: PIC24FJ128GA FAMILY GENERAL BLOCK DIAGRAM

PSV & Table Data Access

Control Block

Address Latch

Program Memory

Data Latch

Interrupt

Controller

Instruction Decode &

Control

PCH PCL

PCU

Program Counter

Stac k

Control

Logic

Address Bus

Repeat Control

Logic

Data Bus

Inst Latch

Inst Register

Divide

Support

Data Latch

Data RAM

Address

Latch

Read AGU Write AGU

EA MUX

Literal Data

16-bit ALU

PIC24FJ128GA FAMILY

TABLE 1-2: PIC24FJ128GA FAMILY PINOUT DESCRIPTIONS

Function

AN0 16 20 25 I ANA A/D Analog Inputs.

AN1151924IANA

AN2141823IANA

AN3131722IANA

AN4121621IANA

AN5 11 15 20 I ANA

AN6172126IANA

AN7182227IANA

AN8212732IANA

AN9222833IANA

AN10 23 29 34 I ANA

AN11 24 30 35 I ANA

AN12 27 33 41 I ANA

AN13 28 34 42 I ANA

AN14 29 35 43 I ANA

AN15 30 36 44 I ANA

DD 19 25 30 P — Positive Supply for Analog Modules.

SS 20 26 31 P — Ground Reference for Analog Modules.

BCLK1353848O—UART1 IrDA

BCLK2293539O—UART2 IrDA

C1IN- 12 16 21 I ANA Comparator 1 Negative Input.

C1IN+ 11 15 20 I ANA Comparator 1 Positive Input.

C1OUT 21 27 32 O — Comparator 1 Output.

C2IN- 14 18 23 I ANA Comparator 2 Negative Input.

C2IN+ 13 17 22 I ANA Comparator 2 Positive Input.

C2OUT 22 28 33 O — Comparator 2 Output.

CLKI 39 49 63 I ANA Main Clock Input Connection.

CLKO 40 50 64 O — System Clock Output.

CN0 48 60 74 I ST Interrupt-on-Change Inputs.

CN1475973IST

CN2162025IST

CN3151924IST

CN4141823IST

CN5131722IST

CN6121621IST

CN7 11 15 20 I ST

CN8 4 6 10 I ST

CN9 5 7 11 I ST

CN10 6 8 12 I ST

CN11 8 10 14 I ST

CN12303644IST

CN13526681IST

CN14536782IST

CN15546883IST

CN16556984IST

CN17313949IST

Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer

64-pin 80-pin 100-pin

ANA = Analog level input/output I

Pin Number

I/O

Input

Buffer

Baud Clock.

C™ = I2C/SMBus input buffer

Description

PIC24FJ128GA FAMILY

TABLE 1-2: PIC24FJ128GA FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Function

CN18 32 40 50 I ST Interrupt-on-Change Inputs.

CN19 — 65 80 I ST

CN20 — 37 47 I ST

CN21 — 38 48 I ST

REF 23 29 34 O ANA Comparator Voltage Reference Output.

EMUC1 15 19 24 I/O ST In-Circuit Emulator Clock Input/Output.

EMUD1 16 20 25 I/O ST In-Circuit Emulator Data Input/Output.

EMUC2 17 21 26 I/O ST In-Circuit Emulator Clock Input/Output.

EMUD2 18 22 27 I/O ST In-Circuit Emulator Data Input/Output.

ENVREG 57 71 86 I ST Enable for On-Chip Voltage Regulator.

IC1 42 54 68 I ST Input Capture Inputs.

IC2435569IST

IC3445670IST

IC4455771IST

IC5526479IST

INT0 35 45 55 I ST External Interrupt Inputs.

INT1 42 13 18 I ST

INT2 43 14 19 I ST

INT3 44 52 66 I ST

INT4 45 53 67 I ST

MCLR

OC1 46 58 72 O — Output Compare/PWM Outputs.

OC2496176O—

OC3506277O—

OC4516378O—

OC5526681O—

OCFA 17 21 26 I ST Output Compare Fault A Input.

OCFB 30 36 44 I ST Output Compare Fault B Input.

OSC1 39 49 63 I ANA Main Oscillator Input Connection.

OSC2 40 50 64 O ANA Main Oscillator Output Connection.

PGC1 15 19 24 I/O ST In-Circuit Debugger and ICSP™ Programming Clock

PGD1 16 20 25 I/O ST In-Circuit Debugger and ICSP Programming Data.

PGC2 17 21 26 I/O ST In-Circuit Debugger and ICSP™ Programming Clock.

PGD2 18 22 27 I/O ST In-Circuit Debugger and ICSP Programming Data.

Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer

64-pin 80-pin 100-pin

ANA = Analog level input/output I

Pin Number

I/O

7 9 13 I ST Master Clear (Device Reset) Input. This line is brought

Input

Buffer

low to cause a Reset.

C™ = I2C/SMBus input buffer

Description

PIC24FJ128GA FAMILY

TABLE 1-2: PIC24FJ128GA FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Function

64-pin 80-pin 100-pin

PMA0 30 36 44 I/O ST Parallel Master Port Address Bit 0 Input (Buffered Slave

PMA1 29 35 43 I/O ST

PMA2 8 10 14 O — Parallel Master Port Address (Demultiplexed Master

PMA3 6 8 12 O —

PMA4 5 7 11 O —

PMA5 4 6 10 O —

PMA6 16 24 29 O —

PMA7 22 23 28 O —

PMA8 32 40 50 O —

PMA9 31 39 49 O —

PMA10 28 34 42 O —

PMA11 27 33 41 O —

PMA12 24 30 35 O —

PMA13 23 29 34 O —

PMBE 51 63 78 O — Parallel Master Port Byte Enable Strobe.

PMCS1 45 57 71 O — Parallel Master Port Chip Select 1 Strobe/Address bit 14.

PMCS2 44 56 70 O — Parallel Master Port Chip Select 2 Strobe/Address bit 15.

PMD0 60 76 93 I/O ST Parallel Master Port Data (Demultiplexed Master mode)

PMD1 61 77 94 I/O ST

PMD2 62 78 98 I/O ST

PMD3 63 79 99 I/O ST

PMD4 64 80 100 I/O ST

PMD5 1 1 3 I/O ST

PMD6 2 2 4 I/O ST

PMD7 3 3 5 I/O ST

PMRD 53 67 82 O — Parallel Master Port Read Strobe.

PMWR 52 66 81 O — Parallel Master Port Write Strobe.

Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer

ANA = Analog level input/output I

Pin Number

I/O

Input

Buffer

modes) and Output (Master modes).

Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and Output (Master modes).

modes).

or Address/Data (Multiplexed Master modes).

C™ = I2C/SMBus input buffer

Description

PIC24FJ128GA FAMILY

TABLE 1-2: PIC24FJ128GA FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Function

64-pin 80-pin 100-pin

RA0 — — 17 I/O ST PORTA Digital I/O.

RA1 — — 38 I/O ST

RA2 — — 58 I/O ST

RA3 — — 59 I/O ST

RA4 — — 60 I/O ST

RA5 — — 61 I/O ST

RA6 — — 91 I/O ST

RA7 — — 92 I/O ST

RA9 — 23 28 I/O ST

RA10 — 24 29 I/O ST

RA14 — 52 66 I/O ST

RA15 — 53 67 I/O ST

RB0 16 20 25 I/O ST PORTB Digital I/O.

RB1151924I/OST

RB2141823I/OST

RB3131722I/OST

RB4121621I/OST

RB5 11 15 20 I/O ST

RB6172126I/OST

RB7182227I/OST

RB8212732I/OST

RB9222833I/OST

RB10 23 29 34 I/O ST

RB11 24 30 35 I/O ST

RB12 27 33 41 I/O ST

RB13 28 34 42 I/O ST

RB14 29 35 43 I/O ST

RB15 30 36 44 I/O ST

RC1 — 4 6 I/O ST PORTC Digital I/O.

RC2 — — 7 I/O ST

RC3 — 5 8 I/O ST

RC4 — — 9 I/O ST

RC12394963I/OST

RC13475973I/OST

RC14486074I/OST

RC15405064I/OST

Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer

ANA = Analog level input/output I

Pin Number

I/O

Input

Buffer

C™ = I2C/SMBus input buffer

Description

PIC24FJ128GA FAMILY

TABLE 1-2: PIC24FJ128GA FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Function

64-pin 80-pin 100-pin

RD0 46 58 72 I/O ST PORTD Digital I/O.

RD1496176I/OST

RD2506277I/OST

RD3516378I/OST

RD4526681I/OST

RD5536782I/OST

RD6546883I/OST

RD7556984I/OST

RD8425468I/OST

RD9435569I/OST

RD10445670I/OST

RD11 45 57 71 I/O ST

RD12 — 64 79 I/O ST

RD13 — 65 80 I/O ST

RD14 — 37 47 I/O ST

RD15 — 38 48 I/O ST

RE0 60 76 93 I/O ST PORTE Digital I/O.

RE1617794I/OST

RE2627898I/OST

RE3637999I/OST

RE4 64 80 100 I/O ST

RE5 1 1 3 I/O ST

RE6 2 2 4 I/O ST

RE7 3 3 5 I/O ST

RE8 — 13 18 I/O ST

RE9 — 14 19 I/O ST

RF0 58 72 87 I/O ST PORTF Digital I/O.

RF1597388I/OST

RF2344252I/OST

RF3334151I/OST

RF4313949I/OST

RF5324050I/OST

RF6354555I/OST

RF7 — 44 54 I/O ST

RF8 — 43 53 I/O ST

RF12 — — 40 I/O ST

RF13 — — 39 I/O ST

Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer

ANA = Analog level input/output I

Pin Number

I/O

Input

Buffer

C™ = I2C/SMBus input buffer

Description

PIC24FJ128GA FAMILY

TABLE 1-2: PIC24FJ128GA FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Function

64-pin 80-pin 100-pin

RG0 — 75 90 I/O ST PORTG Digital I/O.

RG1 — 74 89 I/O ST

RG2374757I/OST

RG3364656I/OST

RG6 4 6 10 I/O ST

RG7 5 7 11 I/O ST

RG8 6 8 12 I/O ST

RG9 8 10 14 I/O ST

RG12 — — 96 I/O ST

RG13 — — 97 I/O ST

RG14 — — 95 I/O ST

RG15 — — 1 I/O ST

RTCC 42 54 68 O — Real-Time Clock Alarm Output.

SCK1 35 45 55 O — SPI1 Serial Clock Output.

SCK2 4 6 10 I/O ST SPI2 Serial Clock Output.

SCL1 37 47 57 I/O I

SCL2 32 52 58 I/O I

SDA1 36 46 56 I/O I

SDA2 31 53 59 I/O I

SDI1 34 44 54 I ST SPI1 Serial Data Input.

SDI2 5 7 11 I ST SPI2 Serial Data Input.

SDO1 33 43 53 O — SPI1 Serial Data Output.

SDO2 6 8 12 O — SPI2 Serial Data Output.

SOSCI 47 59 73 I ANA Secondary Oscillator/Timer1 Clock Input.

SOSCO 48 60 74 O ANA Secondary Oscillator/Timer1 Clock Output.

SS1

SS2

T1CK 48 60 74 I ST Timer1 Clock.

T2CK — 4 6 I ST Timer2 External Clock Input.

T3CK — — 7 I ST Timer3 External Clock Input.

T4CK — 5 8 I ST Timer4 External Clock Input.

T5CK — — 9 I ST Timer5 External Clock Input.

TCK 27 33 38 I ST JTAG Test Clock/Programming Clock Input.

TDI 28 34 60 I ST JTAG Test Data/Programming Data Input.

TDO 24 14 61 O — JTAG Test Data Output.

TMS 23 13 17 I ST JTAG Test Mode Select Input.

Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer

ANA = Analog level input/output I

Pin Number

I/O

14 18 23 I/O ST Slave Select Input/Frame Select Output (SPI1).

8 10 14 I/O ST Slave Select Input/Frame Select Output (SPI2).

Input

Buffer

C I2C1 Synchronous Serial Clock Input/Output.

C I2C2 Synchronous Serial Clock Input/Output.

C I2C1 Data Input/Output.

C I2C2 Data Input/Output.

C™ = I2C/SMBus input buffer

Description

PIC24FJ128GA FAMILY

TABLE 1-2: PIC24FJ128GA FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Function

U1CTS 43 37 47 I ST UART1 Clear to Send Input.

U1RTS

U1RX 34 42 52 I ST UART1 Receive.

U1TX 33 41 51 O DIG UART1 Transmit Output.

U2CTS

U2RTS

U2RX 31 39 49 I ST UART 2 Receive Input.

U2TX 32 40 50 O — UART2 Transmit Output.

DD 10, 26, 38 12, 32, 48 2, 16, 37,

DDCAP 56 70 85

DDCORE 56 70 85

REF- 15 23 28 I ANA A/D and Comparator Reference Voltage (Low) Input.

REF+ 16 24 29 I ANA A/D and Comparator Reference Voltage (High) Input.

SS 9, 25, 41 11, 31, 51 15, 36, 45,

Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer

64-pin 80-pin 100-pin

ANA = Analog level input/output I

Pin Number

I/O

35 38 48 O — UART1 Request to Send Output.

21 27 40 I ST UART2 Clear to Send Input.

29 35 39 O — UART2 Request to Send Output.

46, 62

65, 75

Input

Buffer

P — Positive Supply for Peripheral Digital Logic and I/O pins.

P—

P — Ground Reference for Logic and I/O pins.

External Filter Capacitor Connection (regulator enabled).

Positive Supply for Microcontroller Core Logic (regulator disabled).

C™ = I2C/SMBus input buffer

Description

PIC24FJ128GA FAMILY

NOTES:

PIC24FJ128GA FAMILY

2.0 CPU

The PIC24 CPU has a 16-bit (data) modified Harvard architecture with an enhanced instruction set, and a 23-bit instruction word with a variable length opcode field. The Program Counter (PC) is 24 bits wide and addresses up to 4M instructions of user program memory space. A single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a single cycle, with the exception of instructions that change the program flow, the double-word move (MOV.D) instruction and the table instructions. Overhead-free program loop constructs are supported using the REPEAT instructions, which are interruptible at any point.

PIC24 devices have sixteen 16-bit working registers in the programmer’s model. Each of the working registers can act as a data, address or address offset register. The 16th working register (W15) operates as a software Stack Pointer for interrupts and calls.

The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K word boundary defined by the 8-bit Program Space Visibility Page (PSVPAG) register. The program to data space mapping feature lets any instruction access program space as if it were data space.

The Instruction Set Architecture (ISA) has been significantly enhanced beyond that of the PIC18, but maintains an acceptable level of backward compatibility. All PIC18 instructions and addressing modes are supported either directly or through simple macros. Many of the ISA enhancements have been driven by compiler efficiency needs.

The core supports Inherent (no operand), Relative, Literal, Memory Direct and three groups of addressing modes. All modes support Register Direct and various Register Indirect modes. Each group offers up to 7 addressing modes. Instructions are associated with predefined addressing modes depending upon their functional requirements.

For most instructions, the core is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three-parameter instructions can be supported, allowing trinary operations (that is, A + B = C) to be executed in a single cycle.

A high-speed 17-bit by 17-bit multiplier has been included to significantly enhance the core arithmetic capability and throughput. The multiplier supports signed, unsigned and mixed mode 16-bit by 16-bit or 8-bit by 8-bit integer multiplication. All multiply instructions execute in a single cycle.

The 16-bit ALU has been enhanced with integer divide assist hardware that supports an iterative non-restoring divide algorithm. It operates in conjunction with the REPEAT instruction looping mechanism, and a selection of iterative divide instructions, to support 32-bit (or 16-bit) divided by 16-bit integer signed and unsigned division. All divide operations require 19 cycles to complete but are interruptible at any cycle boundary.

The PIC24 has a vectored exception scheme with up to 8 sources of non-maskable traps and up to 118 interrupt sources. Each interrupt source can be assigned to one of seven priority levels.

A block diagram of the CPU is shown in Figure 2-1.

2.1 Programmer’s Model

The programmer’s model for the PIC24 is shown in Figure 2-2. All registers in the programmer’s model are memory mapped and can be manipulated directly by instructions. A description of each register is provided in Table 2-1. All registers associated with the programmer’s model are memory mapped.

PIC24FJ128GA FAMILY

FIGURE 2-1: PIC24 CPU CORE BLOCK DIAGRAM

PSV & Table Data Access Control Block

Interrupt

Controller

PCU Program Counter

Stac k

Control

Logic

PCH PCL

Loop

Control

Logic

Data Bus

Data Latch

Data RAM

Address

Latch

Address Latch

Program Memory

Data Latch

Address Bus

Instruction

Decode &

Control

Control Signals

to Various Blocks

ROM Latch

Instruction Reg

Hardware

Multiplier

Divide

Support

RAGU WAGU

EA MUX

Literal Data

16 x 16

W Register Array

16-Bit ALU

To Peripheral Modules

PIC24FJ128GA FAMILY

TABLE 2-1: CPU CORE REGISTERS

W0 through W15 Working register array

PC 23-bit Program Counter

SR ALU STATUS register

SPLIM Stack Pointer Limit Value register

TBLPAG Table Memory Page Address register

PSVPAG Program Space Visibility Page Address register

RCOUNT Repeat Loop Counter register

CORCON CPU Control Register

FIGURE 2-2: PROGRAMMER’S MODEL

015

Divider Working Registers

Multiplier Registers

W0 (WREG)

W10

W11

W12

W13

W14

W15

Frame Pointer

Stack Pointer

Working/Address Registers

Stack Pointer Limit

——

Program Counter

Data Table Page Address

Program Space Visibility Page Address

REPEAT Loop Counter

STATUS Register (SR)

Core Control Register (CORCON)

SPLIM

TBLPAG

PSVPAG

RCOUNT

IPL

210

SRL

NOVZ C

IPL3 PSV

SRH

———————

15 0

————————————

Registers or bits shadowed for PUSH.S and POP.S instructions.

PIC24FJ128GA FAMILY

2.2 CPU Control Registers

REGISTER 2-1: SR: CPU STATUS REGISTER

Upper Byte:

U-0 U-0 U-0 U-0 U-0 U-0 U -0 R/W-0

— — — — — — —DC

bit 15 bit 8

Lower Byte:

(1)

R/W-0

(2)

IPL2

bit 7 bit 0

bit 15-9 Unimplemented: Read as ‘0’

bit 8 DC: ALU Half Carry/Borrow bit

1 = A carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized data)

of the result occurred

0 = No carry-out from the 4th or 8th low-order bit of the result has occurred

bit 7-5 IPL2:IPL0: CPU Interrupt Priority Level Status bits

111 = CPU interrupt priority level is 7 (15). User interrupts disabled. 110 = CPU interrupt priority level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU interrupt priority level is 4 (12) 011 = CPU interrupt priority level is 3 (11) 010 = CPU interrupt priority level is 2 (10) 001 = CPU interrupt priority level is 1 (9) 000 = CPU interrupt priority level is 0 (8)

Note 1: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.

2: The IPL bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU interrupt priority

level. The value in parentheses indicates the IPL when IPL3 = 1.

bit 4 RA: REPEAT Loop Active bit

1 = REPEAT loop in progress 0 = REPEAT loop not in progress

bit 3 N: ALU Negative bit

1 = Result was negative 0 = Result was non-negative (zero or positive)

bit 2 OV: ALU Overflow bit

1 = Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation 0 = No overflow has occurred

bit 1 Z: ALU Zero bit

1 = An operation which effects the Z bit has set it at some time in the past 0 = The most recent operation which effects the Z bit has cleared it (i.e., a non-zero result)

bit 0 C: ALU Carry/Borrow

1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred

R/W-0

IPL1

bit

(2)

(1)

R/W-0

IPL0

(2)

(1)

R-0 R/W-0 R/W-0 R/W-0 R/W-0

RA N OV Z C

(2)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC24FJ128GA FAMILY

REGISTER 2-2: CORCON: CORE CONTROL REGISTER

Upper Byte:

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

Lower Byte:

U-0 U-0 U-0 U-0 R/C-0 R/W-0 U-0 U-0

— — — — IPL3 PSV — —

bit 7 bit 0

bit 15-4 Unimplemented: Read as ‘0’

bit 3 IPL3: CPU Interrupt Priority Level Status bit

1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less

Note: User interrupts are disabled when IPL3 = 1.

bit 2 PSV: Program Space Visibility in Data Space Enable bit

1 = Program space visible in data space 0 = Program space not visible in data space

bit 1-0 Unimplemented: Read as ‘0’

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

2.3 Arithmetic Logic Unit (ALU)

The PIC24 ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU may affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register. The C and DC Status bits operate as Borrow for subtraction operations.

The ALU can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location.

and Digit Borrow bits, respectively,

The PIC24 CPU incorporates hardware support for both multiplication and division. This includes a dedicated hardware multiplier and support hardware for 16-bit divisor division.

2.3.1 MULTIPLIER

The ALU contains a high-speed 17-bit x 17-bit multiplier. It supports unsigned, signed or mixed sign operation in several multiplication modes:

1. 16-bit x 16-bit signed

2. 16-bit x 16-bit unsigned

3. 16-bit signed x 5-bit (literal) unsigned

4. 16-bit unsigned x 16-bit unsigned

5. 16-bit unsigned x 5-bit (literal) unsigned

6. 16-bit unsigned x 16-bit signed

7. 8-bit unsigned x 8-bit unsigned

PIC24FJ128GA FAMILY

2.3.2 DIVIDER

The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operation with the following data sizes:

1. 32-bit signed/16-bit signed divide

2. 32-bit unsigned/16-bit unsigned divide

3. 16-bit signed/16-bit signed divide

4. 16-bit unsigned/16-bit unsigned divide

The quotient for all divide instructions ends up in W0 and the remainder in W1. 16-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn) and any W register (aligned) pair

(m+1):Wm) for the 32-bit dividend. The divide algo-

(W rithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute.

2.3.3 MULTI-BIT SHIFT SUPPORT

The PIC24 ALU supports both single-bit and single-cycle, multi-bit arithmetic and logic shifts. Multi-bit shifts are implemented using a shifter block, capable of performing up to a 15-bit arithmetic right shift, or up to a 15-bit left shift, in a single cycle. All multi-bit shift instructions only support register direct addressing for both the operand source and result destination.

A full summary of instructions that use the shift operation is provided below in Table 2-2.

TABLE 2-2: INSTRUCTIONS THAT USE THE SINGLE AND MULTI-BIT SHIFT OPERATION

Instruction Description

ASR Arithmetic shift right source register by one bit.

ASRF Arithmetic shift right the content of the register by one bit.

ASRW Arithmetic shift right source register by up to 15 bits, value held in the W register referenced

within instruction.

ASRK Arithmetic shift right source register up to 15 bits. Shift value is literal.

SL Shift left source register by one bit.

SLF Shift left the content of the file register by one bit.

SLW Shift left source register by up to 15 bits, value held in the W register referenced instruction.

SLK Shift left source register up to 15 bits. Shift value is literal.

LSR Logical shift right source register by one bit.

LSRF Logical shift right the content of the register by one bit.

LSRW Logical shift right source register by up to 15 bits, value held in the W register referenced

within instruction.

LSRK Logical shift right source register up to 15 bits. Shift value is literal.

PIC24FJ128GA FAMILY

3.0 MEMORY ORGANIZATION

As Harvard architecture devices, PIC24 microcontrollers feature separate program and data memory spaces and busses. This architecture also allows the direct access of program memory from the data space during code execution.

3.1 Program Address Space

The program address memory space of PIC24FJ128GA family devices is 4M instructions. The space is addressable by a 24-bit value derived from

either the 23-bit Program Counter (PC) during program execution, or from table operation or data space remapping, as described in Section 3.3 “Interfacing Program and Data Memory Spaces”.

User access to the program memory space is restricted to the lower half of the address range (000000h to 7FFFFFh). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG<7> to permit access to the Configuration bits and Device ID sections of the configuration memory space.

PIC24FJ128GA FAMILY

3.1.1 PROGRAM MEMORY ORGANIZATION

The program memory space is organized in word addressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. The lower word always has an even address, while the upper word has an odd address (Figure 3-2).

Program memory addresses are always word-aligned on the lower word, and addresses are incremented or decremented by two during code execution. This arrangement also provides compatibility with data memory space addressing and makes it possible to access data in the program memory space.

3.1.2 HARD MEMORY VECTORS

All PIC24 devices reserve the addresses between 00000h and 000200h for hard coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user at 000000h, with the actual address for the start of code at 000002h.

PIC24 devices also have two interrupt vector tables, located from 000004h to 0000FFh and 000100h to 0001FFh. These vector tables allow each of the many device interrupt sources to be handled by separate ISRs. A more detailed discussion of the interrupt vector tables is provided in Section 6.1 “Interrupt Vector Tabl e”.

3.1.3 FLASH CONFIGURATION WORDS

In PIC24FJ128GA family devices, the top two words of on-chip program memory are reserved for configuration information. On device Reset, the configuration information is copied into the appropriate Configuration registers. The addresses of the Flash Configuration Word for devices in the PIC24FJ128GA family are shown in Table 3-1. Their location in the memory map is shown with the other memory vectors in Figure 3-1.

The Configuration Words in program memory are a compact format. The actual Configuration bits are mapped in several different registers in the configuration memory space. Their order in the Flash Configuration Words do not reflect a corresponding arrangement in the configuration space. Additional details on the device Configuration Words are provided in

Section 23.1 “Configuration Bits”.

TABLE 3-1: FLASH CONFIGURATION

WORDS FOR PIC24FJ128GA FAMILY DEVICES

Program

Device

PIC24FJ64GA 22 00ABFCh:

PIC24FJ96GA 32 00FFFCh:

PIC24FJ128GA 44 0157FCh:

Memory

(K words)

Configuration

Word

Addresses

00ABFEh

00FFFEh

0157FEh

FIGURE 3-2: PROGRAM MEMORY ORGANIZATION

msw

Address (lsw Address)

000001h 000003h 000005h 000007h

most significant word

00000000

Program Memory

‘Phantom’ Byte

(read as ‘0’)

least significant word

Instruction Width

PC Address

0816

000000h 000002h 000004h 000006h

PIC24FJ128GA FAMILY

3.2 Data Address Space

The PIC24 core has a separate 16-bit wide data memory space, addressable as a single linear range. The data space is accessed using two Address Generation Units (AGUs), one each for read and write operations. The data space memory map is shown in Figure 3-3.

All Effective Addresses (EAs) in the data memory space are 16 bits wide, and point to bytes within the data space. This gives a data space address range of 64 Kbytes, or 32K words. The lower half of the data memory space (that is, when EA<15> = 0) is used for implemented memory addresses, while the upper half (EA<15> = 1) is reserved for the Program Space Visibility area (see Section 3.3.3 “Reading Data from Program Memory Using Program Space Visibility”).

PIC24FJ128GA family devices implement a total of 8 Kbytes of data memory. Should an EA point to a location outside of this area, an all zero word or byte will be returned.

3.2.1 DATA SPACE WIDTH

The data memory space is organized in byte addressable, 16-bit wide blocks. Data is aligned in data memory and registers as 16-bit words, but all data space EAs resolve to bytes. The Least Significant Bytes of each word have even addresses, while the Most Significant Bytes have odd addresses.

FIGURE 3-3: DATA SPACE MEMORY MAP FOR PIC24FJ128GA FAMILY DEVICES

LSB

Address

0000h

07FEh 0800h

1FFEh 2000h

07FEh 0800h

SFR

Space

Near

Data Space

Implemented

Data RAM

MSB

Address

0001h

07FFh

0801h

1FFFh

2001h

27FFh

2801h

LSBMSB

SFR Space

Data RAM

Unimplemented

Read as ‘0’

7FFFh

8001h

Program Space

Visibility Area

FFFFh

Note: Data memory areas are not shown to scale.

7FFFh 8000h

FFFEh

PIC24FJ128GA FAMILY

3.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT

To maintain backward compatibility with PICmicro devices and improve data space memory usage efficiency, the PIC24 instruction set supports both word and byte operations. As a consequence of byte accessibility, all effective address calculations are internally scaled to step through word-aligned memory. For example, the core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] will result in a value of Ws + 1 for byte operations and Ws + 2 for word operations.

Data byte reads will read the complete word which contains the byte, using the LSb of any EA to determine which byte to select. The selected byte is placed onto the LSB of the data path. That is, data memory and registers are organized as two parallel byte-wide entities with shared (word) address decode but separate write lines. Data byte writes only write to the corresponding side of the array or register which matches the byte address.

All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error trap will be generated. If the error occurred on a read, the instruction underway is completed; if it occurred on a write, the instruction will be executed but the write will not occur. In either case, a trap is then executed, allowing the system and/or user to examine the machine state prior to execution of the address Fault.

All byte loads into any W register are loaded into the Least Significant Byte. The Most Significant Byte is not modified.

A sign-extend instruction (SE) is provided to allow users to translate 8-bit signed data to 16-bit signed

values. Alternatively, for 16-bit unsigned data, users can clear the MSB of any W register by executing a zero-extend (ZE) instruction on the appropriate address.

Although most instructions are capable of operating on word or byte data sizes, it should be noted that some instructions operate only on words.

3.2.3 NEAR DATA SPACE

The 8-Kbyte area between 0000h and 1FFFh is referred to as the near data space. Locations in this space are directly addressable via a 13-bit absolute address field within all memory direct instructions. The remainder of the data space is addressable indirectly. Additionally, the whole data space is addressable using MOV instructions, which support Memory Direct Addressing with a 16-bit address field.

3.2.4 SFR SPACE

The first 2 Kbytes of the near data space, from 0000h to 07FFh, are primarily occupied with Special Function Registers (SFRs). These are used by the PIC24 core and peripheral modules for controlling the operation of the device.

SFRs are distributed among the modules that they control, and are generally grouped together by module. Much of the SFR space contains unused addresses; these are read as ‘0’. A diagram of the SFR space, showing where SFRs are actually implemented, is shown in Table 3-2. Each implemented area indicates a 32-byte region where at least one address is implemented as an SFR. A complete listing of implemented SFRs, including their addresses, is shown in Tables 3-3 through 3-30.

TABLE 3-2: IMPLEMENTED REGIONS OF SFR DATA SPACE

SFR Space Address

xx00 xx20 xx40 xx60 xx80 xxA0 xxC0 xxE0

000h Core ICN Interrupts

100h Timers Capture

200h I

300h A/D — — — — I/O

400h

500h

600h PMP RTC/Comp CRC — — — I/O

700h

Legend: — = No implemented SFRs in this block

C™ UART SPI — — I/O

— — — — — — — —

— — System NVM/PMD — — — —

— Compare — — —

—

PIC24FJ128GA FAMILY

All

0000

0800

xxxx

0000

xxxx

0000

Resets

xxxx

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

WREG0 0000 Working Register 0

WREG1 0002 Working Register 1

WREG2 0004 Working Register 2

WREG3 0006 Working Register 3

WREG4 0008 Working Register 4

WREG5 000A Working Register 5

WREG6 000C Working Register 6

WREG7 000E Working Register 7

WREG8 0010 Working Register 8

WREG9 0012 Working Register 9

WREG10 0014 Working Register 10

WREG11 0016 Working Register 11

WREG12 0018 Working Register 12

WREG13 001A Working Register 13

WREG14 001C Working Register 14

WREG15 001E Working Register 15

SPLIM 0020 Stack Pointer Limit

PCL 002E Program Counter, Low Word

PCH 0030 — — — — — — — — Program Counter, High Byte

TBLPAG 0032 — — — — — — — — Table Page Address Pointer

PSVPAG 0034 — — — — — — — — Program Memory Visibility Page Address Pointer

RCOUNT 0036 Repeat Loop Counter

SR 0042 — — — — — — — DC IPL2 IPL1 IPL0 RA N OV Z C

CORCON 0044 — — — — — — — — — — — —IPL3PSV— —

DISICNT 0052 — — Disable Interrupts Counter

TABLE 3-3: CPU CORE REGISTERS MAP

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24FJ128GA FAMILY

All

0000

4444

4440

4444

0044

Resets

4444

0004

4440

4444

0044

4440

0040

0440

0400

4440

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTCON1 0080 NSTDIS — — — — — — — — — — MATHERR ADDRERR STKERR OSCFAIL —

INTCON2 0082 ALTIVT DISI — — — — — — — — — INT4EP INT3EP INT2EP INT1EP INT0EP

IFS0 0084 — — AD1IF U1TXIF U1RXIF SPI1IF SPF1IF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF

IFS1 0086 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF — — — — INT1IF CNIF CMIF MI2C1IF SI2C1IF

IFS2 0088 — —PMPIF— — —OC5IF— IC5IF IC4IF IC3IF — — — SPI2IF SPF2IF

IFS3 008A —RTCIF — — — — — — — INT4IF INT3IF — —MI2C2IFSI2C2IF—

IFS4 008C — — — — — — — — — — — — CRCIF U2ERIF U1ERIF —

IEC0 0094 — — AD1IE U1TXIE U1RXIE SPI1IE SPF1IE T3IE T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE

IEC1 0096 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE — — — — INT1IE CNIE CMIE MI2C1IE SI2C1IE

IEC2 0098 — —PMPIE— — —OC5IE— IC5IE IC4IE IC3IE — — —SPI2IESPF2IE

IEC3 009A —RTCIE — — — — — — — INT4IE INT3IE — — MI2C2IE SI2C2IE —

IEC4 009C — — — — — — — — — — — — CRCIE U2ERIE U1ERIE —

IPC0 00A4 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0

IPC1 00A6 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 — IC2IP2 IC2IP1 IC2IP0 — — — —

IPC2 00A8 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPF1IP2 SPF1IP1 SPF1IP0 — T3IP2 T3IP1 T3IP0

IPC3 00AA — — — — — — — — — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0

IPC4 00AC — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMI P0 — MI2C1P2 MI2C1P1 MI2C1P0 — SI2C1P2 SI2C1P1 SI2C1P0

IPC5 00AE — — — — — — — — — — — — — INT1IP2 INT1IP1 INT1IP0

IPC6 00B0 — T4IP2 T4IP1 T4IP0 — OC4IP2 OC4IP1 OC4IP0 — OC3IP2 OC3IP1 OC3IP0 — — — —

IPC7 00B2 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 — INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0

IPC8 00B4 — — — — — — — — — SPI2IP2 SPI2IP1 SPI2IP0 — SPF2IP2 SPF2IP1 SPF2IP0

IPC9 00B6 — IC5IP2 IC5IP1 IC5IP0 — IC4IP2 IC4IP1 IC4IP0 — IC3IP2 IC3IP1 IC3IP0 — — — —

IPC10 00B8 — — — — — — — — — OC5IP2 OC5IP1 OC5IP0 — — — —

IPC11 00BA — — — — — — — — — PMPIP2 PMPIP1 PMPIP0 — — — —

IPC12 00BC — — — — — MI2C2P2 MI2C2P1 MI2C2P0 — SI2C2P2 SI2C2P1 SI2C2P0 — — — —

IPC13 00BE — — — — — INT4IP2 INT4IP1 INT4IP0 — INT3IP2 INT3IP1 INT3IP0 — — — —

IPC15 00C2 — — — — — RTCIP2 RTCIP1 RTCIP0 — — — — — — — —

IPC16 00C4 — CRCIP2 CRCIP1 CRCIP0 — U2ERIP2 U2ERIP1 U2ERIP0 — U1ERIP2 U1ERIP1 U1ERIP0 — — — —

TABLE 3-4: INTERRUPT CONTROLLER REGISTER MAP

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24FJ128GA FAMILY

All

0000

Resets

0000

All

xxxx

FFFF

0000

xxxx

FFFF

0000

xxxx

FFFF

0000

Resets

0000

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TMR1 0100 Timer1 Register

PR1 0102 Period Register 1

T1CON 0104 TON —TSIDL— — — — — — TGATE TCKPS1 TCKPS0 — TSYNC TCS —

TMR2 0106 Timer2 Register

TMR3HLD 0108 Timer3 Holding Register (For 32-bit timer operations only)

TMR3 010A Timer3 Register

PR2 010C Period Register 2

PR3 010E Period Register 3

T2CON 0110 TON —TSIDL— — — — — — TGATE TCKPS1 TCKPS0 T32 —TCS—

T3CON 0112 TON —TSIDL— — — — — — TGATE TCKPS1 TCKPS0 — —TCS—

TMR4 0114 Timer4 Register

TMR5HLD 0116 Timer5 Holding Register (For 32-bit operations only)

TMR5 0118 Timer5 Register

PR4 011A Period Register 4

PR5 011C Period Register 5

T4CON 011E TON —TSIDL— — — — — — TGATE TCKPS1 TCKPS0 T32 —TCS—

T5CON 0120 TON —TSIDL— — — — — — TGATE TCKPS1 TCKPS0 — —TCS—

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE

CNEN2 0062 — — — — — — — — — — CN21IE CN20IE CN19IE CN18IE CN17IE CN16IE

CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE

CNPU2 006A — — — — — — — — — — CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE

TABLE 3-5: ICN REGISTER MAP

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 3-6: TIMER REGISTER MAP

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24FJ128GA FAMILY

All

xxxx

0000

xxxx

0000

xxxx

0000

xxxx

0000

xxxx

0000

xxxx

0000

xxxx

0000

xxxx

0000

xxxx

Resets

0000

Resets

0000

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

IC1BUF 0140 Input 1 Capture Register

IC1CON 0142 — —ICSIDL— — — — — ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0

IC2BUF 0144 Input 2 Capture Register

IC2CON 0146 — —ICSIDL— — — — — ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0

IC3BUF 0148 Input 3 Capture Register

IC3CON 014A — —ICSIDL— — — — — ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0

IC4BUF 014C Input 4 Capture Register

IC4CON 014E — —ICSIDL— — — — — ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0

IC5BUF 0150 Input 5 Capture Register

IC5CON 0152 — —ICSIDL— — — — — ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0

TABLE 3-7: INPUT CAPTURE REGISTER MAP

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 3-8: OUTPUT COMPARE REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

OC1RS 0180 Output Compare 1 Secondary Register

OC1R 0182 Output Compare 1 Register

OC1CON 0184 — —OCSIDL— — — — — — — — OCFLT OCTSEL OCM2 OCM1 OCM0

OC2RS 0186 Output Compare 2 Secondary Register

OC2R 0188 Output Compare 2 Register

OC2CON 018A — —OCSIDL— — — — — — — — OCFLT OCTSEL OCM2 OCM1 OCM0

OC3RS 018C Output Compare 3 Secondary Register

OC3R 018E Output Compare 3 Register

OC3CON 0190 — —OCSIDL— — — — — — — — OCFLT OCTSEL OCM2 OCM1 OCM0

OC4RS 0192 Output Compare 4 Secondary Register

OC4R 0194 Output Compare 4 Register

OC4CON 0196 — —OCSIDL— — — — — — — — OCFLT OCTSEL OCM2 OCM1 OCM0

OC5RS 0198 Output Compare 5 Secondary Register

OC5R 019A Output Compare 5 Register

OC5CON 019C — —OCSIDL— — — — — — — — OCFLT OCTSEL OCM2 OCM1 OCM0

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24FJ128GA FAMILY

All

0000

00FF

0000

1000

0000

00FF

0000

1000

0000

Resets

0000

Resets

0000

TABLE 3-9: I2C1 REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

I2C1RCV 0200 — — — — — — — — Receive Register

I2C1TRN 0202 — — — — — — — — Transmit Register

I2C1BRG 0204 — — — — — — — Baud Rate Generator

I2C1CON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN

I2C1STAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF

I2C1ADD 020A — — — — — — Address Register

I2C1MSK 020C — — — — — — Address Mask

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

I2C2RCV 0210 — — — — — — — — Receive Register

I2C2TRN 0212 — — — — — — — — Transmit Register

I2C2BRG 0214 — — — — — — — Baud Rate Generator

I2C2CON 0216 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN

I2C2STAT 0218 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2CPOV D/A P S R/W RBF TBF

I2C2ADD 021A — — — — — — Address Register

I2C2MSK 021C — — — — — — Address Mask

TABLE 3-10: I2C2 REGISTER MAP

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24FJ128GA FAMILY

All

0000

0110

xxxx

0000

Resets

0000

All

0000

0110

xxxx

0000

Resets

0000

All

0000

Resets

0000

All

0000

Resets

0000

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL

U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA

U1TXREG 0224 — — — — — — — Transmit Register

U1RXREG 0226 — — — — — — — Receive Register

U1BRG 0228 Baud Rate Generator Prescaler

TABLE 3-11: UART1 REGISTER MAP

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

U2MODE 0230 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL

U2STA 0232 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA

U2TXREG 0234 — — — — — — — Transmit Register

U2RXREG 0236 — — — — — — — Receive Register

U2BRG 0238 Baud Rate Generator Prescaler

TABLE 3-12: UART2 REGISTER MAP

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SPI1STAT 0240 SPIEN — SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 —SPIROV— — — — SPITBF SPIRBF

SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0

SPI1CON2 0244 FRMEN SPIFSD SPIFPOL — — — — — — — — — — — SPIFE SPIBEN

SPI1BUF 0248 SPI1 Transmit and Receive Buffer

TABLE 3-13: SPI1 REGISTER MAP

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SPI2STAT 0260 SPIEN — SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 —SPIROV— — — — SPITBF SPIRBF

SPI2CON1 0262 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0

SPI2CON2 0264 FRMEN SPIFSD SPIFPOL — — — — — — — — — — — SPIFE SPIBEN

SPI2BUF 0268 SPI2 Transmit and Receive Buffer

TABLE 3-14: SPI2 REGISTER MAP

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24FJ128GA FAMILY

All

xxxx

0000

Resets

0000

All

C6FF

xxxx

Resets

(2)

TRISA0

(2)

TRISA1

(2)

TRISA2

(2)

TRISA3

(2)

TRISA4

(2)

TRISA5

(2)

TRISA6

(2)

0000

(2)

RA0

ODA0

LATA0

(2)

RA1

ODA1

LATA1

(2)

RA2

ODA2

LATA2

(2)

RA3

ODA3

LATA3

(2)

RA4

ODA4

LATA4

(2)

RA5

ODA5

LATA5

(2)

RA6

ODA6

LATA6

(2)

— TRISA7

(1)

TRISA9

(1)

— — — TRISA10

(1)

TRISA14

(1)

TRISA15

—RA7

—LATA7

(1)

RA9

LATA9

(1)

— — —RA10

— — —LATA10

(1)

RA14

LATA14

(1)

RA15

LATA15

—ODA7

(1)

ODA9

(1)

— — —ODA10

(1)

ODA14

(1)

ODA15

2: Implemented in 100-pin devices only

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ADC1BUF0 0300 ADC Data Buffer 0

ADC1BUF1 0302 ADC Data Buffer 1

ADC1BUF2 0304 ADC Data Buffer 2

ADC1BUF3 0306 ADC Data Buffer 3

ADC1BUF4 0308 ADC Data Buffer 4

ADC1BUF5 030A ADC Data Buffer 5

ADC1BUF6 030C ADC Data Buffer 6

ADC1BUF7 030E ADC Data Buffer 7

ADC1BUF8 0310 ADC Data Buffer 8

ADC1BUF9 0312 ADC Data Buffer 9

ADC1BUFA 0314 ADC Data Buffer 10

ADC1BUFB 0316 ADC Data Buffer 11

ADC1BUFC 0318 ADC Data Buffer 12

ADC1BUFD 031A ADC Data Buffer 13

ADC1BUFE 031C ADC Data Buffer 14

ADC1BUFF 031E ADC Data Buffer 15

AD1CON1 0320 ADON —ADSIDL— — — FORM1 FORM0 SSRC2 SSRC1 SSRC0 — — ASAM SAMP DONE

AD1CON2 0322 VCFG2 VCFG1 VCFG0 OFFCAL — CSCNA — —BUFS— SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS

AD1CON3 0324 ADRC — — SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0

AD1CHS 0328 CH0NB — — — CH0SB3 CH0SB2 CH0SB1 CH0SB0 CH0NA — — — CH0SA3 CH0SA2 CH0SA1 CH0SA0

AD1PCFG 032C PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0

AD1CSSL 0330 CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 3-15: ADC REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TRISA 02C0

PORTA 02C2

LATA 02C4

ODCA 06C0

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.

TABLE 3-16: PORTA REGISTER MAP

Note 1: Implemented in 80-pin and 100-pin devices only.

PIC24FJ128GA FAMILY

All

FFFF

xxxx

Resets

0000

All

F01E

xxxx

Resets

—

(1)

TRISC1

(2)

TRISC2

(1)

TRISC3

(2)

TRISC4

0000

—

(1)

RC1

ODC

LATC1

(2)

RC2

ODC

LATC2

(1)

RC3

ODC

LATC3

(2)

RC4

LATC4

All

FFFF

xxxx

Resets

0000

ODD

RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0

ODD

LATD11 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0

TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0

(1)

RD12

ODD12

LATD12

TRISD12

(1)

RD13

ODD13

LATD13

TRISD13

(1)

RD14

ODD14

LATD14

TRISD14

(1)

RD15

ODD15

LATD15

TRISD15

2: Implemented in 100-pin devices only

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TRISB 02C6 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0

PORTB 02C8 RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0

LATB 02CA LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0

ODCB 06C6 ODB15 ODB14 ODB13 ODB12 ODB11 ODB10 ODB9 ODB8 ODB7 ODB6 ODB5 ODB4 ODB3 ODB2 ODB1 ODB0

TABLE 3-17: PORTB REGISTER MAP

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TRISC 02CC TRISC15 TRISC14 TRISC13 TRISC12 — — — — — — —

PORTC 02CE RC15 RC14 RC13 RC12 — — — — — — —

LATTC 02D0 LATC15 LATC14 LATC13 LATC12 — — — — — — —

ODCC 06CC ODC15 ODC14 ODC13 ODC12 — — — — — — —ODC

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.

TABLE 3-18: PORTC REGISTER MAP

Note 1: Implemented in 80-pin and 100-pin devices only.

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TRISD 02D2

PORTD 02D4

LATD 02D6

ODCD 06D2

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.

TABLE 3-19: PORTD REGISTER MAP

Note 1: Implemented in 80-pin and 100-pin devices only.

PIC24FJ128GA FAMILY

All

31FF

xxxx

03FF

xxxx

RE6 RE5 RE4 RE3 RE2 RE1 RE0

LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0

0000

ODE6 ODE5 ODE4 ODE3 ODE2 ODE1 ODE0

Resets

TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0

RE7

ODE

LATE7

TRISE7

(1)

RE8

ODE

LATE8

TRISE8

(1)

Resets

TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0

(2)

TRISF7

(2)

TRISF8

0000

RF6 RF5 RF4 RF3 RF2 RF1 RF0

ODF6 ODF5 ODF4 ODF3 ODF2 ODF1 ODF0

LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0

(2)

RF7

ODF7

LATF7

(2)

All

F3CF

xxxx

Resets

(2)

TRISG0

(2)

0000

(2)

RG0

ODG0

LATG0

(2)

All

0000

Resets

— — TRISG9 TRISG8 TRISG7 TRISG6 — — TRISG3 TRISG2 TRISG1

— — RG9 RG8 RG7 RG6 — — RG3 RG2 RG1

— — LATG9 LATG8 LATG7 LATG6 — — LATG 3 L ATG2 LATG 1

— — ODG9 ODG8 ODG7 ODG6 — — ODG3 ODG2 ODG1

(1)

RG12

ODG12

LATG12

(1)

RG13

ODG13

LATG13

(1)

RG14

ODG14

LATG14

(1)

— — —

TRISF12

TRISF13

— — —RF8

(1)

RG12

(1)

RG13

— — — LATF8

LATF12

LATF13

— — —ODF8

(1)

ODF12

(1)

ODF13

TRISG12

(1)

TRISG13

(1)

TRISG14

(1)

— — — — — — — — — — — — — — RTSECSEL PMPTTL

RG15

ODG15

LATG15

TRISG15

2: Implemented in 80-pin and 100-pin devices only.

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TRISE 02D8 — — — — — — TRISE9

PORTE 02DA — — — — — —RE9

LATE 02DC — — — — — —LATE9

ODCE 06D8 — — — — — —ODE9

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.

TABLE 3-20: PORTE REGISTER MAP

Note 1: Implemented in 80-pin and 100-pin devices only.

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TRISF 02DE — —

PORTF 02E0 — —

LATF 02E2 — —

ODCF 06DE — —

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.

TABLE 3-21: PORTF REGISTER MAP

Note 1: Implemented in 100-pin devices only.

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TRISG 02E4

PORTG 02E6

TABLE 3-22: PORTG REGISTER MAP

LATG 02E8

ODCG 06E4

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.

2: Implemented in 80-pin and 100-pin devices only.

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PADCFG1 02FC

Note 1: Implemented in 100-pin devices only

TABLE 3-23: PAD CONFIGURATION MAP

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.

PIC24FJ128GA FAMILY

All

0000

Resets

0000

OB3E OB2E OB1E OB0E

— —

All

xxxx

0000

xxxx

Resets

0000

All

0000

Resets

Parallel Port Data Out Register 1 (Buffers 0 and 1)

IB3F IB2F IB1F IB0F OBE OBUF

— —

CS2 CS1 Parallel Port Destination Address<13:0> (Master modes)

IBF IBOV

0604

(1)

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PMCON 0600 PMPEN — PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN CSF1 CSF0 ALP CS2P CS1P BEP WRSP RDSP

PMMODE 0602 BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0 WAITB1 WAITB0 WAITM3 WAITM2 WAITM1 WAITM0 WAITE1 WAITE0

PMADDR

PMDOUT1

PMDOUT2 0606 Parallel Port Data Out Register 2 (Buffers 2 and 3)

PMDIN1 0608 Parallel Port Data In Register 1 (Buffers 0 and 1)

PMPDIN2 060A Parallel Port Data In Register 2 (Buffers 2 and 3)

PMPEN 060C PTEN15 PTEN14 PTEN13 PTEN12 PTEN11 PTEN10 PTEN9 PTEN8 PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2 PTEN1 PTEN0

PMSTAT 060E

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 3-24: PARALLEL MASTER/SLAVE PORT REGISTER MAP

Note 1: PMADDR and PMDOUT1 share the same physical register. The register functions as PMDOUT1 only in Slave modes, and as PMADDR only in Master modes.

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TABLE 3-25: REAL-TIME CLOCK AND CALENDAR REGISTER MAP

ALRMVAL 0620 Alarm Value Register Window based on APTR<1:0>

0626 RTCEN — RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0

(1)

ALCFGRPT 0622 ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0

RTCVAL 0624 RTCC Value Register Window based on RTCPTR<1:0>

RCFGCAL

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: RCFGCAL register Reset value dependent on type of Reset.

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CMCON 0630 CMIDL — C2EVT C1EVT C2EN C1EN C2OUTEN C1OUTEN C2OUT C1OUT C2INV C1INV C2NEG C2POS C1NEG C1POS

CVRCON 0632 — — — — — — — — CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0

TABLE 3-26: DUAL COMPARATOR REGISTER MAP

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24FJ128GA FAMILY

All

(1)

0000

Resets

0000

All

(2)

xxxx

0300

Resets

0000

(1)

All

0000

Resets

All

0000

Resets

0000

— — — — — — — — NVMKEY<7:0>

2: OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset.

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CRCCON 0640 — — CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT — CRCGO PLEN3 PLEN2 PLEN1 PLEN0

CRCXOR 0642 CRC XOR Polynomial Register

CRCDAT 0644 CRC Data Input Register

CRCWDAT 0646 CRC Result Register

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 3-27: CRC REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

RCON 0740 TRAPR IOPUWR — — — — CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR

OSCCON 0742 — COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0 CLKLOCK —LOCK—CF— SOSCEN OSWEN

CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 DOZEN RCDIV2 RCDIV1 RCDIV0 — — — — — — — —

OSCTUN 0748 — — — — — — — — — — TUN<5:0>

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 3-28: SYSTEM REGISTER MAP

Note 1: RCON register Reset values dependent on type of Reset.

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

NVMCON 0760 WR WREN WRERR — — — — — — ERASE — — NVMOP3 NVMOP2 NVMOP1 NVMOP0

NVMKEY 0766

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 3-29: NVM REGISTER MAP

Note 1: Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TABLE 3-30: PMD REGISTER MAP

— — — IC5MD IC4MD IC3MD IC2MD IC1MD — — — OC5MD OC4MD OC3MD OC2MD OC1MD

T5MD T4MD T3MD T2MD T1MD — — — I2C1MD U2MD U1MD SPI2MD SPI1MD — —ADCMD

PMD1 0770

PMD2 0772

— — — — — CMPMD RTCCMD PMPMD CRCPMD — — — — — I2C2MD —

PMD3 0774

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24FJ128GA FAMILY

3.2.5 SOFTWARE STACK

In addition to its use as a working register, the W15 register in PIC24 devices is also used as a software Stack Pointer. The pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as shown in Figure 3-4. Note that for a PC push during any CALL instruction, the MSB of the PC is zero-extended before the push, ensuring that the MSB is always clear.

Note: A PC push during exception processing

will concatenate the SRL register to the MSB of the PC prior to the push.

The Stack Pointer Limit register (SPLIM) associated with the Stack Pointer sets an upper address boundary for the stack. SPLIM is uninitialized at Reset. As is the case for the Stack Pointer, SPLIM<0> is forced to ‘0’ because all stack operations must be word-aligned. Whenever an EA is generated using W15 as a source or destination pointer, the resulting address is compared with the value in SPLIM. If the contents of the Stack Pointer (W15) and the SPLIM register are equal and a push operation is performed, a stack error trap will not occur. The stack error trap will occur on a subsequent push operation. Thus, for example, if it is desirable to cause a stack error trap when the stack grows beyond address 2000h in RAM, initialize the SPLIM with the value, 1FFEh.

Similarly, a Stack Pointer underflow (stack error) trap is generated when the Stack Pointer address is found to be less than 0800h. This prevents the stack from interfering with the Special Function Register (SFR) space.

A write to the SPLIM register should not be immediately followed by an indirect read operation using W15.

FIGURE 3-4: CALL STACK FRAME

0000h

Stack Grows Towards

000000000

Higher Address

PC<15:0>

PC<22:16>

015

W15 (before CALL)

W15 (after CALL)

POP : [--W15] PUSH : [W15++]

3.3 Interfacing Program and Data Memory Spaces

The PIC24 architecture uses a 24-bit wide program space and 16-bit wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces.

Aside from normal execution, the PIC24 architecture provides two methods by which program space can be accessed during operation:

• Using table instructions to access individual bytes

or words anywhere in the program space

• Remapping a portion of the program space into

the data space (Program Space Visibility)

Table instructions allow an application to read or write to small areas of the program memory. This makes the method ideal for accessing data tables that need to be updated from time to time. It also allows access to all bytes of the program word. The remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look ups from a large table of static data. It can only access the least significant word of the program word.

3.3.1 ADDRESSING PROGRAM SPACE

Since the address ranges for the data and program spaces are 16 and 24 bits respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. The solution depends on the interface method to be used.

For table operations, the 8-bit Table Page register (TBLPAG) is used to define a 32K word region within the program space. This is concatenated with a 16-bit EA to arrive at a full 24-bit program space address. In this format, the Most Significant bit of TBLPAG is used to determine if the operation occurs in the user memory (TBLPAG<7> = 0) or the configuration memory (TBLPAG<7> = 1).

For remapping operations, the 8-bit Program Space Visibility register (PSVPAG) is used to define a 16K word page in the program space. When the Most Significant bit of the EA is ‘1’, PSVPAG is concatenated with the lower 15 bits of the EA to form a 23-bit program space address. Unlike table operations, this limits remapping operations strictly to the user memory area.

Table 3-31 and Figure 3-5 show how the program EA is created for table operations and remapping accesses from the data EA. Here, P<23:0> refers to a program space word, whereas D<15:0> refers to a data space word.

PIC24FJ128GA FAMILY

TABLE 3-31: PROGRAM SPACE ADDRESS CONSTRUCTION

Access Type

Instruction Access (Code Execution)

TBLRD/TBLWT

(Byte/Word Read/Write)

Program Space Visibility (Block Remap/Read)

Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of

the address is PSVPAG<0>.

Access

Space

User 0 PC<22:1> 0

User TBLPAG<7:0> Data EA<15:0>

Configuration TBLPAG<7:0> Data EA<15:0>

User 0 PSVPAG<7:0> Data EA<14:0>

<23> <22:16> <15> <14:1> <0>

0xxx xxxx xxxx xxxx xxxx xxxx

1xxx xxxx xxxx xxxx xxxx xxxx

0 xxxx xxxx xxx xxxx xxxx xxxx

FIGURE 3-5: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

Program Space Address

0xx xxxx xxxx xxxx xxxx xxx0

(1)

Program Counter

Table Operations

Program Space Visibility (Remapping)

(1)

(2)

User/Configuration

1/0

(1)

Space Select

TBLPAG

8 bits

PSVPAG

8 bits

Select

23 bits

24 bits

23 bits

16 bits

15 bits

0Program Counter

1/0

Byte Select

Note 1: The LSb of program space addresses is always fixed as ‘0’, in order to maintain word alignment of

data in the program and data spaces.

2: Table operations are not required to be word-aligned. Table read operations are permitted in the

configuration memory space.

PIC24FJ128GA FAMILY

3.3.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS

The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space, without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data.

The PC is incremented by two for each successive 24-bit program word. This allows program memory addresses to directly map to data space addresses. Program memory can thus be regarded as two 16-bit word wide address spaces, residing side by side, each with the same address range. TBLRDL and TBLWTL access the space which contains the least significant data word, and TBLRDH and TBLWTH access the space which contains the upper data byte.

Two table instructions are provided to move byte or word sized (16-bit) data to and from program space. Both function as either byte or word operations.

1. TBLRDL (Table Read Low): In Word mode, it

maps the lower word of the program space location (P<15:0>)

In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when byte select is ‘1’; the lower byte is selected when it is ‘0’.

to a data address (D<15:0>).

2. TBLRDH (Table Read High): In Word mode, it maps the entire upper word of a program address (P<23:16>) to a data address. Note that D<15:8>, the “phantom byte”, will always be ‘0’.

In Byte mode, it maps the upper or lower byte of the program word to D<7:0> of the data address, as above. Note that the data will always be ‘0’ when the upper “phantom” byte is selected (byte select = 1).

In a similar fashion, two table instructions, TBLWTH and TBLWTL, are used to write individual bytes or words to a program space address. The details of their operation are explained in Section 4.0 “Flash Program Memory”.

For all table operations, the area of program memory space to be accessed is determined by the Table Page register (TBLPAG). TBLPAG covers the entire program memory space of the device, including user and configuration spaces. When TBLPAG<7> = 0, the Table Page is located in the user memory space. When TBLPAG<7> = 1, the page is located in configuration space.

Note: Only table read operations will execute in

the configuration memory space and only then, in implemented areas such as the Device ID. Table write operations are not allowed.

FIGURE 3-6: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS

Program Space

TBLPAG

23 15 0

000000h

020000h

030000h

800000h

00000000

‘Phantom’ Byte

TBLRDH.B (Wn<0> = 0)

TBLRDL.B (Wn<0> = 1)

TBLRDL.B (Wn<0> = 0)

TBLRDL.W

The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in the user memory area.

Data EA<15:0>

081623

PIC24FJ128GA FAMILY

3.3.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY

The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This provides transparent access of stored constant data from the data space without the need to use special instructions (i.e., TBLRDL/H).

Program space access through the data space occurs if the Most Significant bit of the data space EA is ‘1’ and program space visibility is enabled by setting the PSV bit in the Core Control register (CORCON<2>). The location of the program memory space to be mapped into the data space is determined by the Program Space Visibility Page register (PSVPAG). This 8-bit register defines any one of 256 possible pages of 16K words in program space. In effect, PSVPAG functions as the upper 8 bits of the program memory address, with the 15 bits of the EA functioning as the lower bits. Note that by incrementing the PC by 2 for each program memory word, the lower 15 bits of data space addresses directly map to the lower 15 bits in the corresponding program space addresses.

Data reads to this area add an additional cycle to the instruction being executed, since two program memory fetches are required.

Although each data space address, 8000h and higher, maps directly into a corresponding program memory address (see Figure 3-7), only the lower 16 bits of the

24-bit program word are used to contain the data. The upper 8 bits of any program space locations used as data should be programmed with ‘1111 1111’ or ‘0000 0000’ to force a NOP. This prevents possible issues should the area of code ever be accidentally executed.

Note: PSV access is temporarily disabled during

table reads/writes.

For operations that use PSV and are executed outside a REPEAT loop, the MOV and MOV.D instructions will require one instruction cycle in addition to the specified execution time. All other instructions will require two instruction cycles in addition to the specified execution time.

For operations that use PSV which are executed inside a REPEAT loop, there will be some instances that require two instruction cycles in addition to the specified execution time of the instruction:

• Execution in the first iteration

• Execution in the last iteration

• Execution prior to exiting the loop due to an interrupt

• Execution upon re-entering the loop after an interrupt is serviced

Any other iteration of the REPEAT loop will allow the instruction accessing data, using PSV, to execute in a single cycle.

FIGURE 3-7: PROGRAM SPACE VISIBILITY OPERATION

When CORCON<2> = 1 and EA<15> = 1:

Program Space

PSVPAG

The data in the page designated by PSVPAG is mapped into the upper half of the data memory

space....

23 15 0

000000h

010000h

018000h

800000h

Data Space

PSV Area

0000h

8000h

FFFFh

Data EA<14:0>

...while the lower 15 bits of the EA specify an exact address within the PSV area. This corresponds exactly to the same lower 15 bits of the actual program space address.

PIC24FJ128GA FAMILY

DS39747B-page 44 Advance Information ©

PIC24FJ128GA FAMILY

4.0 FLASH PROGRAM MEMORY

Note: This data sheet summarizes the features

of this group of PIC24FJ devices. It is not intended to be a comprehensive reference source.

The PIC24FJ128GA family of devices contains internal Flash program memory for storing and executing application code. The memory is readable, writable and erasable during normal operation over the entire V range.

Flash memory can be programmed in two ways:

1. In-Circuit Serial Programming (ICSP)

2. Run-Time Self-Programming (RTSP)

ICSP allows a PIC24FJ128GA family device to be serially programmed while in the end application circuit. This is simply done with two lines for Programming Clock and Programming Data (which are named PGCx and PGDx, respectively), and three other lines for power (V

DD), ground (VSS) and Master Clear (MCLR).

This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed.

RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may write program memory data in blocks of 64 instructions (192 bytes) at a time, and erase program memory in blocks of 512 instructions (1536 bytes) at a time.

4.1 Table Instructions and Flash

Programming

Regardless of the method used, all programming of Flash memory is done with the table read and table write instructions. These allow direct read and write access to the program memory space from the data memory while the device is in normal operating mode. The 24-bit target address in the program memory is formed using bits<7:0> of the TBLPAG register and the Effective Address (EA) from a W register specified in the table instruction, as shown in Figure 4-1.

The TBLRDL and the TBLWTL instructions are used to read or write to bits<15:0> of program memory. TBLRDL and TBLWTL can access program memory in both Word and Byte modes.

The TBLRDH and TBLWTH instructions are used to read or write to bits<23:16> of program memory. TBLRDH and TBLWTH can also access program memory in Word or Byte mode.

FIGURE 4-1: ADDRESSING FOR TABLE REGISTERS

24 bits

Using

Using Table Instruction

User/Configuration Space Select

Program Counter

1/0

TBLPAG Reg

8 bits

Program Counter

Working Reg EA

24-bit EA

16 bits

Byte Select

PIC24FJ128GA FAMILY

4.2 RTSP Operation

The PIC24 Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user to erase blocks of eight rows (512 instructions) at a time, and to program one row at a time. The 8-row erase blocks and single-row write blocks are edgealigned, from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively.

The program memory implements holding buffers that can contain 64 instructions of programming data. Prior to the actual programming operation, the write data must be loaded into the buffers in sequential order. The instructions words loaded must always be from a group of 64 boundaries.

The basic sequence for RTSP programming is to set up a Table Pointer, then do a series of TBLWT instructions to load the buffers. Programming is performed by setting the control bits in the NVMCON register. A total of 64 TBLWTL and TBLWTH instructions are required to load the instructions.

All of the table write operations are single-word writes (2 instruction cycles), because only the buffers are written. A programming cycle is required for programming each row.

4.3 Control Registers

There are two SFRs used to read and write the program Flash memory: NVMCON and NVMKEY.

The NVMCON register (Register 4-1) controls which blocks are to be erased, which memory type is to be programmed and the start of the programming cycle.

NVMKEY is a write-only register that is used for write protection. To start a programming or erase sequence, the user must consecutively write 55h and AAh to the NVMKEY register. Refer to Section 4.4 “Programming

Operations” for further details.

4.4 Programming Operations

A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. A programming operation is nominally 4 ms in duration and the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON<15>) starts the operation, and the WR bit is automatically cleared when the operation is finished.

PIC24FJ128GA FAMILY

REGISTER 4-1: NVMCOM: FLASH MEMORY CONTROL REGISTER

Upper Byte:

bit 15 bit 8

R/SO-0

(1)

R/W-0

(1)

R/W-0

WR WREN WRERR

(1)

U-0 U-0 U-0 U-0 U-0

— — — — —

Lower Byte:

U-0 R/W-0

(1)

U-0 U-0 R/W-0

— ERASE — —NVMOP3

bit 7 bit 0

bit 15 WR: Write Control bit

1 = Initiates a Flash memory program or erase operation

The operation is self-timed and the bit is cleared by hardware once operation is complete.

0 = Program or erase operation is complete and inactive

bit 14 WREN: Write Enable bit

1 = Enable Flash program/erase operations 0 = Inhibit Flash program/erase operations

bit 13 WRERR: Write Sequence Error Flag bit

1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically

on any set attempt of the WR bit)

0 = The program or erase operation completed normally

bit 12-7 Unimplemented: Read as ‘0’

bit 6 ERASE: Erase/Program Enable bit

1 = Perform the erase operation specified by NVMOP3:NVMOP0 on the next WR command 0 = Perform the program operation specified by NVMOP3:NVMOP0 on the next WR command

bit 5-4 Unimplemented: Read as ‘0’

bit 3-0 NVMOP3:NVMOP0: NVM Operation Select bits

1111 = Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0) 0010 = Memory row erase operation (ERASE = 1) or no operation (ERASE = 0) 0001 = Memory row program operation (ERASE = 0) or no operation (ERASE = 1)

(2)

(1)

(2)

NVMOP2

R/W-0

(1)

(2)

R/W-0

NVMOP1

(1)

(2)

R/W-0

NVMOP0

(1)

(2)

Note 1: These bits can only be reset on POR.

2: All other combinations of NVMOP3:NVMOP0 are unimplemented.

Legend:

R = Readable bit W = Writable bit SO = Settable-Only bit U = Unimplemented bit

-n = Value at Reset ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC24FJ128GA FAMILY

4.4.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY

The user can program one row of program Flash memory at a time. To do this, it is necessary to erase the 8-row erase block containing the desired row. The general process is:

1. Read eight rows of program memory

(512 instructions) and store in data RAM.

2. Update the program data in RAM with the

desired new data.

3. Erase the block (see Example 4-1):

a) Set the NVMOP bits (NVMCOM<3:0>) to

‘0010’ to configure for block erase. Set the ERASE (NVMCOM<6>) and WREN (NVMCOM<14>) bits.

b) Write the starting address of the block to be

erased into the TBLPAG and W registers. c) Write 55h to NVMKEY. d) Write AAh to NVMKEY. e) Set the WR bit (NVMCOM<15>). The erase

cycle begins and the CPU stalls for the dura-

tion of the erase cycle. When the erase is

done, the WR bit is cleared automatically.

4. Write the first 64 instructions from data RAM into the program memory buffers (see Example 4-2).

5. Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure

for row programming. Clear the ERASE bit

and set the WREN bit. b) Write 55h to NVMKEY. c) Write AAh to NVMKEY. d) Set the WR bit. The programming cycle

begins and the CPU stalls for the duration of

the write cycle. When the write to Flash mem-

ory is done, the WR bit is cleared automati-

cally.

6. Repeat steps 4 and 5, using the next available 64 instructions from the block in data RAM by incrementing the value in TBLPAG, until all 512 instructions are written back to Flash memory.

For protection against accidental operations, the write initiate sequence for NVMKEY must be used to allow any erase or program operation to proceed. After the programming command has been executed, the user must wait for the programming time until programming is complete. The two instructions following the start of the programming sequence should be NOPs, as shown in Example 4-3.

EXAMPLE 4-1: ERASING A PROGRAM MEMORY BLOCK

; Set up NVMCON for block erase operation

MOV #0x4042, W0 ;

; Init pointer to row to be ERASED

MOV W0, NVMCON ; Initialize NVMCON

MOV #tblpage(PROG_ADDR), W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #tbloffset(PROG_ADDR), W0 ; Initialize in-page EA[15:0] pointer TBLWTL W0, [W0] ; Set base address of erase block DISI #5 ; Block all interrupts with priority <7

; for next 5 instructions MOV #0x55, W0 MOV W0, NVMKEY ; Write the 55 key MOV #0xAA, W1 ; MOV W1, NVMKEY ; Write the AA key BSET NVMCON, #WR ; Start the erase sequence NOP ; Insert two NOPs after the erase NOP ; command is asserted

PIC24FJ128GA FAMILY

EXAMPLE 4-2: LOADING THE WRITE BUFFERS

; Set up NVMCON for row programming operations

; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled

; Perform the TBLWT instructions to write the latches ; 0th_program_word

; 1st_program_word

; 2nd_program_word

; 63rd_program_word

MOV #0x4001, W0 ; MOV W0, NVMCON ; Initialize NVMCON

MOV #0x0000, W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #0x6000, W0 ; An example program memory address

MOV #LOW_WORD_0, W2 ; MOV #HIGH_BYTE_0, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch

MOV #LOW_WORD_1, W2 ; MOV #HIGH_BYTE_1, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch

MOV #LOW_WORD_2, W2 ; MOV #HIGH_BYTE_2, W3 ; TBLWTL W2, TBLWTH W3,

•

MOV #LOW_WORD_31, W2 ; MOV #HIGH_BYTE_31, W3 ; TBLWTL W2, TBLWTH W3,

[W0] ; Write PM low word into program latch [W0++] ; Write PM high byte into program latch

EXAMPLE 4-3: INITIATING A PROGRAMMING SEQUENCE

DISI #5 ; Block all interrupts with priority <7

MOV #0x55, W0 MOV W0, NVMKEY ; Write the 55 key MOV #0xAA, W1 ; MOV W1, NVMKEY ; Write the AA key BSET NVMCON, #WR ; Start the erase sequence NOP ; Insert two NOPs after the NOP ; erase command is asserted

; for next 5 instructions

PIC24FJ128GA FAMILY

NOTES:

PIC24FJ128GA FAMILY

5.0 RESETS

The Reset module combines all Reset sources and controls the device Master Reset Signal, SYSRST following is a list of device Reset sources:

• POR: Power-on Reset

•MCLR

: Pin Reset

•SWR: RESET Instruction

• WDT: Watchdog Timer Reset

• BOR: Brown-out Reset

• TRAPR: Trap Conflict Reset

• IOPUWR: Illegal Opcode Reset

• UWR: Uninitialized W Register Reset

A simplified block diagram of the Reset module is shown in Figure 5-1.

Any active source of Reset will make the SYSRST nal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. Most registers are unaffected by a Reset; their status is unknown on POR and unchanged by all other Resets.

FIGURE 5-1: RESET SYSTEM BLOCK DIAGRAM

RESET

Instruction

. The

sig-

Note: Refer to the specific peripheral or CPU

section of this manual for register Reset states.

All types of device Reset will set a corresponding status bit in the RCON register to indicate the type of Reset (see Register 5-1). A POR will clear all bits except for the BOR and POR bits (RCON<1:0>), which are set. The user may set or clear any bit at any time during code execution. The RCON bits only serve as status bits. Setting a particular Reset status bit in software will not cause a device Reset to occur.

The RCON register also has other bits associated with the Watchdog Timer and device power-saving states. The function of these bits is discussed in other sections of this manual.

Note: The status bits in the RCON register

should be cleared after they are read so that the next RCON register value after a device Reset will be meaningful.

MCLR

WDT

Module

Sleep or Idle

VDD Rise

Detect

VDD

Brown-out

Reset

Enable Voltage Regulator

Trap Conflict

Illegal Opcode

Uninitialized W Register

Glitch Filter

POR

SYSRST

BOR

PIC24FJ128GA FAMILY

REGISTER 5-1: RCON: RESET CONTROL REGISTER

Upper Byte:

R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

TRAPR IOPUWR

bit 15 bit 8

Lower Byte:

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1

EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR

bit 7 bit 0

bit 15 TRAPR: Trap Reset Flag bit

1 = A Trap Conflict Reset has occurred 0 = A Trap Conflict Reset has not occurred

bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit

1 = An illegal opcode detection, an illegal address mode, or uninitialized W register used as an Address

Pointer caused a Reset

0 = An illegal opcode or uninitialized W Reset has not occurred bit 13-10 Unimplemented: Read as ‘0’ bit 9 CM: Configuration Word Mismatch Reset Flag bit

1 = A Configuration Word Mismatch Reset has occurred

0 = A Configuration Word Mismatch Reset has not occurred

bit 8 VREGS: Voltage Regulator Standby Enable bit

1 = Regulator remains active during Sleep

0 = Regulator goes to standby during Sleep

bit 7 EXTR: External Reset (MCLR

1 = A Master Clear (pin) Reset has occurred

0 = A Master Clear (pin) Reset has not occurred

bit 6 SWR: Software Reset (Instruction) Flag bit

1 = A RESET instruction has been executed

0 = A RESET instruction has not been executed

bit 5 SWDTEN: Software Enable/Disable of WDT bit

1 = WDT is enabled

0 = WDT is disabled

Note: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless

of the SWDTEN bit setting.

bit 4 WDTO: Watchdog Timer Time-out Flag bit

1 = WDT time-out has occurred

0 = WDT time-out has not occurred

bit 3 SLEEP: Wake From Sleep Flag bit

1 = Device has been in Sleep mode

0 = Device has not been in Sleep mode

bit 2 IDLE: Wake-up From Idle Flag bit

1 = Device was in Idle mode

0 = Device was not in Idle mode

bit 1 BOR: Brown-out Reset Flag bit

1 = A Brown-out Reset has occurred. Note that BOR is also set after Power-on Reset.

0 = A Brown-out Reset has not occurred

bit 0 POR: Power-on Reset Flag bit

1 = A Power-up Reset has occurred

0 = A Power-up Reset has not occurred

Note: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software

does not cause a device Reset.

— — — —CMVREGS

) Pin bit

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC24FJ128GA FAMILY

TABLE 5-1: RESET FLAG BIT OPERATION

Flag Bit Setting Event Clearing Event

TRAPR (RCON<15>) Trap conflict event POR

IOPR (RCON<14>) Illegal opcode or uninitialized W register access POR

EXTR (RCON<7>) MCLR

SWR (RCON<6>) RESET instruction POR

WDTO (RCON<4>) WDT time-out PWRSAV instruction, POR

SLEEP (RCON<3>) PWRSAV #SLEEP instruction POR

IDLE (RCON<2>) PWRSAV #IDLE instruction POR

BOR (RCON<1>) POR, BOR —

POR (RCON<0>) POR —

Note: All Reset flag bits may be set or cleared by the user software.

Reset POR

5.1 Clock Source Selection at Reset

If clock switching is enabled, the system clock source at device Reset is chosen as shown in Table 5-2. If clock switching is disabled, the system clock source is always selected according to the oscillator Configuration bits. Refer to 7.0 “Oscillator Configuration” for further details.

TABLE 5-2: OSCILLATOR SELECTION vs.

TYPE OF RESET (CLOCK SWITCHING ENABLED)

Reset Type Clock Source Determinant

POR Oscillator Configuration Bits

BOR

MCLR

WDTR

SWR

(FNOSC2:FNOSC0)

COSC Control bits (OSCCON<14:12>)

5.2 Device Reset Times

The Reset times for various types of device Reset are summarized in Table 5-3. Note that the system Reset signal, SYSRST, is released after the POR and PWRT delay times expire.

The time that the device actually begins to execute code will also depend on the system oscillator delays, which include the Oscillator Start-up Timer (OST) and the PLL lock time. The OST and PLL lock times occur in parallel with the applicable SYSRST

The FSCM delay determines the time at which the FSCM begins to monitor the system clock source after the SYSRST

signal is released.

delay times.

PIC24FJ128GA FAMILY

TABLE 5-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS

Reset Type Clock Source SYSRST

POR

POR EC, FRC, FRCDIV, LPRC T

+ TSTARTUP + TRST ——1, 2, 3

Delay

System Clock

Delay

ECPLL, FRCPLL TPOR + TSTARTUP + TRST TLOCK TFSCM 1, 2, 3, 5, 6

POR

XT, HS, SOSC T

+ TSTARTUP + TRST TOST TFSCM 1, 2, 3, 4, 6

XTPLL, HSPLL TPOR + TSTARTUP + TRST TOST + TLOCK TFSCM 1, 2, 3, 4, 5, 6

BOR EC, FRC, FRCDIV, LPRC TSTARTUP + TRST ——2, 3

ECPLL, FRCPLL T

STARTUP + TRST TLOCK TFSCM 2, 3, 5, 6

XT, HS, SOSC TSTARTUP + TRST TOST TFSCM 2, 3, 4, 6

XTPLL, HSPLL TSTARTUP + TRST TOST + TLOCK TFSCM 2, 3, 4, 5, 6

MCLR

WDT Any Clock T

Any Clock TRST ——3

RST ——3

Software Any clock TRST ——3

Illegal Opcode Any Clock TRST ——3

Uninitialized W Any Clock T

RST ——3

Trap Conflict Any Clock TRST ——3

Note 1: TPOR = Power-on Reset delay (10 μs nominal).

STARTUP = TVREG (10 μs nominal) if on-chip regulator enabled or TPWRT (64 ms nominal) if on-chip

2: T

regulator disabled.

3: T

RST = Internal state Reset time (20 μs nominal).

OST = Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the

4: T

oscillator clock to the system.

5: T

LOCK = PLL lock time (20 μs nominal). FSCM = Fail-Safe Clock Monitor delay (100 μs nominal).

6: T

FSCM

Delay

Notes

5.2.1 POR AND LONG OSCILLATOR START-UP TIMES

The oscillator start-up circuitry and its associated delay timers are not linked to the device Reset delays that occur at power-up. Some crystal circuits (especially low-frequency crystals) will have a relatively long start-up time. Therefore, one or more of the following conditions is possible after SYSRST

• The oscillator circuit has not begun to oscillate.

• The Oscillator Start-up Timer has NOT expired (if

a crystal oscillator is used).

• The PLL has not achieved a LOCK (if PLL is used).

The device will not begin to execute code until a valid clock source has been released to the system. Therefore, the oscillator and PLL start-up delays must be considered when the Reset delay time must be known.

is released:

5.2.2 FAIL-SAFE CLOCK MONITOR (FSCM) AND DEVICE RESETS

If the FSCM is enabled, it will begin to monitor the system clock source when SYSRST clock source is not available at this time, the device will automatically switch to the FRC oscillator and the user can switch to the desired crystal oscillator in the Trap Service Routine.

is released. If a valid

PIC24FJ128GA FAMILY

5.2.2.1 FSCM Delay for Crystal and PLL Clock Sources

When the system clock source is provided by a crystal oscillator and/or the PLL, a small delay, T automatically be inserted after the POR and PWRT delay times. The FSCM will not begin to monitor the system clock source until this delay expires. The FSCM delay time is nominally 100 μs and provides additional time for the oscillator and/or PLL to stabilize. In most cases, the FSCM delay will prevent an oscillator failure trap at a device Reset when the PWRT is disabled.

FSCM, will

5.3 Special Function Register Reset States

Most of the Special Function Registers (SFRs) associated with the PIC24 CPU and peripherals are reset to a particular value at a device Reset. The SFRs are grouped by their peripheral or CPU function and their Reset values are specified in each section of this manual.

The Reset value for each SFR does not depend on the type of Reset, with the exception of four registers. The Reset value for the Reset Control register, RCON, will depend on the type of device Reset. The Reset value for the Oscillator Control register, OSCCON, will depend on the type of Reset and the programmed values of the oscillator Configuration bits in the FOSC Device Configuration register (see Table 5-2). The RCFGCAL and EECON1 registers are only affected by a POR.

PIC24FJ128GA FAMILY

NOTES:

PIC24FJ128GA FAMILY

6.0 INTERRUPT CONTROLLER

The PIC24 interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the PIC24 CPU. It has the following features:

• Up to 8 processor exceptions and software traps

• 7 user-selectable priority levels

• Interrupt Vector Table (IVT) with up to 118 vectors

• A unique vector for each interrupt or exception source

• Fixed priority within a specified user priority level

• Alternate Interrupt Vector Table (AIVT) for debug support

• Fixed interrupt entry and return latencies

6.1 Interrupt Vector Table

The Interrupt Vector Table (IVT) is shown in Figure 6-1. The IVT resides in program memory, starting at location 000004h. The IVT contains 126 vectors, consisting of 8 non-maskable trap vectors, plus up to 118 sources of interrupt. In general, each interrupt source has its own vector. Each interrupt vector contains a 24-bit wide address. The value programmed into each interrupt vector location is the starting address of the associated Interrupt Service Routine (ISR).

Interrupt vectors are prioritized in terms of their natural priority; this is linked to their position in the vector table. All other things being equal, lower addresses have a higher natural priority. For example, the interrupt associated with vector 0 will take priority over interrupts at any other vector address.

PIC24FJ128GA family devices implement nonmaskable traps and unique interrupts. These are summarized in Table 6-1 and Table 6-2.

6.1.1 ALTERNATE INTERRUPT VECTOR TAB LE

The Alternate Interrupt Vector Table (AIVT) is located after the IVT as shown in Figure 6-1. Access to the AIVT is provided by the ALTIVT control bit (INTCON2<15>). If the ALTIVT bit is set, all interrupt and exception processes will use the alternate vectors instead of the default vectors. The alternate vectors are organized in the same manner as the default vectors.

The AIVT supports emulation and debugging efforts by providing a means to switch between an application

PIC24FJ128GA FAMILY

FIGURE 6-1: PIC24 INTERRUPT VECTOR TABLE

Reset – GOTO Instruction 000000h

Reset – GOTO Address 000002h

Reserved 000004h

Oscillator Fail Trap Vector

Address Error Trap Vector

Stack Error Trap Vector

Math Error Trap Vector

Reserved Reserved

Reserved Interrupt Vector 0 000014h Interrupt Vector 1

— —

— Interrupt Vector 52 00007Ch Interrupt Vector 53 00007Eh Interrupt Vector 54 000080h

—

Interrupt Vector 116 0000FCh Interrupt Vector 117 0000FEh

Reserved 000100h Reserved 000102h Reserved

Decreasing Natural Order Priority

Oscillator Fail Trap Vector

Address Error Trap Vector

Stack Error Trap Vector

Math Error Trap Vector

Reserved Reserved

Reserved Interrupt Vector 0 000114h Interrupt Vector 1

— —

— Interrupt Vector 52 00017Ch Interrupt Vector 53 00017Eh Interrupt Vector 54 000180h

—

Interrupt Vector 116 Interrupt Vector 117 0001FEh

Start of Code 000200h

Interrupt Vector Table (IVT)

Alternate Interrupt Vector Table (AIVT)

(1)

Note 1: See Table 6-2 for the Interrupt Vector list.

TABLE 6-1: TRAP VECTOR DETAILS

Vector Number IVT Address AIVT Address Trap Source

0 000004h 000104h Reserved

1 000006h 000106h Oscillator Failure

2 000008h 000108h Address Error

3 00000Ah 00010Ah Stack Error

4 00000Ch 00010Ch Math Error

5 00000Eh 00010Eh Reserved

6 000010h 000110h Reserved

7 000012h 0001172h Reserved

PIC24FJ128GA FAMILY

TABLE 6-2: IMPLEMENTED INTERRUPT VECTORS

Interrupt Source

ADC1 Conversion Done 13 00002Eh 00012Eh IFS0<13> IEC0<13> IPC3<6:4>

Comparator Event 18 000038h 000138h IFS1<2> IEC1<2> IPC4<10:8>

CRC Generator 67 00009Ah 00019Ah IFS4<3> IEC4<3>

External Interrupt 0 0 000014h 000114h IFS0<0> IEC0<0> IPC0<2:0>

External Interrupt 1 20 00003Ch 00013Ch IFS1<4> IEC1<4> IPC5<2:0>

External Interrupt 2 29 00004Eh 00014Eh IFS1<13> IEC1<13> IPC7<6:4>

External Interrupt 3 53 00007Eh 00017Eh IFS3<5> IEC3<5> IPC13<6:4>

External Interrupt 4 54 000080h 000180h IFS3<6> IEC3<6> IPC13<10:8>

I2C1 Master Event 17 000036h 000136h IFS1<1> IEC1<1> IPC4<6:4>

I2C1 Slave Event 16 000034h 000034h IFS1<0> IEC1<0> IPC4<2:0>

I2C2 Master Event 50 000078h 000178h IFS3<2> IEC3<2> IPC12<10:8>

I2C2 Slave Event 49 000076h 000176h IFS3<1> IEC3<1> IPC12<6:4>

Input Capture 1 1 000016h 000116h IFS0<1> IEC0<1> IPC0<6:4>

Input Capture 2 5 00001Eh 00011Eh IFS0<5> IEC0<5> IPC1<6:4>

Input Capture 3 37 00005Eh 00015Eh IFS2<5> IEC2<5> IPC9<6:4>

Input Capture 4 38 000060h 000160h IFS2<6> IEC2<6> IPC9<10:8>

Input Capture 5 39 000062h 000162h IFS2<7> IEC2<7> IPC9<14:12>

Input Change Notification 19 00003Ah 00013Ah IFS1<3> IEC1<3> IPC4<14:12>

Output Compare 1 2 000018h 000118h IFS0<2> IEC0<2> IPC0<10:8>

Output Compare 2 6 000020h 000120h IFS0<6> IEC0<6> IPC1<10:8>

Output Compare 3 25 000046h 000146h IFS1<9> IEC1<9> IPC6<6:4>

Output Compare 4 26 000048h 000148h IFS1<10> IEC1<10> IPC6<10:8>

Output Compare 5 41 000066h 000166h IFS2<9> IEC2<9> IPC10<6:4>

Parallel Master Port 45 00006Eh 00016Eh IFS2<13> IEC2<13> IPC11<6:4>

Real-Time Clock/Calendar 62 000090h 000190h IFS3<14> IEC3<13> IPC15<10:8>

SPI1 Error 9 000026h 000126h IFS0<9> IEC0<9> IPC2<6:4>

SPI1 Event 10 000028h 000128h IFS0<10> IEC0<10> IPC2<10:8>

SPI2 Error 32 000054h 000154h IFS2<0> IEC0<0> IPC8<2:0>

SPI2 Event 33 000056h 000156h IFS2<1> IEC2<1> IPC8<6:4>

Timer1 3 00001Ah 00011Ah IFS0<3> IEC0<3> IPC0<14:12>

Timer2 7 000022h 000122h IFS0<7> IEC0<7> IPC1<14:12>

Timer3 8 000024h 000124h IFS0<8> IEC0<8> IPC2<2:0>

Timer4 27 00004Ah 00014Ah IFS1<11> IEC1<11> IPC6<14:12>

Timer5 28 00004Ch 00014Ch IFS1<12> IEC1<12> IPC7<2:0>

UART1 Error 65 000096h 000196h IFS4<1> IEC4<1> IPC16<6:4>

UART1 Receiver 11 00002Ah 00012Ah IFS0<11> IEC0<11> IPC2<14:12>

UART1 Transmitter 12 00002Ch 00012Ch IFS0<12> IEC0<12> IPC3<2:0>

UART2 Error 66 000098h 000198h IFS4<2> IEC4<2> IPC16<10:8>

UART2 Receiver 30 000050h 000150h IFS1<14> IEC1<14> IPC7<10:8>

UART2 Transmitter 31 000052h 000152h IFS1<15> IEC1<15> IPC7<14:12>

Vector

Number

IVT Address

AIVT

Address

Interrupt Bit Locations

Flag Enable Priority

IPC16<14:12>

PIC24FJ128GA FAMILY

6.3 Interrupt Control and Status Registers

The PIC24FJ128GA family devices implement a total of 28 registers for the interrupt controller:

• INTCON1

• INTCON2

• IFS0 through IFS4

• IEC0 through IEC4

• IPC0 through IPC14, and IPC16

Global interrupt control functions are controlled from INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit, as well as the control and status flags for the processor trap sources. The INTCON2 register controls the external interrupt request signal behavior and the use of the Alternate Interrupt Vector Table.

The IFS registers maintain all of the interrupt request flags. Each source of interrupt has a status bit which is set by the respective peripherals, or external signal, and is cleared via software.

The IEC registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals.

The IPC registers are used to set the interrupt priority level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels.

The interrupt sources are assigned to the IFSx, IECx and IPCx registers in the same sequence that they are listed in Table 6-2. For example, the INT0 (External Interrupt 0) is shown as having a vector number and a natural order priority of 0. Thus, the INT0IF status bit is found in IFS0<0>, the enable bit in IEC0<0> and the priority bits in the first position of IPC0 (IPC0<2:0>).

Although they are not specifically part of the interrupt control hardware, two of the CPU control registers contain bits that control interrupt functionality. The CPU STATUS register (SR) contains the IPL2:IPL0 bits (SR<7:5>). These indicate the current CPU interrupt priority level. The user may change the current CPU priority level by writing to the IPL bits.

The CORCON register contains the IPL3 bit, which together with IPL2:IPL0, also indicates the current CPU priority level. IPL3 is a read-only bit so that trap events cannot be masked by the user software.

All interrupt registers are described in Register 6-1 through Register 6-30, in the following pages.

PIC24FJ128GA FAMILY

REGISTER 6-1: SR: STATUS REGISTER (IN CPU)

Upper Byte:

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0

— — — — — — —DC

bit 15 bit 8

Lower Byte:

R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

(1,2)

IPL2

bit 7 bit 0

IPL1

(1,2)

IPL0

(1,2)

RA N OV Z C

bit 7-5 IPL2:IPL0: CPU Interrupt Priority Level Status bits

111 = CPU interrupt priority level is 7 (15). User interrupts disabled. 110 = CPU interrupt priority level is 6 (14) 101 = CPU interrupt priority level is 5 (13) 100 = CPU interrupt priority level is 4 (12) 011 = CPU interrupt priority level is 3 (11) 010 = CPU interrupt priority level is 2 (10) 001 = CPU interrupt priority level is 1 (9) 000 = CPU interrupt priority level is 0 (8)

Note 1: The IPL bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU interrupt priority

level. The value in parentheses indicates the IPL if IPL3 = 1.

2: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

(1,2)

REGISTER 6-2: CORCON: CORE CONTROL REGISTER

Upper Byte:

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

Lower Byte:

U-0 U-0 U-0 U-0 R/C-0 R/W-0 U-0 U-0

— — — —IPL3

bit 7 bit 0

bit 3 IPL3: CPU Interrupt Priority Level Status bit

1 = CPU interrupt priority level is greater than 7; peripheral interrupts are disabled 0 = CPU interrupt priority level is 7 or less

Note 1: The IPL3 bit is concatenated with the IPL2:IPL0 bits (SR<7:5>) to form the CPU interrupt priority

level.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

(1)

PSV — —

PIC24FJ128GA FAMILY

REGISTER 6-3: INTCON1: INTERRUPT CONTROL REGISTER 1

Upper Byte:

R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

NSTDIS

bit 15 bit 8

bit 15 NSTDIS: Interrupt Nesting Disable bit

bit 14-5 Unimplemented: Read as ‘0’

bit 4 MATHERR: Arithmetic Error Trap Status bit

bit 3 ADDRERR: Address Error Trap Status bit

bit 2 STKERR: Stack Error Trap Status bit

bit 1 OSCFAIL: Oscillator Failure Trap Status bit

bit 0 Unimplemented: Read as ‘0’

— — — — — — —

Lower Byte:

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0

— — — MATHERR ADDRERR STKERR OSCFAIL —

bit 7 bit 0

1 = Interrupt nesting is disabled 0 = Interrupt nesting is enabled

1 = Overflow trap has occurred 0 = Overflow trap has not occurred

1 = Address error trap has occurred 0 = Address error trap has not occurred

1 = Stack error trap has occurred 0 = Stack error trap has not occurred

1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC24FJ128GA FAMILY

REGISTER 6-4: INTCON2: INTERRUPT CONTROL REGISTER 2

Upper Byte:

R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0

ALTIVT DISI

bit 15 bit 8

Lower Byte:

bit 7 bit 0

bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit

1 = Use alternate vector table 0 = Use standard (default) vector table

bit 14 DISI: DISI Instruction Status bit

1 = DISI instruction is active 0 = DISI is not active

bit 13-5 Unimplemented: Read as ‘0’

bit 4 INT4EP: External Interrupt 4 Edge Detect Polarity Select bit

1 = Interrupt on negative edge 0 = Interrupt on positive edge

bit 3 INT3EP: External Interrupt 3 Edge Detect Polarity Select bit

1 = Interrupt on negative edge 0 = Interrupt on positive edge

bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit

1 = Interrupt on negative edge 0 = Interrupt on positive edge

bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit

1 = Interrupt on negative edge 0 = Interrupt on positive edge

bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit

1 = Interrupt on negative edge 0 = Interrupt on positive edge

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

— — — — — —

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — INT4EP INT3EP INT2EP INT1EP INT0EP

PIC24FJ128GA FAMILY

REGISTER 6-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0

Upper Byte:

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — AD1IF U1TXIF U1RXIF SPI1IF SPF1IF T3IF

bit 15 bit 8

Lower Byte:

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

T2IF OC2IF IC2IF

bit 7 bit 0

bit 15,14 Unimplemented: Read as ‘0’ bit 13 AD1IF: A/D Conversion Complete Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 12 U1TXIF: UART1 Transmitter Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 11 U1RXIF: UART1 Receiver Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 10 SPI1IF: SPI1 Event Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 9 SPF1IF: SPI1 Fault Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 8 T3IF: Timer3 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 7 T2IF: Timer2 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 6 OC2IF: Output Compare Channel 2 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 5 IC2IF: Input Capture Channel 2 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 4 Unimplemented: Read as ‘0’

bit 3 T1IF: Timer1 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 0 INT0IF: External Interrupt 0 Flag Status bit

= Interrupt request has occurred

0 = Interrupt request has not occurred

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

— T1IF OC1IF IC1IF INT0IF

PIC24FJ128GA FAMILY

REGISTER 6-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1

Upper Byte:

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0

U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF

bit 15 bit 8

Lower Byte:

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — INT1IF CNIF CMIF MI2C1IF SI2C1IF

bit 7 bit 0

bit 15 U2TXIF: UART2 Transmitter Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 14 U2RXIF: UART2 Receiver Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 13 INT2IF: External Interrupt 2 Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 12 T5IF: Timer5 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 11 T4IF: Timer4 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 10 OC4IF: Output Compare Channel 4 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 9 OC3IF: Output Compare Channel 3 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 8-5 Unimplemented: Read as ‘0’

bit 4 INT1IF: External Interrupt 1 Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 3 CNIF: Input Change Notification Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 2 CMIF: Comparator Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 1 MI2C1IF: Master I2C1 Event Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 0 SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

—

PIC24FJ128GA FAMILY

REGISTER 6-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2

Upper Byte:

U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0

— —PMPIF— — —OC5IF—

bit 15 bit 8

Lower Byte:

R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0

IC5IF IC4IF IC3IF

bit 7 bit 0

bit 15-14 Unimplemented: Read as ‘0’

bit 13 PMPIF: Parallel Master Port Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 12-10 Unimplemented: Read as ‘0’

bit 9 OC5IF: Output Compare Channel 5 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 8 Unimplemented: Read as ‘0’

bit 7 IC5IF: Input Capture Channel 5 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 6 IC4IF: Input Capture Channel 4 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 5 IC3IF: Input Capture Channel 3 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 4-2 Unimplemented: Read as ‘0’

bit 1 SPI2IF: SPI2 Event Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 0 SPI2IF: SPI2 Fault Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

— — — SPI2IF SPF2IF

PIC24FJ128GA FAMILY

REGISTER 6-8: IFS3: INTERRUPT FLAG STATUS REGISTER 3

Upper Byte:

U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0

—RTCIF— — — — — —

bit 15 bit 8

Lower Byte:

U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0

—INT4IFINT3IF— —MI2C2IFSI2C2IF —

bit 7 bit 0

bit 15 Unimplemented: Read as ‘0’

bit 14 RTCIF: Real-Time Clock/Calendar Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 13-7 Unimplemented: Read as ‘0’

bit 6 INT4IF: External Interrupt 4 Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 5 INT3IF: External Interrupt 3 Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 4-3 Unimplemented: Read as ‘0’

bit 2 MI2C2IF: Master I2C2 Event Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 1 SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 0 Unimplemented: Read as ‘0’

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC24FJ128GA FAMILY

REGISTER 6-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4

Upper Byte:

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

Lower Byte:

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0

— — — — CRCIF U2ERIF U1ERIF —

bit 7 bit 0

bit 15-4 Unimplemented: Read as ‘0’

bit 3 CRCIF: CRC Generator Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 2 U2ERIF: UART2 Error Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 1 U1ERIF: UART1 Error Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 0 Unimplemented: Read as ‘0’

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC24FJ128GA FAMILY

REGISTER 6-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0

Upper Byte:

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — AD1IE U1TXIE U1RXIE SPI1IE SPF1IE T3IE

bit 15 bit 8

Lower Byte:

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

T2IE OC2IE IC2IE

bit 7 bit 0

bit 15-14 Unimplemented: Read as ‘0’ bit 13 AD1IE: A/D Conversion Complete Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 12 U1TXIE: UART1 Transmitter Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 11 U1RXIE: UART1 Receiver Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 10 SPI1IE: SPI1 Transfer Complete Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 9 SPF1IE: SPI1 Fault Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 8 T3IE: Timer3 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 7 T2IE: Timer2 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 6 OC2IE: Output Compare Channel 2 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 5 IC2IE: Input Capture Channel 2 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 4 Unimplemented: Read as ‘0’

bit 3 T1IE: Timer1 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 0 INT0IE: External Interrupt 0 Enable bit

= Interrupt request enabled

0 = Interrupt request not enabled

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

— T1IE OC1IE IC1IE INT0IE

PIC24FJ128GA FAMILY

REGISTER 6-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1

Upper Byte:

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0

U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE

bit 15 bit 8

Lower Byte:

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — INT1IE CNIE CMIE MI2C1IE SI2C1IE

bit 7 bit 0

bit 15 U2TXIE: UART2 Transmitter Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 14 U2RXIE: UART2 Receiver Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 13 INT2IE: External Interrupt 2 Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 12 T5IE: Timer5 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 11 T4IE: Timer4 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 10 OC4IE: Output Compare Channel 4 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 9 OC3IE: Output Compare Channel 3 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 8-5 Unimplemented: Read as ‘0’

bit 4 INT1IE: External Interrupt 1 Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 3 CNIE: Input Change Notification Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 2 CMIE: Comparator Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 1 MI2C1IE: Master I2C1 Event Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 0 SI2C1IE: Slave I2C1 Event Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

—

PIC24FJ128GA FAMILY

REGISTER 6-12: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2

Upper Byte:

U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0

— —PMPIE— — —OC5IE—

bit 15 bit 8

Lower Byte:

R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0

IC5IE IC4IE IC3IE

bit 7 bit 0

bit 15-14 Unimplemented: Read as ‘0’

bit 13 PMPIE: Parallel Master Port Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 12-10 Unimplemented: Read as ‘0’

bit 9 OC5IE: Output Compare Channel 5 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 8 Unimplemented: Read as ‘0’

bit 7 IC5IE: Input Capture Channel 5 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 6 IC4IE: Input Capture Channel 4 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 5 IC3IE: Input Capture Channel 3 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 4-2 Unimplemented: Read as ‘0’

bit 1 SPI2IE: SPI2 Event Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 0 SPF2IE: SPI2 Fault Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

— — — SPI2IE SPF2IE

PIC24FJ128GA FAMILY

REGISTER 6-13: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3

Upper Byte:

U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0

—RTCIE— — — — — —

bit 15 bit 8

Lower Byte:

U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0

— INT4IE INT3IE — — MI2C2IE SI2C2IE —

bit 7 bit 0

bit 15 Unimplemented: Read as ‘0’

bit 14 RTCIE: Real-Time Clock/Calendar Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 13-7 Unimplemented: Read as ‘0’

bit 6 INT4IE: External Interrupt 4 Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 5 INT3IE: External Interrupt 3 Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 4-3 Unimplemented: Read as ‘0’

bit 2 MI2C2IE: Master I2C2 Event Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 1 SI2C2IE: Slave I2C2 Event Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 0 Unimplemented: Read as ‘0’

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC24FJ128GA FAMILY

REGISTER 6-14: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4

Upper Byte:

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

Lower Byte:

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0

— — — — CRCIE U2ERIE U1ERIE —

bit 7 bit 0

bit 15-4 Unimplemented: Read as ‘0’

bit 3 CRCIE: CRC Generator Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 2 U2ERIE: UART2 Error Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 1 U1ERIE: UART1 Error Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 0 Unimplemented: Read as ‘0’

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC24FJ128GA FAMILY

REGISTER 6-15: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0

Upper Byte:

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0

bit 15 bit 8

Lower Byte:

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0

bit 7 bit 0

bit 15 Unimplemented: Read as ‘0’

bit 14-12 T1IP2:T1IP0: Timer1 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 OC1IP2:OC1IP0: Output Compare Channel 1 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 IC1IP2:IC1IP0: Input Capture Channel 1 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 INT0IP2:INT0IP0: External Interrupt 0 Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC24FJ128GA FAMILY

REGISTER 6-16: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1

Upper Byte:

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0

bit 15 bit 8

Lower Byte:

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— IC2IP2 IC2IP1 IC2IP0 — — — —

bit 7 bit 0

bit 15 Unimplemented: Read as ‘0’

bit 14-12 T2IP2:T2IP0: Timer2 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 OC2IP2:OC2IP0: Output Compare Channel 2 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 IC2IP2:IC2IP0: Input Capture Channel 2 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3-0 Unimplemented: Read as ‘0’

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC24FJ128GA FAMILY

REGISTER 6-17: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2

Upper Byte:

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0

bit 15 bit 8

Lower Byte:

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— SPF1IP2 SPF1IP1 SPF1IP0 — T3IP2 T3IP1 T3IP0

bit 7 bit 0

bit 15 Unimplemented: Read as ‘0’

bit 14-12 U1RXIP2:U1RXIP0: UART1 Receiver Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 SPI1IP2:SPI1IP0: SPI1 Event Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 SPF1IP2:SPF1IP0: SPI1 Fault Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 T3IP2:T3IP0: Timer3 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC24FJ128GA FAMILY

REGISTER 6-18: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3

Upper Byte:

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

Lower Byte:

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0

bit 7 bit 0

bit 15-7 Unimplemented: Read as ‘0’

bit 6-4 AD1IP2:AD1IP0: A/D Conversion Complete Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 U1TXIP2:U1TXIP0: UART1 Transmitter Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC24FJ128GA FAMILY

REGISTER 6-19: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4

Upper Byte:

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0

bit 15 bit 8

Lower Byte:

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— MI2C1P2 MI2C1P1 MI2C1P0 — SI2C1P2 SI2C1P1 SI2C1P0

bit 7 bit 0

bit 15 Unimplemented: Read as ‘0’

bit 14-12 CNIP2:CNIP0: Input Change Notification Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 CMIP2:CMIP0: Comparator Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 MI2C1P2:MI2C1P0: Master I2C1 Event Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 SI2C1P2:SI2C1P0: Slave I2C1 Event Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC24FJ128GA FAMILY

REGISTER 6-20: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5

Upper Byte:

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

Lower Byte:

U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0

— — — — — INT1IP2 INT1IP1 INT1IP0

bit 7 bit 0

bit 15-3 Unimplemented: Read as ‘0’

bit 2-0 INT1IP2:INT1IP0: External Interrupt 1 Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC24FJ128GA FAMILY

REGISTER 6-21: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6

Upper Byte:

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— T4IP2 T4IP1 T4IP0 — OC4IP2 OC4IP1 OC4IP0

bit 15 bit 8

Lower Byte:

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— OC3IP2 OC3IP1 OC3IP0 — — — —

bit 7 bit 0

bit 15 Unimplemented: Read as ‘0’

bit 14-12 T4IP2:T4IP0: Timer4 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 OC4IP2:OC4IP0: Output Compare Channel 4 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 OC3IP2:OC3IP0: Output Compare Channel 3 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3-0 Unimplemented: Read as ‘0’

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC24FJ128GA FAMILY

REGISTER 6-22: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7

Upper Byte:

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0

bit 15 bit 8

Lower Byte:

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T51P0

bit 7 bit 0

bit 15 Unimplemented: Read as ‘0’

bit 14-12 U2TXIP2:U2TXIP0: UART2 Transmitter Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 U2RXIP2:U2RXIP0: UART2 Receiver Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 INT2IP2:INT2IP0: External Interrupt 2 Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 T5IP2:T5IP0: Timer5 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC24FJ128GA FAMILY

REGISTER 6-23: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8

Upper Byte:

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

Lower Byte:

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— SPI2IP2 SPI2IP1 SPI2IP0 — SPF2IP2 SPF2IP1 SPF2IP0

bit 7 bit 0

bit 15-7 Unimplemented: Read as ‘0’

bit 6-4 SPI2IP2:SPI2IP0: SPI2 Event Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 SPF2IP2:SPF2IP0: SPI2 Fault Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC24FJ128GA FAMILY

REGISTER 6-24: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9

Upper Byte:

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— IC5IP2 IC5IP1 IC5IP0 — IC4IP2 IC4IP1 IC4IP0

bit 15 bit 8

Lower Byte:

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— IC3IP2 IC3IP1 IC3IP0 — — — —

bit 7 bit 0

bit 15 Unimplemented: Read as ‘0’

bit 14-12 IC5IP2:IC5IP0: Input Capture Channel 5 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 IC4IP2:IC4IP0: Input Capture Channel 4 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 IC3IP2:IC3IP0: Input Capture Channel 3 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3-0 Unimplemented: Read as ‘0’

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC24FJ128GA FAMILY

REGISTER 6-25: IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10

Upper Byte:

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

Lower Byte:

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— OC5IP2 OC5IP1 OC5IP0 — — — —

bit 7 bit 0

bit 15-7 Unimplemented: Read as ‘0’

bit 6-4 OC5IP2:OC5IP0: Output Compare Channel 5 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3-0 Unimplemented: Read as ‘0’

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

REGISTER 6-26: IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11

Upper Byte:

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

Lower Byte:

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— PMPIP2 PMPIP1 PMPIP0 — — — —

bit 7 bit 0

bit 15-7 Unimplemented: Read as ‘0’

bit 6-4 PMPIP2:PMPIP0: Parallel Master Port Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3-0 Unimplemented: Read as ‘0’

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC24FJ128GA FAMILY

REGISTER 6-27: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12

Upper Byte:

U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0

— — — — — MI2C2P2 MI2C2P1 MI2C2P0

bit 15 bit 8

Lower Byte:

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— SI2C2P2 SI2C2P1 SI2C2P0 — — — —

bit 7 bit 0

bit 15-11 Unimplemented: Read as ‘0’

bit 10-8 MI2C2P2:MI2C2P0: Master I2C2 Event Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 SI2C2P2:SI2C2P0: Slave I2C2 Event Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3-0 Unimplemented: Read as ‘0’

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC24FJ128GA FAMILY

REGISTER 6-28: IPC13: INTERRUPT PRIORITY CONTROL REGISTER 13

Upper Byte:

U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0

— — — — — INT4IP2 INT4IP1 INT4IP0

bit 15 bit 8

Lower Byte:

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— INT3IP2 INT3IP1 INT3IP0 — —

PIC24FJ128GA FAMILY

REGISTER 6-29: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15

Upper Byte:

U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0

— — — — — RTCIP2 RTCIP1 RTCIP0

bit 15 bit 8

Lower Byte:

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 7 bit 0

bit 15-11 Unimplemented: Read as ‘0’

bit 10-8 RTCIP2:RTCIP0: Real-Time Clock/Calendar Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 7-0 Unimplemented: Read as ‘0’

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC24FJ128GA FAMILY

REGISTER 6-30: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16

Upper Byte:

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— CRCIP2 CRCIP1 CRCIP0 — U2ERIP2 U2ERIP1 U2ERIP0

bit 15 bit 8

Lower Byte:

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— U1ERIP2 U1ERIP1 U1ERIP0 — — — —

bit 7 bit 0

bit 15 Unimplemented: Read as ‘0’

bit 14-12 CRCIP2:CRCIP0: CRC Generator Error Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 U2ERIP2:U2ERIP0: UART2 Error Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 U1ERIP2:U1ERIP0: UART1 Error Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3-0 Unimplemented: Read as ‘0’

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC24FJ128GA FAMILY

6.4 Interrupt Setup Procedures

6.4.1 INITIALIZATION

To configure an interrupt source:

1. Set the NSTDIS Control bit (INTCON1<15>) if nested interrupts are not desired.

2. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx Control register. The priority level will depend on the specific application and type of interrupt source. If multiple priority levels are not desired, the IPCx register control bits for all enabled interrupt sources may be programmed to the same non-zero value.

Note: At a device Reset, the IPC registers are

initialized, such that all user interrupt sources are assigned to priority level 4.

3. Clear the interrupt flag status bit associated with the peripheral in the associated IFSx Status register.

4. Enable the interrupt source by setting the interrupt enable control bit associated with the source in the appropriate IECx Control register.

6.4.2 INTERRUPT SERVICE ROUTINE

The method that is used to declare an ISR and initialize the IVT with the correct vector address will depend on the programming language (i.e., ‘C’ or assembler) and the language development toolsuite that is used to develop the application. In general, the user must clear the interrupt flag in the appropriate IFSx register for the source of interrupt that the ISR handles. Otherwise, the ISR will be re-entered immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level.

6.4.3 TRAP SERVICE ROUTINE

A Trap Service Routine (TSR) is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR.

6.4.4 INTERRUPT DISABLE

All user interrupts can be disabled using the following procedure:

1. Push the current SR value onto the software stack using the PUSH instruction.

2. Force the CPU to priority level 7 by inclusive ORing the value OEh with SRL.

To enable user interrupts, the POP instruction may be used to restore the previous SR value.

Note that only user interrupts with a priority level of 7 or less can be disabled. Trap sources (level 8-15) cannot be disabled.

The DISI instruction provides a convenient way to disable interrupts of priority levels 1-6 for a fixed period of time. Level 7 interrupt sources are not disabled by the DISI instruction.

PIC24FJ128GA FAMILY

NOTES:

PIC24FJ128GA FAMILY

7.0 OSCILLATOR CONFIGURATION

Note: This data sheet summarizes the features

of this group of PIC24FJ devices. It is not intended to be a comprehensive reference source.

The oscillator system for PIC24FJ128GA family devices has the following features:

• A total of four external and internal oscillator options

as clock sources, providing 11 different clock modes

• On-chip 4x PLL to boost internal operating frequency on select internal and external oscillator sources

• Software-controllable switching between various clock sources

• Software-controllable postscaler for selective clocking of CPU for system power savings

• A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown

A simplified diagram of the oscillator system is shown in Figure 7-1.

FIGURE 7-1: PIC24FJ128GA FAMILY CLOCK DIAGRAM

PIC24FJ128GA Family

Secondary Oscillator

SOSCO

SOSCEN

SOSCI

Enable Oscillator

7.1 CPU Clocking Scheme

The system clock source can be provided by one of four sources:

• Primary Oscillator (POSC) on the OSC1 and OSC2 pins

• Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins

• Fast Internal RC (FRC) Oscillator

• Low-Power Internal RC (LPRC) Oscillator

Clock Source Option

The primary oscillator and FRC sources have the option of using the internal 4x PLL. The frequency of the FRC clock source can optionally be reduced by the programmable clock divider. The selected clock source generates the processor and peripheral clock sources.

The processor clock source is divided by two to produce the internal instruction cycle clock, F document, the instruction cycle clock is also denoted by F

OSC/2. The internal instruction cycle clock, FOSC/2,

can be provided on the OSC2 I/O pin for some operating modes of the primary oscillator.

CY. In this

PIC24FJ128GA FAMILY

7.2 Oscillator Configuration

The oscillator source (and operating mode) that is used at a device Power-on Reset event is selected using Configuration bit settings. The oscillator Configuration bit settings are located in the Configuration registers in the program memory (refer to Section 23.1 “Configuration Bits” for further details.) The Primary Oscillator Configuration bits, POSCMD1:POSCMD0 (Configuration Word 2<1:0>), and the Initial Oscillator Select Configuration bits, FNOSC2:FNOSC0 (Configuration Word 2<10:8>), select the oscillator source that is used at a Power-on Reset. The FRC primary oscillator with postscaler (FRCDIV) is the default (unprogrammed) selection.

The secondary oscillator, or one of the internal oscillators, may be chosen by programming these bit locations.

The Configuration bits allow users to choose between the various clock modes, shown in Table 7-1.

7.2.1 CLOCK SWITCHING MODE CONFIGURATION BITS

The FCKSM Configuration bits (Configuration Word 2<7:6>) are used to jointly configure device clock switching and the Fail-Safe Clock Monitor (FSCM). Clock switching is enabled only when FCKSM1 is programmed (‘0’). The FSCM is enabled only when FCKSM1:FCKSM0 are both programmed (‘00’).

TABLE 7-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION

Oscillator Mode Oscillator Source

Fast RC Oscillator with Postscaler (FRCDIV)

(Reserved) Internal 00 110 1

Low-Power RC Oscillator (LPRC) Internal 00 101 1

Secondary (Timer1) Oscillator (SOSC)

Primary Oscillator (HS) with PLL Module (HSPLL)

Primary Oscillator (XT) with PLL Module (ECPLL)

Primary Oscillator (EC) with PLL Module (XTPLL)

Primary Oscillator (HS) Primary 10 010

Primary Oscillator (XT) Primary 01 010

Primary Oscillator (EC) Primary 00 010

Fast RC Oscillator with PLL Module (FRCPLL)

Fast RC Oscillator (FRC) Internal 00 000 1

Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit.

2: This is the default oscillator mode for an unprogrammed (erased) device.

Internal 00 111 1, 2

Secondary 00 100 1

Primary 10 011

Primary 01 011

Primary 00 011

Internal 00 001 1

POSCMD1:

POSCMD0

FNOSC2:

FNOSC0

Note

7.3 Control Registers

The operation of the oscillator is controlled by three Special Function Registers:

• OSCCON

•CLKDIV

•OSCTUN

The OSCCON register (Register 7-1) is the main control register for the oscillator. It controls clock source switching, and allows the monitoring of clock sources.

The Clock Divider register (Register 7-2) controls the features associated with Doze mode, as well as the postscaler for the FRC oscillator.

The FRC Oscillator Tune register (Register 7-3) allows the user to fine tune the FRC oscillator over a range of approximately ±12%. Each bit increment or decrement changes the factory calibrated frequency of the FRC oscillator by a fixed amount.

PIC24FJ128GA FAMILY

REGISTER 7-1: OSCCON: OSCILLATOR CONTROL REGISTER

Upper Byte:

U-0 R-0 R-0 R-0 U-0 R/W-x

— COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0

bit 15 bit 8

(1)

R/W-x

(1)

R/W-x

(1)

Lower Byte:

R/SO-0 U-0 R-0

CLKLOCK

bit 7 bit 0

bit 15 Unimplemented: Read as ‘0’ bit 14-12 COSC2:COSC0: Current Oscillator Selection bits

111 = Fast RC Oscillator with Postscaler (FRCDIV) 110 = Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with postscaler and PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC)

bit 11 Unimplemented: Read as ‘0’ bit 10-8 NOSC2:NOSC0: New Oscillator Selection bits

bit 7 CLKLOCK: Clock Selection Lock Enabled bit

If FSCM is enabled (FCKSM1 =

1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit

If FSCM is disabled (FCKSM1 = 0):

Clock and PLL selections are never locked and may be modified by setting the OSWEN bit. bit 6 Unimplemented: Read as ‘0’ bit 5 LOCK: PLL Lock Status bit

1 = PLL module is in lock or PLL module start-up timer is satisfied

0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled

bit 4 Unimplemented: Read as ‘0’ bit 3 CF: Clock Fail Detect bit

1 = FSCM has detected a clock failure

0 = No clock failure has been detected

bit 2 Unimplemented: Read as ‘0’ bit 1 SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit

1 = Enable secondary oscillator

0 = Disable secondary oscillator

bit 0 OSWEN: Oscillator Switch Enable bit

1 = Initiate an oscillator switch to clock source specified by NOSC2:NOSC0 bits

0 = Oscillator switch is complete

Note 1: Reset values for these bits are determined by the FNOSC Configuration bits.

2: Also resets to ‘0’ during any valid clock switch, or whenever a non-PLL Clock mode is selected.

—LOCK—CF— SOSCEN OSWEN

1):

(2)

U-0 R/CO-0 U-0 R/W-0 R/W-0

Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit CO = Clear-Only bit SO = Set-Only bit

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC24FJ128GA FAMILY

REGISTER 7-2: CLKDIV: CLOCK DIVIDER REGISTER

Upper Byte:

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1

ROI DOZE2 DOZE1 DOZE0 DOZEN

bit 15 bit 8

Lower Byte:

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 7 bit 0

bit 15 ROI: Recover on Interrupt bit

1 = Interrupts clear the DOZEN bit and reset the CPU peripheral clock ratio to 1:1 0 = Interrupts have no effect on the DOZEN bit

bit 14-12 DOZE2:DOZE0: CPU Peripheral Clock Ratio Select bits

111 = 1:128 110 = 1:64 101 = 1:32 100 = 1:16 011 = 1:8 010 = 1:4 001 = 1:2 000 = 1:1

bit 11 DOZEN: DOZE Enable bit

1 = DOZE2:DOZE0 bits specify the CPU peripheral clock ratio 0 = CPU peripheral clock ratio set to 1:1

Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs.

bit 10-8 RCDIV2:RCDIV0: FRC Postscaler Select bits

111 = 31.25 kHz (divide by 256) 110 = 125 kHz (divide by 64) 101 = 250 kHz (divide by 32) 100 = 500 kHz (divide by 16) 011 = 1 MHz (divide by 8) 010 = 2 MHz (divide by 4) 001 = 4 MHz (divide by 2) 000 = 8 MHz (divide by 1)

bit 7-0 Unimplemented: Read as ‘0’

(1)

RCDIV2 RCDIV1 RCDIV0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC24FJ128GA FAMILY

REGISTER 7-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER

Upper Byte:

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

Lower Byte:

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0

bit 7 bit 0

bit 15-6 Unimplemented: Read as ‘0’

bit 5-0 TUN5:TUN0: FRC Oscillator Tuning bits

011111 = Maximum frequency deviation

011110 =

•

000001 =

000000 = Center frequency, oscillator is running at factory calibrated frequency

111111 =

•

100001 =

100000 = Minimum frequency deviation

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

7.4 Clock Switching Operation

With few limitations, applications are free to switch between any of the four clock sources (POSC, SOSC, FRC and LPRC) under software control and at any time. To limit the possible side effects that could result from this flexibility, PIC24 devices have a safeguard lock built into the switching process.

Note: Primary Oscillator mode has three

different submodes (XT, HS and EC) which are determined by the POSCMD Configuration bits. While an application can switch to and from Primary Oscillator mode in software, it cannot switch between the different primary submodes without reprogramming the device.

7.4.1 ENABLING CLOCK SWITCHING

To enable clock switching, the FCKSM1 Configuration bit in the Configuration register must be programmed to ‘0’. (Refer to Section 23.1 “Configuration Bits” for further details.) If the FCKSM1 Configuration bit is unprogrammed (‘1’), the clock switching function and Fail-Safe Clock Monitor function are disabled. This is the default setting.

The NOSC control bits (OSCCON<10:8>) do not control the clock selection when clock switching is disabled. However, the COSC bits (OSCCON<14:12>) will reflect the clock source selected by the FNOSC Configuration bits.

The OSWEN control bit (OSCCON<0>) has no effect when clock switching is disabled. It is held at ‘0’ at all times.

PIC24FJ128GA FAMILY

7.4.2 OSCILLATOR SWITCHING SEQUENCE

At a minimum, performing a clock switch requires this basic sequence:

1. If desired, read the COSC bits

(OSCCON<14:12>), to determine the current oscillator source.

2. Perform the unlock sequence to allow a write to

the OSCCON register high byte.

3. Write the appropriate value to the NOSC control

bits (OSCCON<10:8>) for the new oscillator source.

4. Perform the unlock sequence to allow a write to

the OSCCON register low byte.

5. Set the OSWEN bit to initiate the oscillator

switch.

Once the basic sequence is completed, the system clock hardware responds automatically as follows:

1. The clock switching hardware compares the

COSC status bits with the new value of the NOSC control bits. If they are the same, then the clock switch is a redundant operation. In this case, the OSWEN bit is cleared automatically and the clock switch is aborted.

2. If a valid clock switch has been initiated, the

LOCK (OSCCON<5>) and CF (OSCCON<3>) status bits are cleared.

3. The new oscillator is turned on by the hardware

if it is not currently running. If a crystal oscillator must be turned on, the hardware will wait until the OST expires. If the new source is using the PLL, then the hardware waits until a PLL lock is detected (LOCK = 1).

4. The hardware waits for 10 clock cycles from the

new clock source and then performs the clock switch.

5. The hardware clears the OSWEN bit to indicate a

successful clock transition. In addition, the NOSC bit values are transferred to the COSC status bits.

6. The old clock source is turned off at this time,

with the exception of LPRC (if WDT or FSCM are enabled) or SOSC (if SOSCEN remains set).

Note 1: The processor will continue to execute

code throughout the clock switching sequence. Timing sensitive code should not be executed during this time.

2: Direct clock switches between any

Primary Oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes.

A recommended code sequence for a clock switch includes the following:

1. Disable interrupts during the OSCCON register unlock and write sequence.

2. Execute the unlock sequence for the OSCCON high byte, by writing 78h and 9Ah to OSCCON<15:8> in two back-to-back instructions.

3. Write new oscillator source to the NOSC control bits in the instruction immediately following the unlock sequence.

4. Execute the unlock sequence for the OSCCON low byte by writing 46h and 57h to OSCCON<7:0> in two back-to-back instructions.

5. Set the OSWEN bit in the instruction immediately following the unlock sequence.

6. Continue to execute code that is not clock sensitive (optional).

7. Invoke an appropriate amount of software delay (cycle counting) to allow the selected oscillator and/or PLL to start and stabilize.

8. Check to see if OSWEN is ‘0’. If it is, the switch was successful. If OSWEN is still set, then check the LOCK bit to determine cause of failure.

The core sequence for unlocking the OSCCON register and initiating a clock switch is shown in Example 7-1.

EXAMPLE 7-1: BASIC CODE SEQUENCE

FOR CLOCK SWITCHING

;Place the new oscillator selection in W0 ;OSCCONH (high byte) Unlock Sequence MOV #OSCCONH, w1 MOV #0x78, w2 MOV #0x9A, w3 MOV.b w2, [w1] MOV.b w3, [w1] ;Set new oscillator selection MOV.b WREG, OSCCONH ;OSCCONL (low byte) unlock sequence MOV #OSCCONL, w1 MOV.b #0x01, w0 MOV #0x46, w2 MOV #0x57, w3 MOV.b w2, [w1] MOV.b w3, [w1] ;Start oscillator switch operation MOV.b w0, [w1]

PIC24FJ128GA FAMILY

8.0 POWER-SAVING FEATURES

Note: This data sheet summarizes the features

of this group of PIC24FJ devices. It is not intended to be a comprehensive reference source.

The PIC24FJ128GA family of devices provide the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. All PIC24F devices manage power consumption in four different ways:

• Clock frequency

• Instruction-based Sleep and Idle modes

• Software-controlled Doze mode

• Selective peripheral control in software

Combinations of these methods can be used to selectively tailor an application’s power consumption, while still maintaining critical application features, such as timing sensitive communications.

8.1 Clock Frequency and Clock Switching

PIC24F devices allow for a wide range of clock frequencies to be selected under application control. If the system clock configuration is not locked, users can choose low-power or high-precision oscillators by simply changing the NOSC Configuration bits. The process of changing a system clock during operation, as well as limitations to the process, are discussed in more detail in

Section 7.0 “Oscillator Configuration”.

8.2 Instruction-Based Power-Saving Modes

PIC24F devices have two special power-saving modes that are entered through the execution of a special PWRSAV instruction. Sleep mode stops clock operation and halts all code execution; Idle mode halts the CPU and code execution, but allows peripheral modules to continue operation. The assembly syntax of the PWRSAV instruction is shown in Example 8-1.

Note: SLEEP_MODE and IDLE_MODE are con-

stants defined in the assembler include file for the selected device.

Sleep and Idle modes can be exited as a result of an enabled interrupt, WDT time-out or a device Reset. When the device exits these modes, it is said to “wake-up”.

8.2.1 SLEEP MODE

Sleep mode has these features:

• The system clock source is shut down. If an on-chip oscillator is used, it is turned off.

• The device current consumption will be reduced to a minimum provided that no I/O pin is sourcing current.

• The Fail-Safe Clock Monitor does not operate during Sleep mode since the system clock source is disabled.

• The LPRC clock will continue to run in Sleep mode if the WDT is enabled.

• The WDT, if enabled, is automatically cleared prior to entering Sleep mode.

• Some device features or peripherals may continue to operate in Sleep mode. This includes items such as the input change notification on the I/O ports, or peripherals that use an external clock input. Any peripheral that requires the system clock source for its operation will be disabled in Sleep mode.

The device will wake-up from Sleep mode on any of the these events:

• On any interrupt source that is individually enabled

• On any form of device Reset

• On a WDT time-out

On wake-up from Sleep, the processor will restart with the same clock source that was active when Sleep mode was entered.

EXAMPLE 8-1: PWRSAV INSTRUCTION SYNTAX

PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode

PIC24FJ128GA FAMILY

8.2.2 IDLE MODE

Idle mode has these features:

• The CPU will stop executing instructions.

• The WDT is automatically cleared.

• The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 8.4 “Selective Peripheral Module Control”).

• If the WDT or FSCM is enabled, the LPRC will also remain active.

The device will wake from Idle mode on any of these events:

• Any interrupt that is individually enabled.

• Any device Reset.

• A WDT time-out.

On wake-up from Idle, the clock is re-applied to the CPU and instruction execution begins immediately, starting with the instruction following the PWRSAV instruction, or the first instruction in the ISR.

8.2.3 INTERRUPTS COINCIDENT WITH

POWER SAVE INSTRUCTIONS

Any interrupt that coincides with the execution of a PWRSAV instruction will be held off until entry into Sleep or Idle mode has completed. The device will then wake-up from Sleep or Idle mode.

8.3 Doze Mode

Generally, changing clock speed and invoking one of the power-saving modes are the preferred strategies for reducing power consumption. There may be circumstances, however, where this is not practical. For example, it may be necessary for an application to maintain uninterrupted synchronous communication, even while it is doing nothing else. Reducing system clock speed may introduce communication errors, while using a power-saving mode may stop communications completely.

Doze mode is a simple and effective alternative method to reduce power consumption while the device is still executing code. In this mode, the system clock continues to operate from the same source and at the same speed. Peripheral modules continue to be clocked at the same speed, while the CPU clock speed is reduced. Synchronization between the two clock domains is maintained, allowing the peripherals to access the SFRs while the CPU executes code at a slower rate.

Doze mode is enabled by setting the DOZEN bit (CLKDIV<11>). The ratio between peripheral and core clock speed is determined by the DOZE2:DOZE0 bits (CLKDIV<14:12>). There are eight possible configurations, from 1:1 to 1:256, with 1:1 being the default.

It is also possible to use Doze mode to selectively reduce power consumption in event driven applications. This allows clock sensitive functions, such as synchronous communications, to continue without interruption while the CPU idles, waiting for something to invoke an interrupt routine. Enabling the automatic return to full-speed CPU operation on interrupts is enabled by setting the ROI bit (CLKDIV<15>). By default, interrupt events have no effect on Doze mode operation.

8.4 Selective Peripheral Module Control

Idle and Doze modes allow users to substantially reduce power consumption by slowing or stopping the CPU clock. Even so, peripheral modules still remain clocked and thus consume power. There may be cases where the application needs what these modes do not provide: the allocation of power resources to CPU processing with minimal power consumption from the peripherals.

PIC24F devices address this requirement by allowing peripheral modules to be selectively disabled, reducing or eliminating their power consumption. This can be done with two control bits:

• The Peripheral Enable bit, generically named

“XXXEN”, located in the module’s main control SFR.

• The Peripheral Module Disable (PMD) bit, generi-

cally named “XXXMD”, located in one of the PMD control registers.

Both bits have similar functions in enabling or disabling its associated module. Setting the PMD bit for a module disables all clock sources to that module, reducing its power consumption to an absolute minimum. In this state, the control and status registers associated with the peripheral will also be disabled, so writes to those registers will have no effect and read values will be invalid. Many peripheral modules have a corresponding PMD bit.

In contrast, disabling a module by clearing its XXXEN bit disables its functionality, but leaves its registers available to be read and written to. Power consumption is reduced, but not by as much as the PMD bit does. Most peripheral modules have an enable bit; exceptions include Capture, Compare and RTCC.

To achieve more selective power savings, peripheral modules can also be selectively disabled when the device enters Idle mode. This is done through the control bit of the generic name format “XXXIDL”. By default, all modules that can operate during Idle mode will do so. Using the disable on Idle feature allows further reduction of power consumption during Idle mode, enhancing power savings for extremely critical power applications.

MICROCHIP PIC24FJ128GA Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

High-Performance CPU:

Special Microcontroller Features:

Analog Features:

Peripheral Features:

Pin Diagrams

Pin Diagrams (Continued)

Pin Diagrams (Continued))

Table of Contents

Most Current Data Sheet

Errata

Customer Notification System

1.0 DEVICE OVERVIEW

1.1 Core Features

1.1.1 16-BIT ARCHITECTURE

1.1.2 POWER-SAVING TECHNOLOGY

1.1.4 EASY MIGRATION

1.2 Other Special Features

1.3 Details on Individual Family Members

TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ128GA FAMILY

FIGURE 1-1: PIC24FJ128GA FAMILY GENERAL BLOCK DIAGRAM

2.0 CPU

2.1 Programmer’s Model

FIGURE 2-1: PIC24 CPU CORE BLOCK DIAGRAM

TABLE 2-1: CPU CORE REGISTERS

FIGURE 2-2: PROGRAMMER’S MODEL

2.2 CPU Control Registers

REGISTER 2-1: SR: CPU STATUS REGISTER

REGISTER 2-2: CORCON: CORE CONTROL REGISTER

2.3 Arithmetic Logic Unit (ALU)

2.3.1 MULTIPLIER

2.3.2 DIVIDER

2.3.3 MULTI-BIT SHIFT SUPPORT

TABLE 2-2: INSTRUCTIONS THAT USE THE SINGLE AND MULTI-BIT SHIFT OPERATION

3.0 MEMORY ORGANIZATION

3.1 Program Address Space

3.1.1 PROGRAM MEMORY ORGANIZATION

3.1.2 HARD MEMORY VECTORS

3.1.3 FLASH CONFIGURATION WORDS

FIGURE 3-2: PROGRAM MEMORY ORGANIZATION

3.2 Data Address Space

3.2.1 DATA SPACE WIDTH

FIGURE 3-3: DATA SPACE MEMORY MAP FOR PIC24FJ128GA FAMILY DEVICES

3.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT

3.2.3 NEAR DATA SPACE

3.2.4 SFR SPACE

TABLE 3-2: IMPLEMENTED REGIONS OF SFR DATA SPACE

TABLE 3-5: ICN REGISTER MAP

TABLE 3-6: TIMER REGISTER MAP

TABLE 3-7: INPUT CAPTURE REGISTER MAP

TABLE 3-8: OUTPUT COMPARE REGISTER MAP

TABLE 3-9: I2C1 REGISTER MAP

TABLE 3-10: I2C2 REGISTER MAP

TABLE 3-11: UART1 REGISTER MAP

TABLE 3-12: UART2 REGISTER MAP

TABLE 3-13: SPI1 REGISTER MAP

TABLE 3-15: ADC REGISTER MAP

TABLE 3-16: PORTA REGISTER MAP

TABLE 3-17: PORTB REGISTER MAP

TABLE 3-18: PORTC REGISTER MAP

TABLE 3-19: PORTD REGISTER MAP

TABLE 3-20: PORTE REGISTER MAP

TABLE 3-21: PORTF REGISTER MAP

TABLE 3-22: PORTG REGISTER MAP

TABLE 3-23: PAD CONFIGURATION MAP

TABLE 3-24: PARALLEL MASTER/SLAVE PORT REGISTER MAP

TABLE 3-25: REAL-TIME CLOCK AND CALENDAR REGISTER MAP

TABLE 3-27: CRC REGISTER MAP

TABLE 3-28: SYSTEM REGISTER MAP

TABLE 3-29: NVM REGISTER MAP

TABLE 3-30: PMD REGISTER MAP

3.2.5 SOFTWARE STACK

FIGURE 3-4: CALL STACK FRAME

3.3 Interfacing Program and Data Memory Spaces

3.3.1 ADDRESSING PROGRAM SPACE

TABLE 3-31: PROGRAM SPACE ADDRESS CONSTRUCTION

FIGURE 3-5: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION