MICROCHIP PIC18FXX8 DATA SHEET
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PIC18FXX8
Data Sheet
28/40-Pin High-Performance,
Enhanced Flash Microcontrollers
with CAN Module
2004 Microchip Technology Inc. DS41159D
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Millennium Copyright Act. If suc h a c t s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
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Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K
EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL,
SmartSensor and The Embedded Control Solutions Company
are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Migratable Memory, MPASM,
MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,
PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, rfLAB, rfPICDEM, Select Mode, Sm art Serial,
SmartTel and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
®
8-bit MCUs, KEELOQ
®
code hopping
DS41159D-page ii 2004 Microchip Technology Inc.
PIC18FXX8
28/40-Pin High-Performance, Enhanced Flash
Microcontrollers with CAN
High-Performance RISC CPU:
• Linear program memory addressing up to
2Mbytes
• Linear data memory addressing to 4 Kbytes
• Up to 10 MIPS operation
• DC – 40 MHz clock input
• 4 MHz-10 MHz oscillator/clock inp ut with
PLL active
• 16-bit wide instructions, 8-bit wide data path
• Priority levels for interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
Peripheral Features:
• High current sink/source 25 mA/25 mA
• Three external interrupt pins
•Timer0 module: 8-bit/16-bit timer/counter with
8-bit programmable prescaler
•Timer1 module: 16-bit timer/counter
•Timer2 module: 8-bit timer/counter with 8-bit
period register (time base for PWM)
•Timer3 module: 16-bit timer/counter
• Secondary osc il lat or c loc k option – Timer1/T i me r3
• Capture/Compare/PWM (CCP) modules;
CCP pins can be configured as:
- Capture input: 16-bit, max resolution 6.25 ns
- Compare: 16-bit, max resolution 100 ns (T
- PWM output: PWM resolution is 1 to 10-bit
Max. PWM freq. @:8-bit resolution = 156 kHz
10-bit resolution = 39 kHz
• Enhanced CCP modu le which has al l the features
of the standard CCP module, but also has the
following features for advanced motor control:
- 1, 2 or 4 PWM outputs
- Selectable PWM polar ity
- Programmable PWM dead time
• Master Synchronous Serial Port (MSSP) with two
modes of operation:
- 3-wire SPI™ (Supports all 4 SPI modes)
2
-I
C™ Master and Slave mode
• Addressable USART module:
- Supports interrupt-on-address bit
CY)
Advanced Analog Features:
• 10-bit, up to 8-channel Analog-to-Digital Converter
module (A/D) with:
- Conversion available during Sleep
- Up to 8 channels available
• Analog Comparator module:
- Programmable input and output multiplexing
• Comparator Voltage Reference module
• Programmable Low-Voltage Detection (LVD) module:
- Supports interrupt-on -Low -Voltage Detection
• Programmable Brown-out Reset (BOR)
CAN bus Module Features:
• Complies with ISO CAN Conformance Test
• Message bit rates up to 1 Mbps
• Conforms to CAN 2.0B Active Spec with:
- 29-bit Identifier Fields
- 8-byte message length
- 3 Transmit Message Buffers with prioritizatio n
- 2 Receive Message Buffers
- 6 full, 29-bit Acceptance Filters
- Prioritization of Acceptance Filters
- Multiple Receive Buffers for High Priority
Messages to prevent loss due to overflow
- Advanced Error Management Features
Special Microcontroller Features:
• Power-on Reset (POR), Power-up Tim er (PWR T)
and Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator
• Programmable code protection
• Power-saving Sleep mode
• Selectable oscillator options, including:
- 4x Phase Lock Lo op (PLL) of primary osci ll at or
- Secondary Oscillator (32 kHz) clock input
• In-Circuit Serial ProgrammingTM (ICSPTM) via two pins
Flash Technology:
• Low-power, high-speed Enhanced Flas h tech nolog y
• Fully static design
• Wide operating voltage range (2.0V to 5.5V)
• Industrial and Extended temperature ranges
2004 Microchip Technology Inc. DS41159D-page 1
PIC18FXX8
Program Memory Data Memory
Device
Flash
(bytes)
# Single-Word
Instructions
SRAM
(bytes)
EEPROM
(bytes)
I/O
10-bit
A/D
(ch)
CCP/
ECCP
(PWM)
Comparators
PIC18F248 16K 8192 768 256 22 5 — 1/0 Y Y Y 1/3
PIC18F258 32K 16384 1536 256 22 5 — 1/0 Y Y Y 1/3
PIC18F448 16K 8192 768 256 33 8 2 1/1 Y Y Y 1/3
PIC18F458 32K 16384 1536 256 33 8 2 1/1 Y Y Y 1/3
Pin Diagrams
PDIP
MCLR/VPP
RA0/AN0/CVREF
RA1/AN1
RA2/AN2/V
RA3/AN3/V
RA5/AN4/SS
RE1/AN6/WR/C1OUT
RE2/AN7/CS
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC3/SCK/SCL
RD0/PSP0/C1IN+
RD1/PSP1/C1IN-
REF-
REF+
RA4/T0CKI
/LVDIN
RE0/AN5/RD
/C2OUT
VDD
VSS
OSC1/CLKI
RC1/T1OSI
RC2/CCP1
1
2
3
4
5
6
PIC18F458
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
PIC18F448
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RB7/PGD
RB6/PGC
RB5/PGM
RB4
RB3/CANRX
RB2/CANTX/INT2
RB1/INT1
RB0/INT0
DD
V
VSS
RD7/PSP7/P1D
RD6/PSP6/P1C
RD5/PSP5/P1B
RD4/PSP4/ECCP1/P1A
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3/C2INRD2/PSP2/C2IN+
SPI™
MSSP
Master
USART
2
C™
I
Timers
8/16-bit
PLCC
RA4/T0CKI
RA5/AN4/SS
RE1/AN6/WR/C1OUT
RE2/AN7/CS
OSC2/CLKO/RA6
RC0/T1OSO/T1CK1
/LVDIN
RE0/AN5/RD
/C2OUT
V
DD
VSS
OSC1/CLKI
NC
7
8
9
10
11
12
13
14
15
16
17
REF
REF-
RA2/AN2/V
RA3/AN3/VREF+
RA0/AN0/CV
RA1/AN1
PIC18F448
PIC18F458
20
21
18
19
RC2/CCP1
RC1/T1OSI
RC3/SCK/SCL
RD0/PSP0/C1IN+
RB4
RB7/PGD
NC
RB6/PGC
RB5/PGM
MCLR/VPP
NC
1
23456
22
23
RD1/PSP1/C1IN-
RD2/PSP2/C2IN+
43
44
24
25
RC4/SDI/SDA
RD3/PSP3/C2IN-
42
26
RC5/SDO
40
41
27
28
RC6/TX/CK
39
38
37
36
35
34
33
32
31
30
29
NC
RB3/CANRX
RB2/CANTX/INT2
RB1/INT1
RB0/INT0
VDD
SS
V
RD7/PSP7/P1D
RD6/PSP6/P1C
RD5/PSP5/P1B
RD4/PSP4/ECCP1/P1A
RC7/RX/DT
DS41159D-page 2 2004 Microchip Technology Inc.
Pin Diagrams (Continued)
TQFP
RC7/RX/DT
RD4/PSP4/ECCP1/P1A
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
RB0/INT0
RB1/INT1
RB2/CANTX/INT2
RB3/CANRX
V
VDD
PIC18FXX8
RC5/SDO
RC4/SDI/SDA
RD2/PSP2/C2IN+
RD1/PSP1/C1IN-
RC2/CCP1
RC1/T1OSI
RC6/TX/CK
RD3/PSP3/C2IN-
RD0/PSP0/C1IN+
38
39
40
41
42
43
44
1
2
3
4
SS
5
6
7
8
9
10
11
PIC18F448
PIC18F458
13
141516
12
17
18
RC3/SCK/SCL
35
36
37
21
20
19
NC
34
22
33
32
31
30
29
28
27
26
25
24
23
NC
RC0/T1OSO/T1CKI
OSC2/CLKO/RA6
OSC1/CLKI
SS
V
VDD
RE2/AN7/CS/C2OUT
RE1/AN6/WR
RE0//AN5/RD
RA5/AN4/SS/L VDIN
RA4/T0CKI
/C1OUT
SPDIP, SOIC
/VPP
MCLR
RA0/AN0/CVREF
RA1/AN1
RA2/AN2/V
RA3/AN3/V
RA5/AN4/SS
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC3/SCK/SCL
REF-
REF+
RA4/T0CKI
/LVDIN
V
OSC1/CLKI
RC1/T1OSI
RC2/CCP1
NC
NC
RB4
1
2
3
4
5
6
SS
7
8
9
10
11
12
13
14
/VPP
RB6/PGC
RB7/PGD
RB5/PGM
MCLR
PIC18F248
PIC18F258
+
REF
REF-
REF
RA1/AN1
RA3/AN3/V
RA2/AN2/V
RA0/AN0/CV
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RB7/PGD
RB6/PGC
RB5/PGM
RB4
RB3/CANRX
RB2/CANTX/INT2
RB1/INT1
RB0/INT0
V
DD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
2004 Microchip Technology Inc. DS41159D-page 3
PIC18FXX8
Table of Contents
1.0 Device Overview..........................................................................................................................................................................7
2.0 Oscillator Configurations............................................................................................................................................................ 17
3.0 Reset.......................................................................................................................................................................................... 25
4.0 Memory Organization.................................................................................................................................................................37
5.0 Data EEPROM Memory ......... ..................... ..................... ..................... ..................... ...............................................................59
6.0 Flash Program Memory............... ..................... ..................... ..................... ..................... ...........................................................65
7.0 8 x 8 Hardware Multiplier............................................................................................. ...............................................................75
8.0 Interrupts....................................................................................................................................................................................77
9.0 I/O Ports...................... ..................... ..................... ..................... ................................................................................................ 93
10.0 Parallel Slave Port................. ..................... ..................... .......................................... ...............................................................107
11.0 Timer0 Module ......................................................................................................................................................................... 109
12.0 Timer1 Module ......................................................................................................................................................................... 113
13.0 Timer2 Module ......................................................................................................................................................................... 117
14.0 Timer3 Module ......................................................................................................................................................................... 119
15.0 Capture/Compare/PWM (CCP) Modules .................................................................................................................................123
16.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 131
17.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 143
18.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USA RT ).............................................................. 183
19.0 CAN Module.............................................................................................................................................................................199
20.0 Compatible 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................241
21.0 Comparator Module.............................................................................. .. .... ......... .. .... .... .. .........................................................249
22.0 Comparator Voltage Reference Module........................................... .... .. .... .. ....... .... .. .... .. ....... .... .. ............................................ 255
23.0 Low-Voltage Detect.................................................................................................................................................................. 259
24.0 Special Features of the CPU.............. ..................... ..................... ............................................................................................ 265
25.0 Instruction Set Summary.......................................................................................................................................................... 281
26.0 Development Support...............................................................................................................................................................323
27.0 Electrical Characteristics.......................................................................................................................................................... 329
28.0 DC and AC Characteristics Graphs and Tables.......................................................................................................................361
29.0 Packaging Informa tio n..... ..................... .......................................... ..................... ..................................................................... 377
Appendix A: Data Sheet Revision History.......................................................................................................................................... 385
Appendix B: Device Differences.........................................................................................................................................................385
Appendix C: Device Migrations................................................. .. .... .. ....... .... .. .. .... .. ......... .. .. .... .. .........................................................386
Appendix D: Migrating From Other PICmicro
Index .................................................................................................................................................................................................. 387
On-Line Support........................................................................ .. .... .. ......... .... .. .... ......... .. ................................................................... 397
Systems Information and Upgrade Hot Line...................................................................................................................................... 397
Reader Response.............................................................................................................................................................................. 398
PIC18FXX8 Product Identification System......................................................................................................................................... 399
®
Devices ..................................................................................................................... 386
DS41159D-page 4 2004 Microchip Technology Inc.
PIC18FXX8
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welcome your feedback.
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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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2004 Microchip Technology Inc. DS41159D-page 5
PIC18FXX8
NOTES:
DS41159D-page 6 2004 Microchip Technology Inc.
PIC18FXX8
1.0 DEVICE OVERVIEW
This documen t conta i ns dev ic e spec if i c in for m at i on fo r
the following devices:
• PIC18F248
• PIC18F258
•PIC18F448
•PIC18F458
These devices are available in 28-pin, 40-pin and
44-pin packages. They are differentiated from each
other in four ways:
1. PIC18FX58 devices have twice the Flash
program memory and data RAM of PIC18FX48
devices (32 Kbytes and 1536 bytes vs.
16 Kbytes and 768 bytes, respectively).
2. PIC18F2X8 devices imple me nt 5 A/D channels,
as opposed to 8 for PIC18F4X8 devices.
3. PIC18F2X8 devices implement 3 I/O ports,
while PIC18F4X8 devices implement 5.
4. Only PIC18F4X8 devices implement the
Enhanced CCP module, analog comparators
and the Parallel Slave Port.
All other features for devices in the PIC18FXX8 family,
including the serial communications modules, are
identical. These are summarized in Table 1-1.
Block diagrams of the PIC18F2X8 and PIC18F4X8
devices are provided in Figure 1-1 and Figure 1-2,
respectively. The pinouts for these device families are
listed in Table 1-2.
TABLE 1-1: PIC18FXX8 DEVICE FEATURES
Features PIC18F248 PIC18F258 PIC18F448 PIC18F458
Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz
Internal
Program
Memory
Data Memory (Bytes) 768 1536 768 1536
Data EEPROM Memory (Bytes) 256 256 256 256
Interrupt Sources 17 17 21 21
I/O Ports Ports A, B, C Ports A, B, C Ports A, B, C, D, E Ports A, B, C, D, E
Timers 4 4 4 4
Capture/Compare/PWM Modules 1 1 1 1
Enhanced Capture/Compare/
PWM Modules
Serial Communic ations MSSP, CAN,
Parallel Communications (PSP) No No Yes Yes
10-bit Analog-to-Digital Converter 5 input channels 5 input channels 8 input channels 8 input channels
Analog Comparators No No 2 2
Analog Comparators V
Resets (and Delays) POR, BOR,
Programmable Low-Voltage Detect Yes Yes Yes Yes
Programmable Brown-out Reset Yes Yes Yes Yes
CAN Module Yes Yes Yes Yes
In-Circuit Serial Programming™
(ICSP™)
Instruction Set 75 Instructions 75 Instructions 75 Instructions 75 Instructions
Packages 28-pin SPDIP
Bytes 16K 32K 16K 32K
# of Single-Word
Instructions
REF Output N/A N/A Yes Yes
8192 16384 8192 16384
—— 1 1
Addressable USART
RESET Instruction,
Stack Fu ll,
Stack U nderflow
(PWRT, OST)
Yes Yes Yes Yes
28-pin SOIC
MSSP, CAN,
Addressable USART
POR, BOR,
RESET Instruction,
Stack Full,
Stack U nderflow
(PWRT, OST)
28-pin SPDIP
28-pin SOIC
MSSP, CAN,
Addressable USART
POR, BOR,
RESET Instruction,
Stack Full,
Stack U nderflow
(PWRT, OST)
40-pin PDIP
44-pin PLCC
44-pin TQFP
MSSP, CAN,
Addressable USART
POR, BOR,
RESET Instruction,
Stack Full,
Stack U nderflow
(PWRT, OST )
40-pin PDIP
44-pin PLCC
44-pin TQFP
2004 Microchip Technology Inc. DS41159D-page 7
PIC18FXX8
FIGURE 1-1: PIC18F248/258 BLOCK DIAGRAM
Address Latch
Program Memory
up to 32 Kbytes
Data Latch
OSC2/CLKO/RA6
OSC1/CLKI
T1OSI
T1OSO
21
21
21
16
Instruction
Decode &
Control
Timing
Generation
4X PLL
Precision
Band Gap
Reference
T able Pointer<21>
inc/dec logic
PCLATU
PCU
Program Counter
31 Level Stack
Table Latch
8
ROM Latch
8
PCLATH
PCH PCL
IR
Power-up
Timer
Oscillator
Star t-up T ime r
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Test Mode
Select
8
4
BSR
Decode
BITOP
Data Latch
Data RAM
up to 1536 bytes
Address Latch
Address<12>
12
FSR0
FSR1
FSR2
inc/dec
logic
PRODH
8 x 8 Multiply
3
8
8
Data Bus<8>
12
4
Bank0, F
PRODL
W
8
ALU<8>
8
PORTA
RA0/AN0/CVREF
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS
PORTB
12
PORTC
8
8
8
OSC2/CLK O/RA 6
RB0/INT0
RB1/INT1
RB2/CANTX/INT2
RB3/CANRX
RB4
RB5/PGM
RB6/PGC
RB7/PGD
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
/LVDIN
Band Gap
PBOR
PLVD
DataEEPROM
Timer0
Timer1 Timer2
CCP1
MCLR
VDD, VSS
USART
Timer3
Synchronous
Serial Port
10-bit
ADC
CAN Module
DS41159D-page 8 2004 Microchip Technology Inc.
FIGURE 1-2: PIC18F448/458 BLOCK DIAGRAM
PIC18FXX8
Address Latch
Program Memory
up to 32 Kbytes
Data Latch
OSC2/CLKO/RA6
OSC1/CLKI
T1OSI
T1OSO
21
21
21
16
Instruction
Decode &
Control
Timing
Generation
4X
PLL
Precision
Band Gap
Reference
T able Pointer<21>
inc/dec logic
PCLATU
PCU
Program Counter
31 Level Stack
Table Latch
8
ROM Latch
IR
Power-up
Oscillator
Start-up Timer
Power-on
Watchdog
Brown-out
Test Mode
8
PCLATH
PCH PCL
Timer
Reset
Timer
Reset
Select
8
4
BSR
Decode
BITOP
Data Latch
Data RAM
up to 1536 Kbyt es
Address Latch
Address<12>
12
FSR0
FSR1
FSR2
inc/dec
logic
8 x 8 Multiply
3
8
8
ALU<8>
Data Bus<8>
12
4
Bank0, F
PRODLPRODH
W
8
8
PORTA
RA0/AN0/CVREF
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS
PORTB
12
PORTC
8
8
8
PORTD
PORTE
OSC2/CLKO/RA6
RB0/INT0
RB1/INT1
RB2/CANTX/INT2
RB3/CANRX
RB4
RB5/PGM
RB6/PGC
RB7/PGD
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RD0/PSP0/C1IN+
RD1/PSP1/C1INRD2/PSP2/C2IN+
RD3/PSP3/C2INRD4/PSP4/ECCP1/P1A
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
RE0/AN5/RD
RE1/AN6/WR//C1OUT
RE2/AN7/CS/C2OUT
/LVDIN
Band Gap
MCLR
VDD, VSS
PBOR
PLVD
DataEEPROM
Timer0
Comparators
Timer1 Timer2
CCP1
USART
Enhanced
CCP
Timer3
USART
10-bit
ADC
Synchronous
Serial Port
Parallel
Slave Port
CAN Module
2004 Microchip Technology Inc. DS41159D-page 9
PIC18FXX8
TABLE 1-2: PIC18FXX8 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
SPDIP, SOIC PDIP TQFP PLCC
Pin
Type
Buffer
Type
DescriptionPIC18F248/258 PIC18F448/458
MCLR/VPP
MCLR
VPP
NC — — 12, 13,
OSC1/CLKI
OSC1
CLKI
OSC2/CLKO/RA6
OSC2
CLKO
RA6
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
11182
I
P
1, 17,
33, 34
9 133014
10 14 31 15
28, 40
— — These pins should be left
IICMOS/ST
O
O
I/O
ST
—
CMOS
—
—
TTL
Master Clear (input) or
programming voltage (output).
Master Clear (Reset) input.
This pin is an active low Reset
to the device.
Programming voltage inpu t.
unconnected.
Oscillator crystal or external clock
input.
Oscillator crystal input or
external clock sou rce inpu t. ST
buffer when configured in RC
mode; otherwise, CMOS.
External clock source input.
Always associated with pin
function OSC1 (see OSC1/
CLKI, OSC2/CLKO pins).
Oscillator crystal or clock output.
Oscillator crystal output.
Connects to crystal or
resonator in Crystal Oscillator
mode.
In RC mode, OSC2 pin output s
CLKO, which has 1/4 the
frequency of OSC1 and
denotes the instruction cycle
rate.
General purpose I/O pin.
DD)
DS41159D-page 10 2004 Microchip Technology Inc.
TABLE 1-2: PIC18FXX8 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
RA0/AN0/C
RA0
AN0
CVREF
RA1/AN1
RA1
AN1
VREF
Pin
Type
SPDIP, SOIC PDIP TQFP PLCC
22193
33204
I/O
O
I/O
Buffer
Type
TTL
I
Analog
Analog
TTL
I
Analog
PIC18FXX8
DescriptionPIC18F248/258 PIC18F448/458
PORTA is a bidirectional I/O port.
Digital I/O.
Analog input 0.
Comparator voltage reference
output.
Digital I/O.
Analog input 1.
RA2/AN2/V
RA2
AN2
V
RA3/AN3/V
RA3
AN3
V
RA4/T0CKI
RA4
T0CKI
RA5/AN4/SS
RA5
AN4
SS
LVDIN
RA6 See the OSC2/CLKO/RA6 pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
REF-
REF-
REF+
REF+
/LVDIN
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
44215
I/O
I
I
55226
I/O
I
I
66237
I/OITTL/OD
77248
I/O
I
I
I
TTL
Analog
Analog
TTL
Analog
Analog
ST
TTL
Analog
ST
Analog
Digital I/O.
Analog input 2.
A/D reference voltage
(Low) input.
Digital I/O.
Analog input 3.
A/D reference voltage
(High) input.
Digital I/O – open-drain when
configured as output.
Timer0 external clock input.
Digital I/O.
Analog input 4.
SPI™ slave select input.
Low-Voltage Detect input.
DD)
2004 Microchip Technology Inc. DS41159D-page 11
PIC18FXX8
TABLE 1-2: PIC18FXX8 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
I/O
Buffer
Type
TTL
I
ST
Pin Name
RB0/INT0
RB0
INT0
Type
SPDIP, SOIC PDIP TQFP PLCC
21 33 8 36
DescriptionPIC18F248/258 PIC18F448/458
PORTB is a bidirectional I/O port.
PORTB can be software
programme d for internal weak
pull-ups on a ll inputs.
Digital I/O.
External interrupt 0.
RB1/INT1
RB1
INT1
RB2/CANTX/INT2
RB2
CANTX
INT2
RB3/CANRX
RB3
CANRX
RB4 25 371441I/OTTL Digital I/O.
RB5/PGM
RB5
PGM
RB6/PGC
RB6
PGC
22 34 9 37
23 35 10 38
24 36 11 39
26 38 15 42
27 39 16 43
I/O
I/O
O
I/O
I/O
I/O
TTL
I
I
I
I
I
ST
TTL
TTL
ST
TTL
TTL
TTL
ST
TTL
ST
Digital I/O.
External interrupt 1.
Digital I/O.
Transmit signal for CAN bus.
External interrupt 2.
Digital I/O.
Receive signal for CAN bus.
Interrupt-on-change pin.
Digital I/O.
Interrupt-on-change pin.
Low-voltage ICSP™
programming enable.
Digital I/O. In-Circuit
Debugger pin.
Interrupt-on-change pin.
ICSP programming clock.
RB7/PGD
RB7
PGD
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DS41159D-page 12 2004 Microchip Technology Inc.
28 40 17 44
I/O
I/O
TTL
ST
Digital I/O. In-Circuit
Debugger pin.
Interrupt-on-change pin.
ICSP programming data.
DD)
TABLE 1-2: PIC18FXX8 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
RC0/T1OSO/T1CKI
RC0
T1OSO
T1CKI
RC1/T1OSI
RC1
T1OSI
Pin
Type
SPDIP, SOIC PDIP TQFP PLCC
11 15 32 16
12 16 35 18
I/O
O
I/O
Buffer
Type
ST
—
I
I
ST
ST
CMOS
PIC18FXX8
DescriptionPIC18F248/258 PIC18F448/458
PORTC is a bidirectional I/O port.
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock
input.
Digital I/O.
Timer1 oscillator input.
RC2/CCP1
RC2
CCP1
RC3/SCK/SCL
RC3
SCK
SCL
RC4/SDI/SDA
RC4
SDI
SDA
RC5/SDO
RC5
SDO
RC6/TX/CK
RC6
TX
CK
RC7/RX/DT
RC7
RX
DT
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
13 17 36 19
14 18 37 20
15 23 42 25
16 24 43 26
17 25 44 27
18 26 1 29
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I/O
O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
I
I
ST
ST
ST
—
ST
—
ST
ST
ST
ST
Digital I/O.
Capture 1 input/Compare 1
output/PWM1 output.
Digital I/O.
Synchronous serial clock
input/output for SPI™ mode.
Synchronous serial clock
input/output for I
Digital I/O.
SPI data in.
2
C data I/O.
I
Digital I/O.
SPI data out.
Digital I/O.
USART asynchronous
transmit.
USART synchronous clock
(see RX/DT).
Digital I/O.
USART asynchronous receive.
USART synchronous data
(see TX/CK).
2
C™ mode.
DD)
2004 Microchip Technology Inc. DS41159D-page 13
PIC18FXX8
TABLE 1-2: PIC18FXX8 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
I/O
I/O
Buffer
Type
ST
TTL
I
Analog
Pin Name
RD0/PSP0/C1IN+
RD0
PSP0
C1IN+
Type
SPDIP, SOIC PDIP TQFP PLCC
— 193821
DescriptionPIC18F248/258 PIC18F448/458
PORTD is a bidirectional I/O port.
These pins have TTL inp ut buf fers
when external memory is enabled.
Digital I/O.
Parallel Slave Port data.
Comparator 1 input.
RD1/PSP1/C1IN-
RD1
PSP1
C1IN-
RD2/PSP2/C2IN+
RD2
PSP2
C2IN+
RD3/PSP3/C2IN-
RD3
PSP3
C2IN-
RD4/PSP4/ECCP1/
P1A
RD4
PSP4
ECCP1
P1A
RD5/PSP5/P1B
RD5
PSP5
P1B
— 203922
I/O
I/O
I
— 214023
I/O
I/O
I
— 224124
I/O
I/O
I
—27230
I/O
I/O
I/O
O
—28331
I/O
I/O
O
ST
TTL
Analog
ST
TTL
Analog
ST
TTL
Analog
ST
TTL
ST
—
ST
TTL
—
Digital I/O.
Parallel Slave Port data.
Comparator 1 input.
Digital I/O.
Parallel Slave Port data.
Comparator 2 input.
Digital I/O.
Parallel Slave Port data.
Comparator 2 input.
Digital I/O.
Parallel Slave Port data.
ECCP1 capture/compare.
ECCP1 PWM output A.
Digital I/O.
Parallel Slave Port data.
ECCP1 PWM output B.
RD6/PSP6/P1C
RD6
PSP6
P1C
RD7/PSP7/P1D
RD7
PSP7
P1D
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DS41159D-page 14 2004 Microchip Technology Inc.
—29432
I/O
I/O
O
—30533
I/O
I/O
O
ST
TTL
—
ST
TTL
—
Digital I/O.
Parallel Slave Port data.
ECCP1 PWM output C.
Digital I/O.
Parallel Slave Port data.
ECCP1 PWM output D.
DD)
TABLE 1-2: PIC18FXX8 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
RE0/AN5/RD
RE0
AN5
RD
RE1/AN6/WR/C1OUT
RE1
AN6
WR
C1OUT
Pin
Type
SPDIP, SOIC PDIP TQFP PLCC
—8259
—92610
I/O
I/O
O
Buffer
Type
ST
I
Analog
I
TTL
ST
I
Analog
I
TTL
Analog
PIC18FXX8
DescriptionPIC18F248/258 PIC18F448/458
PORTE is a bidirectional I/O port.
Digital I/O.
Analog input 5.
Read control for Parallel Slave
Port (see WR
Digital I/O.
Analog input 6.
Write control for Paralle l Slave
Port (see CS
Comparator 1 output.
and CS pins).
and RD pins).
RE2/AN7/CS/C2OUT
RE2
AN7
CS
C2OUT
VSS 19, 8 12, 31 6, 29 13, 34 — — Ground reference for logic and
DD 20 11, 32 7, 28 12, 35 — — Positive supply for logic and I/O
V
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
—102711
I/O
I
I
O
ST
Analog
TTL
Analog
Digital I/O.
Analog input 7.
Chip select control for Parallel
Slave Port (see RD
pins).
Comparator 2 output.
I/O pins.
pins.
and WR
DD)
2004 Microchip Technology Inc. DS41159D-page 15
PIC18FXX8
NOTES:
DS41159D-page 16 2004 Microchip Technology Inc.
PIC18FXX8
2.0 OSCILLATOR
CONFIGURATIONS
2.1 Oscillator Types
The PIC18FXX8 can be operated in one of eight oscillator modes, programmable by three configuration bits
(FOSC2, FOSC1 and FOSC0).
1. LP Low-Power Crystal
2. XT Crystal/Resonator
3. HS High-Speed Crystal/Resonator
4. HS4 High-Speed Crystal/Resonator with
PLL enabled
5. RC External Resistor/Capacito r
6. RCIO External Resistor/Capacitor with I/O
pin enabled
7. EC External Clock
8. ECIO External Clock with I/O pin enabled
2.2 Crystal Oscillator/Ceramic
Resonators
In XT, LP, HS or HS4 (PLL) Oscillator modes, a crystal
or ceramic resonator is connected to the OSC1 and
OSC2 pins to establish oscillation. Figure 2-1 shows
the pin connections . An ext ernal clock source m ay also
be connected to the OSC1 pin, as shown in Figure 2-3
and Figure 2-4.
The PIC18FXX8 oscilla tor d esign requires the use of a
parallel cut crystal.
Note: Use of a series cut crystal may give a fre-
quency out of the crystal manufacturer’s
specifications.
FIGURE 2-1: CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP OSC
CONFIGURATION)
(1)
C1
(1)
C2
Note 1: See Table 2-1 and Table 2-2 for recommended
values of C1 and C2.
2: A series resistor (R
strip cut crystals.
3: R
OSC1
XTAL
(2)
RS
OSC2
F varies with the crystal chosen.
(3)
RF
PIC18FXX8
S) may be required for AT
To
Internal
Logic
Sleep
TABLE 2-1: CERAMIC RESONATORS
Ranges Tested:
Mode Freq OSC1 OSC2
XT 455 kHz
2.0 MHz
4.0 MHz
HS 8.0 MHz
16.0 MHz
These values are for design guidance only.
See notes following Table 2-2.
Resonators Used:
455 kHz Panasonic EFO-A455K04B ±0.3%
2.0 MHz Murata Erie CSA2.00MG ±0.5%
4.0 MHz Murata Erie CSA4.00MG ±0.5%
8.0 MHz Murata Erie CSA8.00MT ±0.5%
16.0 MHz Murata Erie CSA16.00MX ±0.5%
All resonators used did not have built-in capacitors.
68-100 pF
15-68 pF
15-68 pF
10-68 pF
10-22 pF
68-100 pF
15-68 pF
15-68 pF
10-68 pF
10-22 pF
2004 Microchip Technology Inc. DS41159D-page 17
PIC18FXX8
TABLE 2-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Osc Type
Crystal
Freq
LP 32.0 kHz 33 pF 33 pF
200 kHz 15 pF 15 pF
XT 200 kHz 47-68 pF 47-68 pF
1.0 MHz 15 pF 15 pF
4.0 MHz 15 pF 15 pF
HS 4.0 MHz 15 pF 15 pF
8.0 MHz 15-33 pF 15-33 pF
20.0 MHz 15-33 pF 15-33 pF
25.0 MHz 15-33 pF 15-33 pF
These values are for design guidance only.
See notes on this page.
32.0 kHz Epson C-001R32.768K-A ±20 PPM
200 kHz STD XTL 200.000KHz ±20 PPM
1.0 MHz ECS ECS-10-13-1 ±50 PPM
4.0 MHz ECS ECS-40-20-1 ±50 PPM
8.0 MHz EPSON CA-301 8.000M-C ±30 PPM
20.0 MHz EPSON CA-301 20.000M-C ±30 PPM
Note 1: Recommended values of C1 and C2 are
identical to the ranges tested (Table 2-1).
2: Higher capacitance inc reases the st abilit y
of the oscillator but also increases the
start-up time.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
4: Rs may be required in HS mode, as well
as XT mode, to avoid overdrivi ng crys t als
with low drive level specification.
Cap. Range C1Cap. Range
Crystals Used
C2
2.3 RC Oscillator
For timing insensitive applications, the “RC” and “RCIO”
device options offer additional cost savings. The RC
oscillator frequency is a function of the supply voltage,
the resistor (R
operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal
process parameter variation. Furthermore, the differ-
ence in lead frame capacit ance between package types
will also affect the oscillation frequency, especially for
EXT values. The user also needs to take into
low C
account variation due to tolerance of external R and C
components used. Figure 2-2 shows how the RC
combination is connected.
In the RC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used f or t e st pu r pos es or t o sy nc hr o n iz e ot he r
logic.
Note: If the oscillator frequency divided by 4
FIGURE 2-2: RC OSCILLATOR MODE
REXT
CEXT
VSS
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
The RCIO Oscillato r mode f unc tions like t he RC m ode,
except that the OSC2 pin becomes an additional
general purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6).
EXT) and capacitor (CEXT) values and the
signal is not required in the application, it
is recommended to use RCIO mode to
save current.
VDD
PIC18FXX8
OSC1
F
OSC/4
OSC2/CLKO
C
EXT > 20 pF
Internal
Clock
DS41159D-page 18 2004 Microchip Technology Inc.
PIC18FXX8
2.4 External Clock Input
The EC and ECIO Oscillator mode s require an externa l
clock source to be connected to the OSC1 pin. The
feedback device between OSC1 and OSC2 is turned
off in these modes to save current. There is no oscillator start-up time required after a Power-on Reset or
after a recovery from Sleep mode.
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used f or t e st pu r pos es or t o sy nc hr o n iz e ot he r
logic. Figure 2-3 shows the pin connections for the EC
Oscillator mode.
FIGURE 2-3: EXTERNAL CLOCK INPUT
OPERATION (EC OSC
CONFIGURATION)
PIC18FXX8
Clock from
Ext. System
OSC/4
F
The ECIO Oscillator mode func ti ons li ke t he EC m od e,
except that the OSC2 pin becomes an additional
general purpose I/O pin. Figure 2-4 shows the pin
connections for the ECIO Osci ll ator mode.
OSC1
OSC2
FIGURE 2-4: EXTERNAL CLOCK INPUT
OPERATION (ECIO
CONFIGURATION)
PIC18FXX8
Clock from
Ext. System
OSC1
I/O (OSC2)
2.5 HS4 (PLL)
A Phase Locked Loop circuit is pro vided as a programmable option for users that want to multiply the
frequency of the incoming cry sta l oscil lator sig nal by 4.
For an input clock frequency of 10 MHz, the internal
clock frequency will be multiplied to 40 MHz. This is
useful for customers who are concerned with EMI due
to high-frequency crystals.
The PLL can only be enabled when the oscillator
configuration bi ts are pro grammed for HS mod e. If the y
are programmed for any other mode, the PLL is not
enabled and the system clock will come directly from
OSC1.
The PLL is one of the modes of the FOSC2:FOSC0
configuration bits. The oscillator mode is specified
during device programming.
A PLL lock timer is used to ensure that the PLL has
locked before device execution starts. The PLL lock
timer has a time-out referred to as T
PLL.
FIGURE 2-5: PLL BLOCK DIAGRAM
OSC2
Crystal
Osc
OSC1
Phase
Comparator
F
IN
FOUT
FOSC2:FOSC0 = 110
Loop
Filter
Divide by 4
VCO
SYSCLK
MUX
2004 Microchip Technology Inc. DS41159D-page 19
PIC18FXX8
2.6 Oscillator Switching Feature
The PIC18FXX8 devices include a featu re that allows
the system clock source to be switc hed from the mai n
oscillator to an alternate low-frequency clock source.
For the PIC18FXX8 devices, this alternate clock source
is the Timer1 oscillator. If a low-frequency crystal
(32 kHz, for example) has been attached to the Timer1
oscillator pins and the Timer1 oscillator has been
enabled, the device can switch to a Low-Power Execution mode. Figure 2-6 shows a block diagram of the
system clock sources. The clock switching feature is
enabled by programming the Oscillator Switching
Enable (OSCSEN
CONFIG1H, to a ‘0’. Clock switching is disabled in an
erased device. See Section 1 2.2 “Timer 1 Oscillat or”
for further details of the Timer1 oscillator and
Section 24.1 “Configuration Bits” for Configuration
register details.
FIGURE 2-6: DEVICE CLOCK SOURCES
) bit in Configuration register,
PIC18FXX8
OSC2
OSC1
T1OSO
T1OSI
Main Oscillator
Sleep
Timer 1 Oscillator
T1OSCEN
Enable
Oscillator
2.6.1 SYSTEM CLOCK SWITCH BIT
The system clock source switching is performed under
software control. The system clock switch bit, SCS
(OSCCON register), controls the clock switching. When
the SCS bit is ‘0’, the system clock source comes from
the main oscillator selected by the FOSC2:FOSC0
configuration bits. When the SCS bit is set, the system
clock source comes from the Timer1 oscilla tor . The SCS
bit is cleared on all forms of Reset.
Note: The Timer1 oscillator must be enabled to
switch the system clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control register (T1CON). If the Timer1 oscillator is not
enabled, any write to the SCS bit will be
ignored (SCS bit forced cleared) and the
main oscillator con t in ues to be t he s ys tem
clock source.
4 x PLL
TOSC
TT1P
Clock Source Option
for Other Modules
TOSC/4
MUX
Clock
Source
TSCLK
Note: I/O pins have diode protection to VDD and VSS.
REGISTER 2-1: OSCCON: OSCILLATOR CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-1
— — — — — — —SCS
bit 7 bit 0
bit 7-1 Unimplemented: Read as ‘0’
bit 0 SCS: System Clock Switch bit
When
OSCSEN configuration bit = 0 and T1OSCEN bit is set:
1 = Switch to Timer1 oscillator/clock pin
0 = Use primary oscillator/clock input pin
OSCSEN is clear or T1OSCEN is clear:
When
Bit is force d clear.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
DS41159D-page 20 2004 Microchip Technology Inc.
PIC18FXX8
2.6.2 OSCILLATOR TRANSITIONS
The PIC18FXX8 devices contain circuitry to prevent
“glitches” when switching between oscillator sources.
Essentially, the circuitry waits for eight rising edges of
the clock source that the processor is swit ching to. This
ensures that the n ew c lo ck s ourc e is s t able and that its
pulse width will not be less than the shortest pulse
width of the two clock sources.
Figure 2-7 shows a timing diagram indicating the transition from the main oscillator to the Timer1 oscillator.
The Timer1 oscillator is assumed to be running all the
The sequence of events that takes place when switching from the Timer1 oscillator to the main oscillator will
depend on the mode of the main oscillator. In addition
to eight clock cycles of the main oscillator, additional
delays may take place.
If the main oscillator is configured for an external
crystal (HS, XT, LP), the transition will take place after
an oscillator st art-up time (T
OST) has occurred. A timing
diagram indicating the transition from the Timer1
oscillator to the main oscillator for HS, XT and LP
modes is shown in Figure 2-8.
time. After the SCS bit is set, th e proce ssor is frozen at
the next occurring Q1 cycle . After eight synchroniz ation
cycles are counted from the Timer1 oscillator,
operation resumes. No additional delays are required
after the synchronization cy cle s.
FIGURE 2-7: TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR
Q1
T1OSI
OSC1
Internal
System
Clock
SCS
(OSCCON<0>)
Program
Counter
TOSC
Q4
Q3Q2
Q1
TDLY
TT1P
21345678
Tscs
PC + 2PC
Q3Q2Q1
Q4 Q1
Q2 Q3 Q4 Q1
PC + 4
Note 1: Delay on internal system clock is eight oscillator cycles for synchronization.
FIGURE 2-8: TIMING DIAGRAM FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, XT , LP)
T1OSI
OSC1
OSC2
Internal System
Clock
(OSCCON<0>)
Note 1: T
SCS
Program
Counter
OST = 1024 TOSC (drawing not to scale).
Q3 Q4
PC PC + 2
Q1
TOST
TOSC
TT1P
12345678
TSCS
Q1 Q2 Q3 Q4 Q1 Q2
Q3
PC + 4
2004 Microchip Technology Inc. DS41159D-page 21
PIC18FXX8
If the main oscillator is configured for HS4 (PLL) mode,
an oscillator start-up time (T
time-out (T
PLL) will occur. The PLL time-out is typically
OST) plus an additional PLL
2 ms and allows the PLL to lock to the main oscillator
frequency. A timing diagram indicating the transition
from the Timer 1 oscilla tor to the mai n oscillator f or HS4
mode is shown in Figure 2-9.
If the main oscillato r is co nfigure d in th e RC, R CIO, EC
or ECIO modes, the re is no oscillator start-u p t im e-ou t.
Operation will resume after eight cycles of the main
oscillator have been counted. A ti ming diag ram indicating the transition from the Timer1 oscillator to the main
oscillator for RC, RC IO, EC and EC IO mo des is sho wn
in Figure 2-10.
FIGURE 2-9: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS WITH PLL)
Q3
PC + 4
T1OSI
OSC1
OSC2
PLL Clock
Input
Internal System
Note 1: T
Clock
(OSCCON<0>)
SCS
Program
Counter
OST = 1024 TOSC (drawing not to scale).
Q4 Q1
TOST
PC PC + 2
TPLL
TOSC
TT1P
TSCS
123456
Q1 Q2 Q3 Q4 Q1 Q2
8
7
Q4
FIGURE 2-10: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)
Q3 Q4
T1OSI
OSC1
OSC2
Internal System
Note 1: RC Oscillator mode assumed.
Clock
(OSCCON<0>)
SCS
Program
Counter
Q1
PC PC + 2
TT1P
TOSC
12345 678
TSCS
Q1 Q2 Q3 Q4 Q1 Q2 Q3
Q4
PC + 4
DS41159D-page 22 2004 Microchip Technology Inc.
PIC18FXX8
2.7 Effects of Sleep Mode on the
On-Chip Oscillator
When the device executes a SLEEP instruction, the
on-chip clocks and oscillator are turned off and the
device is held at the beginning of an instruction cycle
(Q1 state). With the os ci lla tor o f f, the OSC1 and OSC2
signals will stop oscillating. Since all the transistor
switching currents have been removed, Sleep mode
achieves the lowest current consumption of the device
(only leakage currents). Enabling any on-chip feature
that will operate during Sleep will increase the current
consumed during Sleep. The user can wake from
Sleep through external Reset, Watchdog Timer Reset
or through an interrupt.
2.8 Power-up Delays
Power-up delays are con trolled by two time rs so that no
external Reset circuitry is required for most applications. The delays ensure that the device is kept in
Reset until the device power supply and clock are
stable. For additional information on Reset operation,
see Section 3.0 “Reset”.
The first timer is the Power-up Timer (PWRT), which
optionally provides a fixed delay of T
#D033) on power-up only (POR and BOR). The second
timer is the Oscillator S t art-up T imer (OST), inten ded to
keep the chip in Reset until the crystal oscillator is
stable.
With the PLL enabled ( HS4 Osc ill ato r mo de), the timeout sequence following a Power-on Reset is different
from other oscillator modes. The time-out sequence is
as follows: the PWRT time-out is invoked after a POR
time delay has expired, then the Oscillator Start-up
Timer (OST) is invoked. However, this is still not a
sufficient a mount of ti me to allow the PLL to l ock at hig h
frequencies. The PWRT timer is used to provide an
additional fixed 2ms (nominal) to allow the PLL ample
time to lock to the incoming clock frequency.
TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE
OSC Mode OSC1 Pin OSC2 Pin
RC Floating, external resistor should pull high At logic low
RCIO Floating, external resistor should pull high Configured as PORTA, bit 6
ECIO Floating Configured as PORTA, bit 6
EC Floating At logic low
LP, XT and HS Feedback inverter disabled at quiescent
voltage level
Note: See Table 3-1 in Section 3.0 “Reset” for time-outs due to Sleep and MCLR
Feedback inverter disabled at quiescent
voltage level
Reset.
PWRT (parameter
2004 Microchip Technology Inc. DS41159D-page 23
PIC18FXX8
NOTES:
DS41159D-page 24 2004 Microchip Technology Inc.
PIC18FXX8
3.0 RESET
The PIC18FXX8 differentiates between various kinds
of RESET:
a) Power-on Reset (POR)
b) MCLR
c) MCLR Rese t during Sleep
d) Watchdog Timer (WDT) Reset during normal
e) Programmable Brown-out Reset (PBOR)
f) RESET Instr uction
g) Stack Full Reset
h) Stack Underflow Reset
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset”
Reset during normal operation
operation
state on Power-on Reset, MCLR
out Reset, MCLR
Reset during Sleep and by the
RESET instruction.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal operation. Status bits from the RCON register, RI
POR
and BOR are set or cleared differently in different
Reset situations, as indicated in Table 3-2. These bits
are used in software to determine the nature of the
Reset. See Table 3-3 for a full description of the Reset
states of all registers.
A simplified block di agram of the On-Chip Reset Circu it
is shown in Figure 3-1.
The Enhanced MCU devices have a MCLR
in the MCLR
Reset path. The filter will detect and
ignore small pulses.
A WDT Reset does not drive MCLR
, WDT Reset, Brown-
FIGURE 3-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET
Instruction
Stack
Pointer
Stack Full/Underflow Reset
External Reset
, TO, PD,
noise filter
pin low.
MCLR
WDT
Module
V
DD Rise
Detect
VDD
OSC1
Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.
Brown-out
Reset
OST/PWRT
OST
On-chip
RC OSC
2: See Table 3-1 for time-out situations.
PWRT
(1)
Sleep
WDT
Time-out
Reset
Power-on Reset
BOREN
10-bit Ripple Counter
10-bit Ripple Counter
S
R
Enable PWRT
Enable OST
Chip_Reset
Q
(2)
2004 Microchip Technology Inc. DS41159D-page 25
PIC18FXX8
.
t
l
3.1 Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip when a
DD rise is detected. To take advantage of the POR
V
circuitry, connect the MCLR
resistor) to V
DD. This eliminates external RC compo-
pin directly (or through a
nents usually needed to create a Power-on Reset
delay. A minimum rise rate for V
DD is specified (refer to
parameter D004). For a slow rise time, see Figure 3-2.
When the device starts normal operation (exits the
Reset condition), device operating parameters
(voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating conditions are met. Brown-out Reset may be used to meet
the voltage start-up condition.
3.2 MCLR
PIC18FXX8 devices have a noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
It should be noted that a WDT Reset does not drive
pin low.
MCLR
The behavior of the ESD protection on the MCLR
differs from previous devices of this family. Voltages
applied to the pin that exceed its specification can
result in both Resets and current draws outside of
device specification during the Reset event. For this
reason, Microchip recommends that the MCLR
longer be tied directly to V
DD. The use of an RC
network, as shown in Figure 3-2, is suggested.
pin
pin no
3.3 Power-up Timer (PWRT)
The Power-up Timer provides a fixed nominal time-out
(parameter #33), only on power-up from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in R eset as long a s the PWRT is active.
The PWRT’s ti me delay allows V
able level. A configuration bit (PWRTEN
DD to rise to an accept-
in CONFIG2L
register) is provided to enable/disable the PWRT.
The power-up time dela y will vary f rom chip to chip due
DD, temperature and process variation. See DC
to V
parameter #33 for details.
3.4 Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter #32). This additional
delay ensures that the crystal oscillator or resonator
has started and stabilized.
The OST time-out is invoked only for XT, LP, HS and
HS4 modes and only on Power-on Reset or wake-up
from Sleep.
3.5 PLL Lock Time-out
With the PLL enabled, the time-ou t sequen ce foll owin g
a Power-on Reset is different from other oscillator
modes. A portion of the Po wer-up Timer is used to provide a fixed time-out th at is suff icient for the PLL to lock
to the main oscillator fre quenc y. This PLL lock time-out
PLL) is typically 2 ms and follows the oscillator
(T
start-up time-out (OST).
FIGURE 3-2: EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW V
V
DD
D
R
C
Note 1: External Power-on Reset circuit is required
only if the V
The diode D helps discharge the capacitor
quickly when V
2: R < 40 kΩ is recommended to make sure tha
the voltage drop across R does not violate
the device’s electrical specification.
3: R1 = 100Ω to 1 kΩ will limit any current flow-
ing into MCLR
the event of MCLR/
Electrostatic Discharge (ESD) or Electrica
Overstress (EOS).
DD power-up slope is too slow
DD POWER-UP)
R1
MCLR
PIC18FXXX
DD powers down.
from external capacitor C, in
VPP pin breakdown due to
3.6 Brown-out Reset (BOR)
A configuration bit, BOREN, can disable (if clear/
programmed), or enable (if set), the Brown-out Reset
circuitry. If VDD falls below parameter D005 for greater
than parameter #35, the brown-out situation resets the
chip. A Reset may not occur if VDD falls below parameter D005 for less than parameter #35. The chip will
remain in Brown-out Reset unt il V
The Power-up T im er wil l th en be invoked and will keep
the chip in Reset an additional time delay (parameter
#33). If V
DD drops below BVDD while the Power-up
Timer is ru nni ng, the chip will go back in to a Bro wn-out
Reset and the Power-up Timer will be initialized. Once
DD rises above BVDD, the Power-up Timer will
V
execute the additional time delay.
DD rises above BVDD.
DS41159D-page 26 2004 Microchip Technology Inc.
PIC18FXX8
3.7 Time-out Sequence
On power-up, the time-out sequence is as follows:
First, PWRT time-out is invoked after the POR time
delay has expired, then OST is activated. The total
time-out will vary based on oscillator configuration and
the status o f th e PW RT . Fo r e xa mple, in RC mode with
the PWRT disabled, there will be no time-out at all.
Figure 3-3, Figure 3-4, Figure 3-5, Figure 3-6 and
Figure 3-7 depict time-out sequences on power-up.
Since the time-outs occur from the POR pulse, if MC LR
is kept low long enough, the time-outs will expire.
Bringing MCLR
(Figure 3-5). This is useful for testing purposes or to
synchronize more than one PIC18FXX8 device
operating in parallel.
Table 3-2 shows the Reset condi tions f or some Spec ial
Function Registers, while Table 3-3 shows the Reset
conditions for all registers.
high will begin execution immediately
TABLE 3-1: TIME-OUT IN VARIOUS SITUATIONS
Oscillator
Configuration
HS with PLL enabled
HS, XT, LP 72 ms + 1024 TOSC 1024 TOSC 72 ms + 1024 TOSC 1024 TOSC
EC 72 ms — 72 ms —
External RC 72 ms — 72 ms —
Note 1: 2 ms = Nominal time required for the 4x PLL to lock.
2: 72 ms is the nominal Power-up Timer delay.
(1)
PWRTEN
72 ms + 1024 TOSC + 2 ms 1024 TOSC + 2 ms 72 ms + 10 24 TOSC + 2 m s 1024 TOSC + 2 ms
Power-up
= 0 PWRTEN = 1
(2)
Brown-out
(2)
REGISTER 3-1: RCON REGISTER BITS AND POSITIONS
R/W-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-1
IPEN
bit 7 bit 0
— —RITO PD POR BOR
Wake-up from
Sleep or
Oscillator Switch
TABLE 3-2: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Condition
Power-on Reset 0000h 0--1 110q 1 1 1 0 0 u u
MCLR Reset during normal
operation
Software Reset during normal
operation
Stack Full Reset during normal
operation
Stack Underflow Reset during
normal operation
MCLR
Reset during Sleep 0000h 0--0 011q u 1 0 u u u u
WDT Reset 0000h 0--0 011q u 0 1 u u u u
WDT Wake-up PC + 2 0--1 101q u 0 0 u u u u
Brown-out Reset 0000h 0--1 110q 1 1 1 u 0 u u
Interrupt wake-up from Sleep PC + 2
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (000008h or 0000 18h ).
Program
Counter
0000h 0--0 011q u u u u u u u
0000h 0--0 011q 0 u u u u u u
0000h 0--0 011q u u u 1 1 u 1
0000h 0--0 011q u u u 1 1 1 u
(1)
RCON
Register
0--1 101q u 1 0 u u u u
TO PD POR BOR STKFUL STKUNF
RI
2004 Microchip Technology Inc. DS41159D-page 27
PIC18FXX8
FIGURE 3-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD )
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
TOST
FIGURE 3-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR
VDD
MCLR
INTERNAL POR
PWRT TI ME-OUT
OST TIME-OUT
INTERNAL RESET
TPWRT
NOT TIED TO VDD): CASE 1
TOST
FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
DS41159D-page 28 2004 Microchip Technology Inc.
NOT TIED TO VDD): CASE 2
TOST
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