MICROCHIP PIC18F97J60 DATA SHEET

PIC18F97J60 Family

Data Sheet

64/80/100-Pin High-Performance,

1-Mbit Flash Microcontrollers

with Ethernet

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC

32

logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

®

MCUs and dsPIC® DSCs, KEELOQ

®

code hopping

PIC18F97J60 FAMILY

64/80/100-Pin High-Performance,

1-Mbit Flash Microcontrollers with Ethernet

Ethernet Features:

• IEEE 802.3™ Compatible Ethernet Controller

• Fully Compatible with 10/100/1000Base-T Networks

• Integrated MAC and 10Base-T PHY

• 8-Kbyte Transmit/Receive Packet Buffer SRAM

• Supports One 10Base-T Port

• Programmable Automatic Retransmit on Collision

• Programmable Padding and CRC Generation

• Programmable Automatic Rejection of Erroneous Packets

• Activity Outputs for 2 LED Indicators

•Buffer:

- Configurable transmit/receive buffer size

- Hardware-managed circular receive FIFO

- Byte-wide random and sequential access

- Internal DMA for fast memory copying

- Hardware assisted checksum calculation for

various protocols

•MAC:

- Support for Unicast, Multicast and Broadcast

packets

- Programmable Pattern Match of up to 64 bytes

within packet at user-defined offset

- Programmable wake-up on multiple packet

formats

•PHY:

- Wave shaping output filter

Flexible Oscillator Structure:

• Selectable System Clock derived from Single 25 MHz External Source:

- 2.778 to 41.667 MHz

• Internal 31 kHz Oscillator

• Secondary Oscillator using Timer1 @ 32 kHz

• Fail-Safe Clock Monitor:

- Allows for safe shutdown if oscillator stops

• Two-Speed Oscillator Start-up

External Memory Bus (100-pin devices only):

• Address Capability of up to 2 Mbytes

• 8-Bit or 16-Bit Interface

• 12-Bit, 16-Bit and 20-Bit Addressing modes

Peripheral Highlights:

• High-Current Sink/Source: 25 mA/25 mA on PORTB and PORTC

• Five Timer modules (Timer0 to Timer4)

• Four External Interrupt pins

• Two Capture/Compare/PWM (CCP) modules

• Three Enhanced Capture/Compare/PWM (ECCP) modules:

- One, two or four PWM outputs

- Selectable polarity

- Programmable dead time

- Auto-shutdown and auto-restart

• Up to Two Master Synchronous Serial Port (MSSP) modules supporting SPI (all 4 modes) and I Master and Slave modes

• Up to Two Enhanced USART modules:

- Supports RS-485, RS-232 and LIN 1.2

- Auto-wake-up on Start bit

- Auto-Baud Detect (ABD)

• 10-Bit, Up to 16-Channel Analog-to-Digital Converter module (A/D):

- Auto-acquisition capability

- Conversion available during Sleep

• Dual Analog Comparators with Input Multiplexing

• Parallel Slave Port (PSP) module (100-pin devices only)

2

C™

Special Microcontroller Features:

• 5.5V Tolerant Inputs (digital-only pins)

• Low-Power, High-Speed CMOS Flash Technology:

- Self-reprogrammable under software control

• C compiler Optimized Architecture for Reentrant Code

• Power Management Features:

- Run: CPU on, peripherals on

- Idle: CPU off, peripherals on

- Sleep: CPU off, peripherals off

• Priority Levels for Interrupts

• 8 x 8 Single-Cycle Hardware Multiplier

• Extended Watchdog Timer (WDT):

- Programmable period from 4 ms to 134s

• Single-Supply 3.3V In-Circuit Serial Programming™ (ICSP™) via Two Pins

• In-Circuit Debug (ICD) with 3 Breakpoints via Two Pins

• Operating Voltage Range of 2.35V to 3.6V (3.1V to

3.6V using Ethernet module)

• On-Chip 2.5V Regulator

PIC18F97J60 FAMILY

Flash

Device

PIC18F66J60 64K 3808 8192 39 11 2/3 1 Y Y 1 2 2/3 N N

PIC18F66J65 96K 3808 8192 39 11 2/3 1 Y Y 1 2 2/3 N N

PIC18F67J60 128K 3808 8192 39 11 2/3 1 Y Y 1 2 2/3 N N

PIC18F86J60 64K 3808 8192 55 15 2/3 1 Y Y 2 2 2/3 N N

PIC18F86J65 96K 3808 8192 55 15 2/3 1 Y Y 2 2 2/3 N N

PIC18F87J60 128K 3808 8192 55 15 2/3 1 Y Y 2 2 2/3 N N

PIC18F96J60 64K 3808 8192 70 16 2/3 2 Y Y 2 2 2/3 Y Y

PIC18F96J65 96K 3808 8192 70 16 2/3 2 Y Y 2 2 2/3 Y Y

PIC18F97J60 128K 3808 8192 70 16 2/3 2 Y Y 2 2 2/3 Y Y

Program

Memory

(bytes)

SRAM

Data

Memory

(bytes)

Ethernet

TX/RX Buffer

(bytes)

I/O

10-Bit

A/D (ch)

CCP/

ECCP

MSSP

SPI

Master

2

I

C™

EUSART

Comparators

Timers

8/16-Bit

PSP

External

Memory Bus

Pin Diagrams

64-Pin TQFP

PIC18F97J60 FAMILY

RE1/P2C

RE0/P2D

RB0/INT0/FLT0

RB1/INT1

RB2/INT2

RB3/INT3

RG4/CCP5/P1D

RF5/AN10/CV

RF2/AN7/C1OUT

MCLR

VSS

VDDCORE/VCAP

RF7/SS1

RF6/AN11

REF

RF4/AN9

RF3/AN8

SSPLL

RE2/P2B

RE3/P3C

RE4/P3B

RE5/P1C

RD0/P1B

64

63 62 61

1

2

3 4

5

6

7

8

9

10

11

12

13

14

15

16

17 18 19 20 21 22 23 24 25 26

VDD

RD1/ECCP3/P3A

RD2/CCP4/P3D

V

VSS

PIC18F66J60

PIC18F66J65

PIC18F67J60

SSTX

VDDPLL

RBIAS

V

TPOUT+

TPOUT-

54 53 52 5158 57 56 5560 59

27 28 29 30 32

50 49

31

DDTX

V

48

47

46 45

44

43

42

41

40

39

38

37

36

35

34

33

VDDRX

TPIN+

TPIN-

VSSRX

RB4/KBI0

RB5/KBI1

RB6/KBI2/PGC

VSS

OSC2/CLKO

OSC1/CLKI

VDD

RB7/KBI3/PGD

RC5/SDO1

RC4/SDI1/SDA1

RC3/SCK1/SCL1

RC2/ECCP1/P1A

RF1/AN6/C2OUT

RA1/LEDB/AN1

RA0/LEDA/AN0

SS

V

VDD

RA5/AN4

RA4/T0CKI

RC6/TX1/CK1

RC7/RX1/DT1

RC0/T1OSO/T13CKI

RC1/T1OSI/ECCP2/P2A

DD

AV

ENVREG

REF-

AVSS

RA2/AN2/V

RA3/AN3/VREF+

PIC18F97J60 FAMILY

Pin Diagrams (Continued)

80-Pin TQFP

(1)

/P2A

(2)

(1)

(2)

RH2

RH3

RE1/P2C

RE0/P2D

RB0/INT0/FLT0

RB1/INT1 RB2/INT2

RB3/INT3

MCLR

RG4/CCP5/P1D

VSS

VDDCORE/VCAP

RF7/SS1

RF6/AN11

RF5/AN10/CV

REF

RF4/AN9

RF3/AN8

RF2/AN7/C1OUT

RH7/AN15/P1B

RH6/AN14/P1C

RH1

RH0

RE2/P2B

RE3/P3C

RE4/P3B

RE5/P1C

RE6/P1B

RE7/ECCP2

RD0

VDDVSS

RD1

RD2

VSSPLL

68 67 66 6572 71 70 6974 7378 77 76 757980

VDDPLL

RBIAS

SSTX

V

64 63 62 61

1

2

3

4

5

6

7

8

9

10

11

12

PIC18F86J60

PIC18F86J65

PIC18F87J60

13

14

15

16

17

18

(2)

19

20

21 22 23 24 25 26 27 28 29 30 31 32

33 34

37

35 36 38

DDTX

TPOUT+

TPOUT-

V

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

VDDRX

TPIN+

TPIN-

V

SSRX

RG0/ECCP3/P3A

RG1/TX2/CK2

RB4/KBI0

RB5/KBI1

RB6/KBI2/PGC

V

SS

OSC2/CLKO

OSC1/CLKI

VDD

RB7/KBI3/PGD

RC5/SDO1

RC4/SDI1/SDA1

RC3/SCK1/SCL1

RC2/ECCP1/P1A

RG2/RX2/DT2

RG3/CCP4/P3D

RA5/AN4

RA4/T0CKI

(1)

/P2A

(1)

RC6/TX1/CK1

RJ5

RJ4

RC7/RX1/DT1

(2)

DD

AV

REF-

AVSS

SS

V

VDD

ENVREG

RA2/AN2/V

RA1/LEDB/AN1

RF1/AN6/C2OUT

RH5/AN13/P3B

RH4/AN12/P3C

RA3/AN3/VREF+

RA0/LEDA/AN0

RC0/T1OSO/T13CKI

RC1/T1OSI/ECCP2

Note 1: The ECCP2/P2A pin placement depends on the CCP2MX Configuration bit setting.

2: P1B, P1C, P3B and P3C pin placement depends on the ECCPMX Configuration bit setting.

Pin Diagrams (Continued)

100-Pin TQFP

RE1/AD9/WR/P2C

RE0/AD8/RD

RB0/INT0/FLT0

RB3/INT3/ECCP2

RG4/CCP5/P1D

VDDCORE/VCAP

RF5/AN10/CVREF

RF2/AN7/C1OUT

RH7/AN15/P1B RH6/AN14/P1C

RH2/A18 RH3/A19

/P2D

RB1/INT1 RB2/INT2

(1)

/P2A

RG6 RG5

RF0/AN5

MCLR

V

RF7/SS1

RF6/AN11

RF4/AN9 RF3/AN8

NC

SS

DD

1 2 3 4 5 6 7

(1)

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

(2)

24

(2)

25

(1)

/P2A

(1)

(2)

RE3/AD11/P3C

RE2/AD10/CS/P2B

RE4/AD12/P3B

RE5/AD13/P1C

RE6/AD14/P1B

RH1/A17

RH0/A16

99

100

26

2829303132333435363738

27

RE7/AD15/ECCP2

95

969897

PIC18F97J60 FAMILY

RD0/AD0/PSP0

RD1/AD1/PSP1

RD2/AD2/PSP2

RD3/AD3/PSP3

RD4/AD4/PSP4/SDO2

VDDVSS

RD5/AD5/PSP5/SDI2/SDA2

RD6/AD6/PSP6/SCK2/SCL2

RD7/AD7/PSP7/SS2

9294939190898887868584838281807978

PIC18F96J60 PIC18F96J65 PIC18F97J60

43

42

41

40

39

SSTX

VSSPLL

VDDPLL

RBIAS

V

82818079787677

45

44

4647484950

TPOUT+

DDTX

TPOUT-

V

76

77

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

VDDRX

TPIN+ TPIN-

SSRX

V RG0/ECCP3/P3A RG1/TX2/CK2 RB4/KBI0 RB5/KBI1 RB6/KBI2/PGC RJ2/WRL V

SS

OSC2/CLKO OSC1/CLKI

DD

V RJ3/WRH VSS VDD RJ6/LB RB7/KBI3/PGD RC5/SDO1 RC4/SDI1/SDA1 RC3/SCK1/SCL1 RC2/ECCP1/P1A RG2/RX2/DT2 RG3/CCP4/P3D

(2)

DD

AV

AVSS

ENVREG

RF1/AN6/C2OUT

RH5/AN13/P3B

RH4/AN12/P3C

RA3/AN3/VREF+

REF-

RA2/AN2/V

RA1/LEDB/AN1

RA0/LEDA/AN0

SS

V

VDD

RG7

RJ7/UB

(1)

SS

V

/P2A

(1)

RA5/AN4

RA4/T0CKI

RJ5/CE

RJ1/OE

RJ4/BA0

RJ0/ALE

RC6/TX1/CK1

RC7/RX1/DT1

RC0/T1OSO/T13CKI

RC1/T1OSI/ECCP2

Note 1: The ECCP2/P2A pin placement depends on the CCP2MX Configuration bit and Processor mode settings.

2: P1B, P1C, P3B and P3C pin placement depends on the ECCPMX Configuration bit setting.

PIC18F97J60 FAMILY

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

Register on our web site at www.microchip.com to receive the most current information on all of our products.

PIC18F97J60 FAMILY

NOTES:

PIC18F97J60 FAMILY

1.0 DEVICE OVERVIEW

This document contains device-specific information for the following devices:

• PIC18F66J60 • PIC18F87J60

• PIC18F66J65 • PIC18F96J60

• PIC18F67J60 • PIC18F96J65

• PIC18F86J60 • PIC18F97J60

• PIC18F86J65

This family introduces a new line of low-voltage devices with the foremost traditional advantage of all PIC18 microcontrollers – namely, high computational performance and a rich feature set at an extremely competitive price point. These features make the PIC18F97J60 family a logical choice for many high-performance applications where cost is a primary consideration.

1.1 Core Features

1.1.1 OSCILLATOR OPTIONS AND FEATURES

All of the devices in the PIC18F97J60 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These options include:

• Two Crystal modes, using crystals or ceramic

resonators.

• Two External Clock modes, offering the option of

a divide-by-4 clock output.

• A Phase Lock Loop (PLL) frequency multiplier,

available to the external oscillator modes, which allows clock speeds of up to 41.667 MHz.

• An internal RC oscillator with a fixed 31 kHz

output which provides an extremely low-power option for timing-insensitive applications.

The internal oscillator block provides a stable reference source that gives the family additional features for robust operation:

• Fail-Safe Clock Monitor: This option constantly

monitors the main clock source against a reference signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown.

• Two-Speed Start-up: This option allows the

internal oscillator to serve as the clock source from Power-on Reset, or wake-up from Sleep mode, until the primary clock source is available.

1.1.2 EXPANDED MEMORY

The PIC18F97J60 family provides ample room for application code, from 64 Kbytes to 128 Kbytes of code space. The Flash cells for program memory are rated to last 100 erase/write cycles. Data retention without refresh is conservatively estimated to be greater than 20 years.

The PIC18F97J60 family also provides plenty of room for dynamic application data with 3808 bytes of data RAM.

1.1.3 EXTERNAL MEMORY BUS

In the unlikely event that 128 Kbytes of memory are inadequate for an application, the 100-pin members of the PIC18F97J60 family also implement an External Memory Bus (EMB). This allows the controller’s internal program counter to address a memory space of up to 2 Mbytes, permitting a level of data access that few 8-bit devices can claim. This allows additional memory options, including:

• Using combinations of on-chip and external memory up to the 2-Mbyte limit

• Using external Flash memory for reprogrammable application code or large data tables

• Using external RAM devices for storing large amounts of variable data

1.1.4 EXTENDED INSTRUCTION SET

The PIC18F97J60 family implements the optional extension to the PIC18 instruction set, adding eight new instructions and an Indexed Addressing mode. Enabled as a device configuration option, the extension has been specifically designed to optimize reentrant application code originally developed in high-level languages, such as C.

1.1.5 EASY MIGRATION

Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve.

PIC18F97J60 FAMILY

1.2 Other Special Features

• Communications: The PIC18F97J60 family incorporates a range of serial communication peripherals, including up to two independent Enhanced USARTs and up to two Master SSP modules, capable of both SPI and I and Slave) modes of operation. In addition, one of the general purpose I/O ports can be reconfigured as an 8-bit Parallel Slave Port for direct processor-to-processor communications.

• CCP Modules: All devices in the family incorporate two Capture/Compare/PWM (CCP) modules and three Enhanced CCP (ECCP) modules to maximize flexibility in control applications. Up to four different time bases may be used to perform several different operations at once. Each of the three ECCP modules offers up to four PWM outputs, allowing for a total of twelve PWMs. The ECCP modules also offer many beneficial features, including polarity selection, programmable dead time, auto-shutdown and restart and Half-Bridge and Full-Bridge Output modes.

• 10-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reducing code overhead.

• Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit prescaler, allowing an extended time-out range. See Section 27.0 “Electrical Characteristics” for time-out periods.

2

C™ (Master

1.3 Details on Individual Family Members

Devices in the PIC18F97J60 family are available in 64-pin, 80-pin and 100-pin packages. Block diagrams for the three groups are shown in Figure 1-1, Figure 1-2 and Figure 1-3.

The devices are differentiated from each other in four ways:

1. Flash program memory (three sizes, ranging

from 64 Kbytes for PIC18FX6J60 devices to 128 Kbytes for PIC18FX7J60 devices).

2. A/D channels (eleven for 64-pin devices, fifteen

for 80-pin pin devices and sixteen for 100-pin devices).

3. Serial communication modules (one EUSART

module and one MSSP module on 64-pin devices, two EUSART modules and one MSSP module on 80-pin devices and two EUSART modules and two MSSP modules on 100-pin devices).

4. I/O pins (39 on 64-pin devices, 55 on 80-pin

devices and 70 on 100-pin devices).

All other features for devices in this family are identical. These are summarized in Table 1-1, Table 1-2 and Table 1-3.

The pinouts for all devices are listed in Table 1-4, Table 1-5 and Table 1-6.

PIC18F97J60 FAMILY

TABLE 1-1: DEVICE FEATURES FOR THE PIC18F97J60 FAMILY (64-PIN DEVICES)

Features PIC18F66J60 PIC18F66J65 PIC18F67J60

Operating Frequency DC – 41.667 MHz DC – 41.667 MHz DC – 41.667 MHz

Program Memory (Bytes) 64K 96K 128K

Program Memory (Instructions) 32764 49148 65532

Data Memory (Bytes) 3808

Interrupt Sources 26

I/O Ports Ports A, B, C, D, E, F, G

I/O Pins 39

Timers 5

Capture/Compare/PWM Modules 2

Enhanced Capture/Compare/PWM Modules 3

Serial Communications MSSP (1), Enhanced USART (1)

Ethernet Communications (10Base-T) Yes

Parallel Slave Port Communications (PSP) No

External Memory Bus No

10-Bit Analog-to-Digital Module 11 Input Channels

Resets (and Delays) POR, BOR, RESET Instruction, Stack Full,

Stack Underflow, MCLR

Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled

Packages 64-Pin TQFP

, WDT (PWRT, OST)

TABLE 1-2: DEVICE FEATURES FOR THE PIC18F97J60 FAMILY (80-PIN DEVICES)

Features PIC18F86J60 PIC18F86J65 PIC18F87J60

Operating Frequency DC – 41.667 MHz DC – 41.667 MHz DC – 41.667 MHz

Program Memory (Bytes) 64K 96K 128K

Program Memory (Instructions) 32764 49148 65532

Data Memory (Bytes) 3808

Interrupt Sources 27

I/O Ports Ports A, B, C, D, E, F, G, H, J

I/O Pins 55

Timers 5

Capture/Compare/PWM Modules 2

Enhanced Capture/Compare/PWM Modules 3

Serial Communications MSSP (1), Enhanced USART (2)

Ethernet Communications (10Base-T) Yes

Parallel Slave Port Communications (PSP) No

External Memory Bus No

10-Bit Analog-to-Digital Module 15 Input Channels

Resets (and Delays) POR, BOR, RESET Instruction, Stack Full,

Stack Underflow, MCLR

Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled

Packages 80-Pin TQFP

, WDT (PWRT, OST)

PIC18F97J60 FAMILY

TABLE 1-3: DEVICE FEATURES FOR THE PIC18F97J60 FAMILY (100-pin DEVICES)

Features PIC18F96J60 PIC18F96J65 PIC18F97J60

Operating Frequency DC – 41.667 MHz DC – 41.667 MHz DC – 41.667 MHz

Program Memory (Bytes) 64K 96K 128K

Program Memory (Instructions) 32764 49148 65532

Data Memory (Bytes) 3808

Interrupt Sources 29

I/O Ports Ports A, B, C, D, E, F, G, H, J

I/O Pins 70

Timers 5

Capture/Compare/PWM Modules 2

Enhanced Capture/Compare/PWM Modules 3

Serial Communications MSSP (2), Enhanced USART (2)

Ethernet Communications (10Base-T) Yes

Parallel Slave Port Communications (PSP) Yes

External Memory Bus Yes

10-Bit Analog-to-Digital Module 16 Input Channels

Resets (and Delays) POR, BOR, RESET Instruction, Stack Full,

Stack Underflow, MCLR

Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled

Packages 100-Pin TQFP

, WDT (PWRT, OST)

PIC18F97J60 FAMILY

FIGURE 1-1: PIC18F66J60/66J65/67J60 (64-PIN) BLOCK DIAGRAM

OSC2/CLKO OSC1/CLKI

ENVREG

Table Pointer<21>

inc/dec logic

21

20

Address Latch

Program Memory

(64, 96, 128 Kbytes)

Data Latch

8

Instruction Bus <16>

Timing

Generation

INTRC

Oscillator

Precision Band Gap Reference

Voltage

Regulator

VDDCORE/VCAP

PCLATU

PCU

Table Latch

ROM Latch

Instruction

Decode and

Control

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

V

DD,

SS

8

PCLATH

PCH PCL

Program Counter

31 Level Stack

STKPTR

IR

State Machine Control Signals

(2)

MCLR

Data Bus<8>

8

Data Latch

Data Memory

(3808 Bytes)

Address Latch

Data Address<12>

4

BSR

FSR0 FSR1 FSR2

inc/dec

logic

Address

Decode

3

BITOP

8

12

Access

Bank

PRODLPRODH

8 x 8 Multiply

W

8

ALU<8>

8

PORTA

(1)

RA0:RA5

PORTB

(1)

RB0:RB7

4

12

PORTC

RC0:RC7

(1)

PORTD

(1)

RD0:RD2

8

PORTE

(1)

RE0:RE5

8

PORTF

RF1:RF7

(1)

PORTG

(1)

RG4

ADC

10-Bit

ECCP1

ECCP2

ECCP3 CCP4 CCP5

Timer2Timer1 Timer3Timer0

Timer4

MSSP1

Comparators

EUSART1

Ethernet

Note 1: See Table 1-4 for I/O port pin descriptions.

2: BOR functionality is provided when the on-board voltage regulator is enabled.

PIC18F97J60 FAMILY

FIGURE 1-2: PIC18F86J60/86J65/87J60 (80-PIN) BLOCK DIAGRAM

OSC2/CLKO

OSC1/CLKI

ENVREG

Table Pointer<21>

inc/dec logic

21

20

Address Latch

Program Memory

(64, 96, 128 Kbytes)

Data Latch

8

Instruction Bus <16>

Timing

Generation

INTRC

Oscillator

Precision Band Gap Reference

Voltage

Regulator

PCLATH

PCLATU

PCU

Program Counter

31 Level Stack

STKPTR

Table Latch

ROM Latch

IR

Instruction Decode &

Control

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

(2)

Reset

Data Bus<8>

8

PCH PCL

State Machine

Control Signals

8

Data Latch

Data Memory

PORTA

RA0:RA5

(1)

(3808 Bytes)

Address Latch

12

PORTB

RB0:RB7

(1)

Data Address<12>

BSR

4

FSR0 FSR1 FSR2

inc/dec

logic

Address Decode

4

12

Access

Bank

PORTC

RC0:RC7

(1)

12

PORTD

(1)

RD0:RD2

PORTE

(1)

RE0:RE7

8

PORTF

RF1:RF7

PORTG

RG0:RG4

PORTH

RH0:RH7

(1)

3

BITOP

8

PRODLPRODH

8 x 8 Multiply

W

8

ALU<8>

8

PORTJ

RJ4:RJ5

(1)

ECCP1

VDDCORE/VCAP

ADC

10-Bit

ECCP2 ECCP3

DD, VSS

V

MCLR

Timer2Timer1 Timer3Timer0

CCP4 CCP5

EUSART1

Timer4

EUSART2

Comparators

MSSP1

Ethernet

Note 1: See Table 1-5 for I/O port pin descriptions.

2: BOR functionality is provided when the on-board voltage regulator is enabled.

PIC18F97J60 FAMILY

FIGURE 1-3: PIC18F96J60/96J65/97J60 (100-PIN) BLOCK DIAGRAM

Data Bus<8>

Table Pointer<21>

inc/dec logic

21

Address Latch

Program Memory

(64, 96, 128 Kbytes)

Data Latch

System Bus Interface

Instruction Bus <16>

AD15:AD0, A19:A16 (Multiplexed with PORTD, PORTE and PORTH)

State Machine Control Signals

OSC2/CLKO OSC1/CLKI

ENVREG

Generation

INTRC

Oscillator

Precision Band Gap Reference

Voltage

Regulator

Timing

20

8

PCLATH

PCLATU

PCH PCL

PCU

Program Counter

31 Level Stack

STKPTR

Table Latch

ROM Latch

IR

Instruction Decode &

Control

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

(2)

Reset

8

Data Latch

Data Memory

PORTA

RA0:RA5

(1)

(3808 Bytes)

Address Latch

12

PORTB

RB0:RB7

(1)

Data Address<12>

BSR

4

FSR0 FSR1 FSR2

inc/dec

logic

Address

Decode

4

12

Access

Bank

PORTC

RC0:RC7

(1)

12

PORTD

RD0:RD7

(1)

PORTE

(1)

RE0:RE7

8

PORTF

RF0:RF7

PORTG

RG0:RG7

PORTH

RH0:RH7

(1)

3

BITOP

8

PRODLPRODH

8 x 8 Multiply

W

8

ALU<8>

8

PORTJ

(1)

RJ0:RJ7

ADC

10-Bit

ECCP1

VDDCORE/VCAP

ECCP2 ECCP3

V

Timer2Timer1 Timer3Timer0

DD, VSS

MCLR

Timer4

EUSART1

Comparators

EUSART2

MSSP1

MSSP2CCP4 CCP5

Ethernet

Note 1: See Table 1-6 for I/O port pin descriptions.

2: BOR functionality is provided when the on-board voltage regulator is enabled.

PIC18F97J60 FAMILY

TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS

Pin Name

Pin Number

TQFP

Type

Buffer

Type

Description

MCLR

OSC1/CLKI

OSC1

CLKI

OSC2/CLKO

OSC2

CLKO

RA0/LEDA/AN0

RA0 LEDA AN0

RA1/LEDB/AN1

RA1 LEDB AN1

RA2/AN2/V

RA3/AN3/V

RA4/T0CKI

RA5/AN4

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

REF-

RA2 AN2

REF-

V

REF+

RA3 AN3

REF+

V

RA4 T0CKI

RA5 AN4

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

7 I ST Master Clear (Reset) input. This pin is an active-low Reset

to the device.

39

40

24

23

22

21

28

27

O

I/O

O

I/O

O

I/O

I

CMOS

I

Analog

I

Analog

I

Analog

I

Analog

I

Analog

I

Analog

I

Analog

Oscillator crystal or external clock input.

ST

—

TTL

—

TTL

—

TTL

ST ST

TTL

Oscillator crystal input or external clock source input. ST buffer when configured in internal RC mode; CMOS otherwise. External clock source input. Always associated with pin function OSC1. (See related OSC2/CLKO pin.)

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In Internal RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate.

PORTA is a bidirectional I/O port.

Digital I/O. Ethernet LEDA indicator output. Analog input 0.

Digital I/O. Ethernet LEDB indicator output. Analog input 1.

Digital I/O. Analog input 2. A/D reference voltage (low) input.

Digital I/O. Analog input 3. A/D reference voltage (high) input.

Digital I/O. Timer0 external clock input.

Digital I/O. Analog input 4.

DD)

PIC18F97J60 FAMILY

TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RB0/INT0/FLT0

RB0 INT0 FLT0

RB1/INT1

RB1 INT1

RB2/INT2

RB2 INT2

RB3/INT3

RB3 INT3

RB4/KBI0

RB4 KBI0

RB5/KBI1

RB5 KBI1

RB6/KBI2/PGC

RB6 KBI2 PGC

RB7/KBI3/PGD

RB7 KBI3 PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

Pin Number

TQFP

3

4

5

6

44

43

42

37

Type

I/O

I I

I/O

I

I/O

I

I/O

I

I/O

I

I/O

I

I/O

I

I/O

I

I/O

Buffer

Type

TTL

ST ST

TTL

ST

TTL

ST

TTL

ST

TTL TTL

ST

TTL TTL

ST

Description

PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.

Digital I/O. External interrupt 0. Enhanced PWM Fault input (ECCP modules); enabled in software.

Digital I/O. External interrupt 1.

Digital I/O. External interrupt 2.

Digital I/O. External interrupt 3.

Digital I/O. Interrupt-on-change pin.

Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP™ programming clock pin.

Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin.

DD)

PIC18F97J60 FAMILY

TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RC0/T1OSO/T13CKI

RC0 T1OSO T13CKI

RC1/T1OSI/ECCP2/P2A

RC1 T1OSI ECCP2 P2A

RC2/ECCP1/P1A

RC2 ECCP1 P1A

RC3/SCK1/SCL1

RC3 SCK1 SCL1

RC4/SDI1/SDA1

RC4 SDI1 SDA1

RC5/SDO1

RC5 SDO1

RC6/TX1/CK1

RC6 TX1 CK1

RC7/RX1/DT1

RC7 RX1 DT1

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

Pin Number

TQFP

30

29

33

34

35

36

31

32

Type

I/O

O

I

I/O

I

I/O

O

I/O I/O

O

I/O I/O I/O

I/O

I

I/O

O

I/O

O

I/O

I

I/O

Buffer

Type

ST

—

ST

CMOS

ST

—

ST ST

—

ST ST ST

ST

—

ST

—

ST

ST ST ST

Description

PORTC is a bidirectional I/O port.

Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input.

Digital I/O. Timer1 oscillator input. Capture 2 input/Compare 2 output/PWM2 output. ECCP2 PWM output A.

Digital I/O. Capture 1 input/Compare 1 output/PWM1 output. ECCP1 PWM output A.

Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I

Digital I/O. SPI data in. I2C data I/O.

Digital I/O. SPI data out.

Digital I/O. EUSART1 asynchronous transmit. EUSART1 synchronous clock (see related RX1/DT1 pin).

Digital I/O. EUSART1 asynchronous receive. EUSART1 synchronous data (see related TX1/CK1 pin).

2

C™ mode.

DD)

PIC18F97J60 FAMILY

TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RD0/P1B

RD0 P1B

RD1/ECCP3/P3A

RD1 ECCP3 P3A

RD2/CCP4/P3D

RD2 CCP4 P3D

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

Pin Number

TQFP

60

59

58

Type

I/O

O

I/O I/O

O

I/O I/O

O

Buffer

Type

ST

—

ST ST

—

ST ST

—

Description

PORTD is a bidirectional I/O port.

Digital I/O. ECCP1 PWM output B.

Digital I/O. Capture 3 input/Compare 3 output/PWM3 output. ECCP3 PWM output A.

Digital I/O. Capture 4 input/Compare 4 output/PWM4 output. CCP4 PWM output D.

DD)

PIC18F97J60 FAMILY

TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RE0/P2D

RE0 P2D

RE1/P2C

RE1 P2C

RE2/P2B

RE2 P2B

RE3/P3C

RE3 P3C

RE4/P3B

RE4 P3B

RE5/P1C

RE5 P1C

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

Pin Number

TQFP

2

1

64

63

62

61

Type

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

Buffer

Type

ST

—

ST

—

ST

—

ST

—

ST

—

ST

—

Description

PORTE is a bidirectional I/O port.

Digital I/O. ECCP2 PWM output D.

Digital I/O. ECCP2 PWM output C.

Digital I/O. ECCP2 PWM output B.

Digital I/O. ECCP3 PWM output C.

Digital I/O. ECCP3 PWM output B.

Digital I/O. ECCP1 PWM output C.

DD)

PIC18F97J60 FAMILY

TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RF1/AN6/C2OUT

RF1 AN6 C2OUT

RF2/AN7/C1OUT

RF2 AN7 C1OUT

RF3/AN8

RF3 AN8

RF4/AN9

RF4 AN9

RF5/AN10/CV

RF5 AN10 CVREF

RF6/AN11

RF6 AN11

RF7/SS1

RF7 SS1

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

REF

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD)

Pin Number

TQFP

17

16

15

14

13

12

11

Type

I/O

I

O

I/O

I

O

I/O

I

I/O

I

I/O

I

O

I/O

I

I/O

I

Buffer

Type

ST

Analog

—

ST

Analog

—

ST

Analog

ST

Analog

ST

Analog

—

ST

Analog

ST

TTL

Description

PORTF is a bidirectional I/O port.

Digital I/O. Analog input 6. Comparator 2 output.

Digital I/O. Analog input 7. Comparator 1 output.

Digital I/O. Analog input 8.

Digital I/O. Analog input 9.

Digital I/O. Analog input 10. Comparator reference voltage output.

Digital I/O. Analog input 11.

Digital I/O. SPI slave select input.

PIC18F97J60 FAMILY

TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

TQFP

RG4/CCP5/P1D

8

RG4 CCP5 P1D

V

SS 9, 25, 41, 56 P — Ground reference for logic and I/O pins.

DD 26, 38, 57 P — Positive supply for peripheral digital logic and I/O pins.

V

AVSS 20 P — Ground reference for analog modules.

DD 19 P — Positive supply for analog modules.

AV

ENVREG 18 I ST Enable for on-chip voltage regulator.

DDCORE/VCAP

V

10

VDDCORE

VCAP

SSPLL 55 P — Ground reference for Ethernet PHY PLL.

V

VDDPLL 54 P — Positive 3.3V supply for Ethernet PHY PLL.

SSTX 52 P — Ground reference for Ethernet PHY transmit subsystem.

V

VDDTX 49 P — Positive 3.3V supply for Ethernet PHY transmit subsystem.

SSRX 45 P — Ground reference for Ethernet PHY receive subsystem.

V

VDDRX 48 P — Positive 3.3V supply for Ethernet PHY receive subsystem.

RBIAS 53 I Analog Bias current for Ethernet PHY. Must be tied to V

TPOUT+ 51 O — Ethernet differential signal output.

TPOUT- 50 O — Ethernet differential signal output.

TPIN+ 47 I Analog Ethernet differential signal input.

TPIN- 46 I Analog Ethernet differential signal input.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

Type

I/O I/O

O

P

Buffer

Type

ST ST

—

Description

PORTG is a bidirectional I/O port.

Digital I/O. Capture 5 input/Compare 5 output/PWM5 output. ECCP1 PWM output D.

Core logic power or external filter capacitor connection.

Positive supply for microcontroller core logic (regulator disabled). External filter capacitor connection (regulator enabled).

SS via a resistor;

see Section 18.0 “Ethernet Module” for specification.

DD)

PIC18F97J60 FAMILY

TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS

Pin Name

Pin Number

TQFP

Typ e

Buffer

Type

Description

MCLR

OSC1/CLKI

OSC1

CLKI

OSC2/CLKO

OSC2

CLKO

RA0/LEDA/AN0

RA0 LEDA AN0

RA1/LEDB/AN1

RA1 LEDB AN1

RA2/AN2/V

RA3/AN3/V

RA4/T0CKI

RA5/AN4

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.

REF-

RA2 AN2

REF-

V

REF+

RA3 AN3

REF+

V

RA4 T0CKI

RA5 AN4

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

2: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 3: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 4: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).

9 I ST Master Clear (Reset) input. This pin is an active-low Reset to

the device.

49

50

30

29

28

27

34

33

O

I/O

O

I/O

O

I/O

I

CMOS

I

Analog

I

Analog

I

Analog

I

Analog

I

Analog

I

Analog

I

Analog

Oscillator crystal or external clock input.

ST

—

TTL

—

TTL

—

TTL

ST ST

TTL

Oscillator crystal input or external clock source input. ST buffer when configured in internal RC mode; CMOS otherwise. External clock source input. Always associated with pin function OSC1. (See related OSC2/CLKO pin.)

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In Internal RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate.

PORTA is a bidirectional I/O port.

Digital I/O. Ethernet LEDA indicator output. Analog input 0.

Digital I/O. Ethernet LEDB indicator output. Analog input 1.

Digital I/O. Analog input 2. A/D reference voltage (low) input.

Digital I/O. Analog input 3. A/D reference voltage (high) input.

Digital I/O. Timer0 external clock input.

Digital I/O. Analog input 4.

DD)

PIC18F97J60 FAMILY

TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RB0/INT0/FLT0

RB0 INT0 FLT0

RB1/INT1

RB1 INT1

RB2/INT2

RB2 INT2

RB3/INT3

RB3 INT3

RB4/KBI0

RB4 KBI0

RB5/KBI1

RB5 KBI1

RB6/KBI2/PGC

RB6 KBI2 PGC

RB7/KBI3/PGD

RB7 KBI3 PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.

2: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 3: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 4: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).

Pin Number

TQFP

5

6

7

8

54

53

52

47

Typ e

I/O

I I

I/O

I

I/O

I

I/O

I

I/O

I

I/O

I

I/O

I

I/O

I

I/O

Buffer

Type

TTL

ST ST

TTL

ST

TTL

ST

TTL

ST

TTL TTL

ST

TTL TTL

ST

Description

PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.

Digital I/O. External interrupt 0. Enhanced PWM Fault input (ECCP modules); enabled in software.

Digital I/O. External interrupt 1.

Digital I/O. External interrupt 2.

Digital I/O. External interrupt 3.

Digital I/O. Interrupt-on-change pin.

Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP™ programming clock pin.

Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin.

DD)

PIC18F97J60 FAMILY

TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RC0/T1OSO/T13CKI

RC0 T1OSO T13CKI

RC1/T1OSI/ECCP2/P2A

RC1 T1OSI

(1)

ECCP2

(1)

P2A

RC2/ECCP1/P1A

RC2 ECCP1 P1A

RC3/SCK1/SCL1

RC3 SCK1 SCL1

RC4/SDI1/SDA1

RC4 SDI1 SDA1

RC5/SDO1

RC5 SDO1

RC6/TX1/CK1

RC6 TX1 CK1

RC7/RX1/DT1

RC7 RX1 DT1

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.

2: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 3: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 4: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).

Pin Number

TQFP

36

35

43

44

45

46

37

38

Typ e

I/O

O

I

I/O

I

I/O

O

I/O I/O

O

I/O I/O I/O

I/O

I

I/O

O

I/O

O

I/O

I

I/O

Buffer

Type

ST

—

ST

CMOS

ST

—

ST ST

—

ST ST ST

ST

—

ST

—

ST

ST ST ST

Description

PORTC is a bidirectional I/O port.

Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input.

Digital I/O. Timer1 oscillator input. Capture 2 input/Compare 2 output/PWM2 output. ECCP2 PWM output A.

Digital I/O. Capture 1 input/Compare 1 output/PWM1 output. ECCP1 PWM output A.

Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I

Digital I/O. SPI data in. I2C data I/O.

Digital I/O. SPI data out.

Digital I/O. EUSART1 asynchronous transmit. EUSART1 synchronous clock (see related RX1/DT1 pin).

Digital I/O. EUSART1 asynchronous receive. EUSART1 synchronous data (see related TX1/CK1 pin).

2

C™ mode.

DD)

PIC18F97J60 FAMILY

TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RD0 72 I/O ST Digital I/O.

RD1 69 I/O ST Digital I/O.

RD2 68 I/O ST Digital I/O.

RE0/P2D

RE0 P2D

RE1/P2C

RE1 P2C

RE2/P2B

RE2 P2B

RE3/P3C

RE3

(2)

P3C

RE4/P3B

RE4

(2)

P3B

RE5/P1C

RE5

(2)

P1C

RE6/P1B

RE6

(2)

P1B

RE7/ECCP2/P2A

RE7

(3)

ECCP2

(3)

P2A

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.

2: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 3: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 4: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).

Pin Number

TQFP

4

3

78

77

76

75

74

73

Typ e

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

I/O I/O

O

Buffer

Type

ST

—

ST

—

ST

—

ST

—

ST

—

ST

—

ST

—

ST ST

—

Description

PORTD is a bidirectional I/O port.

PORTE is a bidirectional I/O port.

Digital I/O. ECCP2 PWM output D.

Digital I/O. ECCP2 PWM output C.

Digital I/O. ECCP2 PWM output B.

Digital I/O. ECCP3 PWM output C.

Digital I/O. ECCP3 PWM output B.

Digital I/O. ECCP1 PWM output C.

Digital I/O. ECCP1 PWM output B.

Digital I/O. Capture 2 input/Compare 2 output/PWM2 output. ECCP2 PWM output A.

DD)

PIC18F97J60 FAMILY

TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RF1/AN6/C2OUT

RF1 AN6 C2OUT

RF2/AN7/C1OUT

RF2 AN7 C1OUT

RF3/AN8

RF3 AN8

RF4/AN9

RF4 AN9

RF5/AN10/CV

RF5 AN10 CVREF

RF6/AN11

RF6 AN11

RF7/SS1

RF7 SS1

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.

REF

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD)

2: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 3: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 4: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).

Pin Number

TQFP

23

18

17

16

15

14

13

Typ e

I/O

I

O

I/O

I

O

I/O

I

I/O

I

I/O

I

O

I/O

I

I/O

I

Buffer

Type

ST

Analog

—

ST

Analog

—

ST

Analog

ST

Analog

ST

Analog

—

ST

Analog

ST

TTL

Description

PORTF is a bidirectional I/O port.

Digital I/O. Analog input 6. Comparator 2 output.

Digital I/O. Analog input 7. Comparator 1 output.

Digital I/O. Analog input 8.

Digital I/O. Analog input 9.

Digital I/O. Analog input 10. Comparator reference voltage output.

Digital I/O. Analog input 11.

Digital I/O. SPI slave select input.

PIC18F97J60 FAMILY

TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

RG0/ECCP3/P3A

RG0 ECCP3 P3A

RG1/TX2/CK2

RG1 TX2 CK2

RG2/RX2/DT2

RG2 RX2 DT2

RG3/CCP4/P3D

RG3 CCP4 P3D

RG4/CCP5/P1D

RG4 CCP5 P1D

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to V

Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.

2: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 3: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 4: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).

Pin Number

TQFP

56

55

42

41

10

Typ e

I/O I/O

O

I/O

O

I/O

I

I/O

I/O I/O

O

I/O I/O

O

Buffer

Type

ST ST

—

ST

—

ST

ST ST ST

ST ST

—

ST ST

—

Description

PORTG is a bidirectional I/O port.

Digital I/O. Capture 3 input/Compare 3 output/PWM3 output. ECCP3 PWM output A.

Digital I/O. EUSART2 asynchronous transmit. EUSART2 synchronous clock (see related RX2/DT2 pin).

Digital I/O. EUSART2 asynchronous receive. EUSART2 synchronous data (see related TX2/CK2 pin).

Digital I/O. Capture 4 input/Compare 4 output/PWM4 output. ECCP3 PWM output D.

Digital I/O. Capture 5 input/Compare 5 output/PWM5 output. ECCP1 PWM output D.

DD)

MICROCHIP PIC18F97J60 DATA SHEET

Ethernet Features:

Flexible Oscillator Structure:

External Memory Bus (100-pin devices only):

Peripheral Highlights:

Special Microcontroller Features:

Pin Diagrams

Pin Diagrams (Continued)

Pin Diagrams (Continued)

Table of Contents

Most Current Data Sheet

Errata

Customer Notification System

1.0 DEVICE OVERVIEW

1.1 Core Features

1.1.1 OSCILLATOR OPTIONS AND FEATURES

1.1.2 EXPANDED MEMORY

1.1.3 EXTERNAL MEMORY BUS

1.1.4 EXTENDED INSTRUCTION SET

1.1.5 EASY MIGRATION

1.2 Other Special Features

1.3 Details on Individual Family Members

TABLE 1-1: DEVICE FEATURES FOR THE PIC18F97J60 FAMILY (64-PIN DEVICES)

TABLE 1-2: DEVICE FEATURES FOR THE PIC18F97J60 FAMILY (80-PIN DEVICES)

TABLE 1-3: DEVICE FEATURES FOR THE PIC18F97J60 FAMILY (100-pin DEVICES)

FIGURE 1-1: PIC18F66J60/66J65/67J60 (64-PIN) BLOCK DIAGRAM

FIGURE 1-2: PIC18F86J60/86J65/87J60 (80-PIN) BLOCK DIAGRAM

FIGURE 1-3: PIC18F96J60/96J65/97J60 (100-PIN) BLOCK DIAGRAM

TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS

TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS