MICROCHIP PIC18F6585, PIC18F8585, PIC18F6680, PIC18F8680 DATA SHEET

PIC18F6585/8585/6680/8680

Data Sheet

64/68/80-Pin High-Performance,

64-Kbyte Enhanced Flash

Microcontrollers with ECAN Module

 2004 Microchip Technology Inc. DS30491C

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously impro ving the cod e protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K

EELOQ, MPLAB, PIC, PICmic ro, PI C START,

PRO MATE, PowerSmart and rfPIC are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.

AmpLab, FilterLab, microID, MXDEV, MXLA B, PICMASTER,
SEEVAL, SmartShunt and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.

Application Maestro, dsPICDEM, dsPICDEM.net,
dsPICworks, ECAN, ECONOMONITOR, FanSense,
FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP,
ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK,
MPSIM, PICkit, PICDEM, PICDEM.net, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, rfLAB, Select Mode,
SmartSensor, SmartTel and Total Endurance are trademarks
of Microchip Technology Incorporated in the U.S.A. and other
countries.

Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip re cei v ed I S O/T S - 16 949 : 20 02 qu ality system c er ti f ic at io n f or
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in October

2003. The Com pany’s quality sy stem proces ses and pro cedures are for
its PICmicro
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.

®

8-bit MCUs, KEELOQ

®

code hopping devices, Serial

DS30491C-page ii  2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash

Microcontrollers with ECAN Module

High-Performance RISC CPU:

• Source code compatible with the PIC16 and
PIC17 instruction sets

• Linear program memory addressing to 2 Mbytes

• Linear data memory addr essing to 4096 bytes

• 1 Kbyte of data EEPROM

• Up to 10 MIPs operation:

- DC – 40 MHz osc./clock input

- 4 MHz-10 MHz osc./clock input with PLL active

• 16-bit wide instructions, 8-bit wide data path

• Priority levels for interrupts

• 31-level, so ftware accessible hardware stack

• 8 x 8 Single-Cycle Hardware Multiplier

External Memory Interface (PIC18F8X8X Devices Only):

• Address c apability of up to 2 Mbytes

• 16-bit interface

Peripheral Features:

• High current sink/source 25 mA/25 mA

• Four ext ernal inte rrupt pins

• Timer0 module: 8-bit/16-bit timer/counter

• Timer1 module: 16-bit timer/counter

• Timer2 module: 8-bit timer/counter

• Timer3 module: 16-bit timer/counter

• Secondary oscillator clock option – Timer1/Timer3

• One Capture/Compare/PWM (CCP) module:

- Capture is 16-bit, max. resolution 6.25 ns

(T

CY/16)

- Compare is 16-bit, max. resolution 100 ns (T

- PWM output: PWM resolution is 1 to 10-bit

• Enhanced Capture/Compare/PWM (ECCP) module:

- Same Ca pture/Compare featur es as CCP

- One, two or four PWM outputs

- Selectable polarity

- Programmable dead time

- Auto-shutdown on external event

- Auto-restart

• Master Synchronous Serial Port (MSSP) module
with two modes of operation:

- 3-wire SPI™ (supports all 4 SPI modes)

2

-I

C™ Master and Slave mode

• Enhanced Addressable USART module:

- Supports RS-232, RS-485 and LIN 1.2

- Programmable wake-up on Start bit

- Auto-baud detect

• Parallel Slave Port (PSP) module

CY)

Analog Features:

• Up to 16-channel, 10-bit Analog-to-Digital
Converter module (A/D) with:

- Fast sampling rate

- Programmable acquisition time

- Conversion available during Sleep

• Programmable 16-level Low-Voltage Detection
(LVD) module:

- Supports interrupt on Low-Voltage Detection

• Programmable Brown-out Reset (BOR)

• Dual analog comparators:

- Programmable input/output configuration

ECAN Module Features:

• Message bit rates up to 1 Mbps

• Conforms to CAN 2.0B ACTIVE Specification

• Fully backward compatible with PIC18XXX8 CAN
modules

• Three modes of operation:

- Legacy, Enhanced Legacy, FIFO

• Three dedicated tra ns mi t bu f f ers with prioritization

• Two dedicated receive buffers

• Six programmable receive/transmit buffers

• Three full 29-bit acceptance masks

• 16 full 29-bit accept ance filt ers with dy namic asso ciatio n

• DeviceNet™ data byte filter support

• Automatic remote frame handling

• Advanced Error Management features

Special Microcontroller Features:

• 100,000 erase/write cycl e Enhan ced Flas h
program memory typical

• 1,000,000 erase/write cycle Data EEPROM
memory typical

• 1-second programming time

• Flash/Data EEPROM Retention: > 40 years

• Self-reprogrammable under software control

• Power-on Reset (POR), Power-up Timer (PWR T)
and Oscillator Start-up Timer (OST)

• Watchdog Timer (WDT) with its own On-Chip
RC Oscillator

• Programmable code protection

• Power saving Sleep mode

• Selectable oscillator options including:

- Software enabled 4x Phase Lock Loop (of

primary oscillator)

- Secondary Oscillator (32 kHz) clock input

• In-Circuit Serial Programming™ (ICSP™) via two pins

• MPLAB

®

In-Circuit Debug (ICD) via two pins

 2004 Microchip Technology Inc. DS30491C-page 1

PIC18F6585/8585/6680/8680

CMOS Technology:

• Low-power, high-speed Flash technology

• Fully static design

• Wide operating voltage range (2.0V to 5.5V)

• Industrial and Extended tempera ture ranges

Program Memory Data Memory

Device

PIC18F6585 48K 24576 3328 1024 53 12 1/1 Y Y Y/Y 2/3 N
PIC18F6680 64K 32768 3328 1024 53 12 1/1 Y Y Y/Y 2/3 N
PIC18F8585 48K 24576 3328 1024 69 16 1/1 Y Y Y/Y 2/3 Y
PIC18F8680 64K 32768 3328 1024 69 16 1/1 Y Y Y/Y 2/3 Y

Bytes

# Single-Word

Instructions

SRAM

(bytes)

EEPROM

(bytes)

I/O

10-bit

A/D (ch)

CCP/

ECCP

(PWM)

SPI

MSSP

Master

I

2

C

ECAN/

AUSART

Timers

8-bit/16-bit

EMA

DS30491C-page 2  2004 Microchip Technology Inc.

Pin Diagrams

64-Pin TQFP

PIC18F6585/8585/6680/8680

(1)

RE2/CS

RE3

RE4

RE5/P1C

RE6/P1B

RE7/CCP2

RD0/PSP0

VDDVSS

RD1/PSP1

RD2/PSP2

RD3/PSP3

RD4/PSP4

RD5/PSP5

RD6/PSP6

RD7/PSP7

RE1/WR

RE0/RD
RG0/CANTX1
RG1/CANTX2

RG2/CANRX

RG5/MCLR

RG4/P1D

RF7/SS

RF6/AN11/C1IN-

RF5/AN10/C1IN+/CV

RF4/AN9/C2IN-

RF3/AN8/C2IN+

RF2/AN7/C1OUT

RG3
/VPP

VSS
VDD

REF

64

63 62 61

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

17 18 19 20 21 22 23 24 25 26

DD

AV

RF0/AN5

RF1/AN6/C2OUT

PIC18F6X8X

REF-

AVSS

RA2/AN2/V

RA3/AN3/VREF+

RA1/AN1

54 53 52 5158 57 56 5560 59

27 28

SS

V

VDD

RA0/AN0

RA5/AN4/LVDIN

50 49

31

29 30 32

(1)

RA4/T0CKI

RC1/T1OSI/CCP2

RC0/T1OSO/T13CKI

RC6/TX/CK

RC7/RX/DT

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC

SS

V
OSC2/CLKO/RA6
OSC1/CLKI

DD

V
RB7/KBI3/PGD
RC5/SDO
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1/P1A

Note 1: CCP2 pin placement depends on CCP2MX setting.

 2004 Microchip Technology Inc. DS30491C-page 3

PIC18F6585/8585/6680/8680

Pin Diagrams (Continued)

68-Pin PLCC

(1)

RE1/WR

RE0/RD
RG0/CANTX1
RG1/CANTX2

RG2/CANRX

RG5/MCLR

RG4/P1D

RF7/SS

RF6/AN11/C1IN-

RF5/AN10/C1IN+/CV

RF4/AN9/C2IN-

RF3/AN8/C2IN+

RF2/AN7/C1OUT

RG3
/VPP

N/C

SS

V

VDD

REF

RE2/CS

RE3

RE4

RE5/P1C

RE6/P1B

RE7/CCP2

9 8 7 6 5 4 3 2 1 6867666564636261

10
11

12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

2728 2930 3132 33 34 35 36 37 38 39 40 41 42 43

DD

AVSS

AV

RF0/AN5

RA2/AN2/VREF-

RF1/AN6/C2OUT

RA3/AN3/VREF+

N/C

RD0/PSP0

VDDVSS

Top View

PIC18F6X8X

SS

V

N/C

RA1/AN1

RA0/AN0

RD1/PSP1

RD2/PSP2

RD3/PSP3

DD

V

RA4/T0CKI

RA5/AN4/LVDIN

(1)

RD4/PSP4

RC1/T1OSI/CCP2

RD5/PSP5

RD6/PSP6

RC0/T1OSO/T13CKI

RC6/TX/CK

RD7/PSP7

RC7/RX/DT

60
59

58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
V

SS

N/C
OSC2/CLKO/RA6

OSC1/CLKI

DD

V
RB7/KBI3/PGD
RC5/SDO
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1/P1A

Note 1: CCP2 pin placement depends on CCP2MX setting.

DS30491C-page 4  2004 Microchip Technology Inc.

Pin Diagrams (Continued)

80-Pin TQFP

RH2/A18
RH3/A19

RE1/WR/AD9

RE0/RD

/AD8
RG0/CANTX1
RG1/CANTX2

RG2/CANRX

RG3

RG5/MCLR

/VPP

RG4/P1D

VSS
VDD

RF7/SS

RF6/AN11/C1IN-

RF5/AN10/C1IN+/CVREF

RF4/AN9/C2IN-

RF3/AN8/C2IN+

RF2/AN7/C1OUT

RH7/AN15/P1B

RH6/AN14/P1C

(3)
(3)

1
2

3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

PIC18F6585/8585/6680/8680

(3)

(3)

/AD15

/AD0

(2)

(1)

DD

RE2/CS/AD10

RE3/AD11

RE4/AD12

RH0/A16

RH1/A17

80

78

79

RE5/AD13/P1C

77 76 75

21 22 23 24 25 26 27 28 29 30 31 32

RD0/PSP0

RE6/AD14/P1B

RE7/CCP2

V

PIC18F8X8X

VSS

/AD1

(1)

RD1/PSP1

/AD2

(1)

RD2/PSP2

68 67 66 6572 71 70 6974 73

33 34

/AD3

(1)

RD3/PSP3

/AD4

(1)

RD4/PSP4

35 36

/AD5

/AD6

(1)

(1)

(1)

RD5/PSP5

RD6/PSP6

64 63 62 61

37

38

/AD7

RD7/PSP7

39

RJ0/ALE

RJ1/OE

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

RJ2/WRL
RJ3/WRH
RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3/CCP2
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
V

SS

OSC2/CLKO/RA6
OSC1/CLKI
V

DD

RB7/KBI3/PGD
RC5/SDO
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1/P1A
RJ7/UB
RJ6/LB

(2)

40

DD

AV

RH5/AN13

RF0/AN5

RH4/AN12

RF1/AN6/C2OUT

REF-

AVSS

RA2/AN2/V

RA3/AN3/VREF+

SS

V

RA1/AN1

RA0/AN0

(2)

VDD

RJ5/CE

RA4/T0CKI

RC6/TX/CK

RJ4/BA0

RC7/RX/DT

RA5/AN4/LVDIN

RC1/T1OSI/CCP2

RC0/T1OSO/T13CKI

Note 1: PSP is available only in Microcontroller mode.

2: CCP2 pin placement depends on CCP2MX and Processor mode settings.
3: P1B and P1C pin placement depends on ECCPMX setting.

 2004 Microchip Technology Inc. DS30491C-page 5

PIC18F6585/8585/6680/8680

Table of Contents

1.0 Device Overview..........................................................................................................................................................................9

2.0 Oscillator Configurations........ ....................................................................................................................................................23

3.0 Reset..........................................................................................................................................................................................33

4.0 Memory Organization.................................................................................................................................................................51

5.0 Flash Program Memory............... ...................................... ................................................... ...................................................... 83

6.0 External Memory Interface.........................................................................................................................................................93

7.0 Data EEPROM Memory....................... ......................... ......................... ..................................................................................101

8.0 8 x 8 Hardware Multiplier.......................................................................................................................................................... 107

9.0 Interrupts..................................................................................................................................................................................109

10.0 I/O Ports........................................... ......................... ......................... ......................................................................................125

11.0 Timer0 Module .........................................................................................................................................................................155

12.0 Timer1 Module .........................................................................................................................................................................159

13.0 Timer2 Module .........................................................................................................................................................................162

14.0 Timer3 Module .........................................................................................................................................................................164

15.0 Capture/Compare/PWM (CCP) Modules .................................................................................................................................167

16.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 175

17.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 189

18.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (USART)..................................................................229

19.0 10-bit Analog-to-Digital Converter (A/D) Module......................................................................................................................249

20.0 Comparator Module............................................................................................. .... .. .... .. ......................................................... 259

21.0 Comparator Voltage Reference Module.................................. ....... .... .. .... .. ....... .... .. .... .. .... ....... .. .............................................. 265

22.0 Low-Voltage Detect..................................................................................................................................................................269

23.0 ECAN Module..................................... .. .. .. .. .. .. .. .. ..... .. .... .. .. .. .. .. ..... .. .. .. .. .. .. .. .. ..... .. .. .. .. .. .. ...........................................................275

24.0 Special Features of the CPU......................................................................................... ........................................................... 345

25.0 Instruction Set Summary ..........................................................................................................................................................365

26.0 Development Support. .............................................................................................................................................................. 407

27.0 Electrical Characteristics..........................................................................................................................................................413

28.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 449

29.0 Packaging Information....................................................... ....................................................................................................... 465

Appendix A: Revision History............................................................................................................................................................. 469

Appendix B: Device Differences......................................................................................................................................................... 469

Appendix C: Conversion Considerations .................................................................... .... .. .... .. .... ....................................................... 470

Appendix D: Migration from Mid-Range to Enhanced Devices.......................................................................................................... 470

Appendix E: Migration from High-End to Enhanced Devices.............................................................................................................471

Index .................................................................................................................................................................................................. 473

On-Line Support........................................................................ .... .. ......... .... .. .... .... ....... .... ................................................................. 487

Systems Information and Upgrade Hot Line......................................................................................................................................487

Reader Response..............................................................................................................................................................................488

PIC18F6585/8585/6680/8680 Product Identification System ............................................................................................................ 489

DS30491C-page 6  2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications t o better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.

If you have any questions or c omm ents regarding t his publication, p lease c ontact the M arket ing Co mmunications Department via
E-mail at [e-mail] or fax the Reader Response Form in the back of this data sheet to [phone].
We welcome your feedback.

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You can determ ine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:

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 2004 Microchip Technology Inc. DS30491C-page 7

PIC18F6585/8585/6680/8680

NOTES:

DS30491C-page 8  2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

1.0 DEVICE OVERVIEW

All other features for devices in the
PIC18F6585/8585/6680/8680 family are identical.

This documen t conta i ns dev ic e spec if i c in for m at i on fo r
the following devices:

• PIC18F6585 • PIC18F8585

• PIC18F6680 • PIC18F8680

PIC18F6X8X devices are av ailable in 64-pin TQFP an d

These are summarized in Table 1-1.
Block diagrams of the PIC18F6X8X and PIC18F8X8X

devices are provided in Figure 1-1 and Figure 1-2,
respectively. The pinouts for these device families are
listed in Table 1-2.

68-pin PLCC packages. PIC18F8X8X devices are
available in the 80-pin TQFP package. They are
differentiated from each other in four way s :

1. Flash program memory (48 Kbytes for
PIC18FX585 devices, 64Kbytes for
PIC18FX680)

2. A/D channels (1 2 for PIC18F6X8X devices,
16 for PIC1 8F8X8X)

3. I/O ports (7 on PIC18F6X8X devices, 9 on
PIC18F8X8X)

4. External program memory interface (present
only on PIC18F8X8X devices)

T ABLE 1-1: PIC18F6585/8585/6680/8680 DEVICE FEATURES

Features PIC18F6585 PIC18F6680 PIC18F8585 PIC18F8680

Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz

DC–25MHzw/EMA
Program Memory (Bytes) 48K 64K 48K (2 MB EMA) 64K (2 MB EMA)
Program Memory (Instructions) 24576 32768 24576 32768
Data Memory (Bytes) 3328 3328 3328 3328
Data EEPROM Memory (Bytes) 1024 1024 1024 10 24
External Memory Interface No No Yes Yes
Interrupt Sourc e s 29 29 29 29
I/O Ports Ports A
Timers 4 4 4 4
Capture/Compare/PWM M odule 1 1 1 1
Enhanced Capture/Compare/PWM

Module
Serial Communications MSSP,

Enhanced AUSAR T ,

Parallel Communications PSP PSP PSP
10-bit Analog-to-Digital Module 12 input cha nnels 12 input ch annels 16 inp ut cha nnels 16 inpu t chan nels
Resets (and Delays) POR, BOR,

RESET Instruction,

Stack Underflow

(PWRT, OST)
Programmable Low-Voltage Detect Y es Yes Yes Yes
Programmable Brown-out Reset Yes Yes Yes Yes
Instruction Set 75 Instructions 75 Instruc tions 75 Instructions 75 Instructions
Package 64-pin TQFP,

68-pin PLCC

Note 1: PSP is only available in Microcontroller mode.

-G Ports A-GPorts A-H, J Ports A-H, J

11 1 1

ECAN

Stack Full,

MSSP,

Enhanced AUSAR T,

ECAN

POR, BOR,

RESET Instruction,

Stack Full,

Stack Underflow

(PWRT, OST)

64-pin TQFP ,

68-pin PLCC

MSSP,

Enhanced AUSART,

ECAN

(1)

POR, BOR,

RESET Instruction,

Stack Full,

Stack Underflow

(PWRT, OST)

80-pin TQFP 80-pin TQFP

DC–40MHz

DC – 25 MHz w/EMA

MSSP,

Enhanced AUSAR T,

ECAN

(1)

PSP

POR, BOR,

RESET Instruction,

Stack Full,

Stack Underflow

(PWRT, OST)

 2004 Microchip Technology Inc. DS30491C-page 9

PIC18F6585/8585/6680/8680

FIGURE 1-1: PIC18F6X8X BLOCK DIAGRAM

Data Bus<8>

21

Address Latch

Program Memory

(48 Kbytes)

Data Latch

OSC2/CLKO/RA6
OSC1/CLKI

Table Pointer<21>

21

21

Instruction

Decode &

Control

Timing

Generation

Precision

Band Gap
Reference

inc/dec logic

Table Latch

16

PCLATH

PCLATU

PCU

PCH PCL

Program Counter

31 Level Stack

8

ROM Latch

IR

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Te st Mode

Select

8

8

Decode

BITOP

4
BSR

3

8

Data Latch

Data RAM

(3328 bytes)

Address Latch

12

Address<12>

12 4

FSR0
FSR1
FSR2

inc/dec

logic

8 x 8 Multiply

W

8

8

ALU<8>

8

Bank0, F

PRODLPRODH

PORTA

RA0/AN0
RA1/AN1
RA2/AN2/VREF­RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/LVDIN

PORTB

12

PORTC

PORTD

8

PORTE

8

8

PORTF

OSC2/CLKO/RA6

RB2/INT2:RB0/INT0
RB3/INT3
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD

RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2
RC2/CCP1/P1A
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT

RD7/PSP7

RE0/RD
RE1/WR
RE2/CS
RE3
RE4
RE5/P1C
RE6/P1B
RE7/CCP2

RF0/AN5
RF1/AN6/C2OUT
RF2/AN7/C1OUT
RF3/AN8/C2IN+
RF4/AN9/C2IN­RF5/AN10/C1IN+/CVREF
RF6/AN11/C1IN­RF7/SS

(1)

:RD0/PSP0

(1)

BOR

LVD

Timer0

ECCP1

Timer1

CCP2

RG5/

MCLR

AUSARTComparator

DD, VSS

V

Timer2

Timer3

ECAN Module

Synchronous

Serial Port

PORTG

10-bit

ADC

RG0/CANTX1
RG1/CANTX2
RG2/CANRX
RG3
RG4/P1D
RG5/MCLR/VPP

Data EEPROM

Note 1: The CCP2 pin placement depends on the CCP2MX and Processor mode settings.

DS30491C-page 10  2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

FIGURE 1-2: PIC18F8X8X BLOCK DIAGRAM

AD7:AD0

Address Latch

Program Memory

(64 Kbytes)

Data Latch

System Bus Interface

A16, AD15:AD8

OSC2/CLKO/RA6
OSC1/CLKI

BOR

LVD

21

Generation

Timer0

Table Pointer<21>

21

21

16

Instruction
Decode &

Control

Timing

Precision

Band Gap
Reference

inc/dec logic

PCLATU

Table Latch

8

RG5/

MCLR

Timer1

8

PCLATH

PCU

PCH PCL

Program Counter

31 Level Stack

ROM Latch

IR

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Test Mode

Select

V

DD, VSS

Timer2

8

BSR

Decode

BITOP

RJ0/ALE

RJ1/OE

RJ2/WRL

RJ3/WRH

RJ4/BA0

RJ5/CE

RJ6/LB
RJ7/UB

Timer3

4

3

8

Data Bus<8>

Data Latch

Data RAM

(3328 bytes)

Address Latch

12

Address<12>

12 4

FSR0
FSR1
FSR2

inc/dec

logic

8 x 8 Multiply

W

8

8

ALU<8>

8

PORTJ

Bank0, F

PRODLPRODH

PORTA

RA0/AN0
RA1/AN1
RA2/AN2/VREF­RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/LVDIN

PORTB

12

PORTC

PORTD

8

PORTE

8

8

PORTF

PORTG

PORTH

OSC2/CLKO/RA6

RB2/INT2:RB0/INT0
RB3/INT3/CCP2
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD

RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2
RC2/CCP1/P1A
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT

RD7/PSP7
RD0/PSP0/AD0

RE0/RD/AD8

RE1/WR/AD9
RE2/CS/AD10
RE3/AD11
RE4/AD12
RE5/AD13/P1C
RE6/AD14/P1B
RE7/CCP2

RF0/AN5

RF1/AN6/C2OUT

RF2/AN7/C1OUT

RF3/AN8/C2IN+

RF4/AN9/C2IN-

RF5/AN10/C1IN+/CVREF

RF6/AN11/C1IN-

RF7/SS

RG0/CANTX1
RG1/CANTX2
RG2/CANRX

RG3
RG4/P1D

RG5/MCLR/VPP

RH7/AN15/P1B

RH6/AN14/P1C

RH5/AN13

RH4/AN12

RH3/A19:RH0/A16

/AD7:

(1)

/AD15

(1)

(1)

(2)
(2)

(2)
(2)

ECCP1

CCP2

AUSARTComparator

ECAN Module

Synchronous

Serial Port

10-bit

ADC

Note 1: The CCP2 pin placement depends on the CCP2MX and Processor mode settings.

2: P1B and P1C pin placement depends on the ECCPMX setting.

 2004 Microchip Technology Inc. DS30491C-page 11

PIC18F6585/8585/6680/8680

TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS

Pin Number

Pin Name

Pin

Type

TQFP PLCC TQFP

Buffer

Type

DescriptionPIC18F6X8X PIC18F8X8X

RG5/MCLR

RG5
MCLR

VPP

OSC1/CLKI

OSC1

CLKI

OSC2/CLKO/RA6

OSC2

CLKO

RA6

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only.

/VPP

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X8X devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices.
6: PSP is available in Microcontroller mode only.
7: On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX

configuration bit.

716 9

39 50 49

40 51 50

I
I

P

IICMOS/ST

O

O

I/O

ST
ST

CMOS

TTL

Master Clear (input) or programming
voltage (input).

General purpose input pin.
Master Clear (Reset ) in pu t. This pin is
an active-low Reset to the device.
Programming voltage inp ut.

Oscillator crystal or external clock input.

Oscillator crystal input or external clock
source input. ST buffer when configured
in RC mode; otherwise CMOS.

External cloc k source input. Always
associated with pin function OSC1
(see OSC1/CLKI, OSC2/CLKO pins).

Oscillator crystal or clock output.

—

—

Oscillator crystal output.

Connects to crystal or resonator in

Crystal Oscillator mode.

In RC mode, OSC2 pi n o utpu ts CLKO

which has 1/4 the frequency of OSC1

and denotes the instruction cycle rate.

General purpose I/O pin.

DD)

DS30491C-page 12  2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

T ABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

TQFP PLCC TQFP

RA0/AN0

RA0
AN0

RA1/AN1

RA1
AN1

RA2/AN2/V

RA2
AN2
V

RA3/AN3/VREF+

RA3
AN3
V

RA4/T0CKI

RA4
T0CKI

RA5/AN4/LVDIN

RA5
AN4
LVDIN

RA6 See the OSC2/CLKO/RA6 pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

Note 1: Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only.

REF-

REF-

REF+

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X8X devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices.
6: PSP is available in Microcontroller mode only.
7: On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX

configuration bit.

24 34 30

23 33 29

22 32 28

21 31 27

28 39 34

27 38 33

Pin

Type

I/O

I/O

I/O

I/O

I/OIST/OD

I/O

Buffer

Type

PORTA is a bidirectional I/O port.

TTL

I

Analog

TTL

I

Analog

TTL

I

Analog

I

Analog

TTL

I

Analog

I

Analog

ST

TTL

I

Analog

I

Analog

Digital I/O.
Analog input 0.

Digital I/O.
Analog input 1.

Digital I/O.
Analog input 2.
A/D reference voltage (Low) input.

Digital I/O.
Analog input 3.
A/D reference voltage (High) input.

Digital I/O – Open-drain when
configured as output.
Timer0 external clock input.

Digital I/O.
Analog input 4.
Low-voltage detect input.

DescriptionPIC18F6X8X PIC18F8X8X

DD)

 2004 Microchip Technology Inc. DS30491C-page 13

PIC18F6585/8585/6680/8680

TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

TQFP PLCC TQFP

RB0/INT0

RB0
INT0

RB1/INT1

RB1
INT1

RB2/INT2

RB2
INT2

RB3/INT3/CCP2

RB3
INT3

(1)

CCP2

RB4/KBI0

RB4
KBI0

RB5/KBI1/PGM

RB5
KBI1
PGM

RB6/KBI2/PGC

RB6
KBI2
PGC

RB7/KBI3/PGD

RB7
KBI3
PGD

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

Note 1: Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only.

2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X8X devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices.
6: PSP is available in Microcontroller mode only.
7: On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX

configuration bit.

48 60 58

47 59 57

46 58 56

45 57 55

44 56 54

43 55 53

42 54 52

37 48 47

Pin

Type

I/O

I/O

I/O

I/O
I/O
I/O

I/O

I/O
I/O

I/O
I/O

I/O
I/O

Buffer

Type

PORTB is a bidirectional I/O port. PORTB
can be software programmed for internal
weak pull-ups on all inputs.

TTL

I

I

I

I

I

I

ST

TTL

ST

TTL

ST

TTL

ST
ST

TTL

ST

TTL

ST
ST

TTL

ST
ST

TTL

ST

Digital I/O.

External interrupt 0.

Digital I/O.

External interrupt 1.

Digital I/O.

External interrupt 2.

Digital I/O.

External interrupt 3.

Capture 2 input/Compare 2 output/

PWM 2 output.

Digital I/O.

Interrupt-on-change pin.

Digital I/O.

Interrupt-on-change pin.

Low-Voltage ICSP Programming

enable pin.

Digital I/O.

Interrupt-on-change pin.

In-circuit debugger and ICSP

programming clock.

Digital I/O.

Interrupt-on-change pin.

In-circuit debugger and ICSP

programming data.

DescriptionPIC18F6X8X PIC18F8X8X

DD)

DS30491C-page 14  2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

T ABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

TQFP PLCC TQFP

RC0/T1OSO/T13CKI

RC0
T1OSO
T13CKI

RC1/T1OSI/CCP2

RC1
T1OSI

(1, 4)

CCP2

RC2/CCP1/P1A

RC2
CCP1
P1A

RC3/SCK/SCL

RC3
SCK

SCL

RC4/SDI/SDA

RC4
SDI
SDA

RC5/SDO

RC5
SDO

RC6/TX/CK

RC6
TX
CK

RC7/RX/DT

RC7
RX
DT

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

Note 1: Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only.

2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X8X devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices.
6: PSP is available in Microcontroller mode only.
7: On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX

configuration bit.

30 41 36

29 40 35

33 44 43

34 45 44

35 46 45

36 47 46

31 42 37

32 43 38

Pin

Type

I/O

I/O
I/O

I/O
I/O
I/O

I/O
I/O

I/O

I/O
I/O

I/O

I/O
I/O

I/O
I/O

Buffer

Type

PORTC is a bidirectional I/O port.

ST

O

I

I

I

O

O

I

—

ST

ST

CMOS

ST

ST
ST
ST

ST
ST

ST

ST
ST
ST

ST

—

ST

—

ST

ST
ST
ST

Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.

Digital I/O.
Timer1 oscillator input.
CCP2 Capture input/Compare output/
PWM 2 output.

Digital I/O.
CCP1 Capture input/Compare output.
CCP1 PWM output A.

Digital I/O.
Synchronous serial clock input/output
for SPI mode.
Synchronous serial clock input/output
for I

Digital I/O.
SPI data in.

2

C data I/O .

I

Digital I/O.
SPI data out.

Digital I/O.
USART asynchronous tran sm it.
USART synchronous clo ck
(see RX/DT).

Digital I/O.
USART 1 asynchronous receive.
USART 1 synchronous data
(see TX/CK).

2

C mode.

DescriptionPIC18F6X8X PIC18F8X8X

DD)

 2004 Microchip Technology Inc. DS30491C-page 15

PIC18F6585/8585/6680/8680

TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

Pin

Type

TQFP PLCC TQFP

RD0/PSP0/AD0

RD0

(6)

PSP0

(3)

AD0

RD1/PSP1/AD1

RD1

(6)

PSP1

(3)

AD1

RD2/PSP2/AD2

RD2

(6)

PSP2

(3)

AD2

RD3/PSP3/AD3

RD3

(6)

PSP3

(3)

AD3

RD4/PSP4/AD4

RD4

(6)

PSP4

(3)

AD4

RD5/PSP5/AD5

RD5

(6)

PSP5

(3)

AD5

RD6/PSP6/AD6

RD6

(6)

PSP6

(3)

AD6

RD7/PSP7/AD7

RD7

(6)

PSP7

(3)

AD7

58 3 72

55 67 69

54 66 68

53 65 67

52 64 66

51 63 65

50 62 64

49 61 63

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

Note 1: Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only.

2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X8X devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices.
6: PSP is available in Microcontroller mode only.
7: On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX

configuration bit.

I/O
I/O
I/O

I/O
I/O
I/O

I/O
I/O
I/O

I/O
I/O
I/O

I/O
I/O
I/O

I/O
I/O
I/O

I/O
I/O
I/O

I/O
I/O
I/O

Buffer

Type

ST
TTL
TTL

ST
TTL
TTL

ST
TTL
TTL

ST
TTL
TTL

ST
TTL
TTL

ST
TTL
TTL

ST
TTL
TTL

ST
TTL
TTL

DescriptionPIC18F6X8X PIC18F8X8X

PORTD is a bidirectional I/O port. These
pins have TTL input buf fers when ex ternal
memory is enabled.

Digital I/O.
Parallel Slave Port data.
External memory address/data 0.

Digital I/O.
Parallel Slave Port data.
External memory address/data 1.

Digital I/O.
Parallel Slave Port data.
External memory address/data 2.

Digital I/O.
Parallel Slave Port data.
External memory address/data 3.

Digital I/O.
Parallel Slave Port data.
External memory address/data 4.

Digital I/O.
Parallel Slave Port data.
External memory address/data 5.

Digital I/O.
Parallel Slave Port data.
External memory address/data 6.

Digital I/O.
Parallel Slave Port data.
External memory address/data 7.

DD)

DS30491C-page 16  2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

T ABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

Pin

Type

TQFP PLCC TQFP

RE0

(6)

RD
AD8

RE1
WR

AD9

RE2

(6)

CS
AD10

/AD8

(3)

/AD9

(6)

(3)

/AD10

(3)

RE0/RD

RE1/WR

RE2/CS

RE3/AD11

RE3

(3)

AD11

RE4/AD12

RE4

(3)

AD12

RE5/AD13/P1C

RE5

(3)

AD13

(7)

P1C

RE6/AD14/P1B

RE6

(3)

AD14

(7)

P1B

RE7/CCP2/AD15

RE7

(1,4)

CCP2

(3)

AD15

211 4

I/O

I/O

110 3

I/O

I/O

64 9 78

I/O

I/O

63 8 77

I/O
I/O

62 7 76

I/O
I/O

61 6 75

I/O
I/O
I/O

60 5 74

I/O
I/O
I/O

59 4 73

I/O
I/O

I/O

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

Note 1: Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only.

2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X8X devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices.
6: PSP is available in Microcontroller mode only.
7: On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX

configuration bit.

Buffer

Type

DescriptionPIC18F6X8X PIC18F8X8X

PORTE is a bidirectional I/O port.

ST

I

TTL
TTL

ST

I

TTL
TTL

ST

I

TTL
TTL

ST

TTL

ST

TTL

ST

TTL

ST

ST

TTL

ST

ST
ST

Digital I/O.
Read control for Parallel Slave Port
(see WR

and CS pins).

External memory address/data 8.

Digital I/O.
Write control for Parallel Slave Port
(see CS

and RD pins).

External memory address/data 9.

Digital I/O.
Chip select control for Parallel Slave
Port (see RD

and WR).

External memory address/data 10.

Digital I/O.
External memory address/data 11.

Digital I/O.
External memory address/data 12.

Digital I/O.
External memory address/data 13.
ECCP1 PWM output C.

Digital I/O.
External memory address/data 14.
ECCP1 PWM output B.

Digital I/O.
Capture 2 input/Compare 2 output/
PWM 2 output.

TTL

External memory address/data 15.

DD)

 2004 Microchip Technology Inc. DS30491C-page 17

PIC18F6585/8585/6680/8680

TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

TQFP PLCC TQFP

RF0/AN5

RF0
AN5

RF1/AN6/C2OUT

RF1
AN6
C2OUT

RF2/AN7/C1OUT

RF2
AN7
C1OUT

RF3/AN8/C2IN+

RF1
AN8
C2IN+

RF4/AN9/C2IN-

RF1
AN9
C2IN-

RF5/AN10/C1IN+/CV

RF1
AN10
C1IN+

REF

CV

RF6/AN11/C1IN-

RF6
AN11
C1IN-

RF7/SS

RF7
SS

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

Note 1: Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only.

2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X8X devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices.
6: PSP is available in Microcontroller mode only.
7: On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX

configuration bit.

18 28 24

17 27 23

16 26 18

15 25 17

14 24 16

REF

13 23 15

12 22 14

11 21 13

Pin

Type

I/O

I/O

O

I/O

O

I/O

I/O

I/O

O

I/O

I/O

Buffer

Type

PORTF is a bidirectional I/O port.

ST

I

Analog

ST

I

Analog

ST

ST

I

Analog

ST

ST

I

Analog

I

Analog

ST

I

Analog

I

Analog

ST

I

Analog

I

Analog
Analog

ST

I

Analog

I

Analog

ST

I

TTL

Digital I/O.
Analog input 5.

Digital I/O.
Analog input 6.
Comparator 2 output.

Digital I/O.
Analog input 7.
Comparator 1 output.

Digital I/O.
Analog input 8.
Comparator 2 input (+).

Digital I/O.
Analog input 9.
Comparator 2 input (-).

Digital I/O.
Analog input 10.
Comparator 1 input (+).
Comparator V

Digital I/O.
Analog input 11.
Comparator 1 input (-)

Digital I/O.
SPI slave select input.

DescriptionPIC18F6X8X PIC18F8X8X

REF output.

DD)

DS30491C-page 18  2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

T ABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

TQFP PLCC TQFP

RG0/CANTX1

RG0
CANTX1

RG1/CANTX2

RG1
CANTX2

RG2/CANRX

RG2
CANRX

RG3

RG3

RG4/P1D

RG4

P1D
RG5 7 16 9 I ST General purpose input pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

Note 1: Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only.

2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X8X devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices.
6: PSP is available in Microcontroller mode only.
7: On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX

configuration bit.

312 5

413 6

514 7

615 8

817 10

Pin

Type

I/O

I/O

I/O

I/O ST Digital I/O.

I/O

Buffer

Type

PORTG is a bidirectional I/O port.

ST

O

O

I

O

TTL

ST

TTL

ST

TTL

ST

TTL

Digital I/O.
CAN bus transmit 1.

Digital I/O.
CAN bus transmit 2.

Digital I/O.
CAN bus receive.

Digital I/O.
ECCP1 PWM output D.

DescriptionPIC18F6X8X PIC18F8X8X

DD)

 2004 Microchip Technology Inc. DS30491C-page 19

PIC18F6585/8585/6680/8680

TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

TQFP PLCC TQFP

RH0/A16

RH0
A16

RH1/A17

RH1
A17

RH2/A18

RH2
A18

RH3/A19

RH3
A19

RH4/AN12

RH4
AN12

RH5/AN13

RH5
AN13

RH6/AN14/P1C

RH6
AN14

(7)

P1C

RH7/AN15/P1B

RH7
AN15

(7)

P1B

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

Note 1: Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only.

2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X8X devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices.
6: PSP is available in Microcontroller mode only.
7: On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX

configuration bit.

—— 79

—— 80

—— 1

—— 2

—— 22

—— 21

—— 20

—— 19

Pin

Type

I/O

O

I/O

O

I/O

O

I/O

O

I/O

I/O

I/O
I/O

I/O

Buffer

Type

PORTH is a bidirectional I/O port

ST

TTL

ST

TTL

ST

TTL

ST

TTL

ST

I

Analog

ST

I

Analog

ST

I

Analog

ST

ST

I

Analog

Digital I/O.
External memory address 16.

Digital I/O.
External memory address 17.

Digital I/O.
External memory address 18.

Digital I/O.
External memory address 19.

Digital I/O.
Analog input 12.

Digital I/O.
Analog input 13.

Digital I/O.
Analog input 14.
Alternate CCP1 PWM out put C.

Digital I/O.
Analog input 15.
Alternate CCP1 PWM out put B.

DescriptionPIC18F6X8X PIC18F8X8X

(5)

.

DD)

DS30491C-page 20  2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

T ABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

TQFP PLCC TQFP

RJ0/ALE

RJ0

ALE

RJ1/OE

RJ1

OE
RJ2/WRL

RJ2

WRL
RJ3/WRH

RJ3

WRH
RJ4/BA0

RJ4

BA0
RJ5/CE

CE
RJ6/LB

RJ6

LB
RJ7/UB

RJ7

UB
VSS 9, 25,

V

DD 10, 26,

SS 20 30 26 P — Ground reference for analog modules.

AV

DD 19 29 25 P — Positive supply for analog modules.

AV
NC — 1, 18,

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V

Note 1: Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only.

2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X8X devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices.
6: PSP is available in Microcontroller mode only.
7: On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX

configuration bit.

—— 62

—— 61

—— 60

—— 59

—— 39

— — 40 I/O

—— 42

—— 41

41, 56

38, 57

19, 36,

53, 68
2, 20,

37, 49

35, 52

11, 31,

51, 70

12, 32,

48, 71

— — — No connect.

Pin

Type

I/O

I/O

I/O

I/O

I/O

I/O

I/O

Buffer

Type

PORTJ is a bidirectional I/O port

ST

O

O

O

O

O

O

O

O
P — Ground reference for logic and I/O pins.

P — Positive supply for logic and I/O pins.

TTL

ST

TTL

ST

TTL

ST

TTL

ST

TTL

ST

TTL

ST

TTL

ST

TTL

Digital I/O.
External memory address latch
enable.

Digital I/O.
External memory output enable.

Digital I/O.
External memory write low control.

Digital I/O.
External memory write high control.

Digital I/O.
System bus byte address 0 control.

Digital I/O
External memory chip enable.

Digital I/O.
External memory low byte sele ct.

Digital I/O.
External memory high byte select.

DescriptionPIC18F6X8X PIC18F8X8X

(5)

.

DD)

 2004 Microchip Technology Inc. DS30491C-page 21

PIC18F6585/8585/6680/8680

NOTES:

DS30491C-page 22  2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

2.0 OSCILLATOR CONFIGURATIONS

2.1 Oscillator Types

The PIC18F6585/8585/6680/8680 devices can be
operated in eleven different oscillator modes. The user
can program four configuration bits (FOSC3, FOSC2,
FOSC1 and FOSC0) to select one of these eleven
modes:

1. LP Low-Power Crystal

2. XT Crystal/Resonator

3. HS High-Speed Crystal/Resonator

4. RC External Resistor/Cap ac ito r

5. EC External Clock

6. ECIO External Clock with I/O

pin enabled

7. HS+PLL High-Speed Crystal/Resonator

with PLL enabled

8. RCIO External Resist or/Capacitor with

I/O pin enabled

9. ECIO+SPLL External Clock with software

controlled PLL

10. ECIO+PLL External Clock with PLL and I/O

pin enabled

11. HS+SPLL High-Speed Crystal/Resonator

with software control

2.2 Crystal Oscillator/Ceramic Resonators

In XT, LP, HS, HS+PLL or HS+SPLL Oscillator modes,
a crystal or ceramic resonator is connected to the OSC1
and OSC2 pins to establish oscillation. Figure 2-1
shows the pin connections.

The PIC18F6585/8585/6680/8680 oscillator design
requires the use of a parallel cut crystal.

Note: Use of a series cut crystal may give a fre-

quency out of the crystal manufacturers
specifications.

FIGURE 2-1: CRYSTAL/CERAMIC

RESONATOR OPERATION
(HS, XT OR LP
CONFIGURATION)

(1)

C1

(1)

C2

Note 1: See Table 2-1 and Table 2-2 for recommended

2: A series resistor (R

3: R

OSC1

XTAL

(2)

RS

OSC2

values of C1 and C2.

strip cut crystals.

F varies with the oscillator mode chosen.

(3)

RF

Sleep

PIC18FXX80/XX85

S) may be required for AT

To

Internal
Logic

T ABLE 2-1: CAPACITOR SELECTION FOR

CERAMIC RESONATORS

Ranges Tested:

Mode Freq C1 C2

XT 455 kHz

2.0 MHz

4.0 MHz

HS 8.0 MHz

16.0 MHz

These values are for design guid ance only.
See notes following this table.

Resonators Used:

2.0 MHz Murata Erie CSA2.00MG ± 0.5%

4.0 MHz Murata Erie CSA4.00MG ± 0.5%

8.0 MHz Murata Erie CSA8.00MT ± 0.5 %

16.0 MHz Murata Erie CSA16.00MX ± 0.5%

All resonators used di d not have built-in capac itors.

68-100 pF

15-68 pF
15-68 pF

10-68 pF
10-22 pF

68-100 pF

15-68 pF
15-68 pF

10-68 pF
10-22 pF

Note 1: Hig her cap acitance increase s the stabi lity

of the oscillator, but also increases the
start-up time.

2: When operating below 3V V

DD, or when

using certain ceramic resonators at any
voltage, it may be necessary to use high
gain HS mode, try a lower frequency
resonator, or switch to a crystal oscillator.

3: Since each resonator/crystal has its own

characteristics, the user should consul t the
resonator/crystal manufacturer for appro­priate values of external components, or
verify oscillator performance.

 2004 Microchip Technology Inc. DS30491C-page 23

PIC18F6585/8585/6680/8680

TABLE 2-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

Ranges Tested:

Mode Freq C1 C2

LP 32.0 kHz 33 pF 33 pF

200 kHz 15 pF 15 pF

XT 200 kHz 47-68 pF 47-68 pF

1.0 MHz 15 pF 15 pF

4.0 MHz 15 pF 15 pF

HS 4.0 MHz 15 pF 15 pF

8.0 MHz 15-33 pF 15-33 pF

20.0 MHz 15-33 pF 15-33 pF

25.0 MHz TBD TBD

These values are for de sign guid ance only.
See notes following this table.

Crystals Used

32.0 kHz Epson C-001R32.768K-A ± 20 PPM
200 kHz STD XTL 200.000KHz ± 20 PPM

1.0 MHz ECS ECS-10-13-1 ± 50 PPM

4.0 MHz ECS ECS-40-20-1 ± 50 PPM

8.0 MHz Epson CA-301 8.000M-C ± 30 PPM

20.0 MHz Epson CA-301 20.000M-C ± 30 PPM

Note 1: Hi gher capac itance inc reases th e stabilit y

of the oscillator, but also increases the
start-up time.

2: Rs (see Figure 2-1) may be required in

HS mode, as we ll as XT mode , to avoid
overdriving crystals with low drive level
specifications.

3: Since each resonator/crystal has its own

characteristics, the user should consult the
resonator/crystal manufacturer for appro­priate values of external components, or
verify oscillator performance.

An external clock source may also be connected to the
OSC1 pin in the HS, XT and LP modes, as shown in
Figure 2-2.

FIGURE 2-2: EXTERNAL CLOCK INPUT

OPERATION (HS, XT OR
LP OSC CONFIG URAT ION)

Clock from
Ext. System

Open

OSC1

PIC18FXX80/XX85

OSC2

2.3 RC Oscillator

For timing insensitive applications, the “RC” and
“RCIO” device options offer additional cost savings.
The RC oscillator frequency is a function of the supply
voltage, the resistor (R
ues and the operating temperature. In addition to this,
the oscillator frequency will vary from unit to unit, due
to normal process parameter variation. Furthermore,
the difference in lead frame cap acitance bet ween pack­age types will also affect the oscillation frequency,
especially for low C
take into account variation due to tolerance of external
R and C components used. Figure 2-3 shows how the
R/C combination is connected.

In the RC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used f or t e st pu r pos es or t o sy nc hr o n iz e ot he r
logic.

FIGURE 2-3: RC OSCILLATOR MODE

VDD

REXT

CEXT

VSS

F

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ

EXT) and capacitor (CEXT) val-

EXT values. Th e user also needs to

OSC1

Internal

Clock

PIC18FXX80/XX85

OSC2/CLKO

OSC/4

EXT > 20pF

C

The RCIO Oscillator mode functions like the RC mode
except that the OSC2 pin becomes an additional gen­eral purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6).

DS30491C-page 24  2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

2.4 External Clock Input

The EC, ECIO, EC+PLL and EC+SPLL Oscillator
modes require an external clock source to be con­nected to the OSC 1 pin. T he feed back device b etwee n
OSC1 and OSC2 is turned off in these modes to save
current. There is a maximum 1.5 µs start-up requ ired
after a Power-on Reset, or wake-up from Sleep mode.

In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used f or t e st pu r pos es or t o sy nc hr o n iz e ot he r
logic. Figure 2-4 shows the pin connections for the EC
Oscillator mode.

FIGURE 2-4: EXTERNAL CLOCK INPUT

OPERATION
(EC CONFIGURATION)

Clock from
Ext. System

F

OSC/4

The ECIO Oscillator mode func ti ons li ke t he EC m od e,
except that the OSC2 pin becomes an additional gen­eral purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6). Figure 2-5 shows the pin connections
for the ECIO Oscillator mode.

FIGURE 2-5: EXTERNAL CLOCK INPUT

OSC1

PIC18FXX80/XX85

OSC2

OPERATION
(ECIO CONFIGURATION)

2.5 Phase Locked Loop (PLL)

A Phase Locked Loop circuit is provided as a
programmable option for us ers that want to multip ly the
frequency of the in com in g osc il lat or s ig nal by 4 . For an
input clock frequency of 10 MHz, the internal clock
frequency will b e multipli ed to 40 MHz. This is usefu l for
customers who are concerned with EMI due to
high-frequency crystals.

The PLL can only be enabled when the oscillator config­uration bits are programmed for High-Speed Oscillator
or External Clock mode. If they are programmed for any
other mode, the PLL is not enabled and the system clock
will come directly from OSC1. There are two types of
PLL modes: Software Controlled PLL and Configuration
bits Controlled PLL. In Software Controlled PLL mode,
PIC18F6585/8585/6680/8680 executes at regular clock
frequency after all Reset conditions. During execution,
application can enable PLL and switch to 4x clock
frequency operation by setting the PLLEN bit in the
OSCCON register. In Configuration bits Controlled PLL
mode, PIC18F6585/8585/6680/8680 always executes
with 4x clock frequency.

The type of PLL is selected by programming the
FOSC<3:0> configuration bits in the CONFIG1H
Configuration register. The oscillator mode is specified
during device programming.

A PLL lock timer is used to ensure that the PLL has
locked before device execution starts. The PLL lock
timer has a time-out that is called T

PLL.

Clock from
Ext. System

RA6

OSC1

PIC18FXX80/XX85

I/O (OSC2)

FIGURE 2-6: PLL BLOCK DIAGRAM

PLL Enable

Phase

Comparator

F

IN

FOUT

Loop
Filter

Divide by 4

VCO

SYSCLK

MUX

 2004 Microchip Technology Inc. DS30491C-page 25

PIC18F6585/8585/6680/8680

2.6 Oscillator Switching Feature

The PIC18F6585/8585/6680/8680 devices include a
feature that allows the system clock source to be
switched from the main oscillator to an alternate
low-frequency clock source. For the
PIC18F6585/8585/6680/8680 devices, this alternate
clock source is the Timer1 oscillator. If a low-frequency
crystal (32 kHz, for ex am pl e ) ha s bee n at tac he d to the
Timer1 oscillator pins and the Timer1 oscillator has
been enabled, the device can switch to a low-power

FIGURE 2-7: DEVICE CLOCK SOURCES

PIC18FXX80/XX85

OSC2

OSC1

T1OSO

T1OSI

Main Oscillator

Sleep

Timer1 Oscillator

T1OSCEN
Enable
Oscillator

execution mode. Figure 2-7 shows a block diagram of
the system clock sources. The clock switching feature
is enabled by programming the Oscillator Switching
Enable (OSCSEN

) bit in configuration register,
CONFIG1H, to a ‘0’. Clock switching is disabled in an
erased device. See Se ction 12.0 “Timer1 Module” for
further details of the Timer1 oscillator . See Section 24.0
“Special Features of the CPU” for configuration

register details.

4 x PLL

TOSC

TT1P

Tosc/4

MUX

Clock

Source

TSCLK

Clock Source Option
for other Modules

DS30491C-page 26  2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

2.6.1 SYSTEM CLOCK SWITCH BIT

The system clock source switching is p erformed under
software control. The System Clock Switch bits,
SCS1:SCS0 (OSCCON<1:0>), control the clock switch­ing. When the SCS0 bit is ‘ 0’, the system cl ock source
comes from the main oscillator that is selected by the
FOSC configuration bits in configuration register,
CONFIG1H. When the SCS0 bit is set, the system clock
source will come from the Timer1 oscillator. The SCS0
bit is clear ed on al l fo rm s of R eset.

When FOSC bits are programmed for software PLL
mode, the SCS1 bit c an be us ed to select between pri­mary oscillator/clo ck and PLL output . The SCS1 bit wil l
only have an effect on the system clock if the PLL is

REGISTER 2-1: OSCCON REGISTER

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — — LOCK PLLEN SCS1 SCS0

bit 7 bit 0

bit 7-4 Unimplemented: Read as ‘0’
bit 3 LOCK: Phase Lock Loop Lock Status bit

1 = Phase Lock Loop output is stable as system clock
0 = Phase Lock Loop output is not stable and output cannot be used as system clock

(1)

bit 2 PLLEN

1 = Enable Phase Lock Loop output as system clock
0 = Disable Phase Lock Loop

bit 1 SCS1: System Clock Switch bit 1

When PLLEN and LOCK bits are set:

1 = Use PLL output
0 = Use primary oscillator/clock input pin

When PLLEN or LOCK bit is cleared:
Bit is forced clear.

bit 0 SCS0

When

1 = Switch to Timer1 oscillator/clock pin
0 = Use primary oscillator/clock input pin

When
Bit is forced clear.

: Phase Lock Loop Enable bit

(2)

: System Clock Switch bit 0

OSCSEN configuration bit = 0 and T1OSCEN bit = 1:

OSCSEN and T1OSCEN are in other states:

Note 1: PLLEN bit is ignored when configured for ECIO+PLL and HS+PLL. This bit is used

in ECIO+SPLL and HS+SPLL modes only.

2: The setting of SCS0 = 1 supersedes SCS1 = 1.

enabled (PLLEN = 1) and locked (LOCK = 1), else it will
be forced clear. When programmed with Configuration
Controlled PLL mode, the SCS1 bit w ill be forced c lear .

Note: The Timer1 oscillator must be enabled

and operating to switch the system clock
source. The Timer1 oscillator is enabled
by setting the T1OSCEN bit in the Timer1
Control register (T1CON). If the Timer1
oscillator is not enabled, then any write to
the SCS0 bit will be ignored (SCS0 bit
forced cleared) and the main osci llator w ill
continue to be the system clock source.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2004 Microchip Technology Inc. DS30491C-page 27

PIC18F6585/8585/6680/8680

2.6.2 OSCILLATOR TRANSITIONS

PIC18F6585/8585/6680/8680 devices contain circuitry
to prevent “glitches” when switching between oscillator
sources. Essentially, the circuitry waits for eight rising
edges of the clock source that the processor is switch­ing to. This e ns ures t hat the new clock source is st abl e
and that its pulse wid th will not be less than the sho rtest
pulse width of the two clock sources.

A timing diagram, indicating the transition from the
main oscillator to the Timer1 oscillator, is shown in
Figure 2-8. The Timer1 oscillator is assu med to be run-

The sequence of events that takes place when switch­ing from the Timer1 oscillator to the main oscillator will
depend on the mode of the main oscillator. In addition
to eight clock cycles of the main oscillator, additional
delays may take place.

If the main oscillator is configured for an external
crystal (HS, XT, LP), then the transition will take place
after an oscillator start-up time (T

OST) has occurred. A

timing diagram, indicating the transition from the
Timer1 oscillator to the main oscillator for HS, XT and
LP modes, is shown in Figure 2-9.

ning all the time. After the SCS0 bit is set, the processor
is frozen at the next occurring Q1 cycle. After eight
synchronization cycles are counted from the Timer1
oscillator, operation resumes. No additional delays are
required after the synchronization cycles.

FIGURE 2-8: TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR

Q1

T1OSI
OSC1

Internal
System
Clock

SCS
(OSCCON<0>)

Program
Counter

TOSC

Q1

TDLY

TT1P
21 345678

TSCS

PC + 2PC

Q3Q2Q1Q4Q3Q2

Q4 Q1

Q2 Q3 Q4 Q1

PC + 4

Note: TDLY is the delay from SCS high to first count of transition circuit.

FIGURE 2-9: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, XT, LP)

Q3 Q4

T1OSI

OSC1

Internal

System Clock

(OSCCON<0>)

Note: TOST = 1024 TOSC (drawing not to scale).

SCS

Program

Counter

PC PC + 2

Q1

TOST

TT1P

12345678

TSCS

TOSC

Q1 Q2 Q3 Q4 Q1 Q2

Q3

PC + 6

DS30491C-page 28  2004 Microchip Technology Inc.