MICROCHIP PIC18F6525, PIC18F6621, PIC18F8525, PIC18F8621 DATA SHEET
PIC18F6525/6621/8525/8621
Data Sheet
64/80-Pin High-Performance,
64-Kbyte Enhanced Flash
Microcontrollers with A/D
2005 Microchip Technology Inc. DS39612B
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Millennium Copyright Act. If suc h a c t s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and
its use. Use of M icrochip’s prod ucts as critical components in
life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed,
implicitly or otherwise, under any Microchip intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K
EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
PICMASTER, SEEVAL, SmartSensor and The Embedded
Control Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programmin g, IC SP, ICEPI C, M PASM, MPLIB, MPLINK,
MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail,
PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartT el and Total
Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2005, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
®
8-bit MCUs, KEELOQ
®
code hopping
DS39612B-page ii 2005 Microchip Technology Inc.
PIC18F6525/6621/8525/8621
High Performance RISC CPU:
• Linear program memory addressing to 64 Kbytes
• Linear data memory addressing to 4 Kbytes
• 1 Kbyte of data EEPROM
• Up to 10 MIPs operation:
- DC – 40 MHz osc ./clock input
- 4 MHz – 10 MHz os c. /c l ock in put w i th PLL active
• 16-bit wide instructions, 8-bit wide data path
• Priority levels for interrupts
• 31-level, software accessible hardware stack
• 8 x 8 Single-cycle Hardware Multiplier
Peripheral Features:
• High current sink/so ur ce 25 mA/25 mA
• Four external interrup t pin s
• Timer0 module: 8-bit/16-bit tim er/counter
• Timer1 module: 16-bit timer/counter
• Timer2 module: 8-bit timer/counter
• Timer3 module: 16-bit timer/counter
• Timer4 module: 8-bit timer/counter
• Secondary oscilla to r c lock option – Timer1/Timer3
• Two Capture/Compare/PWM (CCP) mo dul es :
- Capture is 16-bit, max. resolution 6.25 ns (T
- Compare is 16-bit, max. resolution 100 ns (T
- PWM output: 1 to 10- bit PWM resolution
• Three Enhanced Capture/Compare/PWM (ECCP)
modules:
- Same Capture/ Compare features as CCP
- One, two or four PWM outputs
- Selectable polarity
- Programmabl e dead time
- Auto-Shutdown on external event
- Auto-Restart
• Master Synchronous Se rial Por t (MSSP) module
with two modes of operation:
- 2/3/4-wire SPI™ (supports all 4 SPI modes)
2
C™ Master and Slave mo de
-I
• Two Enhanced USART modules:
- Supports RS-485, R S-2 32 and LIN 1.2
- Auto-Wake-up on Start bit
- Auto-Baud Ra te D et ect
• Parallel Slave Port (PSP) module
CY/16)
CY)
External Memory Interface (PIC18F8525/8621 Devices Only):
• Address capability of up to 2 Mbytes
• 16-bit interface
Analog Features:
• 10-bit, up to 16-channel Analog-to-Digital
Converter (A/D):
- Auto-Acquisition
- Conversion av ai la bl e du ri ng Sleep
• Programmable 16 -level Low-Voltage Detection
(LVD) module:
- Supports interrupt on Low-Voltage Detection
• Programmable Brown-out Reset (BOR)
• Dual analog comparat or s:
- Programmabl e i nput/output configurati on
Special Microcontroller Features:
• 100,000 erase/writ e cycle Enhanced Flash
program memory typical
• 1,000,000 erase/write cycle Data EEPROM
memory typical
• 1 second program m in g t ime
• Flash/Data EEPROM Reten tion : > 100 y ear s
• Self-reprogramm a bl e under software control
• Power-on Reset (POR) , P ower-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own On-Chip
RC Oscillator for reliable operation
• Programmable co de protection
• Power-saving Sleep mo de
• Selectable oscillator options including:
- 4xenedp1(l-6.9(e(de)-14oTw[(-18 T-13.9(.4(P)-2.9(W)-145(m).66 (4ui1(l66 (217.2(4.2429 TD0.0008 .2(u)-14.6(p).6.2(Eo4DT2-8(p-I•)-720.4I Tw[(•)-I•)-720.4I Tw11 Tcl/.7(h i)4[(•)- Tcl/.7(h i0.000(e)0.9(n)-13.4(t)8270.0.6.2(Eo -11na)7.4(1.3(llaN68 Tw0s14.6(p2.2(2-I•)-7Fo7-1.1286M0116.7(i)8-12.8(e)03Ri.1.1286lo112.886l2•)-7M7 (.2(E38( e886l2•)o )-0.5r)-6.642)-12.8(e)0.4(t)-6.2(.V(ed)-03(b)720.1.2429 11..3(m)-8.642-5.7(20.1.-2.86(r)(e)0.gEv1f)14.1mr)(e)0g(2-I•)-63 Tw0.4(t)-6.2(.V(ed)-03(b)720.1.2429 11..3(m)-8.642-5.7(20.1.-2.86(r)(e)0.gEv1f)1.64V01--7.8(4(r))13.7(007P)-211 TcPH007P1--7.8(4(r))132(oP1--7.n2-5.7((s)-12/2PH0n52M(-18 Taf-9(m)-9(b)72PP1--7.[(•)- Tcls12272c0.001 bh•)-26Tcls12272c0.001 bh1..3(a)6.5(21-0.00•)-26Tcls12272c11.030.e)-14gnd•)-7M7 (.2(E38( e886l2•)o )-0.5r)-6.642)-12.8(e)0.4(t)-6.2(.V(ed)-03(b)720./3.1.-2.(v3j()-12.8(e6.9(e(de)-14oTw[da)6.4(t)-k20.1.-630.0073ai)15.12s1.122-)I(o)0.4e6.9(e(de)-14oTw[da)(-)-73i44.3(1)-22-)I((l)n3(y)-4.6(p)8.6(i)8.6(i)80.4(t1uli)15.vi)-5.P3)]Tu671 TD0Ln173i44.3a)(-)-73i9(s)-1213p -12#074 072)-5P)-22p -R)-1213p -12#074 072)-5P92)-5P)-22gw#074 07gw#074 07e)-8.642-5.7(20.1-6.7)-13.4(t77w#07.4( ()M720.7w#07.41hPP1-a)6.4(t)--7.8(43.V(ed)P57-8.6t[(22-x5o92)h092 i0.01(e1da)6.4(t)-k20.1.-.3(.4(1i)80.4-14.5(g[(•)TM7 n Tc03W)30.(321011.12s1.(0.1.-a4384oTwI•)-63 -5.6(TO492 i051(e1dao6.4(t) 3t.8(pe co/e411492 e)--(t)-5n20.9(n)-13.4(t)8.6(i)-4.6(o)0u-0.2(i0 -113.4(tMi)-5.d/2PH08DMi)-5.d4( )1437-13 H08DMi)-5 3e613 H08DM7377(t)--7.8(43t -11na-13 Hf)1.64V016.2(E9-13 517377(t)f)1.64V016.3Yr)(e)0.gEv(t)7.6V016.3gEv17377a0p07e4a)7.4(1.3(7h:2)-5P92)-5P)-22gw#074 07gw22gw-Pgt)-5P)-22gw#07-9(a)-14-14gnd•.2(E38( e886(m)-8 e714 -1 o)-1394-147((t)30.(32c4.6(e2)-5P9(o(-)-72751.3(7h:2Tc03W)2(Eo -11Fo70Ln173i44.3a))8.6oadel)0.8(es78.6gr)-1i)80.1-2.9(W)-ng–T4.6(p4(t5da)6.4(t)-71m).6(es7n.6(i)-5.–T4.6(p4(t5da)6.4(t)-71m).6(es7n.6(i)-5.–T4.6(p4(t5da)6.4(t)-71m).6(es7n.6(i)015 Tc3 -5.6(b071m).6(i0 - l.6(p4(i5)1gEv Tw[( Tw[(nHm).6( Tw[(nH3hN6ke714 -614(t) 36ke712 Ev(t)7.07gw#-R14.3(-a(.1-6.7)-13.4886n7-5.1i0.00r112( .4886n7tl)0.8i)15.v)8.6(i)8.6(i)80.4(t1u5(r)-9614(tc36(i)8.6(i).4(li)At7gw#-Rt7oTc14(tc3rr(tc36(i)a15.v)8.6(i)8.6(i)80.471 TI2-12#07P9(o(-)-8.6(i)3()S3114 -61714 ()S3)-k20.1.-.3(.4(p). Tw0..0714 -1.2429 5.6(39(ogr)-9(am)g–T4.69 5.617371n.6(T4.6(p3p -1F42t5da)7T4.69 5.r4(t77w#07.4( ()M720.7w#07.41h-51p07e4)dao6.4(t) 3t.8ao6.4001au5.vi)-i0.00r1n/6l2•)-8.9(C)-5.vi)4317)-13.48)-71m) bh•)-2e41149)-14oTwd149)-14oTwd1496(6a2e4114r)-9.1(0.1.)f)1.64V57o(-)-72751(2MA51p0(Eo -11F()2(Eo -n2)]TJ1.07107gw#-)-8(([s2 nHm).6( (p.2573(7h:2)-)gw#-)d/(r)5.3(5.12(i)8.6(ed)-03(b)-5)6.3(r-030.003(5.1260009 TEo -107P7o(-)-uda)6.4(t)-5 3e6(007P) 4/)C7Ea78.4(o)-13.9(de)]TJ0 -1.7Ea7873M/2c0.0.12 (t)7.0d)-7u5(r)-9614(tc36(i(t)7.0d)-7a–80.1-2-51p07t)7.0-14oTw4.69 52)]T2-8(-469 52)]T2-8(-.4(t)-U)8.6(213(se)2)]TJ i)-5.P3e-26Tcl1i]T2-8(-ba2(p)-(-11n™17-7a–8036(m)-80.001au53)-14.d29a-13d3o)-139.6(279a-1380.00iE38n0 -1.2571 (t)-5 3)3(e)623(e81 (t)-541.(0.1.-5Dt) 3t.8(pe co/e411492 e)--(t)-5n20.9(n)-13.4(t)8.6(i)-n)-13.4Dp(i)-5.m8 e71- l.6(6M-5.m8 eR-5.m8 e12(i)8aa8sO eR-56M-5.myu8(es78)V71- l.61.m8 e7)8aa8s(-)-22a0p07e4a l.61.3i44(t) 3t1 (8gEv T01au5.vi)-i0.00r1n/6l2T01au5.l2•gi1(4eC-2.9(WoI74 077(h1)80.471 T)-i0.00r-7p5.vi8(n)-0 -1.7Ea7a l.61.3i44(tl37h:2)-)gw#-)d/(r)5.3(5.12(i)8.6(ed)-03(b)-5)6.3(r-030.003(5.1260009 TEo -171.07140s4gnd•)-7M7 (.0(Eo -11F()2(Eo -n2)b4(n)-8()d/(r)5.3(51da)6.4(t)-k09 T1da)6.8.0008 2()-2O)1.2571)-1)03Yr)(e)0.g6.3(r--6./)622p)-724(se)2)]TJ ini inry typical
2005 Microchip Technology Inc. DS39612B-page 1
PIC18F6525/6621/8525/8621
Pin Diagrams
64-Pin TQFP
(1)
/P2A
(1)
RE3/P3C
RE4/P3B
RE5/P1C
RE6/P1B
RE2/CS/P2B
RE7/ECCP2
RD0/PSP0
VDDVSS
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
RE1/WR/P2C
RE0/RD
/P2D
RG0/ECCP3/P3A
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4/P3D
/VPP/RG5
MCLR
RG4/CCP5/P1D
RF7/SS
RF6/AN11
RF5/AN10/CV
RF4/AN9
RF3/AN8
RF2/AN7/C1OUT
VSS
VDD
REF
64
63 62 61
1
2
3
4
5
(2)
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26
DD
AV
RF0/AN5
RF1/AN6/C2OUT
PIC18F6525
PIC18F6621
REF-
AVSS
RA2/AN2/V
RA3/AN3/VREF+
RA1/AN1
RA0/AN0
54 53 52 5158 57 56 5560 59
27 28
SS
V
VDD
RA5/AN4/LVDIN
50 49
31
29 30 32
(1)
/P2A
(1)
RA4/T0CKI
RC0/T1OSO/T13CKI
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RC6/TX1/CK1
RC7/RX1/DT1
RB0/INT0/FLT0
RB1/INT1
RB2/INT2
RB3/INT3
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
SS
V
OSC2/CLKO/RA6
OSC1/CLKI
V
DD
RB7/KBI3/PGD
RC5/SDO
RC4/SDI/SDA
RC3/SCK/SCL
RC2/ECCP1/P1A
RC1/T1OSI/ECCP2
Note 1: ECCP2/P2A are multiplexed with RC1 when CCP2MX is set, or RE7 when CCP2MX is not set.
2: RG5 is multiplexed with MCLR
and is only available when the MCLR Resets are disabled.
DS39612B-page 2 2005 Microchip Technology Inc.
Pin Diagrams (Cont.’d)
80-Pin TQFP
RH2/A18
RH3/A19
RE1/AD9/WR/P2C
RE0/AD8/RD
RG0/ECCP3/P3A
RG3/CCP4/P3D
MCLR
RG4/CCP5/P1D
RF5/AN10/CVREF
RF2/AN7/C1OUT
RH7/AN15/P1B
RH6/AN14/P1C
/P2D
RG1/TX2/CK2
RG2/RX2/DT2
/VPP/RG5
VSS
VDD
RF7/SS
RF6/AN11
RF4/AN9
RF3/AN8
(3)
(2)
(2)
PIC18F6525/6621/8525/8621
(1)
/P2A
(1)
(2)
(2)
RE3/AD11/P3C
RE4/AD12/P3B
(2)
RE5/AD13/P1C
RE6/AD14/P1B
RE7/AD15/ECCP2
PIC18F8525
PIC18F8621
RD0/AD0/PSP0
(2)
RE2/AD10/CS/P2B
RH0/A16
RH1/A17
80
79
78
77 76 75
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21 22 23 24 25 26 27 28 29 30 31 32
VDDVSS
RD1/AD1/PSP1
68 67 66 6572 71 70 6974 73
33 34
RD2/AD2/PSP2
RD3/AD3/PSP3
35 36 38
RD4/AD4/PSP4
RD5/AD5/PSP5
RD6/AD6/PSP6
RD7/AD7/PSP7
RJ0/ALE
64 63 62 61
37
39
RJ1/OE
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
RJ2/WRL
RJ3/WRH
RB0/INT0/FLT0
RB1/INT1
RB2/INT2
RB3/INT3/ECCP2
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
SS
V
OSC2/CLKO/RA6
OSC1/CLKI
DD
V
RB7/KBI3/PGD
RC5/SDO
RC4/SDI/SDA
RC3/SCK/SCL
RC2/ECCP1/P1A
RJ7/UB
RJ6/LB
(1)
/P2A
(1)
(2)
(2)
RH5/AN13/P3B
RH4/AN12/P3C
DD
AV
RF0/AN5
RF1/AN6/C2OUT
REF-
AVSS
RA2/AN2/V
RA3/AN3/VREF+
RA1/AN1
RA0/AN0
SS
V
VDD
RA5/AN4/LVDIN
(1)
/P2A
(1)
RA4/T0CKI
RC1/T1OSI/ECCP2
RC0/T1OSO/T13CKI
RJ5/CE
RJ4/BA0
RC6/TX1/CK1
RC7/RX1/DT1
Note 1: ECCP2/P2A are multiplexed with RC1 when CCP2MX is set; with RE7 when CCP2MX is cleared and the device
is configured in Microcontroller mode; or with RB3 when CCP2MX is cleared in all other program memory modes.
2: P1B/P1C/P3B/P3C are multiplexed with RE6:RE3 when ECCPMX is set and with RH7:RH4 when ECCPMX is
not set.
3: RG5 is multiplexed with MCLR
and is only available when the MCLR Resets are disabled.
2005 Microchip Technology Inc. DS39612B-page 3
PIC18F6525/6621/8525/8621
Table of Contents
1.0 Device Overview ..........................................................................................................................................................................7
2.0 Oscillator Configurations ............................................................................................................................................................ 21
3.0 Reset.......................................................................................................................................................................................... 29
4.0 Memory Organization................................................................................................................................................................. 39
5.0 F la sh Program Memory............... ..................... ..................... ..................... ..................... ...........................................................61
6.0 External Memory Interface......................................................................................................................................................... 71
7.0 Data EEPROM Memory ............................................................. ..................... ..................... ...................................................... 79
8.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 85
9.0 Interrupts ....................................................................................................................................................................................87
10.0 I/O Ports........................................ ..................... ......................................................................................................................103
11.0 Timer0 Module ......................................................................................................................................................................... 131
12.0 Timer1 Module ......................................................................................................................................................................... 135
13.0 Timer2 Module ......................................................................................................................................................................... 141
14.0 Timer3 Module ......................................................................................................................................................................... 143
15.0 Timer4 Module ......................................................................................................................................................................... 147
16.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 149
17.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 157
18.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 173
19.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)............................................................... 213
20.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 233
21.0 Comparator Module.......................................................................... .... .. .... ....... .... .... .. .... .........................................................243
22.0 Comparator Voltage Reference Module...................................................................................................................................249
23.0 Low-Voltage Detect. .................................................................................................................................................................253
24.0 Special Features of th e CPU.............. ..................... ..................... ........................................ .................................................... 259
25.0 Instruction Set Summary.......................................................................................................................................................... 275
26.0 Development Support...............................................................................................................................................................317
27.0 Electrical Characteristics.......................................................................................................................................................... 323
28.0 DC and AC Characteristics Graphs And Tables ............................................................................ .. ........................................357
29.0 Packaging Inform a tio n..... ..................... ..................... .......................................... ..................................................................... 373
Appendix A: Revision History.............................................................................................................................................................377
Appendix B: Device Differences.........................................................................................................................................................377
Appendix C: Conversion Considerations .................................................................... .... .. .... .. .... ....................................................... 378
Appendix D: Migration From Mid-Range to Enhanced Devices......................................................................................................... 378
Appendix E: Migration From High-End to Enhanced Devices............................................................................................................ 379
Index .................................................................................................................................................................................................. 381
On-Line Support........................................................................ .. .... .. ......... .... .. .... ......... .. ................................................................... 391
Systems Information and Upgrade Hot Line...................................................................................................................................... 391
Reader Response.............................................................................................................................................................................. 392
PIC18F6525/6621/8525/8621 Product Identification System ............................................................................................................393
DS39612B-page 4 2005 Microchip Technology Inc.
PIC18F6525/6621/8525/8621
TO OUR VALUED CUSTOMERS
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If you have any questions or c omm ents regarding t his publication, p lease c ontact the M arket ing Co mmunications Department via
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We welcome your feedback.
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2005 Microchip Technology Inc. DS39612B-page 5
PIC18F6525/6621/8525/8621
NOTES:
DS39612B-page 6 2005 Microchip Technology Inc.
PIC18F6525/6621/8525/8621
1.0 DEVICE OVERVIEW
This documen t conta i ns dev ic e spec if i c in for m at i on fo r
the following devices:
• PIC18F6525
• PIC18F6621
• PIC18F8525
• PIC18F8621
This family offers the advantages of all
PIC18 microcontrollers – namely, high computational
performance at an economical price – with the addition
of high-end urance Enhan ced Flash pro gram memory.
The PIC18F6525/6621/8 525/8621 fa mily als o provide s
an enhanced range of program memory options and
versatile analog fea tures that mak e it ideal fo r complex,
high performance applications.
1.1 Key Features
1.1.1 EXPANDED MEMORY
The PIC18F6525/6621/8525/8621 family provides
ample room for application code and includes
members with 48 Kbytes or 64 Kbytes of code space.
Other memory features are:
• Data RAM and Data EEPROM: The PIC18F6525/
6621/8525/8621 family also provides plenty of room
for application da t a. T he devices have 3840 bytes of
data RAM, as well as 1024bytes of data EEPROM
for long term retention of nonvolatile data.
• Memory Endurance: The Enhanced Flash cells for
both program memory and data EEPROM are rated
to last for many thou sands of erase/write cycl es –
up to 100,000 for program memory and 1,000,000
for EEPROM. Data retention without refresh is
conservatively estimated to be greater than
40 years.
1.1.2 EXTERNAL MEMORY INTERFACE
In the unlikely event t hat 64 Kbytes of program memo ry
is inadequate for an ap plica tion, th e PIC1 8F8525 /8621
members of the family also implement an external
memory interface. This allows the controller’s internal
program counter to address a memory space of up to
2 MBytes, permitting a level of data access that few
8-bit devices can claim.
With the addition of new operati ng mode s, the ext ernal
memory interface offers many new options, including:
• Operating the microcontr oller entirely f rom external
memory
• Using combinations of on-chip and external
memory, up to the 2-Mbyte limit
• Using external Flash memory for reprogrammable
application code or large data tables
• Using external RAM devices for storing large
amounts of variable data
1.1.3 EASY MIGRATION
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve.
The consistent pinout scheme used throughout the
entire family also aids in migrating to the next larger
device. This is true when moving between the 64-pin
members, between the 80-pin members, or even
Jumping From 64-pin To 80-pin Devices.
1.1.4 OTHER SPECI AL FE A TU RES
• Communications: The PIC18F6525/6621/8525/
8621 family incorporates a range of serial communication peripherals, including 2 independent
Enhanced USARTs and a Master SSP module capable of both SPI and I2C (Master and Slave) modes of
operation. Also, for PIC18F6525/6621/8525/8621
devices, one of the general purpose I/O ports can be
reconfigured as an 8-bit Parallel Slave Port for direct
processor to processor communications.
• CCP Modules: All devices in the family incorporate
two Capture/Compare/PWM (CCP) modules and
three Enhanced CCP (ECCP) modules to maximize
flexibility in control applications. Up to four different
time bases may be used to perform several different
operations at once. Each of the three ECCPs offer
up to four PWM outputs, allowing for a total of
12 PWMs. The ECCPs also offer many beneficial
features, including polarity selection, Programmable
Dead Time, Auto-Shutdown and Restart and
Half-Bridge and Full-Bridge Output modes.
• Analog Features: All devices in the family feature
10-bit A/D converters with up to 16 input channels,
as well a s the a bility t o perfor m conver sions du ring
Sleep mode and auto-acquisition conversions. Also
included are dual analog comparators with
programmable input and output configuration, a
programmable Low-Voltage Detect module and a
Programmable Brown-out Reset module.
• Self-programmability: These devices can write to
their own program memory spaces under internal
software control. By using a bootloader routine
located in the protected boot block at the top of
program memor y, it become s possible to crea te an
application that can update itself in the field.
2005 Microchip Technology Inc. DS39612B-page 7
PIC18F6525/6621/8525/8621
1.2 Details on Individual Family Members
The PIC18F6525/6621/8525/8621 devices are available in 64-pin (PIC18F6525/6621) and 80-pin
(PIC18F8525/8621) packages. They are differentiated
from each other in four ways:
1. Flash program memory (48 Kbytes for
PIC18F6525/8525 devices; 64 Kbytes for
PIC18F6621/8621 devic es).
2. A/D channels (12 for PIC18F6525/6621
devices; 16 for PIC18F8525/86 21 dev ic es ).
3. I/O ports (7 on PIC18F6525/6621 devices; 9 on
PIC18F8525/8621 devices).
4. External program memory interface (present
only on PIC18F8525/8621 devices)
All other features for devices in the PIC18F6525/6621/
8525/8621 family are iden tic al. These are summarized
in Table 1-1.
Block diagrams of the PIC18F6525/6621 and
PIC18F8525/8621 devices are provided in Figure 1-1
and Figure 1-2, respectively. The pinouts for these
device families are listed in Table 1-2.
TABLE 1-1: PIC18F6525/6621/8525/8621 DEVICE FEATURES
Features PIC18F6525 PIC18F6621 PIC18F8525 PIC18F8621
Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz
Program Memory (Bytes) 48K 64K 48K 64 K
Program Memory (Instruction s) 24576 32768 24576 3 276 8
Data Memory (Bytes) 3840 3840 3840 384 0
Data EEPROM Memory (Bytes) 1024 1024 1024 1024
External Memory Interface No No Yes Yes
Interrupt Sources 17 17 17 17
I/O Ports Ports A, B, C, D,
E, F, G
Timers 5 5 5 5
Capture/Compare/PWM Modules 2 2 2 2
Enhanced Capture/Compare/
PWM Module
Serial Communications MSSP,
Parallel Communications PSP PSP PSP PSP
10-bit Analog-to-Digital Module 12 input channels 12 input channels 16 input channels 16 input channels
Resets (and Delays) POR, BOR,
RESET Instruction,
Programmable Low-Voltage
Detect
Programmable Brown-out Reset Yes Yes Yes Yes
Instruction Set 77 Instructions 77 Instructions 77 Instructions 77 Instructions
Package 64-pin TQFP 64-pin TQFP 80-pin TQFP 80-pin TQFP
3333
Addressable
EUSART (2)
Stack Full,
Stack Underflow
(PWRT, OST)
Yes Yes Yes Yes
Ports A, B, C, D,
E, F, G
MSSP,
Addressable
EUSART (2)
POR, BOR,
RESET Instruction,
Stack Full,
Stack Underflow
(PWRT, OST)
Ports A, B, C, D, E,
F, G, H, J
MSSP,
Addressable
EUSART (2)
POR, BOR,
RESET Instruction,
Stack Full,
Stack Underflow
(PWRT, OST)
Ports A, B, C, D, E,
F, G, H, J
MSSP,
Addressable
EUSART (2)
POR, BOR,
RESET Instruction,
Stack Full,
Stack Underflow
(PWRT, OST)
DS39612B-page 8 2005 Microchip Technology Inc.
PIC18F6525/6621/8525/8621
FIGURE 1-1: PIC18F6525/6621 BLOCK DIAGRAM
Data Bus<8>
Address Latch
Program Memory
(48/64 Kbytes)
Data Latch
OSC2/CLKO
OSC1/CLKI
BOR
LVD
Data
EEPROM
21
Instruction
Decode and
Control
Timing
Generation
Precision
Band Gap
Reference
T able Pointer<21>
21
inc/dec logic
20
Table Latch
16
PCLATU
PCU
Program Counter
31 Level Stack
8
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Test Mode
Select
DD,
VSS
V
8
PCLATH
PCH PCL
ROM Latch
IR
MCLR
Timer2Timer1 Timer3 Timer4Timer0
8
Decode
BITOP
(2)
4
BSR
3
8
Data Latch
Data RAM
(3.8Kbytes)
Address Latch
Address<12>
12 4
FSR0
FSR1
FSR2
inc/dec
logic
8 x 8 Multiply
W
8
8
ALU<8>
12
Bank 0, F
PRODLPRODH
8
10-bit
12
8
ADC
PORTA
PORTB
PORTC
PORTD
PORTE
8
8
PORTF
PORTG
RA0/AN0
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/LVDIN
OSC2/CLKO/RA6
RB0/INT0/FLT0
RB1/INT1
RB2/INT2
RB3/INT3
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
RC0/T1OSO/T13CKI
RC1/T1OSI /E C CP 2
RC2/ECCP1/P1A
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX1/CK1
RC7/RX1/DT1
RD7/PSP7
RE0/RD/P2D
RE1/WR/P2C
RE2/CS/P2B
RE3/P3C
RE4/P3B
RE5/P1C
RE6/P1B
RE7/ECCP2
RF0/AN5
RF1/AN6/C2OUT
RF2/AN7/C1OUT
RF3/AN8
RF4/AN9
RF5/AN10/CVREF
RF6/AN11
RF7/SS
RG0/ECCP3/P3A
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4/P3D
RG4/CCP5/P1D
MCLR/VPP/RG5
:RD0/PSP0
(1)
(1)
/P2A
(2)
(1)
/P2A
(1)
MSSP
ECCP1
Note 1: ECCP2/P2A are multiplexed with RC1 when CCP2MX is set, or RE7 when CCP2MX is not set.
2: RG5 is multiplexed with MCLR
ECCP2
ECCP3
CCP4 CCP5
and is only available when the MCLR Resets are disabled.
EUSART1Comparator
EUSART2
2005 Microchip Technology Inc. DS39612B-page 9
PIC18F6525/6621/8525/8621
FIGURE 1-2: PIC18F8525/8621 BLOCK DIAGRAM
Data Bus<8>
Table Pointer<21>
21
8
21
inc/dec logic
8
Data Latch
Data RAM
(3.8 Kbytes)
Address Latch
20
PCLATU
Address Latch
Program Memory
(48/64Kbytes)
Data Latch
System Bus Interface
16
Table Latch
8
PCLATH
PCU
PCH PCL
Program Counter
31 Level Stack
ROM Latch
4
Decode
12
Address<12>
12 4
Bank0, FBSR
FSR0
FSR1
FSR2
inc/dec
logic
12
IR
AD15:AD0, A19:16
(4)
8
PRODLPRODH
Instruction
Decode and
Control
BITOP
(3)
MSSP
Star t-up T im er
VDD,VSS
ECCP3
Power-up
Timer
Oscillator
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Test Mode
Select
CCP4 CCP5
MCLR
Timer2Timer1 Timer3 Timer4Timer0
OSC2/CLKO
OSC1/CLKI
BOR
LVD
Note 1: ECCP2/P2A are multiplexed with RC1 when CCP2MX is set; with RE7 when CCP2MX is cleared and the device is configured in
Timing
Generation
Precision
Band Gap
Reference
Data
EEPROM
ECCP1
ECCP2
Microcontroller mode; or with RB3 when CCP2MX is cleared in all other program memory modes.
3
8
8 x 8 Multiply
W
8
8
ALU<8>
EUSART1Comparator
8
10-bit
8
8
ADC
EUSART2
2: P1B/P1C/P3B/P3C are multiplexed with RE6:RE3 when ECCPMX is set and with RH7:RH4 when ECCPMX is not set.
3: RG5 is multiplexed with MCLR
and is only av ailable when the MCLR Resets are disabled.
4: External memory interface pins are multiplexed with PORTD (AD7:AD0), PORTE (AD15:AD8) and PORTH (A19:A16).
PORTA
PORTB
PORTC
PORTD
PORTE
PORTF
PORTG
PORTH
PORTJ
RA0/AN0
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/LVDIN
OSC2/CLKO/RA6
RB0/INT0/FLT0
RB1/INT1
RB2/INT2
RB3/INT3/ECCP2
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
RC0/T1OSO/T13CKI
RC1/T1OSI/ECCP2
RC2/ECCP1/P1A
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX1/CK1
RC7/RX1/DT1
RD7/AD7/PSP7:
RD0/AD0/PSP0
RE0/AD8/RD/P2D
RE1/AD9/WR/P2C
RE2/AD10/CS/P2B
RE3/AD11/P3C
RE4/AD12/P3B
RE5/AD13/P1C
RE6/AD14/P1B
RE7/AD15/ECCP2
RF0/AN5
RF1/AN6/C2OUT
RF2/AN7/C1OUT
RF3/AN8
RF4/AN9
RF5/AN10/CVREF
RF6/AN11
RF7/SS
RG0/ECCP3/P3A
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4/P3D
RG4/CCP5/P1D
MCLR/VPP/RG5
RH0/A16:RH3/A19
RH4/AN12/P3C
RH5/AN13/P3B
RH6/AN14/P1C
RH7/AN15/P1B
RJ0/ALE
RJ1/OE
RJ2/WRL
RJ3/WRH
RJ4/BA0
RJ5/CE
RJ6/LB
RJ7/UB
(4)
(2,4)
(2,4)
(2,4)
(2,4)
(3)
(2)
(2)
(2)
(2)
(1)
(1)
/P2A
(1)
(1)
/P2A
(4)
(4)
(4)
(1)
(1,4)
/P2A
(4)
DS39612B-page 10 2005 Microchip Technology Inc.
PIC18F6525/6621/8525/8621
T ABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS
Pin Name
/VPP/RG5
MCLR
MCLR
VPP
RG5
OSC1/CLKI
OSC1
CLKI
OSC2/CLKO/RA6
OSC2
CLKO
RA6
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all
2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices).
3: External memory interface functions are only available on PIC18F8525/8621 devices.
4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for
5: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX is not set (Microcontroller mode).
6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8525/8621 devices.
7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is not set.
8: AV
9: RG5 is multiplexed with MCLR
(9)
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
Program Memory modes except Microcontroller).
all PIC18F6525/6621 devices.
DD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of
the part in user or ICSP™ modes. See parameter D001 for details.
PIC18F6X2X PIC18F8X2X
Pin Number
79
39 49
40 50
and is only available when the MCLR Resets are disabled.
Pin
Buffer
Type
O
O
I/O
Type
I
P
I
IICMOS/ST
ST
—
ST
CMOS
—
—
TTL
Description
Master Clear (input) or programming
voltage (output).
Master Clear (Res et) inpu t. Thi s pin is an
active-low Reset to the device.
Programming voltage inpu t.
Digital input.
Oscillator crystal or extern al cl ock in put .
Oscillator crystal input or ex te rnal clock
source input. ST buffer when configured
in RC mode; otherwise CMOS.
External clock source input. Alwa ys
associated with pin function OSC1 (see
OSC1/CLKI, OSC2/CLKO pins).
Oscillator crystal or clock output.
Oscillator crystal output. Connects to
crystal or resonator i n C ry s tal oscillator
mode.
In RC mode, OSC2 pin ou tp uts CLKO
which has 1/4 the freque ncy of OSC1
and denotes the instr uct ion cycle rate.
General purpose I/O pin.
DD)
2005 Microchip Technology Inc. DS39612B-page 11
PIC18F6525/6621/8525/8621
TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
PIC18F6X2X PIC18F8X2X
RA0/AN0
24 30
RA0
AN0
RA1/AN1
23 29
RA1
AN1
RA2/AN2/V
REF-
22 28
RA2
AN2
V
REF-
RA3/AN3/VREF+
21 27
RA3
AN3
V
REF+
RA4/T0CKI
28 34
RA4
T0CKI
RA5/AN4/LVDIN
27 33
RA5
AN4
LVDIN
RA6 See the OSC2/CLKO/RA6 pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
Program Memory modes except Microcontroller).
2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices).
3: External memory interface functions are only available on PIC18F8525/8621 devices.
4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for
all PIC18F6525/6621 devices.
5: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX is not set (Microcontroller mode).
6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8525/8621 devices.
7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is not set.
8: AV
DD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of
the part in user or ICSP™ modes. See parameter D001 for details.
9: RG5 is multiplexed with MCLR
and is only available when the MCLR Resets are disabled.
Pin
Type
I/O
I/O
I/O
I/O
Buffer
Type
TTL
I
Analog
TTL
I
Analog
TTL
I
Analog
I
Analog
TTL
I
Analog
I
Analog
I/OIST/OD
ST
I/O
TTL
I
Analog
I
Analog
Description
PORTA is a bidirectional I/O port.
Digital I/O.
Analog input 0.
Digital I/O.
Analog input 1.
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
Digital I/O.
Analog input 3.
A/D reference voltage (high) inp ut .
Digital I/O – Open-drain when configured
as output.
Timer0 external clock input.
Digital I/O.
Analog input 4.
Low-Voltage Detect input.
DD)
DS39612B-page 12 2005 Microchip Technology Inc.
PIC18F6525/6621/8525/8621
T ABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
PIC18F6X2X PIC18F8X2X
RB0/INT0/FLT0
48 58
RB0
INT0
FLT0
RB1/INT1
47 57
RB1
INT1
RB2/INT2
46 56
RB2
INT2
RB3/INT3/ECCP2/P2A
45 55
RB3
INT3
(1)
ECCP2
(1)
P2A
RB4/KBI0
44 54
RB4
KBI0
RB5/KBI1/PGM
43 53
RB5
KBI1
PGM
RB6/KBI2/PGC
42 52
RB6
KBI2
PGC
RB7/KBI3/PGD
37 47
RB7
KBI3
PGD
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
Program Memory modes except Microcontroller).
2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices).
3: External memory interface functions are only available on PIC18F8525/8621 devices.
4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for
all PIC18F6525/6621 devices.
5: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX is not set (Microcontroller mode).
6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8525/8621 devices.
7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is not set.
8: AV
DD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of
the part in user or ICSP™ modes. See parameter D001 for details.
9: RG5 is multiplexed with MCLR
and is only available when the MCLR Resets are disabled.
Pin
Type
I/O
I
I
I/O
I
I/O
I
I/O
I/O
I/O
O
I/O
I
I/O
I
I/O
I/O
I
I/O
I/O
I
I/O
Buffer
Type
TTL
ST
ST
TTL
ST
TTL
ST
TTL
ST
ST
—
TTL
ST
TTL
ST
ST
TTL
ST
ST
TTL
ST
ST
Description
PORTB is a bidirectional I/O port. PORTB
can be software program m ed for internal
weak pull-ups on all inputs.
Digital I/O.
External interrupt 0.
PWM Fau lt input fo r ECCP1 .
Digital I/O.
External interrupt 1.
Digital I/O.
External interrupt 2.
Digital I/O.
External interrupt 3.
Enhanced Capture 2 input, Compare 2
output, PWM2 output.
ECCP2 output P2A.
Digital I/O.
Interrupt-on-chang e pi n.
Digital I/O.
Interrupt-on-chang e pi n.
Low-Voltage ICSP™ programming
enable pin.
Digital I/O.
Interrupt-on-chang e pi n.
In-Circuit Debugger and
ICSP programming cloc k.
Digital I/O.
Interrupt-on-chang e pi n.
In-Circuit Debugger and
ICSP programming data.
DD)
2005 Microchip Technology Inc. DS39612B-page 13
PIC18F6525/6621/8525/8621
TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
PIC18F6X2X PIC18F8X2X
RC0/T1OSO/T13CKI
30 36
RC0
T1OSO
T13CKI
RC1/T1OSI/ECC P2/P2A
29 35
RC1
T1OSI
(2)
ECCP2
(2)
P2A
RC2/ECCP1/P1A
33 43
RC2
ECCP1
P1A
RC3/SCK/SCL
34 44
RC3
SCK
SCL
RC4/SDI/SDA
35 45
RC4
SDI
SDA
RC5/SDO
36 46
RC5
SDO
RC6/TX1/CK1
31 37
RC6
TX1
CK1
RC7/RX1/DT1
32 38
RC7
RX1
DT1
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
Program Memory modes except Microcontroller).
2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices).
3: External memory interface functions are only available on PIC18F8525/8621 devices.
4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for
all PIC18F6525/6621 devices.
5: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX is not set (Microcontroller mode).
6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8525/8621 devices.
7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is not set.
8: AV
DD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of
the part in user or ICSP™ modes. See parameter D001 for details.
9: RG5 is multiplexed with MCLR
and is only available when the MCLR Resets are disabled.
Pin
Type
I/O
O
I
I/O
I
I/O
O
I/O
I/O
O
I/O
I/O
I/O
I/O
I
I/O
I/O
O
I/O
O
I/O
I/O
I
I/O
Buffer
Type
ST
—
ST
ST
CMOS
ST
—
ST
ST
—
ST
ST
ST
ST
ST
ST
ST
—
ST
—
ST
ST
ST
ST
Description
PORTC is a bidirectional I/O port.
Digital I/O.
Timer1 oscillator outp ut.
Timer1/Timer3 external clock input.
Digital I/O.
Timer1 oscillator input.
Enhanced Capture 2 input, Compare 2
output, PWM 2 output.
ECCP2 output P2A.
Digital I/O.
Enhanced Capture 1 input, Compare 1
output, PWM 1 output.
ECCP1 output P1A.
Digital I/O.
Synchronous serial clock input/output for
SPI™ mode.
Synchronous serial clock input/output for
2
C™ mode.
I
Digital I/O.
SPI data in.
2
C data I/O.
I
Digital I/O.
SPI data out.
Digital I/O.
USART1 asynchronous transmit.
USART1 synchrono us cl ock
(see RX1/DT1).
Digital I/O.
USART1 asynchronous rec ei ve.
USART1 synchronous data
(see TX1/CK1).
DD)
DS39612B-page 14 2005 Microchip Technology Inc.
PIC18F6525/6621/8525/8621
T ABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
PIC18F6X2X PIC18F8X2X
RD0/AD0/PSP0
RD0
(3)
AD0
58 72
PSP0
RD1/AD1/PSP1
RD1
(3)
AD1
55 69
PSP1
RD2/AD2/PSP2
RD2
(3)
AD2
54 68
PSP2
RD3/AD3/PSP3
RD3
(3)
AD3
53 67
PSP3
RD4/AD4/PSP4
RD4
(3)
AD4
52 66
PSP4
RD5/AD5/PSP5
RD5
(3)
AD5
51 65
PSP5
RD6/AD6/PSP6
RD6
(3)
AD6
50 64
PSP6
RD7/AD7/PSP7
RD7
(3)
AD7
49 63
PSP7
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
Program Memory modes except Microcontroller).
2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices).
3: External memory interface functions are only available on PIC18F8525/8621 devices.
4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for
all PIC18F6525/6621 devices.
5: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX is not set (Microcontroller mode).
6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8525/8621 devices.
7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is not set.
8: AV
DD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of
the part in user or ICSP™ modes. See parameter D001 for details.
9: RG5 is multiplexed with MCLR
and is only available when the MCLR Resets are disabled.
Pin
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Buffer
Type
ST
TTL
TTL
ST
TTL
TTL
ST
TTL
TTL
ST
TTL
TTL
ST
TTL
TTL
ST
TTL
TTL
ST
TTL
TTL
ST
TTL
TTL
Description
PORTD is a bidir ect ion al I /O p ort . T hese pi ns
have TTL input buffers when ex te rn al
memory is enabled.
Digital I/O.
External memory address/data 0.
Parallel Slave Port data.
Digital I/O.
External memory address/data 1.
Parallel Slave Port data.
Digital I/O.
External memory address/data 2.
Parallel Slave Port data.
Digital I/O.
External memory address/data 3.
Parallel Slave Port data.
Digital I/O.
External memory address/data 4.
Parallel Slave Port data.
Digital I/O.
External memory address/data 5.
Parallel Slave Port data.
Digital I/O.
External memory address/data 6.
Parallel Slave Port data.
Digital I/O.
External memory address/data 7.
Parallel Slave Port data.
DD)
2005 Microchip Technology Inc. DS39612B-page 15
PIC18F6525/6621/8525/8621
TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
PIC18F6X2X PIC18F8X2X
RE0/AD8/RD/P2D
RE0
(3)
AD8
24
RD
P2D
RE1/AD9/WR
RE1
(3)
AD9
/P2C
13
WR
P2C
RE2/AD10/CS/P2B
RE2
(3)
AD10
64 78
CS
P2B
RE3/AD11/P3C
RE3
(3)
AD11
(4)
P3C
RE4/AD12/P3B
RE4
(3)
AD12
(4)
P3B
RE5/AD13/P1C
RE5
(3)
AD13
(4)
P1C
RE6/AD14/P1B
RE6
(3)
AD14
(4)
P1B
RE7/AD15/ECCP2/P2A
RE7
(3)
AD15
(5)
ECCP2
(5)
P2A
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
Program Memory modes except Microcontroller).
2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices).
3: External memory interface functions are only available on PIC18F8525/8621 devices.
4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for
all PIC18F6525/6621 devices.
5: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX is not set (Microcontroller mode).
6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8525/8621 devices.
7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is not set.
8: AV
DD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of
the part in user or ICSP™ modes. See parameter D001 for details.
9: RG5 is multiplexed with MCLR
63 77
62 76
61 75
60 74
59 73
and is only available when the MCLR Resets are disabled.
Pin
Type
I/O
I/O
I
O
I/O
I/O
I
O
I/O
I/O
I
O
I/O
I/O
O
I/O
I/O
O
I/O
I/O
O
I/O
I/O
O
I/O
I/O
I/O
O
Buffer
Type
ST
TTL
TTL
—
ST
TTL
TTL
ST
ST
TTL
TTL
—
ST
TTL
—
ST
TTL
—
ST
TTL
—
ST
TTL
—
ST
TTL
ST
—
Description
PORTE is a bidirectional I/O port.
Digital I/O.
External memory address/data 8.
Read control for Parallel Slave Port.
ECCP2 output P2D.
Digital I/O.
External memory address/data 9.
Write control for Parallel Slave Port.
ECCP2 output P2C.
Digital I/O.
External memory address/data 10.
Chip select control for Parallel Slave Port.
ECCP2 output P2B.
Digital I/O.
External memory address/data 11.
ECCP3 output P3C.
Digital I/O.
External memory address/data 12.
ECCP3 output P3B.
Digital I/O.
External memory address/data 13.
ECCP1 output P1C.
Digital I/O.
External memory address/data 14.
ECCP1 output P1B.
Digital I/O.
External memory address/data 15.
Enhanced Capture 2 input, Compare 2
output, PWM 2 output.
ECCP2 output P2A.
DD)
DS39612B-page 16 2005 Microchip Technology Inc.
PIC18F6525/6621/8525/8621
T ABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
PIC18F6X2X PIC18F8X2X
RF0/AN5
18 24
RF0
AN5
RF1/AN6/C2OUT
17 23
RF1
AN6
C2OUT
RF2/AN7/C1OUT
16 18
RF2
AN7
C1OUT
RF3/AN8
15 17
RF1
AN8
RF4/AN9
14 16
RF1
AN9
RF5/AN10/CV
REF
13 15
RF1
AN10
CVREF
RF6/AN11
12 14
RF6
AN11
RF7/SS
11 13
RF7
SS
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
Program Memory modes except Microcontroller).
2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices).
3: External memory interface functions are only available on PIC18F8525/8621 devices.
4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for
all PIC18F6525/6621 devices.
5: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX is not set (Microcontroller mode).
6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8525/8621 devices.
7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is not set.
8: AV
DD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of
the part in user or ICSP™ modes. See parameter D001 for details.
9: RG5 is multiplexed with MCLR
and is only available when the MCLR Resets are disabled.
Pin
Type
I/O
I
I/O
I
O
I/O
I
O
I/O
I
I/O
I
I/O
I
O
I/O
I
I/O
I
Buffer
Type
ST
Analog
ST
Analog
ST
ST
Analog
ST
ST
Analog
ST
Analog
ST
Analog
Analog
ST
Analog
ST
TTL
Description
PORTF is a bidirectional I/O port.
Digital I/O.
Analog input 5.
Digital I/O.
Analog input 6.
Comparator 2 output.
Digital I/O.
Analog input 7.
Comparator 1 output.
Digital I/O.
Analog input 8.
Digital I/O.
Analog input 9.
Digital I/O.
Analog input 10.
Comparator V
REF output.
Digital I/O.
Analog input 11.
Digital I/O.
SPI™ slave select input.
DD)
2005 Microchip Technology Inc. DS39612B-page 17
PIC18F6525/6621/8525/8621
TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
RG0/ECCP3/P3A
RG0
ECCP3
P3A
RG1/TX2/CK2
RG1
TX2
CK2
RG2/RX2/DT2
RG2
RX2
DT2
RG3/CCP4/P3D
RG3
CCP4
P3D
RG4/CCP5/P1D
RG4
CCP5
P1D
RG5 7 9 — — See MCLR
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
Program Memory modes except Microcontroller).
2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices).
3: External memory interface functions are only available on PIC18F8525/8621 devices.
4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for
all PIC18F6525/6621 devices.
5: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX is not set (Microcontroller mode).
6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8525/8621 devices.
7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is not set.
8: AV
DD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of
the part in user or ICSP™ modes. See parameter D001 for details.
9: RG5 is multiplexed with MCLR
PIC18F6X2X PIC18F8X2X
Pin Number
35
46
57
68
810
and is only available when the MCLR Resets are disabled.
Pin
Type
I/O
I/O
O
I/O
O
I/O
I/O
I
I/O
I/O
I/O
O
I/O
I/O
O
Buffer
Type
ST
ST
—
ST
—
ST
ST
ST
ST
ST
ST
—
ST
ST
—
Description
PORTG is a bidirectional I/O port.
Digital I/O.
Enhanced Capture 3 input, Compare 3
output, PWM 3 output.
ECCP3 output P3A.
Digital I/O.
USART2 asynchronous transmit.
USART2 synchrono us cl ock
(see RX2/DT2).
Digital I/O.
USART2 asynchronous rec ei ve.
USART2 synchronous data
(see TX2/CK2).
Digital I/O.
Capture 4 input, Compare 4 out put,
PWM 4 output.
ECCP3 output P3D.
Digital I/O.
Capture 5 input, Compare 5 out put,
PWM 5 output.
ECCP1 output P1D.
/VPP/RG5 pin.
DD)
DS39612B-page 18 2005 Microchip Technology Inc.
PIC18F6525/6621/8525/8621
T ABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
PIC18F6X2X PIC18F8X2X
RH0/A16
—79
RH0
A16
RH1/A17
—80
RH1
A17
RH2/A18
—1
RH2
A18
RH3/A19
—2
RH3
A19
RH4/AN12/P3C
—22
RH4
AN12
(7)
P3C
RH5/AN13/P3B
—21
RH5
AN13
(7)
P3B
RH6/AN14/P1C
—20
RH6
AN14
(7)
P1C
RH7/AN15/P1B
—19
RH7
AN15
(7)
P1B
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
Program Memory modes except Microcontroller).
2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices).
3: External memory interface functions are only available on PIC18F8525/8621 devices.
4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for
all PIC18F6525/6621 devices.
5: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX is not set (Microcontroller mode).
6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8525/8621 devices.
7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is not set.
8: AV
DD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of
the part in user or ICSP™ modes. See parameter D001 for details.
9: RG5 is multiplexed with MCLR
and is only available when the MCLR Resets are disabled.
Pin
Type
I/O
O
I/O
O
I/O
O
I/O
O
I/O
I
O
I/O
I
O
I/O
I
O
I/O
I
O
Buffer
Type
ST
TTL
ST
TTL
ST
TTL
ST
TTL
ST
Analog
—
ST
Analog
—
ST
Analog
—
ST
Analog
—
Description
PORTH is a bidirectional I/O port
Digital I/O.
External memory address 16.
Digital I/O.
External memory address 17.
Digital I/O.
External memory address 18.
Digital I/O.
External memory address 19.
Digital I/O.
Analog input 12.
ECCP3 output P3C.
Digital I/O.
Analog input 13.
ECCP3 output P3B.
Digital I/O.
Analog input 14.
ECCP1 output P1C.
Digital I/O.
Analog input 15.
ECCP1 output P1B.
DD)
(6)
.
2005 Microchip Technology Inc. DS39612B-page 19
PIC18F6525/6621/8525/8621
TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
PIC18F6X2X PIC18F8X2X
RJ0/ALE
—62
RJ0
ALE
RJ1/OE
—61
RJ1
OE
RJ2/WRL
—60
RJ2
WRL
RJ3/WRH
—59
RJ3
WRH
RJ4/BA0
—39
RJ4
BA0
RJ5/CE
—40
RJ5
CE
RJ6/LB
—41
RJ6
LB
RJ7/UB
—42
RJ7
UB
VSS 9, 25,
41, 56
V
DD 10, 26,
38, 57
(8)
AV
SS
(8)
DD
AV
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
Program Memory modes except Microcontroller).
2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices).
3: External memory interface functions are only available on PIC18F8525/8621 devices.
4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for
all PIC18F6525/6621 devices.
5: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX is not set (Microcontroller mode).
6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8525/8621 devices.
7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is not set.
8: AV
DD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of
the part in user or ICSP™ modes. See parameter D001 for details.
9: RG5 is multiplexed with MCLR
20 26 P — Groun d re fe re nce for analog modules.
19 25 P — Positive supply for analog modules.
and is only available when the MCLR Resets are disabled.
11, 31,
51, 70
12, 32,
48, 71
Pin
Type
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
Buffer
Type
ST
TTL
ST
TTL
ST
TTL
ST
TTL
ST
TTL
ST
TTL
ST
TTL
ST
TTL
Description
PORTJ is a bidirectional I/O port
(6)
Digital I/O.
External memory address latch enable.
Digital I/O.
External memory output enable.
Digital I/O.
External memory write low control.
Digital I/O.
External memory write high control.
Digital I/O.
System bus byte addres s 0 control.
Digital I/O
External memory access i ndi c at or.
Digital I/O.
External memory low byte select.
Digital I/O.
External memory high byte select.
P — Ground reference for logic and I/O pins.
P — Positive supply for logic and I/O pins.
DD)
.
DS39612B-page 20 2005 Microchip Technology Inc.
PIC18F6525/6621/8525/8621
2.0 OSCILLATOR CONFIGURATIONS
2.1 Oscillator Types
The PIC18F6525/6621/8525/8621 devices can be
operated in twelve different oscillator modes. The user
can program four configuration bits (FOSC3, FOSC2,
FOSC1 and FOSC0) to select one of these eight
modes:
1. LP Low-Power Crystal
2. XT Crystal/Resonator
3. HS High-Speed Crystal/Resonator
4. RC External Resistor/Cap ac ito r
5. EC External Clock
6. ECIO External Clock with I/O pin
enabled
7. HS+PLL High-Speed Crystal/Resonator
with PLL enabled
8. RCIO External Resistor/Capacito r with
I/O pin enabled
9. ECIO+SPLL External Clock with software
controlled PLL
10. ECIO +PL L External Clock with PLL and I/O
pin enabled
11. HS+SPLL High-Speed Crystal/Resonator
with software control
12. RC IO E x tern al Resi stor/Capacitor with
I/O pin enabled
2.2 Crystal Oscilla tor/Ceramic Resonators
In XT , LP, HS, HS+PLL or HS+SPLL Oscillator modes, a
crystal or ceramic resonator is connected to the OSC1
and OSC2 pins to establish oscil lation. Figure 2-1 shows
the pin connections.
The PIC18F6525/6621/8525/8621 oscillator design
requires the use of a parallel cut crystal.
Note: Use of a series cut crystal may give a
frequency out of the cryst al manu facturer s
specifications.
FIGURE 2-1: CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP
CONFIGURATION)
Note 1: See Table 2-1 and Table 2-2 for
recommended values of C1 and C2.
2: A series resistor (R
S
T ABLE 2-1: CAPACITOR SELECTION FOR
CERAMIC RESONATORS
Ranges Tested:
Mode Freq C1 C2
XT 455 kHz
2.0 MHz
4.0 MHz
HS 8 .0 MHz
16.0 MHz
These values are for design guidance only.
See notes following this table.
Resonators Used:
2 kHz 8 MHz
4 MHz 16 MHz
Note 1: Higher capac itance inc reases th e stabilit y
of the oscillator but also increases the
start-up time.
2: When operating below 3V V
using certain ceramic resonators at any
voltage, it may be necessary to use high
gain HS mode, try a lower frequency
resonator or switch to a crystal oscillator.
3: Since each resonator/crystal has its own
characteristics, the user should consul t the
resonator/crystal manufacturer for appropriate values of external components or
verify oscillator performance.
68-100 pF
15-68 pF
15-68 pF
10-68 pF
10-22 pF
68-100 pF
15-68 pF
15-68 pF
10-68 pF
10-22 pF
DD, or when
2005 Microchip Technology Inc. DS39612B-page 21
PIC18F6525/6621/8525/8621
TABLE 2-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Ranges Tested:
Mode Freq C1 C2
LP 32.0 kHz 33 pF 33 pF
XT 200 kHz 47-68 pF 47-68 pF
1.0 MHz 15 pF 15 pF
4.0 MHz 15 pF 15 pF
HS 4.0 MHz 15 pF 15 pF
8.0 MHz 15-33 pF 15-33 pF
20.0 MHz 15-33 pF 15-33 pF
25.0 MHz 15-33 pF 15-33 pF
These values are for design guidance only.
See notes following this table.
Crystals Used
32 kHz 4 MHz
200 kHz 8 MHz
1 MHz 20 MHz
Note 1: Higher capacit ance increa ses the st ability
of the oscillator but also increases the
start-up time.
S (see Figure 2-1) may be required in
2: R
HS mode, as we ll as XT mode , to avoid
overdriving crystals with low drive level
specification.
3: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appropriate values of external components or
verify oscillator performance.
An external clock sourc e may also be conne cted to th e
OSC1 pin in the HS, XT and LP modes as shown in
Figure 2-2.
2.3 RC Oscillator
For timing insensitive applications, the “RC” and
“RCIO” device options offer additional cost savings.
The RC oscillator frequency is a function of the supply
voltage, the resistor (R
values and the operating temperature. In addition to
this, the oscillator frequency will vary from unit to unit
due to normal process parameter variation. Furthermore, the difference in lead frame capacitance
between package types will also affect the oscillation
frequency, especially for low C
also needs to take into account variation due to
tolerance of external R and C components used.
Figure 2-3 shows how the R/C combination is
connected.
In the RC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used f or t e st pu r pos es or t o sy nc hr o n iz e ot he r
logic.
FIGURE 2-3: RC OSCILLATOR MODE
VDD
REXT
CEXT
VSS
OSC/4
F
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
The RCIO Oscillator mode functions like the RC mode
except that the OSC2 pin becomes an additional
general purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6).
EXT) and capacitor (CEXT)
EXT values. The user
OSC1
Internal
Clock
PIC18F6X2X/8X2X
OSC2/CLKO
EXT > 20 pF
C
FIGURE 2-2: EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR
LP OSCILLATOR
CONFIGURATION)
Clock from
Ext. System
Open
DS39612B-page 22 2005 Microchip Technology Inc.
OSC1
PIC18F6X2X/8X2X
OSC2
2005 Microchip Technology Inc. DS39612B-page 23
PIC18F6525/6621/8525/8621
2.6 Oscillator Switching Feature
The PIC18F6525/6621/8525/8621 devices include a
feature that allows the system clock source to be
switched from the main oscillator to an alternate low
frequency clock source. For the PIC18F6525/6621/
8525/8621 devices, this alternate clock source is the
Timer1 osc illator. If a low-frequency cryst al (32 kHz , for
example) has been attached to the Timer1 oscillator
pins and the Timer1 oscillator has been enabled, the
device can switch to a low-power execution mode.
FIGURE 2-7: DEVICE CLOCK SOURCES
PIC18F6X2X/8X2X
OSC2
OSC1
T1OSO
T1OSI
Main Oscillator
Sleep
Timer1 Oscillator
T1OSCEN
Enable
Oscillator
Figure 2-7 shows a block diagram of the system clock
sources. The clock switching feature is enabled by
programming the Oscillator Switching Enable
(OSCSEN
) bit in the CONFIG1H Configur ation regist er
to a ‘0’. Clock switchi ng is disabled i n an erased dev ice.
See Section 12.0 “Timer1 Module” for further details
of the Timer1 oscillator. See Section 24.0 “Special
Features of the CPU” for Configuration register
details.
4 x PLL
TOSC
TT1P
TOSC/4
MUX
Clock
Source
TSCLK
Clock Source Option
for Other Modules
DS39612B-page 24 2005 Microchip Technology Inc.
PIC18F6525/6621/8525/8621
2.6.1 SYSTEM CLOCK SWITCH BIT
The system clock sourc e sw it ching is performed under
software control. The system clock switch bits,
SCS1:SCS0 (OSCCON<1:0>), control the clock
switching. When the SCS0 bit is ‘0’, the system clock
source comes from the main oscillator that is selected
by the FOSC configuration bits in the CONFIG1H
Configurat ion register. When the SCS0 bi t is set, the
system clock source will come from the Timer1
oscillator . The SCS0 bit i s cleared on all form s of Reset.
When the FOSC bits are programmed for Soft ware PLL
mode, the SCS1 bit can be used to select between
primary oscillator/clock and PLL output. The SCS1 bit
will only have an effect on the system clock if the PLL
is enabled (PLLEN = 1) and locked (LOC K = 1), else it
will be forced cleared. When programmed with
Configuration Controlled PLL, the SCS1 bit will be
forced clear.
Note: The Timer1 oscillator must be enabled
and operating to switch the system clock
source. The Timer1 oscillator is enabled
by setting the T1OSCEN bit in the Timer1
Control register (T1CON). If the Timer1
oscillator is not enabled, then any write to
the SCS0 bit will be ignored (SCS0 bit
forced cleared) and the main osci llator w ill
continue to be the system clock source.
REGISTER 2-1: OSCCON: OSCILLATOR CONTROL REGISTER
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — —LOCKPLLEN
bit 7 bit 0
(1)
SCS1 SCS0
(2)
bit 7-4 Unimplemented: Read as ‘0’
bit 3 LOCK: Phase Lock Loop Lock Status bit
1 = Phase Lock Loop output is stable as system clock
0 = Phase Lock Loop output is not stable and output cannot be used as system clock
bit 2 PLLEN: Phase Lock Loop Enable bit
1 = Enable Phase Lock Loop output as system clock
0 = Disable Phase Lock Loop
bit 1 SCS1: System Clock Switch bit 1
When PLLEN and LOCK bits are set:
1 = Use PLL output
0 = Use primary oscillator/clock input pin
When PLLEN or LOCK bit is cleared:
Bit is forced clear.
bit 0 SCS0: System Clock Switch bit 0
When OSCSEN configuration bit = 0 and T1OSCEN bit = 1:
1 = Switch to Timer1 oscillator/clock pin
0 = Use primary oscillator/clock input pin
When
OSCSEN and T1OSCEN are in other states:
Bit is forced clear.
Note 1: PLLEN bit is forced set when configured for ECIO+PLL and HS+PLL modes. This
bit is writable fo r ECIO+SPLL and H S+SPLL modes only; forced cleared f or all other
oscillator modes.
2: The setting of SCS0 = 1 supersedes SCS1 = 1.
(1)
(2)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2005 Microchip Technology Inc. DS39612B-page 25
PIC18F6525/6621/8525/8621
2.6.2 OSCILLATOR TRANSITIONS
PIC18F6525/6621/8525/8621 devices contain circuitry
to prevent “glitches” when switching between oscillator
sources. Essentially, the circuitry waits for eight rising
edges of the clock source that the processor is switching to. This e ns ures t hat the new clock source is stable
and that its pulse wid th will not be less than the sho rtest
pulse width of the two clock sources.
A timing diagram indicating the transition from the main
oscillator to the Timer1 oscillator is s hown in Figure2-8.
The Timer1 oscillator is assumed to be running all the
time. After the SCS0 bit is set, the processor i s frozen at
the next occurring Q1 cycle. After eight synchronization
cycles are counted from the Timer1 oscillator, operation
resumes. No additional delays are required after the
synchronization cycles.
FIGURE 2-8: TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR
Q4 Q1
Q3Q2Q1Q4Q3Q2
Q2 Q3 Q4 Q1
PC + 4
T1OSI
OSC1
Internal
System
Clock
Program
Counter
Note: T
SCS
DLY is the delay from SCS high to first count of transition circuit.
(OSCCON<0>)
Q1
TOSC
Q1
TDLY
TT1P
21 345678
TSCS
PC + 2PC
The sequence of events that takes place when switching from the Timer1 oscillator to the main oscillator will
depend on the mode of the main oscillator. In addition
to eight clock cycles of the main oscillator, additional
delays may take place.
If the main oscillator is configured for an external
crystal (HS, XT, LP), then the transition will take place
after an oscillator start-up time (T
OST) has occurred. A
timing diagram, indicating the transition from the
Timer1 oscillator to the main oscillator for HS, XT and
LP modes, is shown in Figure 2-9.
FIGURE 2-9: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, XT, LP)
Q1 Q2 Q3 Q4 Q1 Q2
T1OSI
OSC1
Internal
System Clock
(OSCCON<0>)
SCS
Program
Counter
Note: T
Q3 Q4
PC PC + 2
OST = 1024 TOSC (drawing not to scale).
Q1
TOST
TT1P
12345678
TSCS
TOSC
Q3
PC + 6
DS39612B-page 26 2005 Microchip Technology Inc.
PIC18F6525/6621/8525/8621
If the main oscillator is configured for HS mode with
PLL active, an oscillator start-up time (T
additional PLL time -out (T
PLL) will occur . The PLL tim e-
out is typically 2 ms and allows the PLL to lock to the
main oscillator frequency. A timing diagram, indicating
the transition from the Timer1 oscillator to the main
oscillator for HS+PLL mode, is shown in Figure 2-10.
FIGURE 2-10: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1
(HS WITH PLL ACTIVE, SCS1 = 1)
OST) plus an
Q4 Q1
T1OSI
OSC1
PLL Clock
Input
Internal System
(OSCCON<0>)
Program Counter
Note: T
Clock
SCS
PC PC + 2
OST = 1024 TOSC (drawing not to scale).
TOST
TPLL
TT1P
TOSC
1234 5678
TSCS
Q1 Q2 Q3 Q4 Q1 Q2
If the main oscillator is configured for EC mode with PLL
active, only PLL time-out (T
PLL) will occur . The PLL time-
out is typically 2 ms and allows the PLL to lock to the
main oscillator frequency. A timing diagram, indicating
the transition from the Timer1 oscillator to the main
oscillator for EC with PLL active, is shown in Figure 2-1 1.
FIGURE 2-11: T IMING FOR TRANSITION BETWEEN TIMER1 AND OSC1
(EC WITH PLL ACTIVE, SCS1 = 1)
Q3
PC + 4
Q4
2005 Microchip Technology Inc. DS39612B-page 27
PIC18F6525/6621/8525/8621
If the main oscillato r is c onfigur ed in th e RC, R CIO, EC
or ECIO modes, th ere is no os cillator start-up time-out.
Operation will resume after eight cycles of the main
oscillator have been counted. A timing diagram, indicating the transition from the Timer1 oscillator to the
main oscillator for RC, RCIO, EC and ECIO modes, is
shown in Figure 2-12.
FIGURE 2-12: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)
Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3
TT1P
Q4
T1OSI
OSC1
Internal System
(OSCCON<0>)
Note: RC Oscillator mode assumed.
Clock
SCS
Program
Counter
PC
2.7 Effects of Sleep Mode on the On-Chip Oscillator
When the device e xecutes a SLEEP i nstructio n, the onchip clocks and oscillator are turn ed off and the device
is held at the beginning of an instruction cycle (Q1
state). With the oscillator off, the OSC1 and OSC2
TOSC
12345678
TSCS
PC + 2
switching currents have been removed, Sleep mode
achieves the lowest current consumption of the device
(only leakage currents). Enabling any on-chip feature
that will operate during Sleep will increase the current
consumed during Sleep. The user can wake from
Sleep through external Reset, Watchdog Timer Reset,
or through an interrupt.
signals will stop oscillating. Since all the transistor
TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE
Oscillator Mode OSC1 Pin OSC2 Pin
RC Floating, external resistor should pull high At logic low
RCIO Floating, external resistor should pull high Configured as PORTA, bit 6
ECIO Floating Configured as PORTA, bit 6
EC Floating At logic low
LP, XT and HS Feedback inverter disabled at
quiescent volt ag e leve l
Note: See Table 3-1 in Section 3.0 “Reset” for time-outs due to Sleep and MCLR
Feedback inverter disabled at
quiescent voltage level
Reset.
PC + 4
2.8 Power-up Delays
Power-up delays are con trolled by two time rs so that no
external Reset circuitry is required for most
applications. The delays ensure that the device is kept
in Reset un til the device p ower supply and clock are
stable. For additional information on Reset operation,
see Section 3.0 “Reset”.
The first timer is the Power-up Timer (PWRT) which
optionally provid es a fix ed delay of 72 ms (nominal) on
power-up only (POR and BOR). The second timer is
With the PLL enable d (HS+PL L a nd EC + PLL oscillator
mode), the time-out sequence following a Power-on
Reset is different from other oscillator modes. The
time-out sequence is as follows: First, the PWRT timeout is invoked after a POR time delay has expired.
Then, the Oscillator Start-up Timer (OST) is invoked.
However, this is still not a sufficient amount of time to
allow the PLL to lock at high frequencies. The PWRT
timer is used to provide an additional fixed 2 ms
(nominal) t ime- ou t to al low t he P LL am ple t ime to lo ck
to the incoming clock frequency.
the Oscillator Start-up Timer (OST), intended to keep
the chip in Reset until the crystal oscillator is stable.
DS39612B-page 28 2005 Microchip Technology Inc.
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